PCA9571PW_技术文档

PCA9571

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

Rev. 1 — 22 December 2014

Product data sheet

1. General description

The PCA9571 is a CMOS device that provide 8 bits of General Purpose parallel Output

(GPO) expansion in low voltage processor and handheld battery powered mobile

applications. They operate at 1 MHz I²C-bus speeds on a lightly loaded bus (<100 pF)

while maintaining backward compatibility to Fast-mode (400 kHz) and Standard-mode

(100 kHz).

The PCA9571 is a streamlined GPO that consists of 8-bit push-pull outputs that offer low

current consumption, small packaging options and a low operating voltage range of 1.1 V

to 3.6 V. The latched outputs are symmetrical 4 mA current drive capability at 3.3 V to

drive various control logic. The PCA9571 output expanders provide a simple solution

when additional outputs are needed while keeping interconnections and floor space to a

minimum, for example, in battery powered mobile applications where PCBs are crowded

for interfacing to sensors, push buttons, etc.

The PCA9571 contains an internal Power-On Reset (POR) and a Software Reset feature

that initializes the device to its default state.

2. Features and benefits

 1 MHz I²C-bus interface with 6 mA SDA sink capability for lightly loaded buses

(<100 pF) and improved power consumption

 Compliant with the I²C-bus Fast and Standard modes

 1.1 V to 3.6 V operation

 Latched outputs with a sink/source capability of 4 mA at 3.3 V

 Readable device ID (manufacturer, device type, and revision)

 Software Reset

 Power-On Reset

 Low standby current

 40 C to +85 C operation

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

 Packages offered: XQFN12, TSSOP14 and DHVQFN14

3. Applications

 Smartphones and tablets

 Portable medical equipment

 Portable instrumentation and test measurement

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

Description

Version

PCA9571GU

71

XQFN12

plastic, extremely thin quad flat package; no leads;

SOT1174-1

12 terminals; body 1.70  2.00  0.50 mm

PCA9571BQ^[1]P9571

DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

quad flat package; no leads; 14 terminals; body

2.5  3  0.85 mm

SOT762-1

SOT402-1

PCA9571PW^[1]PCA9571

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

[1] In development. Contact your NXP sales office for availability.

4.1 Ordering options

Table 2.

Ordering options

Type number

Orderable

part number

Package

XQFN12

Packing method

Minimum

order quantity

Temperature

T_amb= 40 C to +85 C

PCA9571GU

PCA9571GUX

Reel 7” Q1/T1

*standard mark SMD

4000

3000

2500

PCA9571BQ^[1]PCA9571BQX

PCA9571PW^[1]PCA9571PWJ

DHVQFN14

TSSOP14

Reel 7” Q1/T1

*standard mark SMD

T_amb= 40 C to +85 C

Reel 13” Q1/T1

*standard mark SMD

[1] In development. Contact your NXP sales office for availability.

5. Block diagram

PCA9571

SCL

SDA

2

SHIFT

REGISTER

OUTPUT

PORT

INPUT

FILTER

I C-BUS

8 bits

P0 to P7

CONTROL

write pulse

read pulse

POWER-ON

RESET

V

DD

V

SS

002aag670

Fig 1. Block diagram of PCA9571

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

2 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

V

DD

I

OH

OL

write pulse

D

Q

data from Shift Register

FF

S

P0 to P7

I

CI

power-on reset

V

SS

D

Q

FF

S

read pulse

CI

data to Shift Register

002aag789

Fig 2. Simplified schematic of the I/Os (P0 to P7)

6. Pinning information

6.1 Pinning

PCA9571GU

terminal 1

index area

terminal 1

index area

P0

1

2

3

4

5

11 SDA

10 SCL

2

3

4

5

6

13

12

11

10

9

P0

SDA

SCL

P7

P1

P2

P3

P1

P2

PCA9571BQ

9

8

7

P7

P6

P3

P6

n.c.

P5

V

SS

P5

002aag942

002aag674

Transparent top view

Fig 3. Pin configuration for XQFN12

Fig 4. Pin configuration for DHVQFN14

1

2

3

4

5

6

7

14

13

12

11

10

9

n.c.

P0

V

DD

SDA

SCL

P7

P1

P2

PCA9571PW

P3

P6

n.c.

P5

V

SS

8

P4

002aag830

Fig 5. Pin configuration for TSSOP14

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

3 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

6.2 Pin description

Table 3.

Symbol

P0

Pin description for XQFN12

1

Description

output 0

P1

2

output 1

P2

3

output 2

P3

4

output 3

V_SS

P4

5

supply ground

output 4

6

P5

7

output 5

P6

8

output 6

P7

9

output 7

SCL

SDA

V_DD

10

11

12

serial clock line

serial data line

supply voltage

Table 4.

Symbol

n.c.

P0

Pin description for TSSOP14, DHVQFN14

1

Description

not connected

output 0

2

P1

3

output 1

P2

4

output 2

P3

5

output 3

n.c.

V_SS

P4

6

not connected

supply ground

output 4

7

8

P5

9

output 5

P6

10

11

12

13

14

output 6

P7

output 7

SCL

SDA

V_DD

serial clock line

serial data line

supply voltage

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

4 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

7. Functional description

Refer to Figure 1 “Block diagram of PCA9571”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA9571 is 4Ah as shown in Figure 6.

slave address

0

1

0

1

0

1

R/W

fixed

aaa-015054

Fig 6. PCA9571 device address

7.2 Software Reset Call, and device ID addresses

Two other different addresses can be sent to the device.

• General Call address: allows to reset the device through the I²C-bus upon reception

of the right I²C-bus sequence. See Section 7.2.1 “Software Reset” for more

information.

• Device ID address: allows to read ID information from the device (manufacturer, part

identification, revision). See Section 7.2.2 “Device ID (PCA9571 ID field)” for more

information.

R/W

0

1

0

002aac115

002aac116

Fig 7. General Call address

Fig 8. Device ID address

7.2.1 Software Reset

The Software Reset Call allows all the devices in the I²C-bus to be reset to the power-up

state value through a specific formatted I²C-bus command. To be performed correctly, it

implies that the I²C-bus is functional and that there is no device hanging the bus.

The Software Reset sequence is defined as following:

1. A START command is sent by the I²C-bus master.

2. The reserved General Call I²C-bus address ‘0000 000’ with the R/W bit set to 0 (write)

is sent by the I²C-bus master.

3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h)

only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I²C-bus

master.

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

5 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

4. Once the General Call address has been sent and acknowledged, the master sends

1 byte. The value of the byte must be equal to 06h.

a. The device acknowledges this value only. If the byte is not equal to 06h, the device

does not acknowledge it.

If more than 1 byte of data is sent, the device does not acknowledge any more.

5. Once the right byte has been sent and correctly acknowledged, the master sends a

STOP command to end the Software Reset sequence: the device then resets to the

default value (power-up value) and is ready to be addressed again within the specified

bus free time. If the master sends a Repeated START instead, no reset is performed.

The I²C-bus master must interpret a non-acknowledge from the device (at any time) as a

‘Software Reset Abort’. The device does not initiate a reset of its registers.

The unique sequence that initiates a Software Reset is described in Figure 9.

2

SWRST Call I C-bus address

SWRST data = 06h

S

0

A

0

1

0

A

P

START condition

R/W

acknowledge

from slave(s)

acknowledge

from slave(s)

PCA9571 is reset.

Registers are set to default power-up values.

002aah233

Fig 9. Software Reset sequence

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

6 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

7.2.2 Device ID (PCA9571 ID field)

The Device ID field is a 3-byte read-only (24 bits) word giving the following information:

• 12 bits with the manufacturer name, unique per manufacturer (for example, NXP).

• 9 bits with the part identification, assigned by manufacturer, the 7 MSBs with the

category ID and the 6 LSBs with the feature ID (for example PCA9571 8-bit I/O

expander).

• 3 bits with the die revision, assigned by manufacturer (for example, Rev X).

The Device ID is read-only, hardwired in the device and can be accessed as follows:

1. START command

2. The master sends the Reserved Device ID I²C-bus address followed by the R/W bit

set to 0 (write): ‘1111 1000’.

3. The master sends the I²C-bus slave address of the slave device it needs to identify.

The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one

that has the I²C-bus slave address).

4. The master sends a Re-START command.

Remark: A STOP command followed by a START command will reset the slave state

machine and the Device ID read cannot be performed. Also, a STOP command or a

Re-START command followed by an access to another slave device will reset the

slave state machine and the Device ID Read cannot be performed.

5. The master sends the Reserved Device ID I²C-bus address followed by the R/W bit

set to 1 (read): ‘1111 1001’.

6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte +

4 MSB of the second byte), followed by the 9 part identification bits (4 LSBs of the

second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of

the third byte).

7. The master ends the reading sequence by NACKing the last byte, thus resetting the

slave device state machine and allowing the master to send the STOP command.

Remark: The reading of the Device ID can be stopped anytime by sending a NACK

command.

If the master continues to ACK the bytes after the third byte, the slave rolls back to the

first byte and keeps sending the Device ID sequence until a NACK has been

detected.

PCA9571 Device ID is shown in Figure 10.

manufacturer

0

1

0

1

0

part identification

revision

002aag792

Fig 10. PCA9571 Device ID field

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

7 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

acknowledge from

one or several slaves

acknowledge from

slave to be identified

2

slave to be identified

I C-bus slave address

Device ID address

of the device to be identified

Device ID address

S

1

0

A A6 A5 A4 A3 A2 A1 A0

x

A Sr

1

0

1

A

START condition

R/W

don’t care

repeated START

condition

R/W

acknowledge

from master

acknowledge

from master

no acknowledge

from master

M

M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5

A

P4 P3 P2 P1 P0 R2 R1 R0 A

P

11 10

STOP condition

manufacturer name = 000000000000

part identification = 100000001

revision = 000

aaa-015053

If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the

master generates a ‘no acknowledge’.

Fig 11. Device ID field reading

8. I/O programming

8.1 I/O architecture

The device’s ports (see Figure 2) are entirely independent and are output ports. The state

of the ports at the pin is transferred from the ports to the microcontroller in the Read mode

(see Figure 13). Output data is transmitted to the ports in the Write mode (see Figure 12).

At power-on all ports are HIGH. The state of the Output Port register determines if either

Q1 or Q2 is on, driving the line either HIGH or LOW. A bit set to 1 in the data byte will drive

the line HIGH at the corresponding port. A bit set to 0 in the data byte will drive the line

LOW at the corresponding port.

If an external voltage is applied to an output, care should be exercised because of the

low-impedance path that exists between the pin and either V_DDor V_SS

.

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) first addresses the slave device. By setting the last

bit of the byte containing the slave address to logic 0 the Write mode is entered. The

device acknowledges and the master sends the data byte for P7 to P0 and is

acknowledged by the device. The 8-bit data is presented on the port lines after it has been

acknowledged by the device. The number of data bytes that can be sent successively is

not limited. The previous data is overwritten every time a data byte has been sent.

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

8 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

SCL

1

2

3

4

5

6

7

8

9

slave address

A6 A5 A4 A3 A2 A1 A0

data 1

P7 P6 P5 P4 P3

data 2

SDA

S

0

A

1

P1 P0

A

P7 P6 P5 P4 P3

0

P1 P0

A

START condition

R/W

P2

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

write to port

t

v(Q)

data output from port

P2 output voltage

DATA 1 VALID

DATA 2 VALID

002aag833

Fig 12. Write mode (output)

8.3 Reading from a port (Input mode)

All ports are outputs and cannot be used as inputs. When reading the device, the data

returned is the port state at the pin. To read, the master (microcontroller) first addresses

the slave device by setting the last bit of the byte containing the slave address to logic 1.

The data byte that follows on the SDA is the value of the ports pins. There is no limit to the

number of bytes read, and the state of the output port pins is updated at each

acknowledge cycle. Logic 1 means that the port is HIGH. Logic 0 means that the port is

LOW.

no acknowledge

from master

slave address

data from port

DATA 1

data from port

DATA 4

SDA

S

A6 A5 A4 A3 A2 A1 A0

1

A

1

P

START condition

R/W acknowledge

from slave

acknowledge

from master

STOP

condition

read from

port

002aag846

Fig 13. Read input port register

8.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the device in a

reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the device registers and I²C-bus/SMBus state machine will initialize to their default

states. See Section 13 for DC and AC characteristics of the POR function.

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

9 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

9. Application design-in information

9.1 I/O expander applications

Figure 14 shows an 8-bit output expander application. The desired HIGH or LOW logic

levels are controlled by the master with speeds of up to 1 MHz on a lightly loaded bus

(<100 pF). This allows the host processor to control various functions quickly and with

very low overhead. The port read function of the device enables the host processor to poll

the status of the output port pins. This is useful for system recovery operations or

debugging.

1.8 V

SDA

SCL

P0

P1

P2

P3

P4

P5

P6

P7

GPS enable

vibrator control

latch control

switch control

audio control

camera control

MP3 control

FM control

CORE

PROCESSOR

002aag680

Fig 14. I/O expander application

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

10 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

10. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

+4

Unit

V

supply voltage

0.5

[1]

input voltage

SCL; SDA

0.5

+4

V

I_IK

input clamping current

output clamping current

SCL; V_I< 0 V

-

18

25

25

mA

C

I_OK

P port; V_O< 0 V or V_O> V_DD

SDA; V_O< 0 V or V_O> V_DD

continuous; P port

-

I_O

output current

-

I_OL

I_DD

T_stg

T_j

LOW-level output current

supply current

continuous; SDA; V_O= 0 V to V_DD

continuous through V_SS

-

100

+150

125

storage temperature

junction temperature

65

-

C

[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

11 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

11. Static characteristics

Table 6.

Static characteristics

T_amb= 40 C to +85 C; V_DD= 1.1 V to 3.6 V; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

V

V_IK

input clamping voltage

supply voltage

I_I= 18 mA

1.2

-

V_DD

V_POR

V_OL

1.1

-

3.6

V

power-on reset voltage

LOW-level output voltage

V_I= V_DDor V_SS; I_O= 0 mA

-

0.7

-

1.0

V

P port; I_OL= 2 mA; V_DD= 1.65 V

P port; I_OL= 3 mA; V_DD= 2.3 V

P port; I_OL= 4 mA; V_DD= 3 V

-

0.25

V

-

0.25

V

-

0.25

V

V_OH

HIGH-level output voltage P port; I_OL= 2 mA; V_DD= 1.65 V

P port; I_OL= 3 mA; V_DD= 2.3 V

1.35

-

V

2.0

-

V

P port; I_OL= 4 mA; V_DD= 3 V

2.7

-

V

I_OL

V_IH

V_IL

LOW-level output current

HIGH-level input voltage

LOW-level input voltage

SDA; V_OL= 0.4 V; V_DD= 2.1 V to 3.6 V

SDA; V_OL= 0.2  V_DD; V_DD= 1.1 V to 2.0 V

SCL, SDA; V_DD= 1.1 V to 1.2 V

SCL, SDA; V_DD= 1.2 V to 3.6 V

SCL, SDA; V_DD= 1.1 V to 1.2 V

SCL, SDA; V_DD= 1.2 V to 3.6 V

3

-

mA

V

1

-

0.8  V_DD

0.7  V_DD

0.5

-

1.2

-

3.6

V

-

0.2  V_DD

0.3  V_DD

1

V

0.5

-

V

I_I

input current

SCL, SDA; V_DD= 1.1 V to 3.6 V;

V_I= V_DDor V_SS

-

A

I_DD

supply current

SDA, P port; V_Ion SDA = V_DDor V_SS

;

I_O= 0 mA; f_SCL= 400 kHz

V_DD= 2.3 V to 3.6 V

V_DD= 1.1 V to 2.3 V

SCL, SDA, P port;

-

6.5

4

15

9

A

V_Ion SCL, SDA = V_DDor V_SS

I_O= 0 mA; f_SCL= 0 kHz

;

V_DD= 2.3 V to 3.6 V

V_DD= 1.1 V to 2.3 V

-

1

3.2

1.7

A

0.6

Active mode: SCL, SDA, P port; I_O= 0 mA;

f

_SCL= 400 kHz; continuous register read

V_DD= 1.1 V to 3.6 V

-

50

6

75

7

A

pF

C

C_i

input capacitance

output capacitance

ambient temperature

V_I= V_DDor V_SS

-

C_o

V_O= V_DDor V_SS

operating in free air

-

3

5

T_amb

40

-

+85

[1] The typical values are at V_DD= 2.2 V and T_amb= 25 C.

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

12 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

11.1 Typical characteristics

aaa-011393

aaa-011394

12

8

120

I

DD

DD(stb)

(nA)

V

= 3.6 V

3.3 V

2.5 V

1.8 V

1.1 V

DD

V

DD

= 3.6 V

3.3 V

2.5 V

1.8 V

1.1 V

(μA)

80

4

40

0

−40

−15

10

35

60

85

(°C)

−40

−15

10

35

60

85

(°C)

T

amb

Fig 15. Supply current versus ambient temperature

Fig 16. Standby supply current versus

ambient temperature

aaa-011395

10

I

DD

(μA)

8

6

4

2

1

1.1

1.8

2.5

3.3

3.6

V

DD

(V)

T_amb= 25 C

Fig 17. Supply current versus supply voltage

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

13 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

aaa-011487

aaa-011488

8

18

I

sink

T

amb

= −40 °C

25 °C

I

sink

(mA)

T

amb

= −40 °C

25 °C

85 °C

6

4

2

0

85 °C

12

6

0

0.2

0.4

0.6

0

0.2

0.4

0.6

V

(V)

V

(V)

OL

a. V_DD= 1.2 V

b. V_DD= 1.8 V

aaa-011489

aaa-011490

30

36

I

sink

(mA)

T

amb

= −40 °C

25 °C

I

sink

(mA)

85 °C

T

amb

= -40 °C

25 °C

20

24

12

0

85 °C

10

0

0.2

0.4

0.6

0

0.2

0.4

0.6

V

(V)

V

(V)

OL

c. V_DD= 2.5 V

Fig 18. I/O sink current versus LOW-level output voltage

d. V_DD= 3.3 V

PCA9571

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Product data sheet

Rev. 1 — 22 December 2014

14 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

aaa-011563

aaa-011564

6

14

I

source

(mA)

T

amb

= −40 °C

25 °C

I

source

(mA)

12

10

8

T

amb

= −40 °C

25 °C

85 °C

4

6

2

0

4

2

0

0.2

0.4

0.6

(V)

0

0.2

0.4

0.6

(V)

V

DD

− V

V

− V

DD OH

OH

a. V_DD= 1.2 V

b. V_DD= 1.8 V

aaa-011565

aaa-011566

25

36

I

source

(mA)

I

source

20

15

10

5

(mA)

T

amb

= −40 °C

25 °C

T

amb

= −40 °C

25 °C

85 °C

24

85 °C

12

0

0.2

0.4

0.6

(V)

0

0.2

0.4

0.6

(V)

V

DD

− V

V

− V

DD OH

OH

c. V_DD= 2.5 V

d. V_DD= 3.3 V

Fig 19. I/O source current versus HIGH-level output voltage

aaa-011567

60

V

OL

(mV)

(1)

(2)

40

20

0

−40

−15

10

35

60

85

(°C)

T

amb

(1) V_DD= 1.8 V; I_sink= 2 mA

(2) V_DD= 1.8 V; I_sink= 100 A

Fig 20. LOW-level output voltage versus temperature

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Product data sheet

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PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

12. Dynamic characteristics

Table 7.

Dynamic characteristics

V_DD= 1.1 V to 3.6 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Standard mode

I²C-bus

Fast mode

I²C-bus

1 MHz

I²C-bus^[1]

Unit

Min

0

Max

100

-

Min

0

Max

Min

0

Max

1000 kHz

f_SCL

t_BUF

SCL clock frequency

400

-

bus free time between a

STOP and START

condition

4.7

1.3

0.5

-

s

t_HD;STAhold time (repeated)

START condition

4.0

4.7

4.0

-

0.6

-

0.26

-

s

ns

t_SU;STA

set-up time for a repeated

START condition

t_SU;STOset-up time for STOP

condition

t_HD;DATdata hold time

0

-

0

-

0

-

[2]

[3]

t_VD;ACKdata valid acknowledge

time

3.45

0.9

0.45 s

t_VD;DATdata valid time

t_SU;DATdata set-up time

-

3.45

-

0.9

-

0.45 s

250

4.7

-

100

1.3

-

50

0.5

-

ns

t_LOW

t_HIGH

t_f

LOW period of the SCL

clock

s

HIGH period of the SCL

clock

4.0

-

0.6

-

0.26

-

s

fall time of both SDA and

SCL signals

-

300

1000

50

20 

(V_DD/ 5.5 V)

300

50

20 

(V_DD/ 5.5 V)

120 ns

50 ns

t_r

rise time of both SDA and

SCL signals

20

-

[4]

t_SP

pulse width of spikes that

must be suppressed by the

input filter

Port timing

t_v(Q)data output valid time

-

200

-

200

-

200 ns

[1] Fm+ mode on a non-standard, lightly loaded bus (<100 pF).

[2] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] _VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[4] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

t

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

13. Power-on reset requirements

In the event of a glitch or data corruption, the device can be reset to its default conditions

by using the power-on reset feature. Power-on reset requires that the device go through a

power cycle to be completely reset. This reset also happens when the device is

powered on for the first time in an application.

V

DD

ramp-up

ramp-down

re-ramp-up

t

d(rst)

time

(dV/dt)

r

f

time to re-ramp

when V drops to V

DD

SS

002aah307

Fig 21. V_DDis lowered below 0.6 V and then ramped up to V_DD

Table 8.

Recommended supply sequencing and ramp rates

T_amb= 25 C (unless otherwise noted). Not tested; specified by design.

Symbol Parameter

Condition

Min

0.1

1

Typ

Max

2000

-

Unit

ms

s

(dV/dt)_f

(dV/dt)_r

t_d(rst)

fall rate of change of voltage

Figure 21

-

rise rate of change of voltage

reset delay time

Figure 21

Figure 21; when V_DDdrops to V_SS

Figure 22

[1]

[2]

V_DD(gl)

glitch supply voltage difference

V_DD= 2.1 V to 3.6 V

V_DD= 1.1 V to 2.1 V

-

1.2

V

-

V_DD 0.9

10

V

t_w(gl)VDD

supply voltage glitch pulse width Figure 22

rising V_DD

-

s

V

V_POR(trip)power-on reset trip voltage

0.7

1.0

[1] Level that V_DDcan glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t_w(gl)VDD= 1 s.

[2] Glitch width that will not cause a functional disruption when V_DD= 1.8 V to 3.6 V, V_DD(gl)= 0.5  V_DD

;

V_DD= 1.1 V to 1.8 V, V_DD(gl)= V_DD 0.9 V.

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (t_w(gl)VDD) and glitch height (V_DD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 22 and Table 8 provide more information on

how to measure these specifications.

V

DD

∆V

DD(gl)

time

002aah309

t

w(gl)VDD

Fig 22. Glitch width and glitch height

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PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition

is released and all the registers and the I²C-bus/SMBus state machine are initialized to

their default states. Figure 23 and Table 8 provide more details on this specification.

V

DD

V

POR

(rising V

)

DD

time

POR

time

002aah096

Fig 23. Power-on reset voltage (V_POR

)

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

14. Parameter measurement information

V

DD

R

= 1 kΩ

L

SDA

DUT

C

= 50 pF

L

002aag803

a. SDA load configuration

(1)

two bytes for read Input port register

STOP

condition condition

(P) (S)

START

Address

Bit 7

Data

Bit 0

STOP

condition

(P)

R/W

Bit 0

Address

Bit 1

ACK

(A)

Bit 7

(MSB)

(LSB)

002aag952

b. Transaction format

t

HIGH

t

SP

LOW

0.7 × V

0.3 × V

DD

SCL

t

r

VD;DAT

t

SU;STO

BUF

t

f

t

SU;STA

VD;ACK

t

f(o)

0.7 × V

0.3 × V

DD

SDA

t

f

t

r

t

VD;ACK

t

HD;DAT

HD;STA

SU;DAT

repeat START condition

STOP condition

002aag804

c. Voltage waveforms

C_Lincludes probe and jig capacitance.

All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z_o= 50 ; t_r/t_f 30 ns.

All parameters and waveforms are not applicable to all devices.

Byte 1 = I²C-bus address; Byte 2, byte 3 = P port data.

(1) See Figure 13.

Fig 24. I²C-bus interface load circuit and voltage waveforms

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PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

500 Ω

Pn

DUT

2 × V

DD

C

= 50 pF

500 Ω

L

002aag805

a. P port load configuration

0.7 × V

0.3 × V

DD

SCL

P0

A

P7

SDA

Pn

t

v(Q)

last stable bit

unstable

data

002aag806

b. Write mode (R/W = 0)

0.7 × V

0.3 × V

DD

SCL

P0

A

P7

t

h(D)

su(D)

Pn

002aag807

c. Read mode (R/W = 1)

C_Lincludes probe and jig capacitance.

t_v(Q)is measured from 0.7  V_DDon SCL to 50 % I/O (Pn) output.

All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z_o= 50 ; t_r/t_f 30 ns.

The outputs are measured one at a time, with one transition per measurement.

All parameters and waveforms are not applicable to all devices.

Fig 25. P port load circuit and voltage waveforms

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

15. Package outline

XQFN12: plastic, extremely thin quad flat package; no leads;

12 terminals; body 1.70 x 2.00 x 0.50 mm

SOT1174-1

X

D

B

A

E

terminal 1

index area

A

1

A

3

detail X

C

∅ v

∅ w

C

A

B

b

y

1

y

C

5

1

7

e

1

e

11

terminal 1

index area

L

1

L

0

1

2 mm

scale

Dimensions

(1)

Unit

A

b

D

E

e

1

L

1

v

w

y

1

3

max 0.5 0.05

mm nom

min

0.25 1.8 2.1

0.127 0.20 1.7 2.0 0.4 1.6 0.50 0.15 0.1 0.05 0.05 0.05

0.15 1.6 1.9 0.45

0.55

0.00

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1174-1_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

JEITA

- - -

10-04-07

10-04-21

SOT1174-1

MO-288

Fig 26. Package outline SOT1174-1 (XQFN12)

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PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

6

L

1

7

8

E

h

e

14

13

9

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

1

max.

0.05 0.30

0.00 0.18

3.1

2.9

1.65

1.35

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT762-1

- - -

MO-241

- - -

Fig 27. Package outline SOT762-1 (DHVQFN14)

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

7

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 28. Package outline SOT402-1 (TSSOP14)

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 9 and 10

Table 9.

SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

 350

220

< 2.5

235

220

 2.5

220

Table 10. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

18. Soldering: PCB footprints

Footprint information for reflow soldering of XQFN12 package

SOT1174-1

2.25

2

0.45

0.22

CU

(11×)

0.32

CU

(1×)

0.45

(1×)

1

CU

2.3

CU

2.55 2.05

0.4

(7×)

1

CU

placement area

solder land

solder land plus solder paste

solder resist, 0.0625 around copper

solder paste deposit, −0.025 around copper,

clearance, 0.125 around occupied area

Dimensions in mm

stencil thickness 0.1

occupied area

sot1174-1_fr

Fig 30. PCB footprint for SOT1174-1 (XQFN12); reflow soldering

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

Footprint information for reflow soldering of DHVQFN14 package

SOT762-1

4.250

3.300

0.240

0.500

0.025

0.105

3.750 2.800

0.400 0.900 1.700 3.500

0.600

1.400

2.200

4.000

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

occupied area

sot762-1_fr

Fig 31. PCB footprint for SOT762-1 (DHVQFN14); reflow soldering

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PCA9571

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

Footprint information for reflow soldering of TSSOP14 package

SOT402-1

Hx

Gx

P2

(0.125)

By

Hy Gy

Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 4.950 5.300 5.800 7.450

sot402-1_fr

Fig 32. PCB footprint for SOT402-1 (TSSOP14); reflow soldering

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PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

19. Abbreviations

Table 11. Abbreviations

Acronym

CDM

ESD

FM

Description

Charged-Device Model

ElectroStatic Discharge

Frequency Modulation

General Purpose Input/Output

Global Positioning Satellite

Human Body Model

Inter-Integrated Circuit bus

Input/Output

GPIO

GPS

HBM

I²C-bus

I/O

IC

Integrated Circuit

ID

Identification

LED

Light Emitting Diode

Least Significant Bit

MPEG audio layer 3

Most Significant Bit

LSB

MP3

MSB

SMBus

System Management Bus

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

20. Revision history

Table 12. Revision history

Document ID

Release date

20141222

Data sheet status

Change notice

Supersedes

PCA9571 v.1

Product data sheet

-

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Remote 8-bit general purpose outputs for 1 MHz I²C-bus

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

21.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

21.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCA9571

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 22 December 2014

32 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA9571

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 22 December 2014

33 of 34

PCA9571

NXP Semiconductors

Remote 8-bit general purpose outputs for 1 MHz I²C-bus

23. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

23

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

7.2.1

7.2.2

Functional description . . . . . . . . . . . . . . . . . . . 5

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5

Software Reset Call, and device ID addresses 5

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5

Device ID (PCA9571 ID field). . . . . . . . . . . . . . 7

8

I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 8

I/O architecture. . . . . . . . . . . . . . . . . . . . . . . . . 8

Writing to the port (Output mode) . . . . . . . . . . . 8

Reading from a port (Input mode) . . . . . . . . . . 9

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.1

8.2

8.3

8.4

9

Application design-in information . . . . . . . . . 10

I/O expander applications. . . . . . . . . . . . . . . . 10

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11

Static characteristics. . . . . . . . . . . . . . . . . . . . 12

Typical characteristics . . . . . . . . . . . . . . . . . . 13

Dynamic characteristics . . . . . . . . . . . . . . . . . 16

Power-on reset requirements . . . . . . . . . . . . . 17

Parameter measurement information . . . . . . 19

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

Handling information. . . . . . . . . . . . . . . . . . . . 24

9.1

10

11

11.1

12

13

14

15

16

17

Soldering of SMD packages . . . . . . . . . . . . . . 24

Introduction to soldering . . . . . . . . . . . . . . . . . 24

Wave and reflow soldering . . . . . . . . . . . . . . . 24

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25

17.1

17.2

17.3

17.4

18

19

20

Soldering: PCB footprints. . . . . . . . . . . . . . . . 27

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31

21

Legal information. . . . . . . . . . . . . . . . . . . . . . . 32

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

21.1

21.2

21.3

21.4

22

Contact information. . . . . . . . . . . . . . . . . . . . . 33

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 December 2014

Document identifier: PCA9571


型号：	PCA9571PW
厂家：	NXP
描述：	SPECIALTY INTERFACE CIRCUIT 接口集成电路
文件：	总34页 (文件大小：1834K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9571PW [NXP]

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