PCA9621PW,118 [NXP]
PCA9621 - 65 mA 8-bit 2-wire bus output port TSSOP 16-Pin;
| 型号： | PCA9621PW,118 |
| 厂家： | 
NXP |
| 描述： | PCA9621 - 65 mA 8-bit 2-wire bus output port TSSOP 16-Pin PC 驱动 光电二极管 接口集成电路 |
| 文件： | 总18页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9621
65 mA 8-bit 2-wire bus output port
Rev. 1 — 9 March 2011
Product data sheet
1. General description
The PCA9621 is a monolithic CMOS integrated circuit for general purpose output drive
configurable from a 2-wire bus interface (including I2C-bus, SMBus, PMBus, and other
systems based on similar principles). Output ports have a 65 mA sink capability, making
them ideal for driving LEDs.
The state of the outputs is determined by a programmable 8-bit register which can be read
and written via signals from the 2-wire bus (e.g., I2C-bus or similar).
The 2-wire bus interface also has 30 mA Fast-mode Plus (Fm+) capability, and
consequently can be run in excess of 1 MHz or up to 4000 pF capacitance. As such, the
PCA9621 can be connected to other 2-wire devices across long cable connections.
It can be mixed with other Fast-mode Plus slaves in systems driven by Fm+ buffers or by
the PCA9646 (fully buffered 4-channel bus switch) to build large scale systems with
high-speed or high-capacitance drive capability, for example large scale LED displays or
controlled lighting.
2. Features and benefits
8 individually selectable open-drain output ports
65 mA static sink capability on all output ports
Ports may be paralleled for up to 500 mA drive
Ideal for simple LED or general purpose output drive
Fast-mode Plus (30 mA, 4000 pF) 2-wire bus capability
Works with I2C-bus (Standard-mode, Fast-mode, and Fast-mode Plus), SMBus
(standard and high power mode), and PMBus
Fast switching times allow operation in excess of 1 MHz
Operating voltages from 2.7 V to 5.5 V
3. Applications
LED and 7-segment displays
Simple high-power (500 mA) LED dimming
General purpose output
Instrumentation indicators
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
4. Ordering information
Table 1.
Ordering information
Tamb = −40 to +85 °C.
Type number
Topside
mark
Package
Name
Description
Version
PCA9621D
PCA9621
PCA9621
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT403-1
PCA9621PW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
5. Block diagram
2.7 V to 5.5 V
V
DD
R1
R2
R3
R4
R5
R6
16
PCA9621
SCL 14
SDA 15
4
P0
P1
P2
P3
P4
LED
LED
high
current
LED
FILTER
5
R7
R8
6
7
9
RESET
3
1
2
2
I C-BUS SLAVE
TRANSCEIVER
R9
A0
A1
R10
10 P5
11 P6
12 P7
A2 13
output
output
8
V
SS
002aaf379
Fig 1. Block diagram of PCA9621
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
2 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
V
DD
SDA
SCL
A2
RESET
P0
1
2
3
4
5
6
7
8
16
15
14
13
A0
A1
V
DD
SDA
SCL
A2
PCA9621D
RESET
P0
P1
P7
PCA9621PW
12 P7
P2
P6
P1
11
10
9
P2
P6
P5
P4
P3
P5
P3
V
SS
P4
V
SS
002aaf381
002aaf382
Fig 2. Pin configuration for SO16
Fig 3. Pin configuration for TSSOP16
6.2 Pin description
Table 2.
Symbol
Pin description
Pin Description
A0
1
address input 0
address input 1
active LOW reset input
output port 0
A1
2
RESET
P0
3
4
P1
5
output port 1
P2
6
output port 2
P3
7
output port 3
VSS
P4
8
negative supply (ground)
output port 4
9
P5
10
11
12
13
14
15
16
output port 5
P6
output port 6
P7
output port 7
A2
address input 2
serial clock line
serial data line
positive supply
SCL
SDA
VDD
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
3 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
7. Functional description
Refer to Figure 1 “Block diagram of PCA9621”.
7.1 VDD, VSS — DC supply pins
The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to
5.5 V. All other I/Os are clamped to VDD and VSS through ESD protection diodes.
7.2 SCL, SDA — 2-wire bus interface
The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I2C-bus style signalling. The interface is Fast-mode Plus
(Fm+) I2C-bus compatible, though the ports contain ESD protection diodes to the positive
and negative supplies. Consequently, VI2C-bus (voltage at SCL and SDA) must remain
within the VDD and VSS supply levels.
7.3 P0 to P7 — output ports
There are eight open-drain output ports whose state is determined by the Control register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.
Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.
The ports are protected by ESD diodes to the supplies so they must not be driven above
the VDD or below the VSS levels.
7.4 RESET — reset IC to default state
The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET signal will clear the contents of the Control register, turning off all output
ports, and resetting the state of the I2C-bus slave transceiver block.
7.5 Power-On Reset (POR)
During power-on, the PCA9621 is internally held in the reset condition for a maximum of
trst = 500 ns. The default condition after reset is for the Control register to be erased
(all zeros), resulting in all output ports being off (high-impedance).
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
4 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
7.6 A0, A1, A2 — address lines
The slave address of the PCA9621 is shown in Figure 4. The address pins (A2, A1, A0)
must be driven to a HIGH or LOW level—they are not internally pulled to a default state.
1
1
0
0
A2 A1 A0 R/W
fixed
externally
selectable
read = 1
write = 0
002aaf383
Fig 4. Slave address
The read/write bit must be set LOW to enable a write to the Control register, or HIGH to
read from the Control register.
7.7 Control register
The Control register of the PCA9621 is shown in Figure 5. Each of the four output ports
can be activated independently by setting the appropriate bit in the Control register.
MSB P7 P6 P5 P4 P3 P2 P1 P0 LSB
002aaf384
1 = ON (sinking)
0 = OFF (high-impedance)
Fig 5. Control register
A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled
(high-impedance). The default reset condition of the register is all zeros, all ports
high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking).
Example: Programming C1h (1100 0001b) into the Control register results in ports P0, P6
and P7 being ON (sinking) and the remaining ports being OFF (high-impedance).
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
5 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
8. Bus transaction
A typical I2C-bus write transaction to the PCA9621 is shown in Figure 6. During a write
transaction, the output ports (P0 to P7) of the PCA9621 are updated upon receipt of the
STOP condition.
slave address
A2 A1 A0
Control register
S
1
1
0
0
0
A
P7 P6 P5 P4 P3 P2 P1 P0
A
P
START
condition
R/W acknowledge
from slave
acknowledge
from slave
STOP
condition
002aaf385
Fig 6. PCA9621 write transaction to Control register
A typical read transaction is shown in Figure 7.
slave address
A2 A1 A0
Control register
S
1
1
0
0
1
A
P7 P6 P5 P4 P3 P2 P1 P0 NA
P
START
condition
R/W acknowledge
from slave
not acknowledge
from master
STOP
condition
002aaf386
Fig 7. PCA9621 read transaction from Control register
9. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
[1]
[1]
[2]
VDD
Vn
II
supply voltage
−0.3
+7
voltage on any other pin
input current
VSS − 0.5
VDD + 0.5
100
V
output ports (P0 to P7)
SDA, SCL pins
-
mA
mA
mA
mA
mW
°C
-
40
address pins A0 to A2; RESET pin
-
20
ISS
ground supply current
total power dissipation
storage temperature
ambient temperature
-
550
Ptot
Tstg
Tamb
-
300
−55
−40
+125
+85
operating
°C
[1] Voltages are specified with respect to pin 8 (VSS).
[2] 100 mA for one pin only in the group P0 to P3, and one pin only in the group P4 to P7. Otherwise 70 mA maximum, any pin.
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
6 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
10. Characteristics
Table 4.
Characteristics
Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power supply
VDD
IDD
supply voltage
supply current
operating
2.7
-
-
-
5.5
1
V
quiescent; VI (RESET pin) = 0 V;
VDD = 5.5 V
μA
I2C-bus ports (SCL, SDA)
VI2C-bus
VIL
I2C-bus voltage
SDA, SCL
VSS − 0.3
-
VDD + 0.3
V
[1]
[1]
[1]
[1]
LOW-level input voltage
VDD = 2.7 V
-
-
0.4
0.5
-
V
VDD = 5.5 V
-
-
V
VIH
HIGH-level input voltage
VDD = 2.7 V
1.2
2.0
−1
-
-
V
VDD = 5.5 V
-
-
V
ILI
input leakage current
pin at VDD or VSS
IOL = 30 mA; VDD = 2.7 V
IOL = 30 mA; VDD = 5.5 V
-
+1
450
275
μA
mV
mV
VOL
LOW-level output voltage
260
140
-
Open-drain output ports (P0 to P7)
IO(sink)
VOL
output sink current
LOW-level; port enabled
IOL = 65 mA
65
-
-
-
mA
mV
mV
LOW-level output voltage
440
1
725
-
IOL = 100 μA
-
RESET
VIH
HIGH-level input voltage
LOW-level input voltage
hysteresis voltage
VDD = 2.7 V
2.0
4.8
-
-
-
V
VDD = 5.5 V
-
-
V
VIL
VDD = 2.7 V
-
650
900
-
mV
mV
mV
mV
μA
ns
VDD = 5.5 V
-
-
Vhys
VDD = 2.7 V
100
200
−1
-
-
VDD = 5.5 V
-
-
ILI
input leakage current
LOW-level reset time
reset time
pin at VDD or VSS
VI < VIL
-
+1
-
[2]
tw(rst)L
trst
25
250
250
RESET pin; from VI > VIH
RESET pin; from VI > VIH
-
500
500
ns
tPOR
power-on reset pulse time
-
ns
Address pins (A0, A1, A2)
VIH
VIL
ILI
HIGH-level input voltage
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
pin at VDD or VSS
1.7
3.5
-
-
-
-
-
-
-
V
-
V
LOW-level input voltage
input leakage current
0.7
1.5
+1
V
-
V
−1
μA
Timing characteristics
tf
fall time of both SDA and
SCL signals
RPU = 200 Ω; measured from
70 % VDD to 30 % VDD
-
-
16
-
-
ns
ns
[3]
tv(Q)
data output valid time
500
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
7 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
[1] Supply voltage dependent; refer to graphs (Figure 8 through Figure 10) for typical trend.
[2] Guaranteed by design, not subject to test.
[3] Time between STOP condition and output port (P0 to P7) being asserted.
002aaf372
002aaf373
250
OL
(mV)
200
400
OL
(mV)
V
V
300
V
= 2.7 V
5.5 V
DD
150
100
50
200
100
0
V
= 5.5 V
DD
2.7 V
400
0
0
200
600
800
1000
(Ω)
−50
0
50
100
150
R
PU
T
(C)
amb
Tamb = 25 °C
IOL = 30 mA
Fig 8. Typical SDA LOW-level output voltage versus
pull-up resistance
Fig 9. Typical SDA LOW-level output voltage versus
ambient temperature
002aaf389
250
V
OL
(mV)
200
150
100
50
0
0
20
40
60
O(sink)
80
(mA)
I
Tamb = 25 °C; VDD = 5.5 V
Fig 10. Typical output port (P0 to P7) LOW-level output voltage versus LOW-level output sink current
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
8 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
11. Application information
Figure 11 shows the PCA9621 in conjunction with the PCA9646 bus multiplexer in a LED
drive application. Each PCA9621 can drive 8 LEDs, and using the address pins on the IC,
up to 8 uniquely addressed devices can sit on one bus branch. The PCA9646 has four
such outputs, giving 256 LEDs in the structure shown.
By additionally using the address pins on the PCA9646, the entire structure may be
repeated 8 times, allowing 2048 LEDs to be uniquely driven. By additionally placing
PCA9646’s in series (refer to the PCA9646 data sheet), the structure may be further
extensively multiplied into a huge array.
5 V
R1
R2
R7
R8
V
DD
V
DD
SCL
SDA
SCL
SC0
SD0
SC0
SD0
SDA
RESET
BUS MASTER
U2
8 LEDs
8 LEDs
PCA9646
8
8
P[7:0]
P[7:0]
PCA9621
PCA9621
U3
U10
R3
R5
R4
R6
8 × PCA9621
each with
8 LEDs = 64 LEDs
SC2
SD2
SC2
SD2
R9
R10
buses SC2/SD2, SC3/SD3
as shown for
SC1
SD1
SC1
SD1
SC0/SD0, SC1/SD1
SC3
SD3
SC3
SD3
A0
Entire structure can be repeated
8 times using PCA9646 address pins
(further expansion possible).
A1
8 LEDs
8 LEDs
8
8
A2
P[7:0]
P[7:0]
V
SS
PCA9621
PCA9621
U1
U11
U18
8 × PCA9621
each with
8 LEDs = 64 LEDs
002aaf397
Fig 11. PCA9621 in a large LED array
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
9 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
Figure 12 shows a simple 7-segment display drive arrangement. All of the 7 segments
plus decimal point can be driven from a single PCA9621. By using the address pins, up to
8 digits can be addressed from a single bus. When running at 1 MHz, all 8 digits can be
updated in less than 0.2 ms.
Further, by using the arrangement described above and shown in Figure 11, the number
of digits driven may be increased significantly.
5 V
R1
R2
SCL
SDA
V
DD
SCL
SDA
P0
P1
P2
P3
P4
P5
P6
P7
3
A[2:0]
RESET
repeat up to 8 times using
address pins on PCA9621
PCA9621
U1
002aaf398
Fig 12. PCA9621 as 7-segment display driver
Figure 13 shows the PCA9621 used in conjunction with other NXP Semiconductors
2-wire bus buffers to form a multiplexer arrangement. Using the PCA9621 to control
multiples of either PCA9521 or PCA9522 produces an isolating bus switch/multiplexer
that has fully compliant I2C-bus I/O levels, low offset voltages, and large noise margins.
Using PCA9522 in this arrangement additionally provides ‘hot-swap’ capability.
3.3 V
R1
R2
V
CC
SCL
SDA
SA1
SB1
SA2
SB2
(1)
400 pF
PCA9521(1)
V
DD
multiple
isolated
buses
SCL
SDA
P0
P1
P2
P3
P4
P5
P6
P7
EN
U2
3.3 V
V
CC
3
A[2:0]
SCLC
SDAC
SCLB
SDAB
(1)
400 pF
RESET
PCA9522(1)
PCA9621
EN
U3
RDY
U1
002aaf399
Address lines allow this structure to be repeated 8 more times.
(1) Or PCA9525 (400 pF), or PCA9605 (4000 pF), or PCA9646 (4 × 4000 pF).
Fig 13. PCA9621 as part of a fully isolating I2C-bus multiplexer
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
10 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 14. Package outline SOT109-1 (SO16)
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
11 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
12 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
13. Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
13 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 5 and 6
Table 5.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 6.
Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
14 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 7.
Abbreviations
Description
Acronym
CMOS
ESD
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Inter-Integrated Circuit bus
Input/Output
I2C-bus
I/O
IC
Integrated Circuit
LED
Light-Emitting Diode
PMBus
POR
Power Management Bus
Power-On Reset
SMBus
System Management Bus
16. References
[1] UM10204, “I2C-bus specification and user manual” — NXP Semiconductors;
www.nxp.com/documents/user_manual/UM10204.pdf
17. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9621 v.1
20110309
Product data sheet
-
-
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
15 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
18.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
16 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
17 of 18
PCA9621
NXP Semiconductors
65 mA 8-bit 2-wire bus output port
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
VDD, VSS — DC supply pins . . . . . . . . . . . . . . . 4
SCL, SDA — 2-wire bus interface . . . . . . . . . . 4
P0 to P7 — output ports . . . . . . . . . . . . . . . . . . 4
RESET — reset IC to default state. . . . . . . . . . 4
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 4
A0, A1, A2 — address lines . . . . . . . . . . . . . . . 5
Control register. . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
Bus transaction . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Handling information. . . . . . . . . . . . . . . . . . . . 13
9
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 13
Introduction to soldering . . . . . . . . . . . . . . . . . 13
Wave and reflow soldering . . . . . . . . . . . . . . . 13
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 14
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 14
14.1
14.2
14.3
14.4
15
16
17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 March 2011
Document identifier: PCA9621
相关型号：
©2020 ICPDF网 联系我们和版权申明