PCA9703PW [NXP]
PARALLEL IN SERIAL OUT SHIFT REGISTER;
| 型号： | PCA9703PW |
| 厂家： | 
NXP |
| 描述： | PARALLEL IN SERIAL OUT SHIFT REGISTER 逻辑集成电路 |
| 文件： | 总27页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
Rev. 2 — 14 June 2012
Product data sheet
1. General description
The PCA9703 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift register
designed to monitor the status of switch inputs. It generates an interrupt when one or
more of the switch inputs change state but allows selected inputs to not generate
interrupts using the interrupt masking feature. The input level is recognized as a HIGH
when it is greater than 0.8 × VDD and as a LOW when it is less than 0.55 × VDD (minimum
LOW threshold of 2.5 V at 5 V node). The PCA9703 can monitor up to 16 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK. The contents of
the shift register are loaded into the interrupt mask register of the device on the rising
edge of CS.
Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the
ESD/overvoltage current to ground. When used with a series resistor (minimum 100 kΩ),
the input can connect to a 12 V battery and support double battery, reverse battery, 27 V
jump start and 40 V load dump conditions in automotive applications. Higher voltages can
be tolerated on the inputs depending on the series resistor used to limit the input current.
The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to
minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN
pull-down prevents floating nodes when the device is used in daisy-chain applications.
With both the high breakdown voltage and high ESD, this device is useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
2. Features and benefits
16 general purpose input ports
18 V tolerant input ports with 100 kΩ external series resistor
Input LOW threshold 0.55 × VDD with minimum of 2.5 V at VDD = 4.5 V
Input hysteresis 0.04 × VDD with minimum of 180 mV at VDD = 4.5 V
Open-drain interrupt output
Interrupt enable pin (INT_EN) disables GPI pins and interrupt output
Interrupt-masking feature allows no interrupt generation from selected inputs
VDD range: 4.5 V to 5.5 V
IDD is very low 2.5 μA maximum
SPI serial interface with speeds up to 5 MHz
SPI supports daisy-chain connection for large switch numbers
AEC-Q100 compliance available
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
ESD protection exceeds 5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating temperature range: −40 °C to +125 °C
Offered in TSSOP24 and HWQFN24 packages
3. Applications
Automotive
Body control modules
Electronic control units (for example, for body controller)
Switch monitoring
SBC wake pin extension
Industrial equipment
Cellular telephones
Emergency lighting
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9703HF
PCA9703PW
9703
HWQFN24 plastic thermal enhanced very very thin quad flat package; SOT994-1
no leads; 24 terminals; body 4 × 4 × 0.75 mm
PCA9703PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
SOT355-1
PCA9703PW/Q900[1] PCA9703PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
[1] PCA9703PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
2 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
5. Block diagram
V
DD
INT
PCA9703
INT_EN
IN0
IN1
DFF0
INPUT
INPUT
INPUT
DFF1
SDOUT
SDIN
SCLK
CS
IN15
DFF15
INPUT
STATUS
REGISTER
20 μA
002aae021
V
SS
Fig 1. Block diagram of PCA9703
6. Pinning information
6.1 Pinning
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SDOUT
INT
V
DD
terminal 1
index area
SDIN
SCLK
CS
3
INT_EN
IN0
4
1
2
3
4
5
6
18
17
16
15
14
13
IN0
IN1
IN2
IN3
IN4
IN5
CS
5
IN1
IN15
IN14
IN13
IN12
IN11
IN10
IN9
IN15
IN14
IN13
IN12
IN11
6
IN2
PCA9703PW
PCA9703PW/Q900
PCA9703HF
7
IN3
8
IN4
9
IN5
10
11
12
IN6
IN7
002aae024
V
IN8
SS
002aae023
Transparent top view
Fig 2. Pin configuration for HWQFN24
Fig 3. Pin configuration for TSSOP24
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
3 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
6.2 Pin description
Table 2.
Symbol Pin
TSSOP24 HWQFN24
Pin description
Type
Description
SDOUT
1
22
output
3-state serial data output; normally
high-impedance
INT
2
3
23
24
output
input
open-drain interrupt output (active LOW)
GPI pin enable and interrupt output enable
1 = GPI pin and interrupt output are enabled
INT_EN
0 = GPI pin and interrupt output are disabled and
interrupt output is high-impedance
IN0
4
1
input
input
input
input
input
input
input
input
ground
input
input
input
input
input
input
input
input
input
input
input
supply
input port 0
IN1
5
2
input port 1
IN2
6
3
input port 2
IN3
7
4
input port 3
IN4
8
5
input port 4
IN5
9
6
input port 5
IN6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
input port 6
IN7
8
input port 7
VSS
IN8
9[1]
10
11
12
13
14
15
16
17
18
19
20
21
ground supply
input port 8
IN9
input port 9
IN10
IN11
IN12
IN13
IN14
IN15
CS
input port 10
input port 11
input port 12
input port 13
input port 14
input port 15
chip select (active LOW)
serial input clock
serial data input (20 μA pull-down)
supply voltage
SCLK
SDIN
VDD
[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
4 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
7. Functional description
PCA9703 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 kΩ series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes, the input is not masked and the interrupt output is
enabled. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled
when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In
cyclically supplied pull-up or pull-down applications, the GPI pull-ups or pull-downs should
be active before the INT_EN is taken HIGH and the INT output should only be sampled
after transient conditions have settled. Additionally, interrupts can be disabled in software
by using the interrupt mask feature. The input port status is accessed via the 4-wire SPI
interface.
Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in
both the input status register and the interrupt mask register. Since a zero in the interrupt
mask register masks the interrupt from that pin, there will not be any interrupts generated.
After power-up it is necessary to access the PCA9703 through the SPI pins in order to
activate the interrupt for any GPI pins. When the PCA9703 is read over the SPI wires, the
input conditions are clocked into the input status register on the CS falling edge. Since the
inputs and the input status register now match, no interrupt is generated and any
pre-existing interrupt is cleared. The input status register data is parallel loaded into the
shift register on the first rising edge of the SCLK. The serial input data is captured on the
opposite clock edge so that there is a 1⁄2 clock cycle hold time. The set-up time is
diminished by the propagation time so the SCLK falling edge to rising edge must be long
enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock
the data out of the PCA9703 and new data from the SDIN into the shift register. There is
no limit to the number of clock cycles that can be applied with the CS LOW, however
sufficient clock cycles should be used to both shift out all of the GPI data and shift in the
new interrupt mask data to the correct position with the MSB first before the CS rising
edge.
For cyclic switch bias applications the switch bias should be applied first, then after the
input voltage is settled the general purpose inputs are switched on by taking the INT_EN
HIGH. This also enables the interrupt output, which will only indicate an interrupt if the GPI
data does not match the input status register on a bit that is enabled by the interrupt mask
register value. If an interrupt is generated, the pull-up or pull-down source should remain
active and the INT_EN should remain active and the SPI pins are used to update the input
status register and read the data out. They are also used to store the new interrupt mask
on the rising edge of CS. After the SPI transaction is complete the INT_EN is taken LOW
to turn the inputs off and disable the INT output. Then the GPI pull-ups or pull-downs can
be turned off. The GPI pins are specifically designed so that any ESD/overstress current
flows to ground, not VDD. They are also specifically designed so that if the input voltage
returns to the same value after pull-up or pull-down bias cycling as before the input pull-up
or pull-down bias cycling, before the input is enabled it will be detected as the same state.
If the Input Status register is read when INT_EN is LOW, the input state at the INT_EN
transition will be output irregardless of the actual input levels since the GPI pins are turned
off.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
5 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
If the VDD falls below the 4.5 V minimum specified supply voltage, the input threshold will
move down since they are a function of the VDD voltage. The input status register and the
interrupt mask register retain their values to below VDD = 2.0 V and power-down can only
be used to generate a power-up reset if the VDD falls below 0.2 V before returning to the
operating range.
Multiple PCA9703 devices can be serially connected for monitoring a large number of
switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK
and CS must be common among all devices and interrupt outputs may be tied together.
No external logic is necessary because all the devices’ interrupt outputs are open-drain
that function as ‘wired-AND’ and can simply be connected together to a single pull-up
resistor.
7.1 SPI bus operation
The PCA9703 interfaces with the controller via the 4-wire SPI bus that is comprised of the
following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial
data out (SDOUT). To access the device, the controller asserts CS LOW, then sends
SCLK and SDIN. When reading is complete and the interrupt mask data is in place, the
controller de-asserts CS. See Figure 4 for register access timing.
7.1.1 CS - chip select
The CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS transitions HIGH the interrupt mask is stored and when CS is HIGH, the SPI
interface is disabled.
7.1.2 SCLK - serial clock input
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel
loads the shift register from the input status register. The subsequent rising edges on
SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the
data on SDIN.
7.1.3 SDIN - serial data input
SDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 μA pull-down
current source to prevent the SDIN node from floating when CS is HIGH.
7.1.4 SDOUT - serial data output
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
6 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
7.1.5 Register access timing
Figure 4 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
sample
SDIN
CS
SCLK
SDIN
MSB in
MSB − 1 in
LSB in
high-impedance
SDOUT
MSB out
MSB − 1 out
LSB out
shift
register
DATA[15:0]
input status
register
DATA[15:0]
interrupt mask
register
002aae286
DATA[15:0] is data on the input pins, IN[15:0].
Shaded areas indicate active but invalid data.
Fig 4. Register access timing
7.1.6 Software reset operation
Software reset will be activated by writing all zeroes into the shift register. This is identical
to having an interrupt mask value of 0X00. Such an operation will reset the device, clear
the input status register to zero and set the interrupt output to HIGH (no interrupt).
7.2 Interrupt output
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 kΩ is recommended.
A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The
value of bits in the mask pattern will determine which input pins will cause an interrupt.
Any bit that is = 0 will disable the input pin corresponding to that bit position from
generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit
pattern is not automatically aligned with the desired input pins. It is the responsibility of the
programmer to shift the correct number of (mask) bits to the correct positions into the shift
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
7 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
register. The interrupt mask bit pattern must be positioned into the shift register prior to the
CS rising edge. Misaligned mask pattern will result in unexpected activation of the
interrupt signal.
The interrupt output is asserted when the input status is changed, and the interrupt mask
bit corresponding to the input pin that caused the change is unmasked (bit value = 1), and
is cleared on the falling edge of CS or when the input port status matches the input status
register. When there are multiple devices, the INT outputs may be tied together to a single
pull-up.
Table 3 illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
Table 3.
Interrupt output function truth table
H = HIGH; L = LOW; X = don’t care
INT_EN Input port status
Input status register[1]
INT output[2]
Mask bit = 1
(unmasked)
Mask bit = 0
(masked)
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
H
L
H
H
X
L
H
X
H
H
[1] Input status register is the value or content of the D flip-flops.
[2] Logic states shown for INT pin assumes 10 kΩ pull-up resistor.
7.3 Interrupt enable
INT_EN is the interrupt output enable input and the general purpose input enable input. It
is an active HIGH input. When the INT_EN pin is LOW the GPI pins are turned off and the
input state is saved to minimize power loss when the input pull-ups or pull-downs are
cycled and the INT output is disabled. The cycled pull-ups or pull-downs should be active
sufficiently long before the INT_EN is taken active that the GPI pin voltage is completely
settled to prevent false or transient interrupt signals.
7.4 General Purpose Inputs
The General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part when the input voltage is above 5.5 V.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
8 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
The minimum required series resistance for applications with input voltages above 5.5 V
is 100 kΩ. For applications requiring an applied voltage above 27 V, Equation 1 is
recommended to determine the series resistor. Failure to include the appropriate input
series resistor may result in product failure and will void the warranty.
voltage applied – 17 V
Rs =
(1)
-----------------------------------------------------------
II
The series resistor should be place physically as close as possible to the connected input
to reduce the effective node capacitance. The input response time is effected by the RC
time constant of the series resistor and the input node capacitance.
7.4.1 VIL, VIH and switching points
A minimum LOW threshold of 2.5 V is guaranteed for the logical switching points for the
inputs. See Figure 5 for details.
V
I
HIGH
V
DD
0.8V
DD
DD
V
IH
V
IL
hysteresis
0.55V
minimum = 0.04V
DD
possible ground shift
LOW
0 V
002aae101
Fig 5. Logic level thresholds
The VIL is specified as a maximum of 0.55 × VDD and is 2.5 V at 4.5 V VDD. This means
that if the user applies 2.5 V or less to the input (with VDD = 4.5 V), or as the voltage
passes this threshold, they will always see a LOW.
The VIH is specified as a minimum of 0.8 × VDD. This means that if the user applies 3.6 V
or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will
always see a HIGH.
Hysteresis minimum is specified as 180 mV at VDD = 4.5 V. This means there will always
be at least 180 mV of difference between the LOW threshold and HIGH threshold to help
prevent oscillations and handle higher noise.
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
9 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
8. Application design-in information
8.1 General application
4.5 V to 5.5 V
18 V
1.5 kΩ
100 kΩ
V
DD
IN0
10 kΩ
relay
INT
CS
CONTROLLER
SCLK
SDIN
OR
18 V
PROCESSOR
SDOUT
100 kΩ
INT_EN
IN1
IN2
180 V
open
PCA9703
500 kΩ
50 kΩ
5 V
10 kΩ
IN15
V
SS
002aae026
Fig 6. Typical application
8.2 Automotive application
Supports:
• 12 V battery (8 V to 16 V)
• Double battery (16 V to 32 V)
• Reverse battery (−8 V to −16 V)
• Jump start (27 V for 60 seconds)
• Load dump (40 V)
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
10 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.1 SBC wake port extension with cyclic biasing
System Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
• Transceivers (HS-CAN, LIN 2.0)
• Scalable voltage regulators
• Watchdog timers; wake-up function
• Fail-safe function
For more information on SBC, refer to
www.nxp.com/products/interface_and_connectivity/system_basis_chips/.
8.2.1.1 UJA106x with PCA9703, standby
V3
alternate
PVR100AD-B5V0
UJA106x
WAKE
IN0
IN1
INT
INT_EN
V2
V1 GND
PCA9703
V
DD
CS
SDIN
V
CC
SDOUT
SCLK
IN15
CSN
V
μC
SS
MOSI
MISO
SCLK
GND
002aae027
Fig 7. UJA106x with PCA9703 with supplied μC (standby)
• PCA9703 fits to SBC UJA106x and UJA107xA family
• PCA9703 can be powered by V1 of SBC
• Extends the SBC with 16 additional wake inputs
• μC can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
– Cyclic bias via V3
– Very low system current consumption even with clamped switches
– Interrupt enable control via V2
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
11 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.1.2 UJA106x with PCA9703, sleep
alternate
alternate
PVR100AD-B5V0
PMEM4010ND
V3
UJA106x
WAKE
V
DD
IN0
IN1
INT_EN
INT
RSTN
V2
alternate
PDTC144TU
PCA9703
V1 GND
CS
SDIN
V
CC
SDOUT
SCLK
IN15
CSN
V
μC
SS
MOSI
MISO
SCLK
GND
002aae028
Fig 8. UJA106x with PCA9703 with unsupplied μC (sleep)
• Very low quiescent system current (50 μA) due to disabled μC and cyclically biasing
of switches
• Wake-up upon change of switches or upon bus traffic (CAN and LIN)
• PCA970x supplied out of cyclically biased transistor regulator
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
12 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.1.3 UJA107xA with PCA9703, standby and sleep
alternate PDTA114E
10 kΩ
BAT
WBIAS
10 kΩ
V1
UJA107xA
alternate
PDTA144E
1 kΩ
1 kΩ
1 kΩ
47 kΩ
47 kΩ
WAKE1
WAKE2
RSTN
V
DD
V1
GND
PCA9703
10 kΩ
10 kΩ
100 kΩ
100 kΩ
INT
IN0
IN1
INT_EN
CS
SDIN
V
CC
SDOUT
SCLK
CSN
IN15
V
μC
SS
MOSI
MISO
SCLK
100 kΩ
GND
002aae029
Fig 9. UJA107xA with PCA9703 with supplied μC (standby)
alternate PDTA114E
10 kΩ
BAT
WBIAS
330 Ω
alternate
10 kΩ
PVR100AD-B5V0
UJA107xA
alternate PDTA144E
1 kΩ
1 kΩ
1 kΩ
47 kΩ
WAKE1
WAKE2
RSTN
470 nF
47 kΩ
V
DD
10 kΩ
V1
GND
alternate
PDTC144T
PCA9703
10 kΩ
100 kΩ
100 kΩ
INT
IN0
IN1
47 kΩ
INT_EN
10 kΩ
CS
SDIN
SDOUT
SCLK
V
CC
CSN
IN15
V
μC
SS
MOSI
MISO
SCLK
100 kΩ
GND
002aae972
Fig 10. UJA107xA with PCA9703 with supplied μC (sleep)
• UJA107xA SBC provides WBIAS pin for cyclic biasing of the inputs
• Compatible with UJA107xA based ASSPs
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
13 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.2 Application examples including switches to battery
BAT BAT
switch bias
switch bias
IN0
IN1
IN0
IN1
PCA9703
PCA9703
clamp 15
IN15
IN15
002aae030
002aae031
Fig 11. Clamp 15 (ignition) detection
Fig 12. Switches to battery and ground with
cyclic biasing
9. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb = −40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
−0.5
-
Max
+6.0
350
Unit
V
VDD
II
supply voltage
input current
[1]
[1]
IN[15:0] pins with series resistor and
VI > 5.5 V
μA
VI
input voltage
GPI pins IN[15:0]; no series resistor
SPI pins
−0.5
−0.5
−65
-
+6
V
+6
V
Tstg
storage temperature
+150
125
°C
°C
Tj(max)
maximum junction temperature
operating
[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 5 “Static characteristics”. See Section 7.4 for series resistor requirements.
PCA9703
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18 V tolerant SPI 16-bit GPI with maskable INT
10. Static characteristics
Table 5.
Static characteristics
VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supply
VDD
supply voltage
supply current
4.5
-
5.0
1.0
5.5
2.5
V
IDD
VDD = 5.5 V; input = 5 V or 18 V;
INT_EN = VDD
μA
[1]
[2]
VPOR
power-on reset voltage
-
1.8
2.2
V
General Purpose Inputs (IN0 to IN15)
VIL
VIH
Vhys
II
LOW-level input voltage
HIGH-level input voltage
hysteresis voltage
input current
-
-
-
-
-
0.55VDD
V
0.8VDD
0.04VDD
-
-
V
[3]
[4]
-
V
GPI recommended maximum current;
VI > 5.5 V; with series resistor Rs
100
μA
IIH
ILI
Ci
HIGH-level input current
input leakage current
input capacitance
each input; VI = VDD
−1
−1
-
-
+1
+1
5.0
μA
μA
pF
VI = 17 V; 100 kΩ series resistor
VI = VSS or VDD
-
2.0
Interrupt output (INT)
IOL
IOH
Co
LOW-level output current
VDD = 4.5 V; VOL = 0.4 V
VOH = VDD
6
-
-
mA
μA
pF
HIGH-level output current
output capacitance
−1
-
-
+1
5
2
SPI and control (SDOUT, SDIN, SCLK, CS, INT_EN)
VIL
VIH
IIH
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level output current
HIGH-level output current
input capacitance
-
-
0.3VDD
V
0.7VDD
-
5.5
40
-
V
SDIN; VI = VDD = 5.5 V
-
20
-
μA
mA
mA
pF
pF
IOL
IOH
Ci
SDOUT; VOL = 0.4 V; VDD = 4.5 V
SDOUT; VOH = VDD − 0.5 V; VDD = 4.5 V
VI = VSS or VDD
5
−5
-
−11
2
-
5
Co
output capacitance
SDOUT; CS = VDD
-
4
6
[1] VDD must be lowered to 0.2 V for at least 5 μs in order to reset device.
[2] Minimum VIL is 2.5 V at VDD = 4.5 V.
[3] Minimum Vhys is 180 mV at VDD = 4.5 V.
[4] For GPI pin voltages > 5.5 V, see Section 7.4.
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18 V tolerant SPI 16-bit GPI with maskable INT
11. Dynamic characteristics
Table 6.
Dynamic characteristics
VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
-
Typ
Max
Unit
MHz
ns
fmax
maximum input clock frequency
rise time
-
5
60
50
-
tr
SDOUT; 10 % to 90 % at 5 V
SDOUT; 90 % to 10 % at 5 V
SCLK
-
35
25
-
tf
fall time
-
ns
tWH
pulse width HIGH
pulse width LOW
SPI enable lead time
SPI enable lag time
SDIN set-up time
SDIN hold time
50
50
50
50
20
30
-
ns
tWL
SCLK
-
-
ns
tSPILEAD
tSPILAG
tsu(SDIN)
th(SDIN)
ten(SDOUT)
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
SDIN to SCLK falling edge
from SCLK falling edge
-
-
ns
-
-
ns
-
-
ns
-
-
ns
SDOUT enable time
from CS LOW to
-
55
ns
SDOUT low-impedance; Figure 16
tdis(SDOUT)
SDOUT disable time
from rising edge of CS to SDOUT
high-impedance; Figure 16
-
-
85
ns
tv(SDOUT)
tsu(SCLK)
th(SCLK)
tPOR
SDOUT valid time
SCLK set-up time
SCLK hold time
from rising edge of SCLK; Figure 17
SCLK falling to CS falling
-
-
-
-
-
55
ns
ns
ns
ns
50
50
-
-
SCLK rising after CS rising
-
power-on reset pulse time
time before CS is active
after VDD > VPOR
250
trel(int)
tv(INT)
interrupt release time
valid time on pin INT
after CS going LOW; Figure 18
-
-
-
500
800
ns
ns
after INn changes or INT_EN
goes HIGH
200
CS
t
t
t
t
h(SCLK)
su(SCLK) SPILEAD
SPILAG
t
t
WL
WH
50 %
50 %
SCLK
SDIN
t
su(SDIN)
t
h(SDIN)
MSB in
t
en(SDOUT)
t
t
dis(SDOUT)
v(SDOUT)
high-impedance
SDOUT
INT
MSB out
t
rel(int)
002aac428
Fig 13. Timing diagram
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NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
2.5 V
0 V
V
V
POR
DD
CS
SCLK
SDOUT
MSB out
MSB − 1
t
POR
002aad158
Fig 14. AC waveform for tPOR timing
CS
INn
STATE 0
STATE 1
STATE 0
INT_EN
INT
t
t
v(INT)
v(INT)
t
t
rel(int)
rel(int)
002aaf294
Fig 15. AC waveform for INT timing
PCA9703
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18 V tolerant SPI 16-bit GPI with maskable INT
12. Test information
V
DD
open
V
R
10 kΩ
DD
L
V
V
O
I
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
10 kΩ
002aac580
Fig 16. Test circuitry for enable/disable times, SDOUT (ten(SDOUT) and tdis(SDOUT)
)
V
DD
V
V
O
I
PULSE
GENERATOR
DUT
C
50 pF
L
R
T
002aac581
Fig 17. Test circuitry for switching times, SDOUT (tv(SDOUT)
)
V
DD
V
R
10 kΩ
DD
L
V
V
O
I
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
002aac582
Fig 18. Test circuitry for switching times, INT
RL = load resistance.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse
generators.
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Product data sheet
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NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
13. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 19. Package outline SOT355-1 (TSSOP24)
PCA9703
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Product data sheet
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PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
b
C
M
M
∅ v
∅ w
C A
B
e
y
y
C
C
1
7
12
L
13
6
e
E
e
2
h
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
e
e
1
e
2
L
v
w
y
y
1
1
h
h
max
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
mm
0.8
0.2
0.5
2.5
2.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-02-07
07-03-03
SOT994-1
- - -
MO-220
Fig 20. Package outline SOT994-1 (HWQFN24)
PCA9703
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18 V tolerant SPI 16-bit GPI with maskable INT
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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18 V tolerant SPI 16-bit GPI with maskable INT
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 8.
Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
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18 V tolerant SPI 16-bit GPI with maskable INT
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 9.
Abbreviations
Description
Acronym
ASSP
CAN
CDM
DUT
ECU
ESD
GPI
Application Specific Standard Product
Controller Area Network
Charged-Device Model
Device Under Test
Electronic Control Unit
ElectroStatic Discharge
General Purpose Input
Human Body Model
HBM
HS-CAN
LIN
High-Speed Controller Area Network
Local Interconnect Network
Most Significant Bit
MSB
PCB
PPAP
RC
Printed-Circuit Board
Production Part Approval Process
Resistor-Capacitor network
System Basis Chip
SBC
SPI
Serial Peripheral Interface
microcontroller
μC
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18 V tolerant SPI 16-bit GPI with maskable INT
16. Revision history
Table 10. Revision history
Document ID
PCA9703 v.2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20120614
Product data sheet
-
PCA9703 v.1
• Section 1 “General description”, fourth paragraph, first sentence changed from “pull-up cycled
applications” to “cyclically supplied pull-up or pull-down applications”
• Section 2 “Features and benefits”, 13th bullet item: deleted phrase “350 V MM per AEC-Q100”
• Section 7 “Functional description”:
–
first paragraph, sixth sentence re-written
–
third paragraph, third sentence changed from “the pull-up should remain active” to “the pull-up
or pull-down source should remain active”
–
third paragraph, sixth sentence changed from “pull-ups can be turned off” to “pull-ups and
pull-downs can be turned off”
–
–
third paragraph, eighth sentence re-written
third paragraph: added new ninth sentence
• Section 7.3 “Interrupt enable”:
–
second sentence re-written
–
third sentence: changed from “pull-up should be active” to “pull-ups or pull-downs should be
active”
• Section 8.2.1 “SBC wake port extension with cyclic biasing”,
–
second paragraph: URL is updated
–
type number “UJA107x” is replaced with “UJA107xA” (including sub-sections that follow)
PCA9703 v.1
20100223
Product data sheet
-
-
PCA9703
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18 V tolerant SPI 16-bit GPI with maskable INT
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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18 V tolerant SPI 16-bit GPI with maskable INT
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9703
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 14 June 2012
26 of 27
PCA9703
NXP Semiconductors
18 V tolerant SPI 16-bit GPI with maskable INT
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
17.4
18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contact information . . . . . . . . . . . . . . . . . . . . 26
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
19
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 5
SPI bus operation. . . . . . . . . . . . . . . . . . . . . . . 6
CS - chip select . . . . . . . . . . . . . . . . . . . . . . . . 6
SCLK - serial clock input . . . . . . . . . . . . . . . . . 6
SDIN - serial data input. . . . . . . . . . . . . . . . . . . 6
SDOUT - serial data output . . . . . . . . . . . . . . . 6
Register access timing . . . . . . . . . . . . . . . . . . . 7
Software reset operation. . . . . . . . . . . . . . . . . . 7
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7
Interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . 8
General Purpose Inputs . . . . . . . . . . . . . . . . . . 8
VIL, VIH and switching points. . . . . . . . . . . . . . . 9
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.2
7.3
7.4
7.4.1
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.2
Application design-in information . . . . . . . . . 10
General application. . . . . . . . . . . . . . . . . . . . . 10
Automotive application . . . . . . . . . . . . . . . . . . 10
SBC wake port extension with cyclic biasing . 11
UJA106x with PCA9703, standby. . . . . . . . . . 11
UJA106x with PCA9703, sleep. . . . . . . . . . . . 12
UJA107xA with PCA9703, standby and sleep 13
Application examples including switches to
battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Static characteristics. . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 21
Introduction to soldering . . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
17.1
17.2
17.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 June 2012
Document identifier: PCA9703
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