PCB2032V [NXP]
IC 256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC, Programmable ROM;
| 型号： | PCB2032V |
| 厂家： | 
NXP |
| 描述： | IC 256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总18页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCB2032
Memory card IC
Product Specification (Rev. 1997 Feb 03)
1997 Feb 03
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
CONTENTS
1
2
3
4
5
Features
General Description
Ordering Information
Block Diagram
Memory Configuration
5.1
Transmission Protocol
Reset and Answer-to-Reset (ATR)
Command Mode - IFD to IC
Outgoing Data/Processing Mode - IC to IFD
Processing Mode
5.1.1
5.1.2
5.1.3
5.1.3.1
5.1.3.2
5.2
Outgoing Data Mode
Clock
5.3
Command format
5.4
Description of Commands
Read Main Memory
Read Protection Memory
Update/Write Commands
Update Main Memory
Write Protection Memory
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
6
RESET Modes
6.1
6.2
6.3
Reset
Answer-To-Reset
Power on Reset
7
Application INFORMATION
7.1
7.2
7.3
7.4
7.5
7.6
Memory Card ICS
Application Identifier (AID)
AP
Proprietary AIDs
ATR-file
Short ATR
8
Limiting Values
9
DC Characteristics
AC Characteristics
Definitions
10
11
12
Life support applications
Note: For mechanical information see separate documents
“Wafer Specifications for Chip Card ICs” and
“Module Specifications for Chip Card ICs”
1997 Feb 03
2
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
1
FEATURES
2
GENERAL DESCRIPTION
• Memory size of 256 x 8-bit EEPROM
• Byte-wise addressing of information
The PCB2032 contains a 256 x 8-bit EEPROM with
programmable write protection for each of the first 32
bytes. Reading of the whole memory is always possible.
The memory can be written and erased byte by byte.
• Irreversible byte-wise write protection of 32 bytes of
main memory
Each of the first 32 bytes can be write/erase protected by
setting a Protection bit (EEPROM converted to ROM). If
set once, the Protection bit cannot be erased.
• Two-wire link protocol
• Answer to RESET according to ISO 7816-3
• Programming time per byte 2.5 ms for erasing and 2.5
ms for writing
• Minimum of 104 erase/write cycles
Additionally, the PCB2032 allows for a verification
procedure. The whole memory can be read always.
• Data retention 10 years (min)
• Contact configuration and serial interface according to
ISO 7816 (synchronous transmission)
• CMOS technology
3
ORDERING INFORMATION
For details contact your local Philips Organisation.
PACKAGE
DESCRIPTION
5” wafer, unsawn; note 1
TEMPERATURE
RANGE (°C)
TYPE NUMBER
NAME
PCB2032 U
PCB2032 V
PCB2032 W
wafer
module
FFC
6- or 8-contact Modules on 35 mm film; note 2
sawn wafer on film frame carrier 6” or 7”; note 1
0 to +70
Notes
1. See “Wafer Specifications for Chip Card ICs”.
2. See “Module Specifications for Chip Card ICs”.
1997 Feb 03
3
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
4
BLOCK DIAGRAM
Fig.1 Block diagram PCB2032.
4
1997 Feb 03
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5
MEMORY CONFIGURATION
The protection bits are used to inhibit alteration of data
stored in the first 32 bytes of the Main Memory. The two
states of the Protection bits are defined as:
The IC contains 256 byte EEPROM of Main Memory,
divided into a protected and main area. The protected
Memory of 32 byte is located at the first address locations
of the main area with the remaining 224 bytes. All
protectable bytes have associated Protection Bits
(32 bit/4 byte).
HIGH = Write enabled
LOW = Write disabled
When a protection bit has been programmed to LOW a
reset of that bit to HIGH is inhibited. Thus, information
stored in the first 32 bytes of the Main Memory are
protected against any alteration.
All bytes of the two memory areas of PCB2032 can always
be read out.
255
MAIN MEMORY
AREA
32 BIT / 4 BYTE
32
31
31
MAIN MEMORY
PROTECTION
BYTEWISE FREEZABLE
BITS
BY PROTECTION BITS
0
0
MSB
LSB
MAIN MEMORY
PROTECTION BITS
Fig.2 Memory mapping.
1997 Feb 03
5
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5.1
Transmission Protocol
5.1.1
RESET AND ANSWER-TO-RESET (ATR)
The transmission protocol is a two-wire link protocol and is
identical to the protocol type S=10 for synchronous
transmission. The characteristics of synchronous
transmission are part of ISO 7816-3.
Reset of the IC complies with the synchronous parts of ISO
7816-3. The RESET can be given at any time during
operation. The first 32 clock pulses will provide the
Answer-to-Reset. (For details see Chapter 7.)
All data changes on I/O are initiated by the falling edge of
CLK.
The IC discards any START/STOP condition during ATR.
After having read the last bit an additional clock pulse is
mandatory in order to set I/O to HIGH.
Any further clock that follows now will not change the level
on I/O.
Fig.3 The activation, RESET and Answer-To-Reset phase.
1997 Feb 03
6
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5.1.2
COMMAND MODE - IFD TO IC
Between the last bit of a bit sequence transmitted from IFD
to IC and the STOP condition, an additional clock pulse is
mandatory in order to set I/O to HIGH.
Any bit sequence transmitted from the interface device
(IFD) to the IC is embedded between a START condition
and a STOP condition:
If not exactly 24 bits are transmitted from IFD, the IC
responds with processing mode.
START condition:
• falling edge on I/O during CLK is HIGH
STOP condition:
• rising edge on I/O during CLK is HIGH
Fig.4 The command phase.
5.1.3
OUTGOING DATA/PROCESSING MODE - IC TO IFD
• The IC discards any START/STOP condition during
processing mode.
After the transmission of a bit sequence from interface
device (IFD) to IC, two operational modes of the IC are to
be distinguished.
• Any further clock that follows when processing mode is
completed will not change the level on I/O.
The IC only indicates the ‘End of Processing’ to the IFD.
The IC provides no information about the result of the
‘processing’.
5.1.3.1
Processing Mode
• In this mode the IC is processing internally. No data bits
are sent.
• During processing the IC has to be clocked continuously
by the IFD. In this phase the I/O is set to LOW by the IC.
The IC signals the end of its internal processing by
setting I/O to HIGH.
1997 Feb 03
7
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5.1.3.2
Outgoing Data Mode
• The IC discards any START/STOP condition during
outgoing data mode.
• In this mode the IC sends data to the IFD.
• Any further clock that follows when outgoing data mode
is completed will not change the state on I/O.
• The first data bit becomes valid on I/O after the first
falling edge on CLK. After the last outgoing bit from the
IC, an additional clock pulse is mandatory in order to set
I/O to HIGH. This prepares the IC for a new START
condition. Note: The number of outgoing bits is known
by the IC and the IFD.
Fig.5 The Output/Processing Mode
1997 Feb 03
8
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5.2
Clock
5.3
Command format
The frequency delivered by the IFD on CLK shall be in the
range of 7 kHz to 50 kHz with a duty cycle between 40%
and 60%. When switching frequencies, no pulse shall be
shorter than 40% of the shorter period.
Each command consists of three bytes. The first byte
(Control byte) defines the command to be executed. The
second one defines the address in the EEPROM memory
and the third one contains the Data byte.
Table 1 Command format
The LSB of transmitted bytes is always send first.
CONTROL BYTE
BYTE ADDRESS
DATA BYTE
MSB
LSB MSB
LSB MSB
LSB
Table 2 Coding of commands
The control byte is coded according to the table below.
CONTROL
BYTE
BYTE
ADDRESS
MSB / LSB
DATA BYTE
COMMAND
MODE
0011.0000
0011.0001
0011.0010
0011.0011
0011.0100
0011.0101
0011.0110
0011.0111
0011.1000
0011.1001
0011.1010
0011.1011
0011.1100
0011.1101
0011.1110
0011.1111
0x00-0xFF
xx
READ MAIN MEMORY
outgoing
--
--
reserved for PCF2042
not defined
−
--
--
processing
−
--
--
reserved for PCF2042
READ PROTECTION MEMORY
not defined
xx
xx
outgoing
processing
processing
processing
processing
−
--
--
--
--
not defined
--
--
not defined
0x00-0xFF
data byte
UPDATE MAIN MEMORY
reserved for PCF2042
not defined
--
--
--
--
processing
processing
processing
processing
processing
processing
--
--
not defined
0x00-0x1F
data byte
WRITE PROTECTION MEMORY
not defined
--
--
--
--
--
--
not defined
not defined
Any faulty input condition from IFD to IC will force the following response after the stop condition:
• the IC responds with processing mode,
• the IC sets I/O to HIGH after 8 falling edges of CLK.
1997 Feb 03
9
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
5.4
Description of Commands
6
RESET MODES
Reset
5.4.1
READ MAIN MEMORY
6.1
The READ MAIN MEMORY command reads out the
content of the Main Memory starting at the given byte
address up to the end of the memory (address 255). The
read access to the Main Memory is always possible.
If RST is set to HIGH for at least 5 µs and if the IFD keeps
CLK in low state during the reset pulse, the IC aborts any
operation, sets the I/O line to HIGH and is then ready for
further operations.
5.4.2
READ PROTECTION MEMORY
6.2
Answer-To-Reset
The READ PROTECTION MEMORY command reads out
the Protection Memory starting at address 0x00 up to the
end of the memory (address 0x03). The read access to the
Protection Memory is always possible.
The Answer-to-reset is initiated according to ISO standard
7816-3. The four data bytes of the ATR are serially output
to I/O with LSB first when 32 clock pulses are applied to
CLK. The I/O is set to HIGH after an additional clock pulse
(see Fig.3 and Chapter 5).
5.4.3
UPDATE/WRITE COMMANDS
6.3
Power on Reset
The EEPROM programming is defined as:
After applying the operating voltage VCC, the I/O goes to
HIGH. Before any data can be programmed at least one of
the read commands or Answer-to-Reset must be given.
Erase: change EEPROM byte from 0xXX to 0xFF
Write: change EEPROM bits from HIGH to LOW (no
changes from LOW to HIGH)
All other data changes require a complete Erase- and
Write-cycle.
If the data byte transmitted equals the current content of
the addressed EEPROM byte, neither the Erase- nor the
Write-cycle will be executed.
The Erase-cycle as well as the Write-cycle takes 2.5 ms
each.
Before any data can be programmed at least one of the
read commands or Answer-to-Reset must be given.
5.4.4
UPDATE MAIN MEMORY
The UPDATE MAIN MEMORY command programs the
EEPROM cell addressed by ‘byte Address’ with the Data
byte transmitted.
The write attempt fails, if the addressed byte has been
protected by the appropriate Protection bit.
5.4.5
WRITE PROTECTION MEMORY
The WRITE PROTECTION MEMORY command
programs the EEPROM protection bit addressed by ‘byte
Address’, only if the Data byte transmitted equals the data
content of the EEPROM byte to be protected. If the
transmitted data byte does not match, the Protection bit
will not be set.
If the transmitted address is greater than 0x1F, the
command is ignored.
1997 Feb 03
10
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
7
APPLICATION INFORMATION
• Personalization of Memory Card ICs
Fig.6 ATR data structure.
Abbreviations used in Figure 6:
TD:
TF:
Tag of discretionary data
Tag of Filler
AID:
AP:
ATR:
DIR:
F:
Application Identifier
Application Personalizer Identifier
Answer-To-Reset
Directory
TM:
TT:
Tag manufacturer data
Tag application template
VDT:
‘Versicherten‘ data template
Filler
The following data are unalterably programmed after
final production test:
H1,H2: ATR protocol bytes
H1, H2, H3, H4, ICM, ICT
H3,H4: ATR historical bytes
ICCF: IC Card Fabricator Identifier
ICCSN: IC Card Serial Number
ICM:
ICT:
LA:
LD:
LF:
IC Manufacturer Identifier
IC Type
Length of AID
Length discretionary data
Length of Filler
LM:
LT:
Length manufacturer data
Length application template
Tag of AID
TA:
1997 Feb 03
11
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
7.1
Memory Card ICS
7.2
Application Identifier (AID)
For the memory ICs a normal Answer to Reset (ATR) of 4
x 8 bit is used. The ATR identifies the card to the terminal.
The ATR, ATR data and DIR data are programmed into
byte 0 to 31 of the EEPROM memory.
Main reason to have an application specific identifier within
every card is that ATR enables to distinguish between
different applications, which are using the same protocol,
same silicon etc.
All these bytes from address 0 up to address 31 (0x1F)
in the memory can be turned into ROM by setting the
according protection bits (see Chapter 5).
So in case the AID is not correct for the applications the
card is used for, the terminal should automatically reject
the card, so any confusion or abuse get avoided.
Once frozen these bytes can not be altered any more!
The memory card ATR looks as follows (see Fig.6):
ATR header:
The application identifier can be applied at GMD
(Gesellschaft für Mathematik und Datensysteme), who
handles the registration for all German applications with a
length up to 16 byte.
H1 .. H4
4 bytes, which refer to the ISO 7816, Part 3
standard (address 0 .. 3)
for Germany:
ID German National Registration Authority
c/o GMD, att. Mr. Bruno Struif
Rheinstrasse 75, 64295 Darmstadt, Germany
H1 =
protocol (here “0xA2” stands for 2-wire bus
protocol/general purpose structure)
H2 =
memory organization, means number of
data units and length of data units (e.g. for
2032 -> “13” stands for: 256 x 8 bit)
For the international registration of RIDs (registrated
application provider identifiers = AID) a provider should -
according to ISO 7816, part 5, chapter 7 - apply to the
standard body of his related country. So every country
should have such an organization like the GMD in
Germany, which signs responsible. In the absence of such
body or organization the secretariat of the ISO technical
body is responsible for the assignment.
H3, H4
H3 =
are the so called historical data as defined in
ISO7816, part 3
category indicator: DIR data exists Yes/No
(here “0x10” = Yes)
H4 =
address of DIR data (here “0x91”, bit 8 set to
“1” says address is valid, address = “0x11”,
so points to the first byte of the DIR file)
7.3
AP
The application personalizer identifier is optional.
The terminal reads the ATR and if H3 = 0x10, the DIR
address is read in H4 and the terminal then jumps to DIR
(H1 .. H4 must always be read!).
7.4
Proprietary AIDs
For very small applications or pilot projects not registered
AIDs can be used. Bits 5 to 8 of the first AID byte at
address “0x15” must be set to logic 1. This means, the AID
has to start with “F”, to indicate, that it is not registered.
DIR data:
The whole ATR is TLV (tag/length/value) coded. This
means there are always three entries:
Tag
indicates position of any of the entries or
identifier, all these tags are given by ISO
Major constraint with unregistered AIDs: there is no
guarantee that application IDs do not overlap!
Length
Value
gives length of the entry in number of data
units (bytes)
7.5
ATR-file
is the contents of the entry or identifier
The ATR-file is coded in the same way as the DIR-file, as
already explained above, and contains information about
the IC manufacturer, the IC-type (so for instance 0x05
stands for PCx2032, 0x15 stands for PCF2042) and the
serial number of the card.
So in the DIR file there is first of all a tag TT for the
application template followed by the length (LT), then
comes the application identifier (AID), also leaded by the
AID-tag (TA) and AID-length (LA). The last part of the DIR
file is the application personalizer ID, which also has this
structure.
1997 Feb 03
12
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
7.6
Short ATR
The ATR within the PCF2006 payphone/debit card IC is
just a so called “short ATR”. It is 16 bytes long and is stored
in the lower partition of the memory (this ATR is not
defined by ISO).
Main purpose is also to identify the card to the terminal.
The codes currently used have to be applied and are
assigned an organization called ProElectron.
The whole procedure and the contents bases on an
agreement of the main smart card IC manufacturer and
system providers.
Contents of the ATR reflects the following information:
• IC manufacturer
• IC type
• Card maker
• application code
The code is not transparent, but can be traced back.
The major target is here as well to distinguish between
different applications.
All IC maker now are members at ProElectron and are
accordingly prepared, the card manufacturers have not got
active yet. (The number itself might be given to preference,
but there is no guarantee.)
The total memory area from address 0 to 23 is write
protected and read only when delivered. PS programs the
ATR, Fab data and fab key (transport code, 24 bit) during
final test and sets all bits in card data and some of the
count data to “1”.
1997 Feb 03
13
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
-0.3
MAX.
UNIT
Supply voltage
Input voltage
+6.0
+6.0
70
V
V
VI
-0.3
Ptot
Tstg
Power dissipation
mW
Storage temperature range
-40
+125
°C
9
DC CHARACTERISTICS
According to ISO 7816-3; Tamb = 0 to +70°C
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
4.5
MAX.
5.5
UNIT
VDD
IDD
VIH
VIL
IIH
V
supply current
-
10
VDD
0.8
50
-
mA
V
input voltage HIGH (I/O, CLK, RST)
input voltage LOW (I/O, CLK, RST)
input current HIGH (I/O, CLK, RST)
output current LOW (I/O)
3.5
0
V
-
µA
mA
µA
µA
IIL
VIL = 0.4 V, note 1
VIL = VDD, note 1
IH = VDD, note 1
0.5
VLI
I
leakage current (CLK, RST)
leakage current HIGH (I/O)
-
-
±10
10
V
Note
1. Open drain output.
1997 Feb 03
14
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
10 AC CHARACTERISTICS
Tamb = 0 to +70°C
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
kHz
fCLCL
tCHCX
rCLK
External clock frequency
Clock high period
-
7
8.6
40
-
52
-
-
µs
Clock pulse ratio
at 52 kHz
60
1
1
-
%
tCLCH
tCHCL
tHD; STA
tSU; STA
tHD; DAT
tSU; DAT
tSU; STO
tRES
Clock rise time
-
-
-
-
-
-
-
-
µs
Clock fall time
-
µs
Hold time for START condition
Set-up time for START condition
Data hold time
4
µs
4
-
µs
1
-
µs
Data set-up time
1
-
µs
Set-up time for STOP condition
RESET pulse width
4
-
µs
14
2.5
2.5
10.0
10000
-
µs
tE
EEPROM erase time
EEPROM write time
EEPROM data retention time
at 51.2 kHz
-
ms
ms
yrs
cycles
tW
at 51.2 kHz
-
tR
Tamb = 55 °C
-
NE/W
EEPROM endurance
tE = 2.5 ms; tW = 2.5 ms
-
(number of erase/write cycles)
C
I/O; RESET; CLK pin capacitive
Tamb = 25 °C
-
10
pF
1997 Feb 03
15
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
11 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
12 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Feb 03
16
Philips Semiconductors
ProductSpecification
Memory card IC
PCB2032
NOTES
1997 Feb 03
17
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