PCD5003A [NXP]
Enhanced Pager Decoder for POCSAG; 增强寻呼机解码器的POCSAG
| 型号： | PCD5003A |
| 厂家： | 
NXP |
| 描述： | Enhanced Pager Decoder for POCSAG |
| 文件： | 总44页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD5003A
Enhanced Pager Decoder for
POCSAG
1999 Jan 08
Product specification
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
CONTENTS
7.43
7.44
7.45
7.46
7.47
7.48
7.49
7.50
7.51
7.52
7.53
7.54
7.55
7.56
7.57
7.58
7.59
7.60
7.61
7.62
Automatic POCSAG alerts
SRAM access
1
2
3
4
5
6
7
FEATURES
RAM write address pointer (06H; read)
RAM read address pointer (08H; read/write)
RAM data output register (09H; read)
EEPROM access
EEPROM address pointer (07H; read/write)
EEPROM data I/O register (0AH; read/write)
EEPROM access limitations
EEPROM read operation
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
EEPROM write operation
Invalid write address
7.1
Introduction
7.2
7.3
The POCSAG paging code
Error correction
Incomplete programming sequence
Unused EEPROM locations
Special programmed function allocation
Synthesizer programming data
Identifier storage allocation
Voltage doubler
7.4
Operating states
7.5
ON status
7.6
OFF status
7.7
Reset
7.8
Bit rates
Level-shifted interface
Signal test mode
7.9
Oscillator
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
7.40
7.41
7.42
Input data processing
Battery saving
Synchronization strategy
Call termination
Enhanced call termination
Call data output format
Sync word indication
Error type indication
Data transfer
Receiver and oscillator control
External receiver control and monitoring
Demodulator quick charge
Battery condition input
Synthesizer control
Serial microcontroller interface
Decoder I2C-bus access
External interrupt
Interrupt Masking
Status/control register
Pending interrupts
Out-of-range Indication
Real-time clock
Periodic interrupt
Received call delay
Alert generation
Alert cadence register (03H; write)
Acoustic alert
Vibrator alert
LED alert
Warbled alert
Direct alert control
Alert priority
8
OPERATING INSTRUCTIONS
8.1
8.2
8.3
8.4
Reset conditions
Power-on reset circuit
Reset timing
Initial programming
9
LIMITING VALUES
10
11
DC CHARACTERISTICS
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
12
OSCILLATOR CHARACTERISTICS
EEPROM CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
13
14
15
16
17
SOLDERING
17.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
17.2
17.3
17.4
17.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
18
19
20
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
Cancelling alerts
1999 Jan 08
2
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
1
FEATURES
• Wide operating supply voltage range: 1.5 to 6.0 V
• EEPROM programming requires only 2.0 V supply
• Low operating current: 50 µA typ. (ON),
25 µA typ. (OFF)
• Slave I2C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
• Temperature range: −25 to +70 °C
• “CCIR Radio paging Code No. 1” (POCSAG)
programming (data transfer at up to 400 kbits/s)
compatible
• Wake-up interrupt for microcontroller, programmable
• 512, 1200 and 2400 bits/s data rates using 76.8 kHz
polarity
crystal
• Direct and I2C-bus control of operating status (ON/OFF)
• Battery-low indication (external detector)
• Out-of-range condition indication
• Built-in data filter (16-times oversampling) and bit clock
recovery
• Advanced ACCESS synchronization algorithm
• 2-bit random and (optional) 4-bit burst error correction
• Real-time clock reference output
• Up to 6 user addresses Receiver Identity Codes (RICs),
each with 4 functions/alert cadences
• On-chip voltage doubler
• Interfaces directly to UAA2080 and UAA2082 paging
receivers.
• Up to 6 user address frames, independently
programmable
• Optional automatic call termination when bit error rate is
high
2
APPLICATIONS
• Display pagers, basic alert-only pagers
• Information services
• Standard POCSAG sync word, plus up to 4 user
programmable sync words
• Personal organizers
• Received data inversion (optional)
• Telepoint
• Call alert via beeper, vibrator or LED
• Telemetry/data transmission.
• 2-level acoustic alert using single external transistor
• Alert control: automatic (POCSAG type), via cadence
register or alert input pin
3
GENERAL DESCRIPTION
• Separate power control of receiver and RF-oscillator for
battery economy
The PCD5003A is a very low power POCSAG decoder
and pager controller. It supports data rates of 512,
1200 and 2400 bits/s using a single 76.8 kHz crystal.
On-chip EEPROM is programmable using a minimum
supply voltage of 2.0 V, allowing ‘over-the-air’
programming. The PCD5003A is fast I2C-bus compatible
(maximum 400 kbits/s).
• Dedicated pin for easy control of superheterodyne
receiver
• Synthesizer set-up and control interface (3-line serial)
• On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
• On-chip SRAM buffer for message data
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
PCD5003AH
LQFP32
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
1999 Jan 08
3
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
5
BLOCK DIAGRAM
7
EEPROM
RESET
SET-UP
RST
26
ZSD
ZSC
ZLE
27
28
SYNTHESIZER
CONTROL
9
EEPROM CONTROL
2
SDA
I C-BUS
10
CONTROL
SCL
24
25
22
DECODING
DATA
CONTROL
RXE
ROE
DQC
RECEIVER
CONTROL
POCSAG
SYNCHRONIZATION
5
INT
REGISTERS
AND
INTERRUPT
CONTROL
RAM
CONTROL
21
DATA FILTER
AND
BAT
23
3
MAIN DECODER
RDI
CLOCK
30
31
1
RECOVERY
VIB
RAM
LED
ATL
ATH
ALC
ALERT
GENERATION
AND
CLOCK
CONTROL
MASTER
DIVIDER
TIMER
REFERENCE
DON
32
2
CONTROL
16
20
4
TS1
TS2
REF
TEST
CONTROL
15
14
13
8
CCN
CCP
VOLTAGE
DOUBLER
AND LEVEL
SHIFTER
18
17
PCD5003A
XTAL1
XTAL2
OSCILLATOR
V
PO
V
PR
6, 19
n.c.
11
12, 29
MGL568
V
V
SS
DD
Fig.1 Block diagram.
1999 Jan 08
4
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
6
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
alert LOW-level output
TS1
16 test input 1 (normally LOW by internal
pull-down)
ATL
1
2
ALC
alert control input (normally LOW by
internal pull-down)
XTAL2
XTAL1
n.c.
17 decoder crystal oscillator output
18 decoder crystal oscillator input
19 not connected
DON
REF
3
4
direct ON/OFF input (normally LOW by
internal pull-down)
real-time clock frequency reference
output
TS2
20 test input 2 (normally LOW by internal
pull-down)
INT
n.c.
RST
5
6
7
interrupt output
not connected
BAT
DQC
RDI
21 battery sense input
22 demodulator quick charge output
23 received POCSAG data input
24 receiver circuit enable output
25 receiver oscillator enable output
26 synthesizer serial data output
27 synthesizer serial clock output
28 synthesizer latch enable output
29 main negative supply voltage
30 vibrator motor drive output
31 LED drive output
reset input (normally LOW by internal
pull-down)
RXE
ROE
ZSD
ZSC
ZLE
VSS
VPR
8
external positive voltage reference
input
I2C-bus serial data input/output
SDA
SCL
VDD
VSS
9
10 I2C-bus serial clock input
11 main positive supply voltage
12 main negative supply voltage
13 voltage converter positive output
VIB
VPO
CCP
LED
ATH
14 voltage converter shunt capacitor
(positive side)
32 alert HIGH-level output
CCN
15 voltage converter shunt capacitor
(negative side)
ATL
ALC
DON
REF
INT
1
2
3
4
5
6
7
8
RXE
24
23 RDI
22 DQC
21 BAT
20 TS2
PCD5003AH
n.c.
19 n.c.
RST
18 XTAL1
17 XTAL2
V
PR
MGL569
Fig.2 Pin configuration.
5
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
between the devices. Pager status includes features
7
FUNCTIONAL DESCRIPTION
Introduction
provided by the PCD5003A such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
7.1
The PCD5003A is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5003A allows for
flexible application in a wide variety of radio pager designs.
A selectable low frequency timing reference is provided for
use in real-time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption.
The PCD5003A is fully compatible with “CCIR Radio
paging Code No. 1” (also known as the POCSAG code)
operating at data rates of 512, 1200 and 2400 bits/s using
a single oscillator crystal of 76.8 kHz.
In addition to the standard POCSAG sync word the
PCD5003A is also capable of recognizing up to 4 User
Programmable Sync Words (UPSWs). This permits the
reception of both private services and POCSAG
transmissions via the same radio channel.
Random and (optional) burst error correction techniques
are applied to the received data to optimize on call success
rate without increasing falsing rate beyond specified
POCSAG levels.
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5003A offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
7.2
The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Programmed Functions (SPFs), which eliminates the need
for external storage devices and interconnection. For other
non-volatile storage 20 bytes of general purpose
EEPROM are available. The low EEPROM programming
voltage makes the PCD5003A well suited for ‘over-the-air’
programming/reprogramming.
Each batch comprises 17 code-words of 32 bits each.
The first code-word is a synchronization code-word with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 code-words each, containing message
information. A code-word in a frame can either be an
address, message or idle code-word.
On request from an external controlling device or
automatically (by SPF programming), the PCD5003A will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
Idle code-words also have a fixed pattern and are used to
fill empty frames or to separate messages.
Address code-words are identified by an MSB of logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address code-word (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
The PCD5003A can also produce a HIGH-level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
The PCD5003A contains a low-power, high-efficiency
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5003A.
Four different call types (‘numeric’, ‘alphanumeric’ and
two ‘alert only’ types) can be distinguished on each user
address. The call type is determined by two function bits in
the address code-word (bits 20 and 21), as shown in
Table 1.
Interface to such an external device is provided by an
I2C-bus which allows received call identity and message
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
1999 Jan 08
6
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Alert-only calls only consist of a single address code-word.
Numeric and alphanumeric calls have message
code-words following the address. A message causes the
frame structure to be temporarily suspended. Message
code-words are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
The POCSAG standard recommends the use of
combinations of data formats and function bits, as given in
Table 1. Other (non-standard) combinations will be
received normally by the PCD5003A. Message data is not
deformatted.
In the PCD5003A error correction methods have been
implemented as shown in Table 2.
Message code-words are identified by an MSB of logic 1
and are coded as shown in Fig.3. The message
information is stored in a 20-bit field (bits 2 to 21). The data
format is determined by the call type: 4 bits per digit for
numeric messages and 7 bits per (ASCII) character for
alphanumeric messages.
Random error correction is default for both address and
message code-words. In addition, burst error correction
can be enabled by SPF programming. Up to 3 erroneous
bits in a 4-bit burst can be corrected.
The error type detected for each code-word is identified in
the message data output to the microcontroller, allowing
rejection of calls with too many errors.
Each code-word is protected against transmission errors
by 10 CRC check bits (bits 22 to 31) and an even-parity bit
(bit 32). This permits correction of maximum 2 random
errors or up to 3 errors in a burst of 4 bits (a 4-bit burst
error) per code-word.
PREAMBLE
BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0
FRAME 1
FRAME 7
Address code-word
Message code-word
0
1
18-bit address
20-bit message
2 function bits
10 CRC bits
P
P
10 CRC bits
MCD456
Fig.3 POCSAG code structure.
1999 Jan 08
7
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 1 POCSAG recommended call types and function bits
BIT 20 (MSB)
BIT 21 (LSB)
CALL TYPE
DATA FORMAT
0
0
1
1
0
1
0
1
numeric
alert only 1
alert only 2
alphanumeric
4-bits per digit
−
−
7-bits per ASCII character
7.3
Error correction
Table 2 Error correction
ITEM
DESCRIPTION
Preamble
4 random errors in 31 bits
2 random errors in 32 bits
Synchronization code-word
Address code-word
2 random errors; plus 4-bit burst errors (optional)
2 random errors; plus 4-bit burst errors (optional)
Message code-word
7.4
Operating states
7.6
OFF status
The PCD5003A has 2 operating states:
• ON status
In OFF status the decoder will neither activate the receiver
or oscillator enable outputs, nor process any data at the
data input. The crystal oscillator remains active to permit
communication with the microcontroller.
• OFF status.
The operating state is determined by a Direct Control input
(DON) and bit D4 in the control register (see Table 3).
In both operating states an accurate timing reference is
available via the REF output. By SPF programming the
signal periodicity may be selected as 32.768 kHz, 50 Hz,
2 Hz or 1⁄60 Hz.
Table 3 Truth table for decoder operating status
CONTROL
BIT D4
OPERATING
STATUS
DON INPUT
7.7
Reset
The decoder can be reset by applying a positive pulse on
input pin RST. A power-on reset circuit consisting of an
RC network can be connected to this input as well.
Conditions during and after a reset are described in
Chapter “Operating instructions”.
0
0
1
1
0
1
0
1
OFF
ON
ON
ON
For successful reset at power-on, a HIGH level must be
present on the RST pin while the device is powering-up.
This can be applied by the microcontroller, or via a suitable
RC power-on reset circuit connected to the RST input.
Reset circuit details and conditions during and after a reset
are described in Chapter 8.
7.5
ON status
In ON status the decoder pulses the receiver and oscillator
enable outputs (respectively RXE and ROE) according to
the code structure and the synchronization algorithm. Data
received serially at the data input (RDI) is processed for
call receipt. Reception of a valid paging call is signalled to
the microcontroller by means of an interrupt signal.
The received address and message data can then be read
via the I2C-bus interface.
1999 Jan 08
8
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
This is possible with the UAA2082 receiver which has
external biasing for the oscillator circuit.
7.8
Bit rates
The PCD5003A can be configured for data rates of 512,
1200 or 2400 bits/s by SPF programming. These data
rates are derived from a single 76.8 kHz oscillator
frequency.
7.12 Synchronization strategy
In ON status the PCD5003A synchronizes to the POCSAG
data stream by means of the Philips ACCESS algorithm.
A flow diagram is shown in Fig.4. Where ‘sync word’ is
used, this implies both the standard POCSAG sync word
and any enabled User Programmable Sync Word
(UPSW).
7.9
Oscillator
The oscillator circuit is designed to operate at 76.8 kHz.
Typically, a tuning fork crystal will be used as a frequency
source. Alternatively, an external clock signal can be
applied to pin XTAL1 (amplitude = VDD to VSS), but a
slightly higher oscillator current is consumed. A 2.2 MΩ
feedback resistor connected between XTAL1 and XTAL2
is required for proper operation.
Several modes of operation can be distinguished
depending on the synchronization state. Each mode uses
a different method to obtain or retain data synchronization.
The receiver and oscillator enable outputs (respectively
RXE and ROE) are switched accordingly, with the
appropriate establishment times (respectively tRXON and
tROON).
To allow easy oscillator adjustment (e.g. by means of a
variable capacitor) a 32.768 kHz reference frequency can
be selected at output REF by SPF programming.
Before comparing received data with preamble, an
enabled sync word or programmed user addresses, the
appropriate error correction is applied.
7.10 Input data processing
Data input is binary and fully asynchronous. Input bit rates
of 512, 1200 and 2400 bits/s are supported. As a
programmable option, the polarity of the received data can
be inverted before further processing.
Initially, after switching to ON status, the decoder is in
switch-on mode. Here the receiver will be enabled for a
period up to 3 batches, testing for preamble and sync
word. Failure to detect preamble or sync word will cause
switching to ‘carrier off’ mode.
The input data is noise filtered by means of a digital filter.
Data is sampled at 16 times the data rate and averaged by
majority decision.
Detection of preamble switches to preamble receive
mode, in which sync word is looked for. The receiver will
remain enabled while preamble is detected. When neither
sync word nor preamble is found within 1 batch duration
‘carrier off’ mode is entered.
The filtered data is used to synchronize an internal clock
generator by monitoring transitions. The recovered clock
phase can be adjusted in steps of 1⁄8 or 1⁄32 bit period per
received bit.
Upon detection of a sync word the data receive mode is
entered. The receiver is activated only during enabled user
address frames and sync word periods. When an enabled
user address has been detected, the receiver will be kept
enabled for message code-word reception until the call
termination criteria are met.
The larger step size is used when bit synchronization has
not been achieved, the smaller when a valid data
sequence has been detected (e.g. preamble or sync
word).
7.11 Battery saving
During call reception data bytes are stored in an internal
SRAM buffer, capable of storing 2 batches of message
data.
Current consumption is reduced by switching off internal
decoder sections whenever the receiver is not enabled.
To further increase battery efficiency, reception and
decoding of an address code-word is stopped as soon as
the uncorrected address field differs by more than 3 bits
from the enabled RICs. If the next code-word must be
received again, the receiver is re-enabled thus observing
Messages are transmitted contiguously, only interrupted
by sync words at the beginning of each batch. When a
message extends beyond the end of a batch, no testing for
sync takes place. Instead, a message data transfer will be
initiated by an interrupt to the external controller. Data
reception continues normally after a period corresponding
to the sync word duration.
the programmed establishment times tRXE and tRDE
.
The current consumption of the complete pager can be
minimized by separately activating the RF oscillator circuit
(at output ROE) before activating the rest of the receiver.
1999 Jan 08
9
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
If any message code-word is found to be uncorrectable,
‘data-fail’ mode is entered and no data transfer will be
attempted at the next sync word position. Instead, a test for
sync word will be carried out.
The type of error correction as well as the call termination
conditions are indicated by status bits in the message data
output.
In the event of the terminating code-word matching an
enabled RIC, a concatenated call will be started with the
call header replacing the terminator of the previous call.
In the data fail mode message reception continues
normally for 1 batch duration. Upon detection of sync word
at the expected position the decoder returns to
‘data receive’ mode. If sync word again fails to appear,
batch synchronization is deemed lost. Call reception is
then terminated and ‘fade recovery’ mode is entered.
Following call termination, transfer of the data received
since the previous sync word period is initiated by means
of an interrupt to the external controller.
The fade recovery mode is intended to scan for sync word
and preamble over an extended window (nominal
position ±8 bits).
7.14 Enhanced call termination
The PCD5003A provides an enhanced mode of call
termination which is enabled by setting SPF byte 3, bit D7.
When enabled, the following call termination conditions
apply, in addition to those listed in Section 7.15.
This is done for a period of up to 15 batches, allowing
recovery of synchronization from long fades in the radio
signal. Detection of preamble switches to
‘preamble receive’ mode, while sync word detection
switches to ‘data receive’ mode. When neither is found
within a period of 15 batches, the radio signal is
considered lost and ‘carrier off’ mode is entered.
• Reception of two consecutive code-words (excluding
sync word), each of which are either uncorrectable or an
address code-word with more than one bit in error.
7.15 Call data output format
The purpose of carrier off mode is to detect a valid radio
transmission and synchronize to it quickly and efficiently.
Because transmissions may start at random, the decoder
enables the receiver for 1 code-word in every
18 code-words looking for preamble or sync word.
By using a buffer containing 32 bits (n bits from the current
scan, 32 − n from the previous scan) effectively every
batch bit position can be tested within a continuous
transmission of at least 18 batches. Detection of preamble
switches to ‘preamble receive’ mode, while sync word
detection switches to ‘data receive’ mode.
POCSAG call information is stored in the decoder SRAM
in blocks of 3 bytes per code-word. Each stored call
consists of a call header, followed by message data blocks
and concluded by a call terminator. In the event of
concatenated messages the call terminator is replaced
with the call header of the next message. An alert-only call
only has a call header and a call terminator.
The formats of a call header, a message data block and a
call terminator are shown in Tables 4, 6 and 8.
A Call Header contains information on the last sync word
received, the RIC which began call reception and the type
of error correction performed on the address code-word.
7.13 Call termination
Call reception is terminated:
A Message Data block contains the data bits from a
message code-word plus the type of error correction
performed. No deformatting is done on the data bits:
numeric data appear as 4-bit groups per digit,
• Upon reception of any address code-word (including idle
code-word) requiring no more than single bit error
correction
alphanumeric data have a 7-bit ASCII representation.
• Upon reception of a correctable address code-word
(error type other than ‘111’; see Table 10) that matches
an enabled RIC
The Call Terminator contains information on the last sync
word received, information on the way the call was
terminated (forced call termination command, loss of sync
word in ‘data fail’ mode) and the type of error correction
performed on the terminating code-word.
• When a forced call termination command is received
from an external controller.
• In ‘data fail’ mode, when a sync word is not found at the
expected batch position.
The last method permits an external controller to stop call
reception depending on the number and type of errors
which occurred in a call. After a forced call termination the
decoder will enter ‘data fail’ mode.
1999 Jan 08
10
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.16 Sync word indication
7.18 Data transfer
The sync word recognized by the PCD5003A is shown in
the call header (bits S3 to S1). The decimal value
represents the identifier number in the EEPROM of the
UPSW in question. A value of 7 indicates the standard
POCSAG sync word.
Data transfer is initiated either during sync word periods or
as soon as the receiver is disabled after call termination.
If the SRAM buffer is full, data transfer is initiated
immediately during the next code-word.
When the PCD5003A is ready to transfer received call
data an external interrupt will be generated via output INT.
Any message data can be read by accessing the RAM
output register via the I2C-bus interface. Bytes will be
output starting from the position indicated by the RAM read
pointer.
7.17 Error type indication
Table 10 shows how the different types of detected errors
are encoded in the call data output format.
A message code-word containing more than a single bit
error (bit E3 = 1) may appear as an address code-word
(bit M1 = 0) after error correction. In this event the
code-word is processed as message data and does not
cause call termination.
OFF to ON status
no preamble or
sync word
switch-on
(3 batches)
sync word
preamble
no preamble or
sync word
preamble receive
(1 batch)
sync word
data receive
data fail
sync word
no sync word
preamble
preamble
preamble
no preamble or
sync word
(1 batch)
sync word
sync word
fade recovery
no preamble or
sync word
(15 batches)
carrier off
MLC247
Fig.4 ACCESS synchronization algorithm.
11
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 4 Call header format
BIT 7
(MSB)
BIT 0
BIT 1
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
(LSB)
1
2
3
0
0
X
S3
S3
X
S2
S2
F0
S1
S1
F1
R3
R3
E3
R2
R2
E2
R1
R1
E1
DF
0
0
Table 5 Call header bit identification
BITS (MSB TO LSB)
IDENTIFICATION
S3 to S1
R3 to R1
DF
identifier number of sync word for current batch (7 = standard POCSAG)
identifier number of user address (RIC)
data fail mode indication (1 = data fail mode); note 1
F0 and F1
E3 to E1
function bits of received address code-word (bits 20 and 21)
detected error type; see Table 10; E3 = 0 in a concatenated call header
Note
1. The DF bit in the call header is set:
a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard
POCSAG or a user-programmed sync word. The sync word identifier (bits S3 to S1) will then be made 0.
b) When any code-word of a previous call received in the same batch was uncorrectable.
Table 6 Message data format
BIT 7
(MSB)
BIT 0
(LSB)
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
M2
M3
M11
M19
M4
M5
M6
M14
E3
M7
M15
E2
M8
M16
E1
M9
M17
M1
M10
M18
M12
M20
M13
M21
Table 7 Message data bit identification
BITS (MSB TO LSB)
IDENTIFICATION
M2 to M21
E3 to E1
M1
message code-word data bits
detected error type; see Table 10
message code-word flag
Table 8 Call terminator format
BIT 7
BYTE NUMBER
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
FT
FT
X
S3
S3
X
S2
S2
X
S1
S1
X
0
0
0
0
0
0
DF
X
E3
E2
E1
0
1999 Jan 08
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Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 9 Call terminator bit identification
BITS (MSB TO LSB)
IDENTIFICATION
FT
forced call termination (1 = yes)
S3 to S1
DF
identifier number of last sync word
data fail mode indication (1 = data fail mode); note 1
detected error type; see Table 10; E3 = 0 in a call terminator
E3 to E1
Note
1. The DF bit in the call terminator is set:
a) When any call data code-word in the terminating batch was uncorrectable, while in ‘data receive’ mode.
b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a
user-programmed sync word, while in ‘data fail’ mode.
Table 10 Error type identification (note 1)
E3
E2
E1
ERROR TYPE
NUMBER OF ERRORS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no errors; correct code-word
parity bit in error
0
1
single bit error
1 + parity
1
single bit error and parity error
not used
4-bit burst error and parity error
2-bit random error
3 (e.g. 1101)
2
uncorrectable code-word
3 or more
Note
1. POCSAG code allows a maximum of three bit errors to be detected per code-word.
Call termination can occur on reception of an address
code-word (or even a message code-word if in enhanced
call termination mode) or when a sync word is not detected
while in the ‘data fail’ mode.
7.20 External receiver control and monitoring
An external controller may enable the receiver control
outputs continuously via an I2C-bus command, overruling
the normal enable pattern. Data reception continues
normally. This mode can be left by means of a reset or an
I2C-bus command.
7.19 Receiver and oscillator control
A paging receiver and an RF oscillator circuit can be
controlled independently via enable outputs RXE and ROE
respectively. Their operating periods are optimized
according to the synchronization mode of the decoder.
Each enable signal has its own programmable
establishment time (see Table 11).
External monitoring of the receiver control output RXE is
possible via bit D6 in the status register, when enabled via
the control register (D2 = 1). Each change of state of
output RXE will generate an external interrupt at output
INT.
1999 Jan 08
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Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
The timing of DQC is as follows: (see Fig.5).
7.21 Demodulator quick charge
• Mode 0: Set along with RXE output (time tRXE before the
first code-word is expected); cleared during the second
Two modes of operation are available that determine the
periods when the DQC is set.
bit of the code-word following tRXE
.
The operating mode is selected by EEPROM
programming of SPF byte 3, bit D5:
• Mode 1: Set during the second bit of the sync word;
cleared after the last bit of the sync word.
• Mode 0 (D5 = 0): DQC is active (logic HIGH) during the
receiver establishment time tRXE in all ACCESS modes
except data receive and data fail. During switch-on,
DQC is active for 1 code-word duration.
Note: During switch-on, tRXE is not used: RXE and DQC
are switched on immediately.
• Mode 1 (D5 = 1): DQC is active during sync word
detection in all ACCESS modes. During switch-on and
preamble receive modes, DQC is active continuously.
Data into RDI
RXE
code-word
code-word
code-word
t
RXE
Mode 0 DQC
Mode 1 DQC
MGL566
Fig.5 Example of DQC timing.
When using the UAA2080 pager receiver a battery-low
condition corresponds to a logic HIGH-level. With a
different sense circuit the reverse polarity can be used as
well, because every change of state is signalled to an
external controller.
7.22 Battery condition input
A logic signal from an external sense circuit signalling
battery condition can be applied to the BAT input. This
input is sampled each time the receiver is disabled
(RXE ↓ 0).
After a reset the initial condition of the battery-low indicator
in the status register is zero.
When enabled via the control register (D2 = 0), the
condition of input BAT is reflected in bit D6 of the status
register. Each change of state of bit D6 causes an external
interrupt at output INT.
1999 Jan 08
14
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 11 Receiver and oscillator establishment times
Table 12 Synthesizer programming pause
(note 1)
BIT RATE (bit/s)
tp (CLOCKS)
tp (µs)
CONTROL
OUTPUT
512
119
33
1
1549
430
13
ESTABLISHMENT TIME
UNIT
1200
2400
RXE
ROE
5
10
30
15
40
30
50
ms
ms
20
7.24 Serial microcontroller interface
Note
The PCD5003A has an I2C-bus serial microcontroller
interface capable of operating at 400 kbits/s.
The PCD5003A is a slave transceiver with a 7-bit I2C-bus
address 39 (bits A6 to A0 = 0100111). Together with the
R/W bit the first byte of an I2C-bus message then becomes
4EH (write) or 4FH (read).
1. The exact values may differ slightly from the above
values, depending on the bit rate (see Table 22).
7.23 Synthesizer control
Control of an external frequency synthesizer is possible
via a dedicated 3-line serial interface (outputs ZSD,
ZSC and ZLE). This interface is common to a number of
available synthesizers. The synthesizer is enabled using
the oscillator enable output ROE.
Data transmission requires 2 lines: SDA (serial data) and
SCL (serial clock), each with an external pull-up resistor.
The clock signal (SCL) for any data transmission must be
generated by the external controlling device.
The frequency parameters must be programmed in
EEPROM. Two blocks of maximum 24 bits each can be
stored. Any unused bits must be programmed at the
beginning of a block: only the last bits are used by the
synthesizer.
A transmission is initiated by a START condition
(S: SCL = 1, SDA = ↓) and terminated by a STOP
condition (P: SCL = 1, SDA = ↑).
Data bits must be stable when SCL is HIGH. If there are
multiple transmissions, the STOP condition can be
replaced with a new START condition.
When the function is selected by SPF programming
(SPF byte 01, bit D6), data is transferred to the
synthesizer each time the PCD5003A is switched from
OFF to ON status. Transfer takes place serially in two
blocks, starting with bit 0 (MSB) of block 1 (see Table 25).
Data is transferred on a byte basis, starting with a device
address and a read/write indicator. Each transmitted byte
must be followed by an acknowledge bit ACK
(active LOW). If a receiving device is not ready to accept
the next complete byte, it can force a bus wait state by
holding SCL LOW.
Data bits on ZSD change on the falling flanks of ZSC. After
clocking all bits into the synthesizer, a latch enable pulse
copies the data to the internal divider registers. A timing
diagram is given in Fig.6.
The general I2C-bus transmission format is shown in Fig.7.
Formats for master/slave communication are shown in
Fig.8.
The data output timing is synchronous, but has a pause in
the bit stream of each block. This pause occurs in the
13th bit while ZSC is LOW. The nominal pause duration tp
depends on the programmed bit rate for data reception
and is shown in Table 12. The total duration of the 13th bit
is given by tZCL + tp.
A similar pause occurs between the first and the second
data block. The delay between the first latch enable pulse
and the second data block is given by tZDL2 + tp.
The complete start-up timing of the synthesizer interface is
given in Fig.13.
1999 Jan 08
15
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
t
ZSD
MSB
LSB
23
0
12
ZSD
ZSC
ZLE
TIME
TIME
t
t
ZDL1
p
t
t
ZDS
ZCL
t
MLC248
ZLE
Fig.6 Synthesizer interface timing.
SDA
MSB
LSB
N
A
MSB
LSB
N
A
S
P
INTERRUPT
SERVICING
SCL
1
2
7
8
9
1
2
7
8
9
START
ADDRESS
R/W
A
DATA
A
STOP
MLC249
Fig.7 I2C-bus message format.
16
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
A = Acknowledge
FROM
FROM
SLAVE
S = START condition
P = STOP condition
MASTER
N = Not acknowledge
(a)
S
S
SLAVE ADDRESS
SLAVE ADDRESS
R/W
A
INDEX
A
DATA
A
DATA
A
P
index
address
0
1
(write)
n bytes with acknowledge
(b)
R/W
A
DATA
A
DATA
N
P
(read)
n bytes with acknowledge
(c)
S
SL. ADR. R/W
A
INDEX
A
DATA
A
S
SL. ADR. R/W
A
DATA
N
P
index
address
1
(read)
0
(write)
n bytes with
acknowledge
n bytes with
acknowledge
change of direction
MLC250
(a) Master writes to slave.
(b) Master reads from slave.
(c) Combined format (shown: write plus read).
Fig.8 Message types.
7.25 Decoder I2C-bus access
Data written to read-only bits will be ignored. Values read
from write-only bits are undefined and must be ignored.
All internal access to the PCD5003A takes place via the
I2C-bus interface. For this purpose the internal registers,
SRAM and EEPROM have been memory mapped and are
accessed via an index register. Table 13 shows the index
addresses of all internal blocks.
Each I2C-bus write message to the PCD5003A must start
with its slave address, followed by the index address of the
memory element to be accessed. An I2C-bus read
message uses the last written index address as a data
source. The different I2C-bus message types are shown in
Fig.8.
Registers are addressed directly, while RAM and
EEPROM are addressed indirectly via address pointers
and I/O registers.
As a slave the PCD5003A cannot initiate bus transfers by
itself. To prevent an external controller from having to
monitor the operating status of the decoder, all important
events generate an external interrupt on output INT.
Remark: The EEPROM memory map is non-contiguous
and organized as a matrix. The EEPROM address pointer
contains both row and column indicators.
1999 Jan 08
17
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 13 Index register
ADDRESS(1)
REGISTER FUNCTION
ACCESS
00H
00H
status
R
W
control
01H
real-time clock: seconds
real-time clock: 1⁄100 second
alert cadence
R/W
R/W
W
02H
03H
04H
alert set-up
W
05H
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
W
05H
R
06H
R
07H
R/W
R/W
R
08H
09H
0AH
EEPROM data input/output
unused
R/W
note 2
0BH to 0FH
Notes
1. The index register only uses the least significant nibble, the upper 4 bits are ignored.
2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.
The interrupt output INT is reset after completion of a
status read operation.
7.26 External interrupt
The PCD5003A can signal events to an external controller
via an interrupt signal on output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
7.27 Interrupt Masking
In the PCD5003A certain interrupts can be suppressed by
masking via the control register. This feature prevents
unnecessary wake-up actions of the microcontroller
causing battery life reduction.
Interrupts are generated by the following events (more
than one event possible):
• Call data available for output (bit D2)
• SRAM pointers becoming equal (bit D3)
• Expiry of periodic time-out (bit D7)
The following interrupts can be masked:
• Out-of-Range (status bit D5): change of state
interrupt, masked by setting control register bit D5
• Expiry of alert time-out (bit D4)
• BAT/RXE monitoring (status bit D6): change of state
interrupt (source selected by control register bit D2),
masked by setting control register bit D6
• Change of state in out-of-range indicator (bit D5)
• Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
• Periodic Timer (status bit D7): timer overflow interrupt,
masked by setting control register bit D7.
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
Although no interrupts are generated by these conditions
when masked via the control register, the corresponding
status bits are normally updated and available via the
status register. At reset the control register is cleared,
causing all interrupts to be enabled.
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position, if data fail mode (short fade recovery
mode in APOC1) is not active.
1999 Jan 08
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Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
All status bits will be reset after a status read operation
except for the out-of-range, battery-low and receiver
enable indicator bits (see note 1 to Table 14).
7.28 Status/control register
The status/control register consists of two independent
registers, one for reading (status) and one for writing
(control).
Status bit D0 is set when call reception is started by
detection of an enabled RIC (user address). This does not
generate an interrupt.
The status register shows the current operating condition
of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain
functions. Tables 14 and 15 show the bit allocations of
both registers.
Table 14 Status register (00H; read)
BIT(1)
VALUE
DESCRIPTION
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
no new call data
new call received
D1 and D0
reserved for future use
reserved for future use
no data to be read (default after reset)
RAM read/write pointers different: data to be read
RAM read/write pointers equal: no more data to read
RAM buffer full or overflow
D3 and D2
D4
D5
D6
D7
alert time-out expired
1
out-of-range
1
BAT input HIGH or RXE output active (selected by control bit D2)
periodic timer interrupt
1
Note
1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is
pending. D2 is reset when the RAM is empty (read and write pointers equal).
Table 15 Control register (00H; write)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
1
1
0
1
1
0
1
1
1
1
forced call termination (automatically reset after termination)
EEPROM programming enable
BAT input selected for monitoring (status bit D6)
RXE output selected for monitoring (status bit D6)
receiver continuously enabled (RXE = 1, ROE = 1)
decoder in OFF status (while DON = 0)
decoder in ON status
D2
D3
D4
D5
D6
D7
out-of-range interrupt masked
BAT/RXE monitor interrupt masked
periodic timer interrupt masked
1999 Jan 08
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Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.29 Pending interrupts
Table 16 Real-time clock; seconds register (01H;
read/write)
A secondary status register is used for storing status bits
of pending interrupts. This occurs:
BIT
VALUE
DESCRIPTION
(MSB: D7)
• When a new call is received while the previous one was
not yet acknowledged by reading the status register
D0
D1
D2
D3
D4
D5
D6
−
−
−
−
−
−
X
1 s
2 s
• When an interrupt occurs during a status read operation.
4 s
After completion of the status read the primary register is
loaded with the contents of the secondary register, which
is then reset. Next, an immediate interrupt is generated,
output INT becoming active 1 decoder clock cycle after it
was reset following the status read.
8 s
16 s
32 s
not used: ignored when written;
undetermined when read
Remark: In the event of multiple pending calls, only the
status bits of the last call are retained.
D7
X
not used: ignored when written;
undetermined when read
7.30 Out-of-range Indication
The out-of-range condition occurs when entering fade
recovery or ‘carrier off’ mode. This condition is reflected in
bit D5 of the status register. The out-of-range condition is
reset when either preamble or a valid sync word is
detected.
Table 17 Real-time clock; 1⁄100 second register (02H;
read/write)
BIT
(MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
−
−
−
−
−
−
−
X
0.01 s
0.02 s
0.04 s
0.08 s
0.16 s
0.32 s
0.64 s
The out-of-range bit (D5) in the status register is updated
each time the receiver is disabled (RXE ↓ 0). Every
change of state in bit D5 generates an interrupt.
7.31 Real-time clock
The PCD5003A provides a periodic reference pulse at
output REF. The frequency of this signal can be selected
by SPF programming:
not used: ignored when written;
undetermined when read
• 32768 Hz
• 50 Hz (square-wave)
• 2 Hz
7.32 Periodic interrupt
1
•
⁄60 Hz.
A periodic interrupt can be realised with the periodic
The 32768 Hz signal does not have a fixed period:
it consists of 32 pulses distributed over 75 main oscillator
cycles at 76.8 kHz. The timing is shown in Fig.15.
interrupt counter. This 8-bit counter is incremented every
1
⁄
100 second and produces an interrupt when it reaches the
value stored in the periodic interrupt modulus register.
The counter register is then reset and counting continues.
When programmed for 1⁄60 Hz (1 pulse per minute) the
pulse at output REF is held off while the receiver is
enabled.
Operation is started by writing a non-zero value to the
modulus register. Writing a zero will stop interrupt
generation immediately and will halt the periodic interrupt
counter after 2.55 seconds.
Except for the 50 Hz frequency the pulse width tRFP is
equal to one decoder clock period.
The modulus register is write-only, the counter register can
only be read. Both registers have the same index
address (05H).
The real-time clock counter runs continuously irrespective
of the operating condition of the PCD5003A. It contains a
seconds register (maximum 59) and a 1⁄100 second
register (maximum 99), which can be read or written via
the I2C-bus. The bit allocation of both registers is shown in
Tables 16 and 17.
1999 Jan 08
20
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.33 Received call delay
Call reception causes both the periodic interrupt modulus and the counter register to be reset.
Since the periodic interrupt counter runs for another 2.55 seconds after a reset, the received call delay
(in 1⁄100 second units) can be determined by reading the counter register.
Table 18 Alert set-up register (04H; write)
BIT (MSB: D7)
VALUE
DESCRIPTION
call alert via cadence register
0
1
D0
POCSAG call alert (pattern selected by D7, D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
0
D1
D2
1
0
1
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL
)
D3
D4
D5
1
acoustic alerts enable (ATL, ATH)
1
vibrator alert enabled (VIB)
1
LED alert enabled (LED)
0 0
0 1
1 0
1 1
POCSAG alert pattern FC = 00, see Fig.9(a)
POCSAG alert pattern FC = 01, see Fig.9(b)
POCSAG alert pattern FC = 10, see Fig.9(c)
POCSAG alert pattern FC = 11, see Fig.9(d)
D7 and D6(1)
Note
1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address code-word, which designate the
POCSAG call type as shown in Table 1.
D7, D6
0 0
(a)
0 1
(b)
1 0
(c)
1 1
MLC251
(d)
Fig.9 POCSAG alert patterns.
1999 Jan 08
21
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
When using the alert cadence register, D1 would normally
be updated by external control when the alert time-out
interrupt occurs at the start of the 8th cadence time slot.
Since D1 acts immediately on the alert level, it is advised
to reset the last bit of the previous pattern to prevent
unwanted audible level changes.
7.34 Alert generation
The PCD5003A is capable of controlling 3 different alert
transducers: acoustic beeper (HIGH and LOW level), LED
and vibrator motor. The associated outputs are ATH/ATL,
LED and VIB respectively. ATL is an open drain output
capable of directly driving an acoustic alerter via a resistor.
The other outputs require external transistors.
7.37 Vibrator alert
Each alert output can be individually enabled via the alert
set-up register. Alert level and warble can be separately
selected. The alert pattern can either be standard
POCSAG or determined via the alert cadence register.
Direct alert control is possible via input ALC.
The vibrator output (VIB) is activated continuously during
a standard POCSAG alert or whenever the alert cadence
register is non-zero.
Two alert levels are supported: LOW level (25 Hz
square-wave) and HIGH level (continuous). The vibrator
level is controlled by bit D1 in the alert set-up register.
The alert set-up register is shown in Table 18.
Standard POCSAG alerts can be selected by setting
bit D0 in the alert set-up register, bits D6 and D7
determining the alert pattern used.
7.38 LED alert
The LED output pattern corresponds either to the selected
POCSAG alert or to the contents of the alert cadence
register. No equivalent exists for HIGH/LOW level alerts.
Automatic generation via all alert outputs of the POCSAG
alert pattern matching the received call type can be
enabled by SPF programming (SPF byte 3, bit D2).
7.39 Warbled alert
7.35 Alert cadence register (03H; write)
When enabled by setting bit D2 in the alert set-up register,
the signals on outputs ATL, ATH and LED are warbled with
a 16 Hz modulation frequency. Output LED is switched on
and off at the modulation rate, while outputs ATL and ATH
switch between fAWH and fAWL alerter frequencies.
When not programmed for POCSAG alerts (alert set-up
register bit D0 = 0), the 8-bit alert cadence register
determines the alert pattern. Each bit represents a
62.5 ms time slot, a logic 1 activating the enabled alert
transducers. The bit pattern is rotated with the
MSB (bit D7) being output first and the LSB (bit D0) last.
7.40 Direct alert control
When the last time slot (bit D0) is started an interrupt is
generated to allow loading of a new pattern. When the
pattern is not changed it will be repeated. Writing a zero to
the alert cadence register will halt alert generation.
A direct alert control input (ALC) is available for generating
user alarm signals (e.g. battery-low warning). A HIGH level
on input ALC activates all enabled alert outputs, overruling
any ongoing alert patterns.
7.36 Acoustic alert
7.41 Alert priority
Acoustic alerts are generated via outputs ATL and ATH.
For LOW level alerts only ATL is active, while for HIGH
level alerts ATH is also active. ATL is driven in counter
phase with ATH.
Generation of a standard POCSAG alert (D0 = 1)
overrides any alert pattern in the alert cadence register.
After completion of the standard alert, the original cadence
is restarted from the position it was left at. The alert set-up
register will now contain the settings for the standard alert.
The alert level is controlled by bit D1 of the alert set-up
register.
The highest priority has been assigned to the alert control
input (ALC). All enabled alert outputs will be activated
while ALC is set. Outputs are activated/deactivated
synchronous with the decoder clock. Activation requires
an extra delay of 1 clock when no alerts are being
generated.
When D1 is reset, for standard POCSAG alerts (D0 = 1) a
LOW level acoustic alert is generated during the first
4 seconds (ATL), followed by 12 seconds at HIGH level
(ATL + ATH). When D1 is set, the full 16 seconds are at
HIGH level. An interrupt is generated upon expiry of the full
alert time.
When input ALC is reset, acoustic alerting does not cease
until the current output frequency cycle has been
completed.
1999 Jan 08
22
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
When enabled by SPF programming (SPF byte 3, bit D2)
standard POCSAG alerts will automatically be generated
on outputs ATL, ATH, LED and VIB upon call reception.
The alert pattern matches the call type as indicated by the
function bits in the received address code-word.
7.42 Cancelling alerts
Standard POCSAG alerts (manual or automatic) are
cancelled by resetting bit D0 in the alert set-up register.
User defined alerts are cancelled by writing a zero to the
alert cadence register. Any ongoing alert is cancelled
when a reset pulse is applied to input RST.
The original settings of the alert set-up register will be lost.
Bit D0 is reset after completion of the alert.
7.43 Automatic POCSAG alerts
Standard alert patterns have been defined for each
POCSAG call type, as indicated by the function bits in the
address code-word (see Table 1). The timing of these alert
patterns is shown in Fig.10.
FC = 00
t
t
ALC
ALP
FC = 01
t
ALP
t
t
ALP
t
ALC
FC = 10
t
t
ALP
ALC
ALP
FC = 11
t
ALP
t
t
t
ALP
ALC
ALC
MLC252
Fig.10 POCSAG alert timing.
1999 Jan 08
23
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.44 SRAM access
7.47 RAM data output register (09H; read)
The on-chip SRAM can hold up to 96 bytes of call data.
Each call consists of a call header (3 bytes), message data
blocks (3 bytes per code-word) and a call terminator
(3 bytes).
The RAM data output register contains the byte addressed
by the RAM read address pointer. It can only be read, each
read operation causing an increment of the RAM read
address pointer.
The RAM is filled by the decoder and can be read via the
I2C-bus interface. The RAM is accessed indirectly by
means of a read address pointer and a data output
register. A write address pointer indicates the first byte
after the last message byte stored.
7.48 EEPROM access
The EEPROM is intended for storage of user addresses
(RICs), sync words and special programmed function
(SPF) bits representing the decoder configuration.
Status register bit D2 is set when the read and write
pointers are different. It is reset only when the SRAM
pointers become equal during reading, i.e. when the RAM
becomes empty.
The EEPROM can store 48 bytes of information and is
organized as a matrix of 8 rows by 6 columns.
The EEPROM is accessed indirectly via an address
pointer and a data I/O register.
Status bit D3 is set when the read and write pointers
become equal. This can be due to a RAM empty or a RAM
full condition. It is reset after a status read operation.
The EEPROM is protected against inadvertent writing by
means of the programming enable bit in the control
register (bit D1).
Interrupts are generated as follows:
The EEPROM memory map is non-contiguous as can be
seen in Fig.11, which shows both the EEPROM
organization and the access method.
• When status bit D2 is set and the receiver is disabled
(RXE = 0): data is available for reading, if data fail mode
(short fade recovery mode in APOC1) is not active
Identifier locations contain RICs or sync words. A total of
20 unassigned bytes is available for general purpose
storage.
• Immediately when status bit D3 is set: RAM is either
empty (status bit D2 = 0) or full (status bit D2 = 1).
To avoid loss of data due to RAM overflow at least 3 bytes
of data must be read during reception of the code-word
following the ‘RAM full’ interrupt.
7.49 EEPROM address pointer (07H; read/write)
An EEPROM location is addressed via the EEPROM
address pointer. It is incremented automatically each time
a byte is read or written via the EEPROM data I/O register.
7.45 RAM write address pointer (06H; read)
The EEPROM address pointer contains two counters, for
the row and the column number. Bits D2 to D0 contain the
column number (0 to 5) and bits D5 to D3 the row number
(0 to 7). Bits D7 and D6 of the address pointer are not
used. Data written to these bits will be ignored, while their
values are undefined when read.
The RAM write address pointer is automatically
incremented during call reception, as the decoder writes
each data byte to RAM. The RAM write address pointer
can only be read. Values range from 00H to 5FH.
Bit D7 (MSB) is not used and its value is undefined when
read.
The column and row counters are connected in series.
Upon overflow of the column counter (column = 5) the row
counter is automatically incremented and the column
counter wraps to 0. On overflow the row counter wraps
from 7 to 0.
7.46 RAM read address pointer (08H; read/write)
The RAM read address pointer is automatically
incremented after reading a data byte via the RAM output
register.
7.50 EEPROM data I/O register (0AH; read/write)
It can be accessed for writing as well as reading.
The byte addressed by the EEPROM address pointer can
be written or read via the EEPROM Data I/O register. Each
access automatically increments the EEPROM address
pointer.
The values range from 00H to 5FH. When at 5FH a read
operation will cause wrapping around to 00H.
Bit D7 (MSB) is not used; it is ignored when written and
undefined when read.
1999 Jan 08
24
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
After writing each block a pause of maximum 7.5 ms is
required to complete the programming operation
internally. During this time the external microcontroller
may generate an I2C-bus stop condition. If another I2C-bus
transfer is started the decoder will pull SCL LOW during
this pause.
7.51 EEPROM access limitations
Since the EEPROM address pointer is used during data
decoding, the EEPROM may not be accessed while the
receiver is active (RXE = 1). It is advised to switch to OFF
state before accessing the EEPROM.
The EEPROM cannot be written unless the EEPROM
programming enable bit (bit D1) in the control register is
set.
After writing the EEPROM programming enable bit (D1) in
the control register must be reset.
For writing a minimum programming supply voltage
7.54 Invalid write address
V
DD(prog) is required (2.0 V typ.). The programming supply
When an invalid write address is used, the column counter
bits (D2 to D0) are forced to zero before being loaded into
the address pointer. The row counter bits are used
normally.
current (IDD(prog)) needed during writing will be ≈ 500 µA.
Any modified SPF settings (bytes 0 to 3) only take effect
after a decoder reset. Modified identifiers are active
immediately.
7.55 Incomplete programming sequence
7.52 EEPROM read operation
A programming sequence may be aborted by an I2C-bus
stop condition. Next, the EEPROM programming enable
bit (D1) in the control register must be reset.
EEPROM read operations must start at a valid address in
the non-contiguous memory map. Single-byte or block
reads are permitted.
Any bytes received of the last 6-byte block will be ignored
and the contents of this (incomplete) EEPROM block will
remain unchanged.
7.53 EEPROM write operation
EEPROM write operations must always take place in
blocks of 6 bytes, starting at the beginning of a row.
Programming a single byte will reset the other bytes in the
same row. Modifying a single byte in a row requires
re-writing the unchanged bytes with their old contents.
7.56 Unused EEPROM locations
A total of 20 EEPROM bytes is available for general
purpose storage (see Table 19).
COLUMN
ADDRESS
POINTER
0
1
2
3
4
5
D7
D0
0
0
1
2
3
4
5
6
7
0
1
0
1
0
I
I
I
I
I
I
D
1
D
2
D
3
D
4
D
5
D
6
ROW COLUMN
I/O REGISTER
ROW
D7
D0
SPF bits
Synthesizer data
Identifiers
unused bytes
MLC254
Fig.11 EEPROM organization and access.
1999 Jan 08
25
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 19 Unused EEPROM addresses
7.57 Special programmed function allocation
The SPF bit allocation in the EEPROM is shown in
Tables 20 to 24. The SPF bits are located in row 0 of the
EEPROM and occupy 4 bytes.
ROW
HEX
0
5
6
7
04 and 05(1)
28 to 2D
30 to 35
Bytes 04H and 05H are not used and are available for
general purpose storage.
38 to 3D
The contents of SPF (bytes 0 to 3) are read into the
associated logic only when the decoder is reset
(HIGH level in input RST).
Note
1. When using bytes 04H and 05H, care must be taken
to preserve the SPF information stored in
bytes 00H to 03H.
Table 20 Special programmed functions (EEPROM address 00H)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
X
X
X
X
X
X
X
1
reserved for future use; logic 0 when read
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use; logic 0 when read
received data inversion enabled
Table 21 Special programmed functions (EEPROM address 01H)
BIT (MSB: D7)
VALUE
DESCRIPTION
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
5 ms receiver establishment time (nominal); note 1
10 ms receiver establishment time (nominal); note 1
15 ms receiver establishment time (nominal); note 1
30 ms receiver establishment time (nominal); note 1
20 ms oscillator establishment time (nominal); note 1
30 ms oscillator establishment time (nominal); note 1
40 ms oscillator establishment time (nominal); note 1
50 ms oscillator establishment time (nominal); note 1
512 bits/s received bit rate
D1 and D0
D3 and D2
D5 and D4
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
D6
D7
synthesizer interface enabled (data is output via ZSD, ZSC and ZLE at
decoder switch-on)
1
voltage converter enabled
Note
1. Since the exact establishment time is related to the programmed bit rate, Table 22 shows the values for the various
bit rates.
1999 Jan 08
26
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 22 Establishment time as a function of bit rate
NOMINAL
ESTABLISHMENT
TIME
ACTUAL ESTABLISHMENT TIME
512 BITS/s
1024 BITS/s
1200 BITS/s
2400 BITS/s
5 ms
10 ms
15 ms
20 ms
30 ms
40 ms
50 ms
5.9 ms (3 bits)
11.7 ms (6 bits)
15.6 ms (8 bits)
23.4 ms (12 bits)
31.2 ms (16 bits)
39.1 ms (20 bits)
46.9 ms (24 bits)
5.9 ms (6 bits)
11.7 ms (12 bits)
15.6 ms (16 bits)
23.4 ms (24 bits)
31.2 ms (32 bits)
39.1 ms (40 bits)
46.9 ms (48 bits)
5.0 ms (6 bits)
10.0 ms (12 bits)
16.7 ms (20 bits)
20.0 ms (24 bits)
26.7 ms (32 bits)
40.0 ms (48 bits)
53.3 ms (64 bits)
5.0 ms (12 bits)
10.0 ms (24 bits)
16.7 ms (40 bits)
20.0 ms (48 bits)
26.7 ms (64 bits)
40.0 ms (96 bits)
53.3 ms (128 bits)
Table 23 Special programmed functions (EEPROM address 02H)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
X
X
not used
not used
0 0
0 1
1 0
1 1
1
32768 Hz real-time clock reference
50 Hz square wave
D3 and D2
2 Hz
1
⁄
60 Hz
D4
D5
signal test mode enabled (REF and INT outputs)
burst error correction enabled
0
D7 and D6
X X
reserved for future use
Table 24 Special programmed functions (EEPROM address 03H)
BIT (MSB: D7)
VALUE
DESCRIPTION
2048 Hz acoustic alerter frequency
0 0
0 1
1 0
1 1
1
2731 Hz acoustic alerter frequency
4096 Hz acoustic alerter frequency
3200 Hz acoustic alerter frequency
automatic POCSAG alert generation enabled
not used
D1 and D0
D2
D3
D4
X
X
not used
0
DQC mode 0
D5
D6
D7
1
DQC mode 1
0
INT output polarity: active LOW
INT output polarity: active HIGH
standard call termination
enhanced call termination
1
0
1
1999 Jan 08
27
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Identifiers are stored in EEPROM rows 2, 3 and 4. Each
identifier location consists of 3 bytes in the same column.
The identifier number is equal to the column number + 1.
7.58 Synthesizer programming data
Data for programming a PLL synthesizer via pins ZSD,
ZSC and ZLE can be stored in row 1 of the EEPROM.
Six bytes are available starting from address 08H.
Only the last 4 identifiers (numbers 3 to 6) can be
programmed as a UPSW. Identifiers 1 and 2 always
represent RICs. A UPSW represents an unused address
and must differ by more than 6 bits from preamble to
guarantee detection.
Data is transferred in two serial blocks of 24 bits each,
starting with bit 0 (MSB) of block 1. Any unused bits must
be programmed at the beginning of a block.
The standard POCSAG sync word is always enabled and
has identifier number 7.
7.59 Identifier storage allocation
Up to 6 different identifiers can be stored in EEPROM for
matching with incoming data. The PCD5003A can
distinguish two types of identifiers:
Table 26 shows the memory locations of the 6 identifiers.
The bit allocation per identifier is given in Table 27.
• User addresses (RIC)
• User Programmable Sync Words (UPSW).
Table 25 Synthesizer programming data (EEPROM address 08H to 0DH)
ADDRESS (HEX)
BIT (MSB: D7)
DESCRIPTION
bits 0 to 7 of data block 1 (bit 0 is MSB)
08
09
0A
0B
0C
0D
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
bits 8 to 15
bits 16 to 23
bits 0 to 7 of data block 2 (bit 0 is MSB)
bits 8 to 15
bits 16 to 23
Table 26 Identifier storage allocation (EEPROM address 10H to 25H)
ADDRESS (HEX)
BYTE
DESCRIPTION
10 to 15
18 to 1D
20 to 25
1
2
3
identifier number 1 to 6
identifier number 1 to 6
identifier number 1 to 6
1999 Jan 08
28
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 27 Identifier bit allocation
BYTE
BIT (MSB: D7)
DESCRIPTION
1
2
D7 to D0
D7 to D0
D7 and D6
D5
bits 2 to 9 of POCSAG code-word (RIC or UPSW); notes 1 and 2
bits 10 to 17
bits 18 and 19
frame number bit FR3 (RIC); note 3
frame number bit FR2 (RIC)
D4
3
D3
frame number bit FR1 (RIC)
D2
identifier type selection (0 = UPSW, 1 = RIC); note 4
identifier enable (1 = enabled)
D1
D0
reserved for future use, logic 0 when read
Notes
1. The bit numbering corresponds with the numbering in a POCSAG code-word: bit 1 is the flag bit (0 = address,
1 = message).
2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0; bits 2 to 19 contain
the identifier bit pattern; they are followed by 2 predetermined random (function) bits and the UPSW is completed by
10 CRC error correction bits and an even-parity bit.
3. Bits FR3 to FR1 (MSB : FR3) contain the 3 least significant bits of the 21-bit RIC.
4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.
The level-shifted interface lines are: RST, DON, ALC, REF
and INT.
7.60 Voltage doubler
An on-chip voltage doubler provides an unregulated
DC output for supplying an LCD or a low power
microcontroller on output VPO. An external ceramic
capacitor of typical 100 nF is required between pins CCN
and CCP. The voltage doubler is enabled via SPF
programming.
The I2C-bus interface lines SDA and SCL can be
level-shifted independently of VPR by means of the
standard external pull-up resistors.
7.62 Signal test mode
A special ‘signal test’ mode is available for monitoring the
performance of a receiver circuit together with the
front-end of the PCD5003A.
7.61 Level-shifted interface
All interface lines are suited for communication with a
microcontroller operating from a higher supply voltage.
The external device must have a common reference at VSS
of the PCD5003A.
For this purpose the output of the digital noise filter and the
recovered bit clock are made available at outputs REF and
INT respectively. All synchronization and decoding
functions are normally active.
The reference voltage for the level-shifted interface must
be applied to input VPR. This could be the on-chip voltage
doubler output VPO if required. When the microcontroller
has a separate (regulated) supply this separate supply
The ‘signal test’ mode is activated/deactivated by SPF
programming.
voltage should be connected to VPR
.
1999 Jan 08
29
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
A more accurate reset duration can be realised with an
8
OPERATING INSTRUCTIONS
Reset conditions
additional external resistor connected to VSS
.
8.1
Recommended minimum values in this case are
C = 2.2 nF and R = 100 kΩ (see Fig.16).
When the PCD5003A is reset by applying a HIGH-level on
input RST, the condition of the decoder is as follows:
8.3
Reset timing
• OFF status (irrespective of DON input level)
• REF output frequency 32768 Hz
• All internal counters reset
The start-up time for the crystal oscillator may exceed
1 second (typ. 800 ms). It is advised to apply a reset
condition at least during the first part of this period.
The minimum reset pulse duration tRST is 50 µs.
• Status/control register reset
• All interrupts enabled
During reset the oscillator is active, but clock signals are
inhibited internally. Once the reset condition is released
the end of the oscillator start-up period can be detected by
a rising edge on output INT.
• No alert transducers selected
• LED, VIB and ATH outputs at LOW level
• ATL output high impedance
During a reset the voltage converter clock (Vclk) is held at
zero. The resulting output voltage drop may cause
problems when the external resetting device is powered by
the internal voltage doubler. A sufficiently large buffer
capacitor between output VPO and VSS must be provided
to supply the microcontroller during reset. The voltage at
• SDA, SCL inputs high impedance
• Voltage converter disabled.
Within tRSU after release of the reset condition (RST LOW)
the programmed functions are activated. The settings
affecting the external operation of the PCD5003A are as
follows:
VPO will not drop below VDD − 0.7 V.
• REF output frequency
• Voltage converter
• INT output polarity
• Signal test mode.
Immediately after a reset all programmable internal
functions will start operating according to a programmed
value of 0. During the first 8 full clock cycles (tRSU) all
programmed values are loaded from EEPROM.
After reset the receiver outputs RXE and ROE become
active immediately, if DON is HIGH and the synthesizer is
disabled. When the synthesizer is enabled, RXE and ROE
will only become active after the second pulse on ZLE
completes the loading of synthesizer data.
When input DON is HIGH, the decoder starts operating in
ON status immediately following tRSU
.
8.2 Power-on reset circuit
During power-up of the PCD5003A a HIGH level of
minimum duration tRST = 50 µs must be applied to
pin RST. This is to prevent EEPROM corruption which
might otherwise occur because of the undefined contents
of the control register.
The full reset timing is shown in Fig.12. The start-up timing
including synthesizer programming is given in Fig.13.
8.4
Initial programming
A newly-delivered PCD5002A has EEPROM contents
which are undefined. The EEPROM should therefore be
programmed, followed by a reset to activate the SPF
settings, before any attempt is made to use the device.
The reset signal can be applied by the external
microcontroller or by an RC power-on reset circuit on
pin RST (C to VPR, R to VSS). Such an RC-circuit should
have a time constant of at least 3tRST = 150 µs.
Input RST has an internal high-ohmic pull-down resistor
(nominal 2 MΩ at 2.5 V supply) which could be used
together with a suitable external capacitor connected to
VPR to create a power-on reset signal. However, since this
pull-down resistor varies considerably with processing and
supply voltage, the resulting time constant is inaccurate.
1999 Jan 08
30
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XTAL1
RST
asynchronous
t
RST
REF
INT
programmed for 32768 Hz
active LOW
active HIGH
active LOW
active HIGH
V
clk
RXE (DON = 1)
(1)
ZLE
(2)
MLC253
t
RSU
(1) The RXE output signal is shown for disabled synthesizer. When the synthesizer is enabled RXE is held off until after the second pulse on ZLE (programming complete).
(2) The ZLE output signal is shown for enabled synthesizer and DON = 1. When DON = 0 output ZLE remains HIGH until ON state is entered (DON = 1 or control register bit D4 = 1).
Fig.12 Reset timing.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
DON
ZSC
ZLE
BLOCK 1
BLOCK 2
t
t
ZDL1
ZDL1
t
t
p
ZDL2
RXE
t
t
clk
ZSU
t
MLC255
OSU
Fig.13 Start-up timing including synthesizer programming.
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
−0.5
MAX.
+7.0
+7.0
UNIT
VDD
VPR
Vn
supply voltage
external reference voltage input
V
V
V
V
V
PR ≥ VDD − 0.8 V
voltage on pins ALC, DON, RST, SDA and SCL Vn ≤ 7.0 V
V
V
−
−
SS − 0.8
V
PR + 0.8
DD + 0.8
Vn1
Ptot
Pout
Tamb
Tstg
voltage on any other pin
total power dissipation
Vn1 ≤ 7.0 V
SS − 0.8
V
250
100
+70
+125
mW
mW
°C
power dissipation per output
operating ambient temperature
storage temperature
−25
−55
°C
1999 Jan 08
32
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
10 DC CHARACTERISTICS
VDD = 2.7 V; VPR = 2.7 V; VSS = 0 V; Tamb = −25 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
voltage converter disabled
1.5
2.7
6.0
V
V
V
V
VPR
external reference voltage input
programming supply voltage
VPR ≥ VDD − 0.8 V
1.5
2.0
2.0
−
2.7
−
6.0
VDD(prog)
voltage converter disabled
voltage converter enabled
note 1
6.0
−
3.0
IDD0
supply current (OFF)
supply current (ON)
25.0
50.0
−
40.0
80.0
800
µA
µA
µA
IDD1
DON = VDD; note 1
−
IDD(prog)
programming supply current
−
Inputs
VIL
LOW-level input voltage
RDI and BAT
VSS
VSS
VSS
−
−
−
0.3VDD
0.3VPR
0.3VDD
V
V
V
DON, ALC and RST
SDA and SCL
VIH
HIGH-level input voltage
RDI and BAT
0.7VDD
0.7VPR
0.7VDD
0
−
−
−
−
VDD
VPR
VPR
−0.5
V
DON, ALC and RST
SDA and SCL
V
V
IIL
LOW-level input current pins
RDI, BAT,TS1, TS2, DON,
ALC and RST
Tamb = 25 °C; VI = VSS
µA
IIH
HIGH-level input current
TS1 and TS2
Tamb = 25 °C
VI = VDD
6
−
20
µA
µA
µA
nA
RDI and BAT
VI = VDD; RXE = 0
VI = VDD; RXE = 1
VI = VPR
6
−
20
RDI and BAT
0
−
0.5
850
DON, ALC and RST
250
500
Outputs
IOL
LOW-level output current
VIB and LED
ATH
Tamb = 25 °C
VOL = 0.3 V
80
250
80
70
13
80
−
−
µA
µA
µA
µA
mA
µA
VOL = 0.3 V
VOL = 0.3 V
VOL = 0.3 V
−
−
INT and REF
ZSD, ZSC and ZLE
ATL
−
−
−
−
VOL = 1.2 V; note 2
OL = 0.3 V
27
−
55
−
ROE, RXE and DQC
V
1999 Jan 08
33
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C
MIN.
TYP.
MAX.
UNIT
IOH
HIGH level output current
VIB and LED
V
V
V
V
OH = 0.7 V
−0.6
−
−
−
−
−
−
−2.4
mA
ATH
OH = 0.7 V
OH = 2.4 V
OH = 2.4 V
−3.0
−80
−60
−
−11.0
mA
µA
µA
µA
µA
INT and REF
ZSD, ZSC and ZLE
ATL
−
−
ATL high-impedance; note 3
VOH = 2.4 V
−0.5
−
ROE, RXE and DQC
−600
Notes
1. Inputs: SDA and SCL pulled up to VDD; all other inputs connected to VSS
.
Outputs: RXE and ROE logic 0; REF: fref = 1⁄60 Hz; all other outputs open-circuit.
Oscillator: no crystal; external clock fosc = 76800 Hz; amplitude: VSS to VDD
Voltage convertor disabled (SPF byte 01, bit D7 = 0; see Table 21).
.
2. Maximum output current is subject to absolute maximum ratings per output (see Chapter 9).
3. When ATL (open-drain output) is not activated it is high impedance.
11 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER)
VDD = 2.7 V; VSS = 0 V; VPR = VPO; Tamb = −25 to +70 °C; Cs = 100 nF; voltage converter enabled.
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
1.5
TYP.
MAX.
UNIT
VDD
VPO(0)
VPO
IPO
−
3.0
−
V
output voltage; no load
output voltage
VDD = 2.7 V; IPO = 0
−
5.4
V
VDD = 2.0 V; IPO = −250 µA
VDD = 2.0 V; VPO = 2.7 V
3.0
3.5
−
V
output current
−400
−650
−650
−900
−
µA
µA
V
DD = 3.0 V; VPO = 4.5 V
−
12 OSCILLATOR CHARACTERISTICS
Quartz crystal type: MX-1V or equivalent. Quartz crystal parameters: f = 76800 Hz; RS(max) = 35 kΩ; CL = 8 pF;
C0 = 1.4 pF; C1 = 1.5 fF. Maximum overall tolerance: ±200 × 10−6 (includes: cutting, temperature, aging).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
UNIT
CXO
gm
output capacitance XTAL2
oscillator transconductance
−
10
12
pF
VDD = 1.5 V
6
µS
13 EEPROM CHARACTERISTICS
SYMBOL
NEW
PARAMETER
erase/write cycles
data retention time
CONDITIONS
MIN.
TYP.
UNIT
1000
10
10000
tDR
Tamb = 70 °C; note 1
−
years
Note
1. Retention cannot be guaranteed for naked dies (PCD5003AU/10).
1999 Jan 08
34
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
14 AC CHARACTERISTICS
V
DD = 2.7 V; VSS = 0 V; VPR = 2.7 V; Tamb = 25 °C;. fosc = 76800 Hz.
SYMBOLS PARAMETER CONDITIONS
System clock
Tclk system clock period
Call alert frequencies
MIN.
TYP.
MAX.
UNIT
fosc = 76800 Hz
−
13.02
−
µs
fAL
alert frequency
SPF byte 03H; bits
D1, D0 = 0 0
D1, D0 = 0 1
D1, D0 = 1 0
D1, D0 = 1 1
−
−
−
−
−
2048
2731
3200
4096
16
−
−
−
−
−
Hz
Hz
Hz
Hz
Hz
fAW
warbled alert; modulation
frequency
alert set-up bit D2 = 1;
outputs ATL, ATH and LED
fAWH
fAWL
fVBP
warbled alert; high acoustic
alert frequency
alert set-up bit D2 = 1;
outputs ATL and ATH
−
−
−
fAL
−
−
−
Hz
Hz
Hz
warbled alert; low acoustic alert alert set-up bit D2 = 1;
frequency
1⁄2fAL
25
outputs ATL and ATH
pulsed vibrator frequency
(square wave)
low-level alert
Call alert duration
tALT
tALL
tALH
tVBL
tVBH
tALC
tALP
alert time-out period
−
−
−
−
−
−
−
16
4
−
−
−
−
−
−
−
s
ATL output time-out period
ATH output time-out period
VIB output time-out period
VIB output time-out period
alert cycle period
low-level alert
high-level alert
low -level alert
high-level alert
s
12
4
s
s
12
1
s
s
alert pulse duration
125
ms
Real-time clock reference
fref
real-time clock reference
frequency
SPF byte 02H; bits
D3, D2 = 0 0; note 1
D3, D2 = 0 1; note 2
D3, D2 = 1 0
−
−
−
−
−
32768
−
−
−
−
−
Hz
Hz
Hz
Hz
µs
50
2
1
D3, D2 = 1 1
⁄
60
tRFP
real-time clock reference pulse all reference frequencies
duration except 50 Hz (square wave)
13.02
1999 Jan 08
35
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Receiver control
tRXT
RXE, ROE transition time
CL = 5 pF
−
100
−
ns
tRXON
RXE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 22)
SPF byte 01H; bits
D1, D0 = 0 0
D1, D0 = 0 1
D1, D0 = 1 0
D1, D0 = 1 1
SPF byte 01H; bits
D3, D2 = 0 0
D3, D2 = 0 1
D3, D2 = 1 0
D3, D2 = 1 1
−
−
−
−
5
−
−
−
−
ms
ms
ms
ms
10
15
30
tROON
ROE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 22)
−
−
−
−
20
30
40
50
−
−
−
−
ms
ms
ms
ms
I2C-bus interface
fSCL
SCL clock frequency
0
−
−
−
−
−
−
−
−
−
−
−
400
−
kHz
µs
µs
ns
ns
ns
ns
pF
µs
µs
µs
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
SCL clock low period
SCL clock HIGH period
data set-up time
1.3
0.6
100
0
−
−
data hold time
−
SDA, SCL rise time
−
300
300
400
−
tf
SDA, SCL fall time
note 3
−
CB
capacitive bus line load
START condition set-up time
START condition hold time
STOP condition set-up time
tSU;STA
tHD;STA
tSU;STO
0.6
0.6
0.6
−
−
Reset
tRST
tRSU
tOSU
external reset duration
set-up time after reset
set-up time after switch-on
50
−
−
−
−
−
µs
µs
ms
oscillator running
oscillator running
105
4
−
Data input
tTDI
data input transition time
data input logic 1 duration
data input logic 0 duration
see Fig.14
see Fig.14
see Fig.14
−
−
−
−
100
∞
µs
tDI1
tBIT
tBIT
tDI0
∞
POCSAG data timing (512 bits/s)
fDI
data input rate
SPF byte 01H;
−
512
−
bits/s
bits D5, D4 = 0 0
tBIT
tCW
tPA
bit duration
−
1.9531
62.5
−
−
−
−
ms
ms
ms
ms
code-word duration
preamble duration
batch duration
−
1125
−
tBAT
−
1062.5
1999 Jan 08
36
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
POCSAG data timing (1200 bits/s)
fDI
data input rate
SPF byte 01H;
−
1200
−
bits/s
bits D5, D4 = 1 0
tBIT
tCW
tPA
bit duration
−
−
833.3
26.7
−
−
−
−
−
µs
code-word duration
preamble duration
batch duration
ms
ms
ms
480
tBAT
−
453.3
POCSAG data timing (2400 bits/s)
fDI
data input rate
SPF byte 01H;
−
2400
−
bits/s
bits D5, D4 = 1 1
tBIT
tCW
tPA
bit duration
−
416.6
13.3
−
−
−
−
−
µs
code-word duration
preamble duration
batch duration
−
ms
ms
ms
240
−
tBAT
226.6
Synthesizer control
tZSU
fZSC
tZCL
tZSD
tZDS
tZDL1
tZLE
synthesizer set-up duration
oscillator running; note 4
note 5
1
−
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
bits
Hz
µs
µs
µs
µs
µs
µs
output clock frequency
clock pulse duration
data bit duration
38400
13.02
26.04
13.02
91.15
13.02
117.19
note 5
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
tZDL2
Notes
1. 32768 Hz reference signal: 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: tRFP). The timing is shown in Fig.15.
2. 50 Hz reference signal: square-wave.
3. The fall time may be faster than prescribed in the I2C-bus specification for very low load capacitance values.
To increase the fall time external capacitance is required.
4. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits.
5. Nominal values; pause in 12th data bit (see Table 12).
1999 Jan 08
37
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
t
t
DI0
DI1
handbook, halfpage
t
MGL100
TDI
Fig.14 Data input timing.
t
RFP
t
RFP
MLC278
2t
RFP
Fig.15 Timing of the 32768 Hz reference signal.
38
1999 Jan 08
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BATTERY
POSITIVE
M
C
s
100 nF
10
µF
(2)
(1)
(1)
function
keys
4.7
4.7
kΩ
kΩ
V
ANT
ATL ATH
RDI
VIB
LED
V
CCP CCN
V
V
V
PO
DD
PR
DATA
OUT
RST
BAT
REF
(2)
RECEIVER
BAT
RXE
PWR
CTRL
DON
INT
OSC
VCO
V
MICROCONTROLLER
REF
ALC
PCD5003A
DECODER
SDA
SCL
V
PWR
CTRL
ROE
V
FREQUENCY
SYNTHESIZER
DATA
CLK
ZSD
ZSC
ZLE
LATCH
V
LCD
V
V
XTAL1
XTAL2
DQC
TS1
n.c.
TS2
SS
DRIVER
V
n.c.
n.c.
LCD
BATTERY
NEGATIVE
76.8 kHz
2.2 MΩ
10 pF
V
LCD
DRIVER
V
2
I C-bus
MGL570
(1) Value depends on number of devices attached.
(2) Values should be chosen to give a time constant of at least 150 µs. C = 2.2 nF and R = 100 kΩ are recommended.
Fig.16 Typical application example (display pager).
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
16 PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
A
24
17
25
16
Z
E
e
H
E
A
E
(A )
3
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
32
9
detail X
1
8
e
Z
D
v M
A
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.4 0.18 7.1
0.3 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.9
0.5
0.9
0.5
mm
1.60
0.25
0.8
1.0
0.2 0.25 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT358 -1
1999 Jan 08
40
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
If wave soldering is used the following conditions must be
observed for optimal results:
17 SOLDERING
17.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
17.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
17.4 Manual soldering
17.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 08
41
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jan 08
42
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
18 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jan 08
43
Philips Semiconductors – a worldwide company
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Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA61
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
465008/00/01/pp44
Date of release: 1999 Jan 08
Document order number: 9397 750 04677
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