PCF2105MU [NXP]
LCD controller/driver; LCD控制器/驱动器
| 型号： | PCF2105MU |
| 厂家： | 
NXP |
| 描述： | LCD controller/driver |
| 文件： | 总48页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF2105
LCD controller/driver
1998 Jul 30
Product specification
Supersedes data of 1997 Dec 08
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
CONTENTS
9.4
Display control
9.4.1
9.4.2
9.4.3
9.5
D
C
B
1
2
3
FEATURES
APPLICATIONS
Cursor/display shift
Function set
DL (parallel mode only)
N and M
Set CGRAM address
Set DDRAM address
Read busy flag and address
GENERAL DESCRIPTION
9.6
3.1
3.2
Packages
Available types
9.6.1
9.6.2
9.7
9.8
9.9
4
5
6
7
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
9.10
9.11
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
PAD FUNCTIONS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
RS: Register Select (parallel control)
R/W: read/write (parallel control)
E: data bus clock (parallel control)
DB7 to DB0: data bus (parallel control)
C60 to C1: column driver outputs
R32 to R1: row driver outputs
10
INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
11
INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
Characteristics of the I2C-bus
Bit transfer
11.1
11.2
11.3
11.4
11.5
11.6
VLCD: LCD power supply
START and STOP conditions
System configuration
Acknowledge
OSC: oscillator
SCL: serial clock line
SDA: serial data line
SA0: address input
T1: test input
I2C-bus protocol
12
LIMITING VALUES
8
FUNCTIONAL DESCRIPTION
13
HANDLING
8.1
8.2
8.3
8.4
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Registers
14
DC CHARACTERISTICS
AC CHARACTERISTICS
TIMING DIAGRAMS
APPLICATION INFORMATION
15
16
17
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
Busy flag
17.1
4-bit operation, 2 × 12 display using internal
reset
8-bit operation, 2 × 12 display using internal
reset
8-bit operation, 2 × 24 display
I2C-bus operation, 2 × 12 display
Initializing by instruction
Address Counter (AC)
Display Data RAM (DDRAM)
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Programming of the MUX rate 1 : 16
Programming of the MUX rate 1 : 32
Reset function
17.2
17.3
17.4
17.5
18
19
20
21
BONDING PAD LOCATIONS
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
9
INSTRUCTIONS
9.1
9.2
9.3
9.3.1
9.3.2
Clear display
Return home
Entry mode set
I/D
S
1998 Jul 30
2
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
1
FEATURES
• Single chip Liquid Crystal Display (LCD) controller/driver
• 1 or 2-line display of up to 24 characters per line, or
2 or 4-line display of up to 12 characters per line
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese syllabary) and user-defined symbols
Furthermore, a fast I2C-bus interface (400 kHz) is
• On-chip generation of intermediate LCD bias voltages
provided.
• On-chip oscillator requires no external components
(external clock also possible)
The PCF2105 is optimized for chip-on-glass applications.
A specific letter code ‘M’ for a character set is programmed
in the Character Generator ROM (CGROM) (see Fig.5).
• Display data RAM: 80 characters
• Character generator ROM: 240 characters
The PCF2105 is a low power CMOS LCD controller/driver,
designed to drive a split screen dot matrix LCD of
1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with a 5 × 8 dot format. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages which
results in a minimum of external components and lower
system power consumption. To allow partial VDD shutdown
the ESD protection system of the SCL and SDA pads does
• Character generator RAM: 16 characters
• 4 or 8-bit parallel bus or 2-wire I2C-bus interface
(400 kHz)
• CMOS and TTL compatible
• 32 row, 60 column outputs
• Multiplex (MUX) rates 1 : 32 and 1 : 16
• Uses common 11-code instruction set
• Logic supply voltage range: VDD − VSS = 2.5 to 6 V
• Display supply voltage range: VDD − VLCD = 3.5 to 9 V
• Low power consumption
not use a diode connected to VDD
.
The chip contains a character generator and displays
alphanumeric and kana characters. The PCF2105
interfaces to most microcontrollers via a 4 or 8-bit parallel
bus, or via the 2-wire I2C-bus.
• I2C-bus address selection (SA0): 011101.
3.1
Packages
2
APPLICATIONS
• PCF2105MU/2: chip with bumps in tray.
• Telecom equipment
• Portable instruments
• Point-of-sale terminals.
3.2
Available types
• PCF2105MU/2: character set ‘M’ in CGROM.
3
GENERAL DESCRIPTION
The PCF2105 integrated circuit is similar to the PCF2114x
(described in the “PCF2116 family” data sheet) but does
not contain the high voltage generator of that device.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF2105MU/2
−
chip with bumps in tray
−
1998 Jul 30
3
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
5
BLOCK DIAGRAM
R32 to R1
C60 to C1
21 to 80
(1)
32
60
COLUMN DRIVERS
60
ROW DRIVERS
32
BIAS
VOLTAGE
GENERATOR
111
V
LCD
6
SHIFT REGISTER
32-BIT
DATA LATCHES
60
SHIFT REGISTER
5 x 12-bit
5
PCF2105
CURSOR + DATA CONTROL
5
2
4
V
DD
CHARACTER
CHARACTER
GENERATOR
ROM
1
GENERATOR
RAM
V
OSCILLATOR
OSC
SS
(CGRAM)
16
(CGROM)
240
CHARACTERS
CHARACTERS
101
T1
TIMING
GENERATOR
8
DISPLAY DATA RAM
(DDRAM) 80 CHARACTERS
7
DISPLAY
ADDRESS
COUNTER
7
ADDRESS
COUNTER (AC)
7
POWER - ON
RESET
INSTRUCTION
DECODER
8
8
DATA
REGISTER (DR)
BUSY
FLAG
INSTRUCTION
REGISTER (IR)
8
7
8
I/O BUFFER
8
102 to 109
98
E
100
R/W
99
RS
97
SCL
110
SDA
3
MGK846
DB7 to DB0
SA0
(1) Pads 5 to 8 and 9 to 12 correspond with symbols R8 to R5 and R32 to R29.
Pads 13 to 20 and 81 to 88 correspond with symbols R24 to R17 and R9 to R16.
Pads 89 to 92 and 93 to 96 correspond with symbols R25 to R28 and R1 to R4.
Fig.1 Block diagram.
1998 Jul 30
4
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
6
PINNING
SYMBOL
PAD
I/O
DESCRIPTION
oscillator/external clock input
OSC
1
2
I
−
VDD
logic supply voltage
SA0
3
I
I2C-bus address selection input
VSS
4
−
logic ground
R8 to R5
R32 to R29
R24 to R17
C60 to C1
R9 to R16
R25 to R28
R1 to R4
SCL
5 to 8
9 to 12
13 to 20
21 to 80
81 to 88
89 to 92
93 to 96
97
O
O
O
O
O
O
O
I
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
LCD column driver outputs
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
I2C-bus serial clock input
data bus clock input
E
98
I
RS
99
I
register select input
R/W
100
I
read/write input
T1
101
I
test input
DB7 to DB0
SDA
102 to 109
110
I/O
I/O
I
8-bit bidirectional data bus input/output
I2C-bus serial data input/output
LCD supply voltage input
VLCD
111
7
PAD FUNCTIONS
RS: Register Select (parallel control)
7.4
DB7 to DB0: data bus (parallel control)
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2105. DB7 acts as the
busy flag, signalling that internal operations are not yet
completed. In 4-bit operations, DB7 to DB4 are used and
DB3 to DB0 must be left open-circuit. There is an internal
pull-up resistor on each of the data lines. Note that
pads DB7 to DB0 must be left open-circuit when I2C-bus
control is used.
7.1
Bit RS selects the register to be accessed for read and
write when the device is controlled by the parallel interface.
RS = 0 selects the instruction register for write and the
busy flag and address counter for read. RS = 1 selects the
data register for both read and write. There is an internal
pull-up resistor on pad RS.
7.2
R/W: read/write (parallel control)
7.5
C60 to C1: column driver outputs
R/W selects either the read (R/W = 1) or write (R/W = 0)
operation when control is by the parallel interface. There is
an internal pull-up resistor on pad R/W.
Pads C60 to C1 output the data for pairs of columns.
This arrangement permits optimized Chip-On-Glass
(COG) layout for 4-line by 12 characters.
7.3
E: data bus clock (parallel control)
7.6
R32 to R1: row driver outputs
Pad E should be HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the falling
edge of the clock. Note that pad E must be connected to
VSS (logic 0) when I2C-bus control is used.
Pads R32 to R1 output the row select waveforms to the
left and right halves of the display.
7.7
VLCD: LCD power supply
Negative power supply for the liquid crystal display.
1998 Jul 30
5
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
7.8
OSC: oscillator
8.2
Oscillator
When the on-chip oscillator is used, pad OSC must be
connected to VDD. An external clock signal, if used, is input
at pad OSC.
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pad OSC must be connected to VDD
.
7.9
SCL: serial clock line
8.3 External clock
Pad SCL is input for the I2C-bus clock signal.
If an external clock is to be used, it must be input at
pad OSC. The resulting display frame frequency is given
7.10 SDA: serial data line
fosc
by fframe
=
------------
Pad SDA is input/output for the I2C-bus data line.
2304
A clock signal must always be present, otherwise the LCD
may be frozen in a DC state.
7.11 SA0: address input
The hardware subaddress line is used to program the
device subaddress for 2 different PCF2105s on the same
I2C-bus.
8.4
Power-on reset
The Power-on reset block initializes the chip after
power-on or power failure.
7.12 T1: test input
8.5
Registers
Pad T1 must be connected to VSS. Not user accessible.
The PCF2105 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select (RS) signal determines which register will be
accessed.
8
FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram for the PCF2105.
Details are explained in subsequent sections.
The IR stores instruction codes such as ‘clear display’ and
‘cursor shift’, and address information for the DDRAM
and CGRAM. The system controller can write data to but
can not read data from the instruction register.
8.1
LCD bias voltage generator
The intermediate bias voltages for the LCD are generated
on-chip. This removes the need for an external resistive
bias chain and significantly reduces the system power
consumption. The optimum levels depend on the multiplex
(MUX) rate and are selected automatically when the
number of lines in the display is defined.
The DR temporarily stores data to be read from the
DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
address counter) is written to the DR prior to being read by
the ‘read data’ instruction.
The optimum value of the LCD operating voltage VOP
depends on the MUX rate, the LCD threshold voltage Vth
and the number of bias levels. The relationships, together
with the discrimination ratio (D) are given in Table 1.
8.6
Busy flag
The Busy Flag (BF) indicates the free or busy status of the
PCF2105. Bit BF = 1 indicates that the chip is busy and
further instructions will not be accepted. The BF is output
at pad DB7 when bit RS = 0 and bit R/W = 1. Instructions
should only be written after checking that BF = 0 or waiting
for the required number of clock cycles.
Using a 5-level bias scheme for MUX rate 1 : 16 allows
VOP < 5 V for most LCDs. The effect on the display
contrast is negligible.
Table 1 Optimum values for VOP
8.7
Address Counter (AC)
NUMBER
OF BIAS
LEVELS
vOP
V on
MUX
RATE
The AC assigns addresses to the DDRAM and CGRAM for
reading and writing and is set by the instructions ‘set
CGRAM address’ and ‘set DDRAM address’. After a
read/write operation the AC is automatically incremented
or decremented by 1. The AC contents are output to the
bus (pads DB6 to DB0) when bit RS = 0 and bit R/W =1.
D =
---------
vth
---------
Voff
1 : 16
1 : 32
5
6
3.67
5.19
1.277
1.196
1998 Jul 30
6
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
8.8
Display Data RAM (DDRAM)
8.11 Cursor control circuit
The DDRAM stores up to 80 characters of display data,
represented by 8-bit character codes. DDRAM locations
not used for storing display data can be used as general
purpose RAM. The basic DDRAM-to-display mapping
scheme is shown in Fig.2. With no display shift, the
characters represented by the codes in the first
12 or 24 DDRAM locations, starting at address 00 in
line 1, are displayed. Subsequent lines display data
starting at addresses 20, 40, or 60 hexadecimal (hex).
Figures 3 and 4 show the DDRAM-to-display mapping
scheme when the display is shifted.
The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.7) at the DDRAM
address contained in the address counter. When the
address counter contains the CGRAM address the cursor
will be inhibited.
8.12 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and
4-line displays the end address of one line and the start
address of the next line are not successive. When the
display is shifted each line wraps around independently of
the others (see Figs 3 and 4).
8.13 LCD row and column drivers
The PCF2105 contains 32 row drivers and 60 column
drivers. They connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 8 and 9 show typical waveforms.
In the 1-line display (MUX rate 1 : 16), the row outputs are
driven in pairs, for example R1/R17 and R2/R18.
This allows the output pairs to be connected in parallel,
thereby providing greater drive capability.
When data is written to the DDRAM, wrap-around occurs
from 4F to 00 in 1-line display and from 27 to 40 and
67 to 00 in 2-line display; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line display.
Unused outputs should be left unconnected.
8.9
Character Generator ROM (CGROM)
The CGROM generates 240 character patterns in 5 × 8
dot format from 8-bit character codes. Figure 5 shows the
character set currently available.
8.10 Character Generator RAM (CGRAM)
Up to 16 user-defined characters may be stored in the
CGRAM. The CGROM and CGRAM use a common
address space, of which the first column is reserved for the
CGRAM (see Fig.5). Figure 6 shows the addressing
principle for the CGRAM.
1998 Jul 30
7
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
non-displayed DDRAM addresses
Display
Position
handbook, 4 columns
1
2
3
4
5
22 23 24
(decimal)
00 01 02 03 04
15 16 17 18 19
4C 4D 4E 4F
DDRAM
Address
(hex)
1-line display
non-displayed DDRAM address
24 25 26 27
00 01 02 03 04
40 41 42 43 44
15 16 17 18 19
55 56 57 58 59
line 1
line 2
DDRAM
Address
(hex)
64 65 66 67
MLA792
2-line display
non-displayed DDRAM addresses
9 10 11 12
handbook, 4 columns
1
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2
DDRAM
Address
(hex)
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
line 4
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
MLA793
4 line display
Fig.2 DDRAM-to-display mapping; no shift.
8
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Display
Position
(decimal)
Display
Position
(decimal)
1
2
3
4
5
22 23 24
16 17 18
1
2
3
4
5
22 23 24
14 15 16
01 02 03 04 05
4F 00 01 02 03
DDRAM
Address
(hex)
DDRAM
Address
(hex)
1-line display
1-line display
line 1
line 2
16 17 18
line 1
01 02 03 04 05
41 42 43 44 45
14 15 16
27 00 01 02 03
DDRAM
Address
(hex)
DDRAM
Address
(hex)
56 57 58
MLA815
67 40 41 42 43
54 55 56 line 2
MLA802
2-line display
2-line display
1
2
3
4
5
6
7
8
9 10 11 12
1
2
3
4
5
6
7
8 9 10 11 12
line 1
line 2
line 3
line 4
line 1
line 2
line 3
01 02 03 04 05 06 07 08 09 0A 0B 0C
21 22 23 24 25 26 27 28 29 2A 2B 2C
41 42 43 44 45 46 47 48 49 4A 4B 4C
13 00 01 02 03 04 05 06 07 08 09 0A
33 20 21 22 23 24 25 26 27 28 29 2A
53 40 41 42 43 44 45 46 47 48 49 4A
73 60 61 62 63 64 65 66 67 68 69 6A
DDRAM
DDRAM
Address
(hex)
Address
(hex)
61 62 63 64 65 66 67 68 69 6A 6B 6C
4-line display
line 4
MLA803
4-line display
MLA816
Fig.3 DDRAM-to-display mapping; right shift.
Fig.4 DDRAM-to-display mapping; left shift.
1998 Jul 30
9
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
CG
RAM 1
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MGK847
Fig.5 Character set ‘M’ in CGROM.
10
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
character codes
(DDRAM data)
CGRAM
address
character patterns
(CGRAM data)
7
6
5
4
3
2
1
0
0
6
0
5
4
3
2
1
0
4
3
2
1
0
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
character
pattern
example 1
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
character
pattern
example 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the
cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in this figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data is logic 1 corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction or
by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address’ instruction.
Fig.6 Relationship between CGRAM addresses, data and display patterns.
1998 Jul 30
11
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
MGA801
cursor
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.7 Cursor and blink display examples.
1998 Jul 30
12
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
frame n
frame n 1
state 1 (ON)
state 2 (ON)
V
DD
V
2
V /V
ROW 1
ROW 9
ROW 2
3
4
V
5
V
LCD
V
V
DD
2
V /V
3
4
1-line display
(1:16)
V
5
V
LCD
V
V
DD
2
V /V
3
4
V
5
V
LCD
V
V
DD
2
V /V
COL 1
3
4
V
5
V
LCD
V
V
DD
2
COL 2
V /V
4
3
5
V
V
LCD
V
OP
0.25 V
0 V
OP
OP
state 1
0.25 V
V
OP
V
OP
0.25 V
0 V
OP
OP
state 2
0.25 V
V
OP
MGA802 - 1
1
2
3
16
1
2
3
16
Fig.8 Typical LCD waveforms; 1-line display.
13
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
frame n
frame n 1
state 1 (ON)
state 2 (ON)
V
DD
V
2
V
3
V
ROW 1
4
V
5
V
LCD
V
DD
V
2
V
3
ROW 9
V
4
V
5
V
LCD
V
DD
V
2
V
3
V
2-line display
(1:32)
ROW 2
4
V
5
V
LCD
V
DD
V
2
V
3
COL 1
V
4
V
5
V
LCD
V
DD
V
2
V
3
COL 2
V
4
V
5
V
LCD
V
OP
0.15 V
OP
0 V
state 1
0.15 V
OP
V
OP
V
OP
0.15 V
state 2 0 V
0.15 V
OP
OP
V
OP
MGA803 - 1
123
32 12 3
32
Fig.9 Typical LCD waveforms; 2-line display.
14
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
To program the MUX rate 1 : 16, bits M and N of the
8.14 Programming of the MUX rate 1 : 16
‘function set’ instruction must be set to logic 0
(see Table 3). Figures 10, 11 and 12 show the DDRAM
addresses of the display characters. The second row of
each figure corresponds to either the right half of a 1-line
display or to the second line of a 2-line display. Wrap
around of data during display shift or when writing data is
non-standard.
With the MUX rate 1 : 16 the PCF2105 can be used in the
following ways:
• To drive a 1-line display of 24 characters
• To drive a 2-line display of 12 characters, resulting in
better contrast. The internal data flow of the chip is
optimized for this purpose.
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
09
11
0A
12
0B
00
01
02
03
04
05
06
07
08
display position
DDRAM address
13
14
15
0E
16
0F
17
10
18
11
19
12
20
13
21
14
22
15
23
16
24
17
0C
0D
MLB899
Fig.10 DDRAM-to-display mapping; no shift.
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
08
11
09
12
0A
4F
00
01
02
03
04
05
06
07
display position
DDRAM address
13
0B
14
15
16
0E
17
0F
18
10
19
11
20
12
21
13
22
14
23
15
24
16
0C
0D
MLB900
Fig.11 DDRAM-to-display mapping; right shift.
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
0A
11
0B
12
01
02
03
04
05
06
07
08
09
0C
display position
DDRAM address
13
14
0E
15
0F
16
10
17
11
18
12
19
13
20
14
21
15
22
16
23
17
24
18
0D
MLB901
Fig.12 DDRAM-to-display mapping; left shift.
15
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Instructions are of 4 categories, those that:
8.15 Programming of the MUX rate 1 : 32
1. Designate PCF2105 functions such as display format,
data length, etc.
With the MUX rate 1 : 32 the PCF2105 can be used in the
following ways:
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
• To drive a 2-line display of 24 characters, use instruction
‘function set’ to set bit M to logic 0 and bit N to logic 1
• To drive a 4-line display of 12 characters, use instruction
‘function set’ to set both bits M and N to logic 1.
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1 (or
decrementing by 1) of internal RAM addresses after each
data write lessens the microcontroller program load.
The display shift in particular can be performed
concurrently with display data write, thus enabling the
designer to develop systems in minimum time with
maximum programming efficiency.
8.16 Reset function
The PCF2105 automatically initializes (resets) when
power is turned on. The state after reset is given in Table 2
(see Tables 3 and 4 for the description of the bits).
Table 2 State after reset
During internal operation, no instruction other than the
‘read busy flag and address’ will be executed.
STEP
DESCRIPTION
1
2
clear display
function set:
Because the busy flag is set to logic 1 while an instruction
is being executed, it is advisable to ensure that the flag is
set to logic 0 before sending the next instruction or wait for
the maximum instruction execution time, as given in
Table 3. An instruction sent while the busy flag is HIGH will
not be executed.
bit DL = 1: 8-bit interface
bits M and N = 0: 1-line display
bit G = 0: not used
3
display control:
bit D = 0: display off
bit C = 0: cursor off
bit B = 0: blink off
9.1
Clear display
‘Clear display’ writes space code 20 (hexadecimal) into all
DDRAM addresses (the character pattern for character
code 20 must be a blank pattern), sets the DDRAM
address counter to logic 0 and returns the display to its
original position if it was shifted. Consequently, the display
disappears and the cursor or blink position goes to the left
edge of the display (the first line if 2 or 4 lines are
displayed) and sets bit I/D of ‘entry mode set’ to logic 1
(increment mode). Bit S of ‘entry mode set’ does not
change.
4
5
entry mode set:
bit I/D = 1: +1(increment)
bit G = 0: not used
default address pointer to DDRAM; the busy
flag indicates the busy state (BF = 1) until
initialization ends; the busy state lasts 2 ms;
the chip may also be initialized by software;
see Tables 10 and 11.
I2C-bus interface reset
The instruction ‘clear display’ requires extra execution
time. This may be allowed for checking the Busy Flag (BF)
or by waiting until 2 ms has elapsed. The latter must be
applied where no read-back options are available, as in
some Chip-On-Glass (COG) applications.
6
9
INSTRUCTIONS
Only two PCF2105 registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow
interface to various types of microcontrollers which
operate at different speeds or to allow interfacing to
peripheral control ICs. The PCF2105 operation is
controlled by the instructions shown in Table 3 together
with their execution time. Details are explained in
subsequent sections.
9.2
Return home
‘Return home’ sets the DDRAM address counter to logic 0
and returns the display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the display (the first line if
2 or 4 lines are displayed). Bits I/D and S of ‘entry mode
set’ do not change.
1998 Jul 30
16
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Table 3 Instructions (note 1)
REQUIRED
INSTRUCTION
NOP
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
no operation
CLOCK
CYCLES(2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Clear display
clears entire display and sets DDRAM
address 00 in Address Counter (AC)
165
Return home
0
0
0
0
0
0
0
0
1
0
sets DDRAM address 00 in the AC;
also returns shifted display to original
position; DDRAM contents remain
unchanged
3
Entry mode set
Display control
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I/D
C
S
B
sets cursor move direction and specifies
shift of display; these operations are
performed during data write and read
3
3
D
sets entire display on/off (D), cursor
on/off (C) and blink of cursor position
character (B)
Cursor/display shift
Function set
0
0
0
0
0
0
0
0
0
1
1
S/C
N
R/L
M
0
0
0
moves cursor and shifts display without
changing DDRAM contents
3
3
DL
G
sets interface data length (DL), number
of display lines (N, M) and voltage
generator control (G); bit G is not used
Set CGRAM
address
0
0
0
0
0
1
0
1
1
ACG
sets CGRAM address
3
3
0
Set DDRAM
address
ADD
AC
sets DDRAM address
Read busy flag and
address
BF
reads BF indicating internal operation is
being performed and reads AC contents
Read data
Write data
1
1
1
0
read data
write data
reads data from CGRAM or DDRAM
writes data to CGRAM or DDRAM
3
3
Notes
1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I2C-bus mode a control byte is required when bit RS or R/W is changed;
control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.
1
fosc
2. Example: fosc = 150 kHz, Tcy
=
= 6.67 µs ; 3 cycles = 20 µs; 165 cycles = 1.1 ms.
--------
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Table 4 Command bit identities, used in Table 3
BIT
LOGIC 0
LOGIC 1
I/D
S
decrement
display freeze
display off
cursor off
increment
display shift
display on
cursor on
D
C
B
character at cursor position does not blink
character at cursor position blinks
S/C
R/L
DL
cursor move
display shift
right shift
8 bits
left shift
4 bits
N (M = 0)
N (M = 1)
BF
2 lines × 12 characters; MUX rate 1 : 16
reserved
2 lines × 24 characters; MUX rate 1 : 32
4 lines × 12 characters; MUX rate 1 : 32
internal operation in progress
end of internal operation
last control byte, only data bytes to follow
Co
next two bytes are a data byte and another control byte
9.3
9.3.1
Entry mode set
I/D
9.4.3
B
The character indicated by the cursor blinks when
bit B = 1. The blink is displayed by switching between
display characters and all dots on with a period of
1 second when fosc = 150 kHz (see Fig.7).
When bit I/D = 1 (0), the DDRAM or CGRAM address
increments (decrements) by 1 when data is written to or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor and blink are inhibited
when the CGRAM is accessed.
At other clock frequencies the blink period is equal to
150 kHz
---------------------
fosc
The cursor and the blink can be set to display
simultaneously.
9.3.2
S
When bit S = 1, the entire display shifts either to the right
(bit I/D = 0) or to the left (I/D = 1) during a DDRAM write.
Consequently, it looks as if the cursor stands still and the
display moves. The display does not shift when reading
from the DDRAM, or when writing to or reading from the
CGRAM. When S = 0 the display does not shift.
9.5
Cursor/display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In the 2 or 4-line display,
the cursor moves to the next line when it passes the last
position of the line (40 or 20 decimal). When the displayed
data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the cursor shift.
9.4
Display control
9.4.1
D
The display is on when bit D = 1 and off when D = 0.
Display data in the DDRAM is not affected and can be
displayed immediately by setting D to logic 1.
9.4.2
C
The cursor is displayed when bit C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions,
I/D, etc. remain in operation during display data write.
The cursor is displayed using 5 dots in the 8th line
(see Fig.7).
1998 Jul 30
18
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
9.6
Function set
9.9
Read busy flag and address
‘Read busy flag and address’ reads the Busy Fag (BF).
When bit BF = 1 it indicates that an internal operation is in
progress. The next instruction will not be executed until
BF = 0, so BF should be checked before sending another
instruction.
9.6.1
DL (PARALLEL MODE ONLY)
Bit DL sets the interface data length. Data is sent or
received in bytes (DB7 to DB0) when DL = 1 or in two
nibbles (DB7 to DB4) when DL = 0. When 4-bit length is
selected, data is transmitted in two cycles using the
parallel bus. In a 4-bit application DB3 to DB0 are left open
(internal pull-ups).
At the same time, the value of the AC expressed in binary
A[6] to A[0] is read out. The address counter is used by
both CGRAM and DDRAM and its value is determined by
the previous instruction.
DL can not be set to logic 0 from the I2C-bus interface.
If DL has been set to logic 0 via the parallel bus,
programming via the I2C-bus interface is complicated.
9.10 Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data (D[7] to D[0]) to the
CGRAM or the DDRAM.
9.6.2
N AND M
Bits N and M set the number of display lines.
Whether the CGRAM or DDRAM is to be written to is
determined by the previous specification of CGRAM or
DDRAM address setting. After writing, the address
automatically increments or decrements by 1, in
accordance with the ‘entry mode set‘.
9.7
Set CGRAM address
‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM
address (ACG in Table 3) into the AC (binary A[5] to A[0]).
Data can then be written to or read from the CGRAM.
Only bits D[4] to D[0] of CGRAM data are valid,
bits D[7] to D[5] are ‘don’t care’.
Only bits 0 to 5 of the CGRAM address are set by the ‘set
CGRAM address’ instruction. Bit 6 can be set using the
‘set DDRAM address’ instruction or by using the
auto-increment feature during CGRAM write. All bits 0 to 6
can be read using the ‘read busy flag and address’
instruction.
9.11 Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D[7] to D[0] from the
CGRAM or DDRAM.
The most recent ‘set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
9.8
Set DDRAM address
The ‘read data’ instruction gates the content of the
Data Register (DR) to the bus while pad E = HIGH. After E
goes LOW again, internal operation increments
(or decrements) the AC and stores RAM data
corresponding to the new AC into the DR.
‘Set DDRAM address’ sets the DDRAM address (ADD in
Table 3) into the AC (binary A[6] to A[0]). Data can then be
written to or read from the DDRAM.
Table 5 Hexadecimal address ranges
Remark: the only three instructions that update the DR are:
• ‘Set CGRAM address’
ADDRESS
00 to 4F
FUNCTION
1 line of 24 characters
2 lines of 12 characters
2 lines of 24 characters
• ‘Set DDRAM address’
00 to 0B and 0C to 4F
00 to 27 and 40 to 67
• ‘Read data’ from CGRAM or DDRAM.
00 to 13, 20 to 33, 40 to 53 4 lines of 12 characters
and 60 to 73
Other instructions (e.g. ‘write data’, ‘cursor/display shift’,
‘clear display’, ‘return home’) will not change the data
register content.
1998 Jul 30
19
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data
transfer is complete after two 4-bit data transfers. It should
be noted that two cycles are also required for the busy flag
check. The 4-bit mode is selected by instruction.
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2105 can send data in either two 4-bit modes or
one 8-bit mode and can thus interface to 4 or 8-bit
microcontrollers.
See Figs 13, 14 and 15 for examples of bus protocol.
In the 8-bit mode data is transferred as 8-bit bytes using
the 8 data lines DB7 to DB0. The control lines E, RS,
and R/W are required.
In the 4-bit mode, the pads DB3 to DB0 must be left
open-circuit. They are pulled up to VDD internally.
In the 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB7 to DB4
RS
R/W
E
DB7
DB6
DB5
DB4
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
BF
AC3
AC2
AC1
AC0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
AC6
AC5
AC4
busy flag and
address counter read
data register
read
instruction
write
MGA804
Fig.13 4-bit transfer example.
20
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
RS
R/W
E
internal
internal operation
not
busy
DB7
IR7
IR3
AC3
AC3
D7
D3
busy
instruction
write
busy flag
check
busy flag
check
instruction
write
MGA805
IR7 and IR3: instruction 7th bit and 3rd bit.
AC3: address counter 3rd bit.
Fig.14 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
not
busy
data
busy
busy
data
DB7
instruction
write
busy flag
check
busy flag
check
busy flag
check
instruction
write
MGA806
Fig.15 Example of busy flag check timing sequence.
21
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
11 INTERFACE TO MICROCONTROLLER (I2C-BUS
INTERFACE)
11.5 Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of 8 bits is followed by an
11.1 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, 2-line communication
between different ICs or modules. The 2 lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
acknowledge bit. The acknowledge bit is a HIGH signal put
on the bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition (see Fig.19).
11.2 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH-level period of the clock pulse as changes in the
data line at this time will be interpreted as a control signal
(see Fig.16).
11.3 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.17).
11.6 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C-bus configuration for the different
PCF2105 read and write cycles is illustrated in
Figs 20, 21 and 22.
11.4 System configuration
A device generating a message is a transmitter, a device
receiving a message is the receiver. The device that
controls the message is the master and the devices which
are controlled by the master are the slaves (see Fig.18).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.16 Bit transfer.
22
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBC622
Fig.17 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.18 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.19 Acknowledgement on the I2C-bus.
23
1998 Jul 30
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acknowledgement
from PCF2105
S
A
0
0
1
1
1
0
1
0
A
1
CONTROL BYTE
A
DATA
A
0
CONTROL BYTE
1 byte
A
DATA
A
P
S
slave address
2n ≥ 0 bytes
n ≥ 0 bytes
update
data pointer
R/W
Co
Co
S
A
0
0
1
1
1
0
1
0
MGK848
PCF2105
slave address
R/W
Fig.20 Master transmits to slave receiver; write mode.
ahdnbok,uflapegwidt
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acknowledgement
from PCF2105
S
A
0
(1)
0
1
1
1
0
1
1
CONTROL BYTE
DATA
0
1
1
CONTROL
DATA
0
A
A
A
A
A
S
slave address
2 bytes
2n ≥ 0 bytes
R/W
Co
Co
acknowledgement
from PCF2105
no acknowledgement
from master
S
A
0
SLAVE
ADDRESS
1
A
DATA
A
DATA
1
P
S
n bytes
last byte
R/W
update
MGK849
data pointer
(1) Last data byte is a dummy byte (may be omitted).
Fig.21 Master reads after setting word address; write word address, set RS and R/W; read data.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
acknowledgement
from PCF2105
acknowledgement
from master
no acknowledgement
from master
S
A
0
SLAVE
ADDRESS
1
A
DATA
A
DATA
1
S
P
last byte
n bytes
R/W
update
data pointer
MGK850
Fig.22 Master reads slave immediately after first byte; read mode (RS previously defined).
12 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.5
MAX.
+8.0
VDD
UNIT
VDD
VLCD
VI(n)
VO(n)
II(n)
logic supply voltage
LCD supply voltage
V
V
V
V
V
V
V
DD − 11
input voltage on pads OSC, RS, R/W, E and DB0 to DB7
output voltage on pads R1 to R32, C1 to C60 and VLCD
DC input current on every pad
SS − 0.5 VDD + 0.5
LCD − 0.5 VDD + 0.5
−10
−10
−50
−
+10
+10
+50
400
100
+150
mA
mA
mA
mW
mW
°C
IO(n)
In
DC output current on every pad
current on VDD, VSS and VLCD
Ptot
total power dissipation
P/out
Tstg
power dissipation per output
−
storage temperature
−65
13 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1998 Jul 30
26
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
14 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
UNIT
Supplies
VDD
logic supply voltage
2.5
−
6.0
V
VLCD
LCD supply voltage
V
−
−
DD − 9
−
VDD − 3.5 V
IDD(ext)
external supply current
note 1
VDD = 5 V; VOP = 9 V;
osc = 150 kHz;
Tamb = 25 °C
DD = 3 V; VOP = 5 V;
osc = 150 kHz;
200
200
500
300
µA
µA
f
V
f
−
150
200
µA
Tamb = 25 °C
II(LCD)
VPOR
input current on VLCD
note 1
−
−
50
100
1.8
µA
Power-on reset voltage level
note 2
1.3
V
Logic
VIL
LOW-level input voltage on pads E,
RS, R/W, DB7 to DB0 and SA0
VSS
−
−
−
0.3VDD
VDD
V
V
VIH
HIGH-level input voltage on pads E,
RS, R/W, DB7 to DB0 and SA0
0.7VDD
VIL(OSC)
VIH(OSC)
Ipu
LOW-level input voltage on pad OSC
HIGH-level input voltage on pad OSC
VSS
VDD − 1.5 V
VDD − 0.1 −
VDD
1.00
V
pull-up current on pads DB7 to DB0,
RS and R/W
pads set to logic 0 (VSS
VOL = 0.4 V; VDD = 5 V
VOH = 4 V; VDD = 5 V
)
0.04
0.15
µA
IOL(DB)
IOH(DB)
IL
LOW-level output current on
pads DB7 to DB0
1.6
−1.0
−1
−
−
−
−
mA
mA
µA
HIGH-level output current on
pads DB7 to DB0
−
leakage current on pads DB7 to DB0, pads set to logic 0 (VSS
)
+1
OSC, E, RS, R/W and SA0
or logic 1 (VDD
)
I2C-bus
SDA and SCL
VIL
VIH
IL
LOW-level input voltage
note 3
note 3
VSS
−
−
−
0.3VDD
VDD
V
HIGH-level input voltage
leakage current
0.7VDD
−1
V
pads set to logic 0 (VSS
)
+1
µA
or logic 1 (VDD
)
Ci
input capacitance
note 4
−
−
−
7
pF
IOL(SDA)
LOW-level output current on SDA
VOL = 0.4 V; VDD = 5 V
3
−
mA
1998 Jul 30
27
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LCD outputs
Ro(ROW)
Ro(COL)
Vbias(tol)
row output resistance on
pads R32 to R1
note 5
note 5
note 6
−
−
−
1.5
3
3
6
kΩ
kΩ
mV
column output resistance on
pads C60 to C1
bias voltage tolerance on
±20
±130
pads R32 to R1 and C60 to C1
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive; internal or external clock with duty factor 50%.
2. Resets all logic when VDD < VPOR
.
3. When the voltages are above VDD or below VSS, an input current may flow; this current must not exceed ±0.5 mA.
4. Tested on sample basis.
5. Resistance of output terminals (R32 to R1 and C60 to C1) with load current IL = 150 µA; VOP = VDD − VLCD = 9 V;
outputs measured one at a time.
6. LCD outputs open-circuit.
15 AC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
ffr(LCD)
fosc
PARAMETER
CONDITIONS
note 1
MIN.
40
90
TYP.
MAX. UNIT
LCD frame frequency (internal clock)
oscillator frequency (external clock)
65
100
225
Hz
150
kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2105); see Fig.23
Tcy(en)
tW(en)
tsu(A)
th(A)
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
220
50
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
25
tsu(D)
th(D)
60
25
READ OPERATION (READING DATA FROM PCF2105 TO MICROCONTROLLER); see Fig.24
Tcy(en)
tW(en)
tsu(A)
th(A)
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
500
220
50
25
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
−
−
−
td(D)
150
100
th(D)
data hold time
20
1998 Jul 30
28
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Timing characteristics: I2C-bus interface; note 2; see Fig.25
fSCL
SCL clock frequency
tolerable spike width on bus
bus free time
−
−
−
−
−
−
400
50
−
kHz
ns
tSW
tBUF
1.3
0.6
µs
tSU;STA
set-up time for a repeated START
condition
−
µs
tHD;STA
tLOW
tHIGH
tr
START condition hold time
SCL LOW time
0.6
1.3
0.6
−
−
−
µs
µs
µs
ns
ns
ns
µs
µs
pF
−
−
SCL HIGH time
−
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
note 3
20 + RCL
300
300
−
tf
note 3
−
20 + RCL
tSU;DAT
tHD;DAT
tSU;STO
CL
note 4
100
0
−
−
−
−
data hold time
notes 5 and 6
0.9
−
set-up time for STOP condition
load capacitance for each bus line
0.6
−
400
Notes
1. VDD = 5.0 V.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
3. CL = total capacitance of one bus line in pF and R = 100 Ω.
4. A fast mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line
is released.
5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
6. The maximum tHD;DAT has only to be met if the device does not stretch tLOW of the SCL signal.
1998 Jul 30
29
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
16 TIMING DIAGRAMS
RS
V
V
V
V
IH
IL
IH
IL
t
t
t
su(A)
h(A)
V
R/W
V
IL
IL
t
h(A)
W(en)
V
V
IH
IH
V
V
E
IL
IL
V
IL
t
h(D)
t
su(D)
V
V
V
V
IH
IL
IH
IL
valid data
DB0 to DB7
MGK851
T
cy(en)
Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2105.
V
V
V
V
IH
IL
IH
IL
RS
t
t
t
su(A)
h(A)
V
V
IH
IH
R/W
t
W(en)
h(A)
V
t
V
IH
IH
E
V
V
V
IL
IL
IL
d(D)
t
h(D)
V
V
V
V
OH
OL
OH
OL
DB0 to DB7
MGK852
T
cy(en)
Fig.24 Parallel bus read operation sequence; reading data from PCF2105 to microcontroller.
30
1998 Jul 30
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START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 0
LSB
R/W
STOP
CONDITION
(P)
BIT 6
(A6)
ACKNOWLEDGE
(A)
PROTOCOL
SDA
t
t
t
r
BUF
LOW
SCL
t
t
HD;STA
f
t
SU;STO
t/f
SCL
MGA811 - 1
t
HIGH
2
ahdnbok,uflapegwidt
Fig.25 I C-bus timing diagram; rise and fall times refer to VIL and VIH.
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
17 APPLICATION INFORMATION
handbook, 4 columns
RS
R/W
E
P20
P21
P22
32
60
R1 to R32
to
LCD
PCF2105
P80CL51
C1 to C60
DB0 to DB7
8
P10 to P17
MGK853
Fig.26 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
RS
R/W
E
P10
P11
P12
32
60
R1 to R32
to
LCD
P80CL51
PCF2105
C1 to C60
DB4 to DB7
4
P14 to P17
MGK854
Fig.27 Direct connection to 8-bit microcontroller; 4-bit bus.
16
V
V
LCD
R7 to R16
LCD
R25 to R32
100 nF
V
V
DD
DD
2 x 24-CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
R1 to R8
R17 to R24
OSC
16
100
nF
PCF2105
60
60
C1 to C60
V
V
SS
SS
MGK855
60
8
DB0 to DB7 E RS R/W
Fig.28 Typical application using parallel interface.
32
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
16
V
V
V
R1 to R16
LCD
100 nF
LCD
V
DD
2 x 24-CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
DD
R17 to R24
OSC
16
100
nF
PCF2105
60
60
C1 to C60
V
V
DD DD
V
V
SS
SS
SCL SDA SA0
V
DD
V
V
LCD
LCD
100 nF
V
V
DD
DD
2 x 12-CHARACTER
LCD DISPLAY
R1 to R16
OSC
16
100
nF
PCF2105
60
C1 to C60
MGK856
V
V
SS
SS
SA0
SCL SDA
V
SS
SCL SDA
MASTER TRANSMITTER
PCF84C81
Fig.29 Application using I2C-bus interface.
33
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
17.1 4-bit operation, 2 × 12 display using internal
17.3 8-bit operation, 2 × 24 display
reset
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the 8th
character is completed (see Table 8). It should be noted
that both lines of the display are always shifted together,
data does not shift from one line to the other.
The program must set functions prior to 4-bit operation.
Table 6 shows an example. When power is turned on, 8-bit
operation is automatically selected and the PCF2105
attempts to perform the first write as an 8-bit operation.
Since nothing is connected to DB3 to DB0, a rewrite is
then required. However, since one operation is completed
in two accesses of 4-bit operation, a rewrite is required to
set the functions (see Table 6 step 3).
17.4 I2C-bus operation, 2 × 12 display
Thus, DB7 to DB4 of the ‘function set’ are written twice.
A control byte is required with most instructions
(see Table 9).
17.2 8-bit operation, 2 × 12 display using internal
reset
17.5 Initializing by instruction
Table 7 shows an example of a 1-line display in 8-bit
operation. The PCF2105 functions must be set by the
‘function set’ instruction prior to display. Since the DDRAM
can store data for 80 characters, the RAM can be used for
advertising displays when combined with display shift
operation. Since the display shift operation changes the
display position only DDRAM contents remain unchanged.
Display data entered first can be displayed when the
‘return home’ instruction is performed.
If the power supply conditions for correctly operating the
internal reset circuit are not met, the PCF2105 must be
initialized by instruction. Tables 10 and 11 show how this
may be performed for 8-bit and 4-bit operation.
1998 Jul 30
34
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Table 6 Example of 4-bit operation; 1-line display; using internal reset
STEP
INSTRUCTION
DISPLAY
OPERATION
initialized; no display appears
1
power supply on (PCF2105 is
initialized by the internal reset
circuit)
2
3
function set
sets to 4-bit operation; in this instance operation is handled
as 8-bits by initialization and only this instruction completes
with one write
RS R/W DB7 DB6 DB5 DB4
0
0
0
0
1
0
function set
RS R/W DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
1
0
0
0
sets to 4-bit operation; selects 2 × 12 display
4-bit operation starts from this point and resetting is needed
4
5
display control
RS R/W DB7 DB6 DB5 DB4
0
0
0
0
0
1
0
1
0
1
0
0
_
_
turns display and cursor on
entire display is blank after initialization
entry mode set
RS R/W DB7 DB6 DB5 DB4
0
0
0
0
0
0
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the
DDRAM or CGRAM
0
0
0
1
1
0
display is not shifted
6
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4
1
0
1
1
0
1
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on
1
0
0
1
1
0
the cursor is incremented by 1 and shifted to the right
1998 Jul 30
35
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Table 7 Example of 8-bit operation; 1-line display; using internal reset (character set ‘M’)
STEP
INSTRUCTION
DISPLAY
OPERATION
initialized; no display appears
1
power supply on (PCF2105 is initialized by the internal reset
function)
2
3
4
5
6
function set
sets to 8-bit operation; selects 2 × 12 display
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
0
0
0
0
display control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
_
_
turns display and cursor on; entire display is blank after
initialization
0
0
0
0
0
0
1
1
1
0
entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of the write to the DDRAM or CGRAM;
display is not shifted
0
0
0
0
0
0
0
1
1
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1 and
shifted to the right
1
0
1
1
0
1
0
0
0
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PH_
writes ‘H’
1
0
1
1
0
0
1
0
0
0
7
8
|
|
|
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PHILIPS_
PHILIPS_
HILIPS_
writes ‘S’
1
0
1
1
0
1
0
0
1
1
9
entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
sets mode for display shift at the time of write
0
0
0
0
0
0
0
1
1
1
10
11
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
writes space
writes ‘M’
1
0
0
0
1
0
0
0
0
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ILIPS M_
1
0
1
1
0
0
1
1
0
1
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STEP
INSTRUCTION
DISPLAY
OPERATION
12
|
|
|
13
14
15
16
17
18
19
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MICROKO
MICROKO
MICROKO
ICROCO
writes ‘O’
1
0
1
1
0
0
1
1
1
1
cursor or display shift
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
shifts only the cursor position to the left
shifts only the cursor position to the left
writes ‘C’ (correction); the display moves to the left
shifts the display and cursor to the right
0
0
0
0
0
1
0
0
0
0
cursor or display shift
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
0
0
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
1
0
0
0
0
1
1
cursor or display shift
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MICROCO
0
0
0
0
0
1
1
1
0
0
cursor or display shift
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MICROCO_ shifts only the cursor to the right
ICROCOM_ writes ‘M’
0
0
0
0
0
1
0
1
0
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
1
0
0
1
1
0
1
20
21
|
|
|
return home
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PHILIPS M returns both display and cursor to the original position
(address 0)
0
0
0
0
0
0
0
0
1
0
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Table 8 Example of 8-bit operation; 2-line display; using internal reset
STEP
INSTRUCTION
DISPLAY
OPERATION
initialized; no display appears
1
power supply on (PCF2105 is initialized by the internal reset
function)
2
3
4
5
function set
sets to 8-bit operation; selects 2 × 24 display
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
0
0
0
display control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
turns display and cursor on; entire display is blank after
initialization
0
0
0
0
0
0
1
1
1
0
entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
_
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the CGRAM or DDRAM;
display is not shifted
0
0
0
0
0
0
0
1
1
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1 and
shifted to the right
1
0
1
1
0
1
0
0
0
0
6
7
|
|
|
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PHILIPS_
writes ‘S’
1
0
1
1
0
1
0
0
1
1
8
9
set DDRAM address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 _
PHILIPS
sets DDRAM address to position the cursor at the head of the
2nd line
0
0
1
1
0
0
0
0
0
0
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M_
PHILIPS
writes ‘M’
1
0
1
1
0
0
1
1
0
1
10
11
|
|
|
write data to CGRAM or DDRAM
PHILIPS
writes ‘O’
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_
1
0
1
1
0
0
1
1
1
1
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STEP
INSTRUCTION
write data to CGRAM or DDRAM
DISPLAY
PHILIPS
OPERATION
12
sets mode for display shift at the time of write
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_
0
0
0
0
0
0
0
1
1
1
13
write data to CGRAM or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ICROCOM_
HILIPS
writes ‘M’; display is shifted to the left; the first and second lines
shift together
1
0
1
1
0
0
1
1
0
1
14
15
|
|
|
return home
PHILIPS
returns both display and cursor to the original position
(address 0)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCOM
0
0
0
0
0
0
0
0
1
0
Table 9 Example of I2C-bus operation; 1-line display; using internal reset (assuming SA0 = VSS); note 1
STEP
INSTRUCTION
DISPLAY
OPERATION
initialized; no display appears
1
2
I2C-bus start
slave address for write
during the acknowledge cycle SDA will be pulled-down by the
PCF2105
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
1
1
1
0
1
0
0
1
3
4
5
6
send a control byte for function set
control byte sets RS and R/W for following data bytes
Co
RS
0
R/W Ack
0
0
1
function set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
selects 1-line display; SCL pulse during acknowledge cycle
starts execution of instruction
0
0
1
X
0
0
0
0
1
display control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
_
_
turns display and cursor on; entire display shows character
hexadecimal 20 (blank in ASCII-like character sets)
0
0
0
0
1
1
1
0
1
entry mode set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM;
display is not shifted
0
0
0
0
0
1
1
0
1
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STEP
INSTRUCTION
DISPLAY
OPERATION
7
I2C-bus start
_
_
for writing data to DDRAM, RS must be set to logic 1; therefore
a control byte is needed
8
9
slave address for write
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
1
1
1
0
1
0
0
1
send a control byte for write data
_
Co
RS
1
R/W Ack
0
0
1
10
11
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
P_
writes ‘P’; the DDRAM has been selected at power-up;
the cursor is incremented by 1 and shifted to the right
1
1
0
1
0
0
0
0
1
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
PH_
writes ‘H’
1
1
0
0
1
0
0
0
1
12
to
15
|
|
|
|
16
write data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
PHILIPS_
writes ‘S’
1
1
0
1
0
0
1
1
1
17
18
(optional I2C-bus stop) I2C-bus start + slave address for
write (as step 8)
PHILIPS_
PHILIPS_
control byte
Co
RS
0
R/W Ack
1
0
1
19
20
21
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
PHILIPS
PHILIPS
PHILIPS
sets DDRAM address 0 in AC; also returns shifted display to
original position; DDRAM contents unchanged; this instruction
does not update the DR
0
0
0
0
0
0
1
0
1
control byte for read
DDRAM content will be read from following instructions;
the R/W has to be set to logic 1 while still in I2C-bus write mode
Co
RS
R/W Ack
0
1
1
1
I2C-bus start
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STEP
INSTRUCTION
DISPLAY
PHILIPS
OPERATION
22
slave address for read
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
during the acknowledge cycle the content of the DR is loaded
into the internal I2C-bus interface and to be shifted out; in the
previous instruction neither a ‘set address’ nor a ‘read data’ has
been performed; therefore the content of the DR was unknown
0
1
1
1
0
1
0
1
1
23
read data: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
PHILIPS
8 × SCL; content loaded into interface during previous
acknowledge cycle and shifted out over SDA; MSB is DB7;
during master acknowledge content of DDRAM address 01 is
loaded into the I2C-bus interface
X
X
X
X
X
X
X
X
1
24
25
read data: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
PHILIPS
PHILIPS
8 × SCL; code of letter ‘H’ is read first; during master
acknowledge code of letter ‘I’ is loaded into the I2C-bus
interface
0
1
0
0
1
0
0
0
0
read data: 8 × SCL + no master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
no master acknowledge; after the content of the I2C-bus
interface register is shifted out no internal action is performed;
no new data is loaded to the interface register; DR is not
updated; AC is not incremented and cursor is not shifted
0
1
0
0
1
0
0
1
1
26
I2C-bus stop
PHILIPS
Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Table 10 Initialization by instruction; 8-bit interface (note 1)
STEP
DESCRIPTION
Power-on or unknown state
|
Wait 2 ms after VDD rises above VPOR
|
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function
set (interface is 8-bits long)
0
0
0
1
1
X
X
X
X
|
Wait 2 ms
|
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function
set (interface is 8-bits long)
0
0
0
1
1
X
X
X
X
|
Wait more than 40 µs
|
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function
set (interface is 8-bits long)
0
0
0
1
1
X
X
X
X
|
|
|
|
BF can be checked after the following instructions;
when BF is not checked, the waiting time between
instructions is the specified instruction time
(see Table 3)
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8-bits long); specify the
number of display lines
0
0
0
1
1
N
M
X
0
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display off
0
0
0
0
0
1
0
0
0
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 clear display
0
0
0
0
0
0
0
0
1
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 entry mode set
0
0
0
0
0
0
1
I/D
S
|
Initialization ends
Note
1. X = don’t care.
1998 Jul 30
42
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Table 11 Initialization by instruction; 4-bit interface; not applicable for I2C-bus operation
STEP
DESCRIPTION
Power-on or unknown state
|
Wait 2 ms after VDD rises above VPOR
|
RS
0
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits
long)
0
0
0
1
1
|
Wait 2 ms
|
RS
0
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits
long)
0
0
0
1
1
|
Wait 40 µs
|
RS
0
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits
long)
0
0
0
1
1
|
|
|
BF can be checked after the following instructions; when BF is not checked,
the waiting time between instructions is the specified instruction time
(see Table 3)
RS
0
R/W DB7 DB6 DB5 DB4 function set (set interface to 4-bits long); interface is 8-bits long
0
0
0
1
0
RS
0
R/W DB7 DB6 DB5 DB4 function set (interface is 4-bits long)
0
0
0
1
0
RS
0
R/W DB7 DB6 DB5 DB4 specify number of display lines and voltage generator characteristic
0
N
M
0
0
RS
0
R/W DB7 DB6 DB5 DB4 display off
0
0
0
1
0
0
0
0
0
0
0
RS
0
R/W DB7 DB6 DB5 DB4 clear display
0
0
0
1
0
0
0
0
0
0
0
RS
0
R/W DB7 DB6 DB5 DB4 entry mode set
0
0
0
0
0
1
0
0
0
I/D
S
|
Initialization ends
1998 Jul 30
43
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
18 BONDING PAD LOCATIONS
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
58
57
56
55
54
53
52
51
50
R15 87
R16 88
R25 89
R26 90
R27
R28
91
92
R1 93
R2
R3 95
R4
94
49
48
47
96
SCL 97
98
E
46 C35
45 C36
44 C37
43 C38
42 C39
41 C40
40 C41
39 C42
38 C43
37 C44
36 C45
35 C46
34 C47
33 C48
32 C49
31 C50
30 C51
29 C52
28 C53
RS 99
100
101
R/W
T1
x
≈ 5.63
mm
0
0
y
DB7 102
DB6 103
DB5
DB4
104
105
PCF2105
DB3 106
DB2 107
DB1 108
DB0 109
SDA 110
V
111
LCD
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
MGK857
≈ 5.10 mm
Chip dimensions: approximately 5.10 × 5.63 mm.
Gold bump dimensions: approximately 89 × 89 × 25 µm.
Fig.30 Bonding pad locations.
44
1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Table 12 Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to centre of chip,
see Fig.30.
SYMBOL
OSC
PAD
x
y
SYMBOL
C42
PAD
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
x
y
1
−2184.5
−2024.5
−1864.5
−1704.5
−1339
−1179
−1019
−859
−699
−539
−379
−219
−59
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2445
−2285
−2125
−1965
−1805
−1645
−1485
−1325
−1165
−1005
−845
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2185
2025
1865
1705
1545
1385
1225
1065
905
−685
VDD
SA0
VSS
R8
2
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
−525
3
−365
4
−205
5
−45
R7
6
115
R6
7
275
R5
8
435
R32
R31
R30
R29
R24
R23
R22
R21
R20
R19
R18
R17
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
9
595
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
755
915
1075
1235
101
1395
261
1555
421
1715
581
1875
741
2035
901
2195
1061
1221
1381
1541
1701
1861
2021
2181
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2355
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
745
585
425
265
105
C8
−55
C7
−215
−375
−535
C6
C5
1998 Jul 30
45
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL
C4
PAD
x
y
77
78
−695
−855
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2308
C3
C2
79
−1015
−1175
−1385
−1545
−1705
−1865
−2025
−2185
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2327.5
−2027.5
1982.5
C1
80
R9
81
R10
R11
82
83
R12
R13
R14
R15
R16
R25
R26
R27
R28
R1
84
85
86
87
88
2148
89
1988
90
1828
91
1668
92
1508
93
1348
R2
94
1188
R3
95
1028
R4
96
868
SCL
E
97
632
98
472
RS
99
312
R/W
T1
100
101
102
103
104
105
106
107
108
109
110
111
−
142
−34
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDA
VLCD
RECPAT ‘F’
RECPAT ‘C’
RECPAT ‘C’
−233
−393
−668
−828
−1103
−1263
−1538
−1698
−1933
−2453
2427.5
−2512.5
2297.5
−
−
1998 Jul 30
46
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 30
47
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/02/pp48
Date of release: 1998 Jul 30
Document order number: 9397 750 04198
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