PCF2113DU/2/F4 [NXP]
LCD controllers/drivers; LCD控制器/驱动器
| 型号： | PCF2113DU/2/F4 |
| 厂家： | 
NXP |
| 描述： | LCD controllers/drivers |
| 文件： | 总65页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF2113x
LCD controllers/drivers
Rev. 04 — 4 March 2008
Product data sheet
1. General description
The PCF2113x is a low-power CMOS LCD controller and driver, designed to drive a dot
matrix LCD display of 2 lines of 12 characters or 1 line of 24 characters with 5 × 8 dot
format. All necessary functions for the display are provided in a single chip, including
on-chip generation of LCD bias voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2113x interfaces to most
microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a
character generator and displays alphanumeric and kana (Japanese) characters.
The letter ‘x’ in PCF2113x characterizes the built-in character set. Various character sets
can be manufactured on request.
2. Features
I Single-chip LCD controller/driver
I 2-line display of up to 12 characters + 120 icons, or 1-line display of up to
24 characters + 120 icons
I 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user-defined
symbols
I Icon mode for e.g. additional segment display section: reduced current consumption
while displaying icons only
I Icon blink function
I Very low current consumption (20 µA to 200 µA):
N Icon mode: < 25 µA
N Power-down mode: < 2 µA
I On-chip:
N Configurable 4, 3 or 2 voltage multiplier, generating LCD supply voltage VLCD
,
independent of VDD, programmable by instruction (external supply also possible)
N Temperature compensation of on-chip generated VLCD: −0.16 %/K to −0.24 %/K
(programmable by instruction)
N Generation of intermediate LCD bias voltages
N Oscillator requires no external components (external clock also possible)
I Display data RAM: 80 characters
I Character generator ROM: 240 characters of 5 × 8 dots
I Character generator RAM: 16 characters of 5 × 8 dots; 3 characters used to drive
120 icons, 6 characters used if icon blink feature is used in application
I 4-bit or 8-bit parallel bus and 2-wire I2C-bus interface
I 18 row and 60 column outputs
PCF2113x
NXP Semiconductors
LCD controllers/drivers
I Multiplex rates (MUX) 1:18 (for normal operation), 1:9 (for single-line operation) and
1:2 (for Icon-only mode)
I Uses common 11 code instruction set (extended)
I Logic supply voltage range VDD1 − VSS1 = 1.8 V to 5.5 V (chip may be driven with two
battery cells)
I VLCD generator supply voltage range VDD2 − VSS2 = 2.2 V to 4.0 V
I Display supply voltage range VLCD − VSS2 = 2.2 V to 6.5 V
I Direct mode to save current consumption for Icon mode and MUX 1:9 (depending on
VDD2 and LCD liquid properties)
I CMOS compatible
I Remark: Icon mode is a way to save current. When only icons are displayed (i.e. only
the lower two rows are active), a much lower operating voltage VLCD can be used and
the switching frequency of the LCD outputs is reduced. In most applications it is
possible to use VDD as VLCD
.
3. Applications
I Telecom equipment
I Point-of-sale terminals
I Portable instruments
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF2113AU/10/F4
PCF2113DU/F4
PCF2113DH/4
-
chip on flexible film carrier
chip in tray
-
-
-
LQFP100
plastic low profile quad flat package; 100 leads; SOT407-1
body 14 × 14 × 1.4 mm
PCF2113DU/2/F4
PCF2113EU/2/F4
PCF2113WU/2/F4
-
-
-
chip with bumps in tray
chip with bumps in tray
chip with bumps in tray
-
-
-
5. Marking
Table 2.
Marking codes
Type number
PCF2113DH/4
Marking code
PCF2113DH
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
2 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
6. Block diagram
C1 to C60
R1 to R18
60
18
COLUMN DRIVERS
ROW DRIVERS
BIAS
V
LCDIN
VOLTAGE
60
GENERATOR
18
V
V
LCDSENSE
DATA LATCHES
SHIFT REGISTER 18-BIT
60
V
LCD
V
LCDOUT
GENERATOR
SHIFT REGISTER 5 × 12 BIT
DD3
5
OSC
OSCILLATOR
CURSOR AND DATA CONTROL
5
V
V
DD1
CHARACTER
CHARACTER
GENERATOR
ROM
DD2
GENERATOR
RAM (128 × 5)
(CGRAM)
(CGROM)
16 CHARACTERS
240 CHARACTERS
TIMING
GENERATOR
V
V
SS1
8
SS2
DISPLAY DATA RAM
(DDRAM)
7
T1
PD
80 CHARACTERS/BYTES
T2
T3
7
7
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
(AC)
7
7
INSTRUCTION
DECODER
PCF2113x
8
DATA
REGISTER
(DR)
INSTRUCTION
REGISTER (IR)
BUSY
FLAG
8
POWER-ON
RESET
8
I/O BUFFER
mge990
DB0 to DB3/SA0 DB4 to DB7
E
R/W
RS
SCL
SDA
Fig 1. Block diagram of PCF2113x
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
3 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
7. Pinning information
7.1 Pinning
V
DD1
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
C3
2
OSC
PD
C4
3
C5
4
T1
C6
V
5
SS1
C7
V
6
C8
SS2
V
7
C9
LCDOUT
V
8
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
LCDIN
9
R9
R10
R11
R12
R13
R14
R15
R16
R18
C60
C59
C58
C57
C56
C55
C54
C53
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PCF2113x
52 C26
51
C27
mge989
Fig 2. Pin configuration for PCF2113DH (LQFP100)
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
4 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
y
84
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
dummy pad 3
C28
dummy pad 6
85
86
87
88
89
90
91
92
93
94
95
C2
C1
R8
R7
R6
R5
R4
R3
R2
R1
R17
C29
C30
C31
C32
C33
C34
C35
PCF2113x
C36
96
97
SCL
SDA
C37
C38
C39
98
E
RS
C40
x
3.36
mm
99
C41
0
0
100
101
102
103
104
105
106
107
108
109
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C42
C43
C44
C45
C46
C47
C48
34
33
32
31
C49
C50
C51
C52
V
DD2
V
DD3
110
111
30
dummy pad 7
dummy pad 2
3.52 mm
mgu205
Fig 3. Bonding pad locations for PCF2113xU (bottom view)
Table 3.
Pin (LQFP100 package) or pad allocation table
Pin
1
2
3
-
Pad
1
Symbol
VDD1
OSC
PD
Pin
-
Pad
84
Symbol
dummy pad
C2
2
76
85
3
77
86
C1
4
T3
78 to 85
86
87 to 94
95
R8 to R1
R17
4
-
5
T1
6
T2
87
96
SCL
5
6
7
-
7
VSS1
88
97
SDA
8
VSS2
89
98
E
9
VLCDOUT
VLCDSENSE
90
99
RS
10
91
100
R/W
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
5 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 3.
Pin (LQFP100 package) or pad allocation table …continued
Pin
Pad
Symbol
Pin
92
93
94
95
96
97
98
99
100
-
Pad
101
102
103
104
105
106
107
108
109
110
-
Symbol
DB7
8
11
VLCDIN
9 to 16
12 to 19
20
R9 to R16
R18
DB6
17
DB5
18 to 25
21 to 28
29
C60 to C53
dummy pad
dummy pad
C52 to C28
dummy pad
dummy pad
C27 to C3
dummy pad
DB4
-
DB3/SA0
DB2
-
30
26 to 50
31 to 55
56
DB1
-
DB0
-
57
VDD2
VDD3
-
51 to 75
-
58 to 82
83
-
Table 4.
Pad
Bonding pad dimensions
Size
galvanic pure Au
Unit
Type
Bump dimensions
(50 ± 6) × (90 ± 6) × (17.5 ± 5)
µm
µm
µm
µm
µm
µm
µm
Height difference in one die
Convex deformation
Pad size (aluminium)
Passivation opening
Pad pitch
< 2
< 5
62 × 100
36 × 76
−635.0
380 ± 25
Wafer thickness (excluding bumps)
Fab 1 [1]
Fab 2 [2]
3.47
Die size X
Die size Y
3.52
mm
mm
3.36
3.31
[1] Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer).
[2] Fab 2 identification starts with AXnnnn, where X represents a letter or a number and n represents a number
between 0 and 9 (6 inch wafer).
Table 5.
Pin and bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type
Pad
X (µm)
−1345
Y (µm)
−1550
Description
VDD1
1
P
1
supply voltage 1 for all except VLCD
generator
[1]
OSC
PD
2
3
I
I
2
3
−1155
−1055
−1550
−1550
oscillator and external clock input
power-down select input; for normal
operation PD is LOW
T3
-
I
4
−845
−1550
test pad; open circuit and not user
accessible
T1
4
-
I
5
6
7
−765
−665
−525
−1550
−1550
−1550
test pin; must be connected to VSS1
test pad; must be connected to VSS1
ground 1 for all except VLCD generator
T2
I
VSS1
5
P
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
6 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
VSS2
VLCDOUT
VLCDSENSE
VLCDIN
R9
Pin
6
Type
P
Pad
8
X (µm)
−455
−295
−145
15
Y (µm)
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1550
−1395
−1255
−1155
−1055
−955
Description
ground 2 for VLCD generator
VLCD output if VLCD is generated internally
input (VLCD) for voltage multiplier regulation
input for generation of LCD bias levels
LCD row driver output
[2]
7
O
I
9
[2][3]
[2]
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
8
I
9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
175
R10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
-
245
LCD row driver output
R11
315
LCD row driver output
R12
385
LCD row driver output
R13
455
LCD row driver output
R14
525
LCD row driver output
R15
595
LCD row driver output
R16
665
LCD row driver output
R18
735
LCD row driver output
C60
805
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
-
C59
875
C58
995
C57
1065
1135
1205
1275
1345
1435
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
C56
C55
C54
C53
dummy pad 1
dummy pad 2
C52
-
-
-
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
C51
C50
C49
C48
−735
C47
−635
C46
−535
C45
−435
C44
−335
C43
−235
C42
−135
C41
−35
C40
65
C39
165
C38
265
C37
365
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
7 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
C36
Pin
42
43
44
45
46
47
48
49
50
-
Type
O
O
O
O
O
O
O
O
O
-
Pad
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
X (µm)
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1435
1335
1225
1115
1005
765
Y (µm)
465
Description
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
-
C35
565
C34
665
C33
765
C32
865
C31
965
C30
1065
1165
1265
1335
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1550
1355
1255
C29
C28
dummy pad 3
dummy pad 4
C27
-
-
-
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
LCD column driver output
-
C26
C25
C24
C23
C22
665
C21
565
C20
465
C19
365
C18
265
C17
165
C16
65
C15
−35
C14
−135
−235
−335
−435
−535
−635
−735
−835
−965
−1065
−1165
−1265
−1465
−1630
−1630
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
dummy pad 5
dummy pad 6
C2
-
-
-
76
O
LCD column driver output
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
8 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 5.
Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
C1
Pin
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Type
O
Pad
86
X (µm)
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
−1630
Y (µm)
1185
1115
1045
975
Description
LCD column driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
I2C-bus serial clock input
I2C-bus serial data input/output
data bus clock input
R8
O
87
R7
O
88
R6
O
89
R5
O
90
905
R4
O
91
835
R3
O
92
765
R2
O
93
695
R1
O
94
625
R17
SCL
SDA
E
O
95
555
[4]
[4]
[4]
I
96
375
I/O
I
97
305
98
85
RS
I
99
−15
register select input
R/W
DB7
DB6
DB5
DB4
DB3/SA0
I
100
101
102
103
104
105
−115
−215
−315
−415
−515
−615
read or write input
[5]
I/O
I/O
I/O
I/O
I/O
8-bit bidirectional bus bit 7
8-bit bidirectional bus bit 6
8-bit bidirectional bus bit 5
8-bit bidirectional bus bit 4
8-bit bidirectional bus bit 3 or I2C-bus
address input
[4][5]
DB2
97
98
99
100
-
I/O
I/O
I/O
P
106
107
108
109
110
111
112
−1630
−1630
−1630
−1630
−1630
−1630
−1465
−715
8-bit bidirectional bus bit 2
8-bit bidirectional bus bit 1
8-bit bidirectional bus bit 0
supply voltage 2 for VLCD generator
supply voltage 3 for VLCD generator
-
DB1
−815
DB0
−915
[6]
VDD2
−1015
−1235
−1395
−1550
[3][6]
VDD3
P
dummy pad 7
dummy pad 8
-
-
-
-
-
[1] When the on-chip oscillator is used this pad must be connected to VDD1
.
[2] When VLCD is generated internally, pins VLCDIN, VLCDOUT and VLCDSENSE must be connected together. When an external VLCD is
supplied, this should be done via VLCDIN. In this case only pins VLCDOUT and VLCDSENSE must be connected together.
[3] In the LQFP100 version this signal is connected internally and is not accessible.
[4] When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode pins DB7 to DB0 must be connected to
VDD1 or left open-circuit.
When the parallel bus is used, the pins SCL and SDA must be connected to pin VSS1 or pin VDD1; they must not be left open-circuit.
When the 4-bit interface is used without reading out from the PCF2113x (bit R/W is set permanently to logic 0), the unused ports DB0 to
DB3 can either be connected to VSS1 or VDD1 instead of leaving them open-circuit.
[5] DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order
lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see Table note 4).
[6] VDD2 and VDD3 must always be equal.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
9 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
8. Functional description
8.1 LCD supply voltage generator
The LCD supply voltage (VLCD) may be generated on-chip. The VLCD generator is
controlled by two internal 6-bit registers: VA and VB. Section 10.10.1 shows how to
program these registers. The nominal LCD operating voltage at room temperature is given
by the relationship:
Voper(nom) = (integer value of register × 0.08 V) + 1.82 V
With a programmed value from 1 to 63, Voper(nom) = 1.90 V to 6.86 V at Tamb = 27 °C.
Values producing more than 6.5 V at operating temperature are not allowed. Operation
above this voltage may damage the device. When programming the operating voltage the
VLCD tolerance and temperature coefficient must be taken into account.
Values below 2.2 V are below the specified operating range of the chip and therefore are
not allowed.
Value 0 for VA and VB switches off the generator (i.e. VA = 0 in Character mode, VB = 0 in
Icon mode).
Usually register VA is programmed with the voltage for Character mode and register VB
with the voltage for Icon mode.
When VLCD is generated on-chip, the VLCD pins must be decoupled to VSS with a suitable
capacitor.
The generated VLCD is independent of VDD and is temperature compensated. When the
VLCD generator and the Direct mode are switched off, an external voltage may be supplied
at pins VLCDIN and VLCDOUT (which are connected together). VLCDIN and VLCDOUT may be
higher or lower than VDD2
.
During Direct mode (program DM bit) the internal VLCD generator is turned off and the
VLCDOUT output voltage is directly connected to VDD2. This reduces the current
consumption during Icon mode and MUX 1:9 (depending on VDD2 and LCD liquid
properties).
The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to 4 V), the
required peak operating voltage of 6.5 V can be generated at any time.
8.2 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This
removes the need for an external resistive bias chain and significantly reduces the system
current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD
threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1:18
maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the
different multiplex rates are shown in Table 6. These bias levels are automatically set to
the given values when switching to the corresponding multiplex rate.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
10 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 6.
Bias levels as a function of multiplex rate
Bias voltages[1]
Multiplex Number
rate
of levels
V1
V2
V3
V4
V5
V6
3
⁄
1
⁄
1
⁄
1
⁄
1:18
1:9
5
5
4
VLCD
VLCD
VLCD
VSS
VSS
VSS
4
2
2
4
3
⁄
1
⁄
1
⁄
1
⁄
4
2
2
4
2
⁄
2
⁄
1
⁄
1
⁄
1:2
3
3
3
3
[1] The values in the table are given relative to VLCD − VSS, e.g. 3⁄4 means {3⁄4 × (VLCD − VSS)} + VSS
.
8.3 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC pin must be connected to VDD1
.
8.4 External clock
If an external clock is to be used, this input is at the OSC pin. The resulting display frame
f osc
frequency is given by: f fr (LCD)
=
-----------
3072
Only in the Power-down mode is the clock allowed to be stopped (pin OSC connected to
SS), otherwise the LCD is frozen in a DC state.
V
8.5 Power-on reset
The on-chip power-on reset block initializes the chip after power-on or power failure. This
is a synchronous reset and requires 3 oscillator cycles to be executed.
8.6 Registers
The PCF2113x has two 8-bit registers: an Instruction Register (IR) and a Data
Register (DR). The Register Select (RS) signal determines which register will be
accessed. The instruction register stores instruction codes such as ‘display clear’, ‘cursor
shift’, and address information for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be written to but not read from by
the system controller.
The data register temporarily stores data to be read from the DDRAM and CGRAM. When
reading, data from the DDRAM or CGRAM corresponding to the address in the instruction
register is written to the data register prior to being read by the ‘read data’ instruction.
8.7 Busy flag
The busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the
chip is busy and further instructions will not be accepted. The busy flag is output to
pin DB7 when bit RS = 0 and bit R/W = 1. Instructions must only be written after checking
that the busy flag is at logic 0 or waiting for the required number of cycles.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
11 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
8.8 Address counter
The Address Counter (AC) assigns addresses to the DDRAM and CGRAM for reading
and writing and is set by the commands ‘set DDRAM address’ and ‘set CGRAM address’.
After a read/write operation the address counter is automatically incremented or
decremented by 1. The address counter contents are output to the bus (DB6 to DB0)
when bit RS = 0 and bit R/W = 1.
8.9 Display data RAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented
by 8-bit character codes. RAM locations which are not used for storing display data can be
used as general purpose RAM. The basic RAM to display addressing scheme is shown in
Figure 4. With no display shift the characters represented by the codes in the first 24 RAM
locations starting at address 00h in line 1 are displayed. Figure 5 and Figure 6 show the
display mapping for right and left shift respectively.
When data is written to or read from the DDRAM, wrap-around occurs from the end of one
line to the start of the next line. When the display is shifted each line wraps around within
itself, independently of the others. Thus all lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the various modes are shown in
Table 7.
non-displayed DDRAM addresses
display
position
1
2
3
4
5
22 23 24
DDRAM
address
00 01 02 03 04
15 16 17 18 19
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
1
2
3
4
5
10 11 12
00 01 02 03 04
09 0A 0B 0C 0D
24 25 26 27
line 1
line 2
DDRAM
address
1
2
3
4
5
10 11 12
40 41 42 43 44
49 4A 4B 4C 4D
64 65 66 67
mge991
2-line display
Fig 4. DDRAM to display mapping: no shift
display
position
1
2
3
4
5
22 23 24
14 15 16
4F 00 01 02 03
DDRAM
address
1-line display
1
2
3
4
5
10 11 12
08 09 0A
line 1
27 00 01 02 03
DDRAM
address
1
2
3
4
5
10 11 12
48 49 4A
67 40 41 42 43
line 2
mge992
2-line display
Fig 5. DDRAM to display mapping: right shift
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
12 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
display
position
1
2
3
4
5
22 23 24
16 17 18
01 02 03 04 05
DDRAM
address
1-line display
1
2
3
4
5
10 11 12
0A 0B 0C
line 1
01 02 03 04 05
DDRAM
address
1
2
3
4
5
10 11 12
4A 4B 4C
41 42 43 44 45
line 2
mge993
2-line display
Fig 6. DDRAM to display mapping: left shift
Table 7.
Address space and wrap-around operation
Mode
1 × 24
2 × 12
1 × 12
Address space
00h to 4Fh
4Fh to 00h
00h to 27h; 40h to 67h
27h to 40h; 67h to 00h
00h to 27h
27h to 00h
Read/write wrap-around
(moves to next line)
Display shift wrap-around 4Fh to 00h
(stays within line)
27h to 00h; 67h to 40h
27h to 00h
8.10 Character generator ROM
The Character Generator ROM (CGROM) generates 240 character patterns in a 5 × 8 dot
format from 8-bit character codes. Figure 7, Figure 8, Figure 9 and Figure 10 show the
character sets that are currently implemented.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
13 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
mlb245
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 7. Character set ‘A’ in CGROM
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
14 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
mgd688
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 8. Character set ‘D’ in CGROM
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
15 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
mgd689
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 9. Character set ‘E’ in CGROM
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
16 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
mgu204
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 10. Character set ‘W’ in CGROM
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
17 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
8.11 Character generator RAM
Up to 16 user-defined characters may be stored in the Character Generator RAM
(CGRAM). Some CGRAM characters (see Figure 18 and Figure 19) are also used to drive
icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both
icon rows are used in the application; 0 if no icons are driven by the icon rows). The
CGROM and CGRAM use a common address space, of which the first column is reserved
for the CGRAM (see Figure 7, Figure 8, Figure 9 and Figure 10).
Figure 11 shows the addressing principle for the CGRAM.
character codes
(DDRAM data)
CGRAM
address
character patterns
(CGRAM data)
character code
(CGRAM data)
7
0
6
5
4
3
2
1
0
0
6
0
5
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
character
pattern
example 1
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
character
pattern
example 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
mge995
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is
performed by logic OR with the cursor. Data in the 8th position appears in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to
selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM
address’ command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be
read using the ‘read busy flag’ and ‘address counter’ command.
Fig 11. Relationship between CGRAM addresses, data and display patterns
8.12 Cursor control circuit
The cursor control circuit generates the cursor underline and/or cursor blink as shown in
Figure 12 at the DDRAM address contained in the address counter.
When the address counter contains the CGRAM address the cursor will be inhibited.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
18 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
cursor
mga801
5 x 7 dot character font
alternating display
Cursor display example
Blink display example
Fig 12. Cursor and blink display examples
icon 1
icon 5
row 17
row 8
row 2
row 1
cursor
001aah687
Bit Q = 1
Fig 13. Example of a display with icons
8.13 Timing generator
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not disturbed by operations on the data buses.
8.14 LCD row and column drivers
The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate
LCD bias voltages in sequence to the display in accordance with the data to be displayed.
R17 and R18 drive the icon rows.
The bias voltages and the timing are selected automatically when the number of lines in
the display is selected. Figure 14, Figure 15, Figure 16 and Figure 17 show typical
waveforms. Unused outputs should be left unconnected.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
19 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n
frame n + 1
state 1 (ON)
state 2 (OFF)
V
V
LCD
2
R1
R2
R3
R4
R5
R6
R7
R8
V /V
3
V
5
ROW 1
ROW 17
ROW 2
COL 1
4
V
SS
V
V
LCD
2
V /V
3
4
V
5
R17
V
SS
V
V
LCD
2
V /V
3
4
V
V
5
SS
V
V
LCD
2
V /V
3
4
V
V
5
SS
V
V
LCD
2
V /V
3
COL 2
4
V
V
5
SS
V
oper
0.5V
oper
0.25V
0 V
oper
state 1
−0.25V
oper
−0.5V
oper
−V
oper
V
oper
0.5V
oper
0.25V
0 V
oper
state 2
−0.25V
oper
−0.5V
oper
−V
oper
mgu217
1
2
3
9
1
2
3
9
R9 to R16 and R18 to be left open
Fig 14. MUX 1:9 LCD waveforms; Character mode
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
20 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n
frame n + 1
state 1 (ON)
state 2 (OFF)
V
V
LCD
2
R1
R2
R3
R4
R5
R6
R7
R8
V /V
3
V
5
ROW 1
ROW 9
ROW 2
COL 1
COL 2
4
V
SS
V
V
LCD
2
V /V
3
4
V
5
R9
V
SS
V
V
LCD
2
V /V
3
4
V
V
5
SS
V
V
LCD
2
V /V
3
4
V
V
5
SS
V
V
LCD
2
V /V
3
4
V
V
5
SS
V
oper
0.5V
oper
0.25V
0 V
oper
state 1
−0.25V
−0.5V
oper
oper
−V
oper
V
oper
0.5V
oper
0.25V
0 V
oper
state 2
−0.25V
oper
−0.5V
oper
−V
oper
mge996
1
2
3
18
1
2
3
18
Fig 15. MUX 1:18 LCD waveforms; Character mode
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
21 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n
frame n + 1
only icons are
driven (MUX 1:2)
V
LCD
ROW 17
ROW 18
2/3
1/3
V
SS
V
LCD
2/3
1/3
V
SS
V
LCD
2/3
1/3
ROW 1 to 16
V
SS
V
LCD
2/3
1/3
COL 1
COL 2
COL 3
ON/OFF
V
SS
V
LCD
2/3
1/3
OFF/ON
V
SS
V
LCD
2/3
1/3
ON/ON
V
SS
V
LCD
2/3
1/3
COL 4
OFF/OFF
V
SS
mge997
Fig 16. MUX 1:2 LCD waveforms; Icon mode (a)
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
22 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
frame n
frame n + 1
state 1 (ON)
state 2 (OFF)
V
oper
2/3V
1/3V
oper
oper
0
R17
state 1
COL 1 −
ROW 17
R18
R1-16
−1/3V
−2/3V
−V
oper
oper
oper
state 3 (OFF)
V
2/3V
1/3V
oper
oper
oper
0
state 2
COL 2 −
ROW 17
−1/3V
−2/3V
−V
oper
oper
oper
V
2/3V
1/3V
oper
oper
oper
0
state 3
COL 1 −
ROW 1 to 16
−1/3V
−2/3V
−V
oper
oper
oper
mge998
Von(RMS) = 0.745Voper
Voff(RMS) = 0.333Voper
Von
D =
= 2.23
----------
Voff
Fig 17. MUX 1:2 LCD waveforms; Icon mode (b)
8.15 Power-down mode
The chip can be put into Power-down mode by applying an external HIGH level to the
PD pin. In Power-down mode all static currents are switched off (no internal oscillator, no
bias level generation and all LCD outputs are internally connected to VSS).
During power-down, information in the RAMs and the chip state are preserved. Instruction
execution during power-down is possible when pin OSC is externally clocked.
8.16 Reset function
The PCF2113x automatically initializes (resets) when power is turned on. The chip
executes a reset sequence, including a ‘clear display’, requiring 165 oscillator cycles. After
the reset the chip has the state shown in Table 8.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
23 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 8.
State after reset
Step Function
Control bit state
Conditions
1
2
clear display
entry mode set
I/D = 1
S = 0
D = 0
C = 0
B = 0
DL = 1
M = 0
H = 0
SL = 0
+1 (increment)
no shift
3
4
display control
function set
display off
cursor off
cursor character blink off
8-bit interface
1-line display
normal instruction set
MUX 1:18 mode
5
default address pointer the Busy Flag (BF) indicates the busy state lasts 2 ms; the chip
to DDRAM
the busy state (BF = 1) until may also be initialized by software;
initialization ends
IM = 0; IB = 0; DM = 0
L = 0; P = 0; Q = 0
TC1 = 0; TC2 = 0
VA = 0; VB = 0
see Table 26 (8-bit interface) and
Table 27 (4-bit interface).
6
7
8
icon control
icons, icon blink and Direct mode
disabled
display or screen
configuration
default configurations
default temperature coefficient
VLCD generator off
VLCD temperature
coefficient
9
set VLCD
10
11
I2C-bus interface reset
set HVgen stages
S1 = 1; S0 = 0
VLCD generator voltage multiplier
set at factor 4
9. Instructions
Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR),
can be directly controlled by the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow interfacing to various types of
microcontrollers which operate at different speeds or to allow interfacing to peripheral
control ICs.
The instruction set for I2C-bus commands is given in Table 9. Section 11.2.1 discusses
how these control and command bytes are embedded in the I2C-bus protocol.
Table 9.
Instruction set for I2C-bus commands
Control byte
I2C-bus
commands
[1]
Command byte
I2C-bus
commands
[1]
Co[2] RS
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
[1] R/W is set together with the slave address.
[2] For explanation, see Table 11.
The PCF2113x operation is controlled by the instructions shown in Table 10 together with
their execution time. Details are explained in subsequent sections.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
24 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
There are 4 types of instructions:
• Designate PCF2113x functions such as display format, data length
• Set internal RAM addresses
• Perform data transfer with internal RAM
• Other functions
In normal use, data transfer instructions are used most frequently. However, automatic
incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write
lessens the microcontroller program load. The display shift in particular can be performed
concurrently with display data write, enabling the designer to develop systems in minimum
time with maximum programming efficiency.
During internal operation, no instructions other than the ‘read busy flag’ and ‘read
address’ instructions will be executed. Because the busy flag is set to logic 1 while an
instruction is being executed, check to ensure it is logic 0 before sending the next
instruction or wait for the maximum instruction execution time, as given in Table 10. An
instruction sent while the busy flag is logic 1 will not be executed.
Table 10. Instruction set with parallel bus commands
Instruction
Control and command bits
Description[1]
Required
clock
cycles
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H = 0 or 1 (basic and extended functions)
NOP
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
no operation
3
3
Function set
DL
M
SL
H
sets interface Data
Length (DL), number of
display lines (M), single
line/MUX 1:9 (SL) and
extended instruction set
control (H)
Read busy flag
and address
counter
0
1
BF
AC
reads the Busy Flag (BF),
indicating internal operating
is being performed, and the
Address Counter (AC)
0
Read data
Write data
1
1
1
0
read data
write data
reads data from CGRAM or
DDRAM
3
3
writes data to CGRAM or
DDRAM
H = 0 (basic functions)
Clear display
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
clears entire display and sets 165
DDRAM address 0 in
address counter
Return home
0
0
sets DDRAM address 0 in
address counter; also
3
returns shifted display to
original position; DDRAM
contents remain unchanged
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
25 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 10. Instruction set with parallel bus commands …continued
Instruction
Control and command bits
Description[1]
Required
clock
cycles
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Entry mode set
0
0
0
0
0
0
0
1
1
I/D
S
sets cursor move direction
(I/D) and specifies shift of
display (S); these operations
are performed during data
write and read
3
Display control
0
0
0
0
0
0
0
0
0
0
0
1
D
C
0
B
0
sets entire display on/off (D),
cursor on/off (C) and blink of
cursor position character (B)
3
3
Cursor/display
shift
S/C R/L
moves cursor or shifts
display (S/C) to right or left
(R/L) without changing the
DDRAM contents
Set CGRAM
address
0
0
0
1
1
ACG
sets CGRAM address;
bit DB6 is to be set by the
command ‘set DDRAM
address’; the descriptions of
the commands provide
details
3
3
Set DDRAM
address
0
0
ADD
sets DDRAM address
H = 1 (extended functions)
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
L
do not use
-
Screen
set screen configuration (L)
3
configuration
Display
configuration
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
P
Q
set display configuration,
columns (P) and rows (Q)
3
3
3
3
Icon control
IM
0
IB
DM set Icon mode (IM), icon
blink (IB), Direct mode (DM)
Temperature
control
TC1 TC2 set temperature coefficient
(TC1 and TC2)
Set HVgen
stages
0
S1
S0
set internal VLCD generator
voltage multiplier stages
(S1 = 1 and S0 = 1 are not
allowed)
Set VLCD
0
0
1
V
voltage
store VLCD in register VA or
in register VB (V)
3
[1] For explanation of symbols, see Table 11.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
26 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 11. Explanation of symbols
Bit
Logic 0
Logic 1
Co
last control byte
another control byte follows after
data/command
RS
select instruction register
data length: 4 bits
select data register
DL
data length: 8 bits
M (no impact if SL = 1)
SL
1 line × 24 character display
2 line × 12 character display
MUX 1:18 (1 line × 24 character MUX 1:9 (1 line × 12 character
or 2 line × 12 character display)
use basic instruction set
decrement
display)
H
use extended instruction set
increment
I/D
S
display freeze
display shift
D
display off
display on
C
cursor off
cursor on
B
cursor character blink off;
cursor character blink on;
character at cursor position does character at cursor position blinks
not blink
S/C
R/L
cursor move
left shift
display shift
right shift
L (no impact if M = 1 or
SL = 1)
left/right screen;
standard connection
left/right screen;
mirrored connection
1st 12 characters of 24;
columns are from 1 to 60
1st 12 characters of 24;
columns are from 60 to 1
2
nd 12 characters of 24;
columns are from 1 to 60
2nd 12 characters of 24;
columns are from 60 to 1
P
column data; left to right; column column data; right to left; column
data is displayed from 1 to 60 data is displayed from 60 to 1
Q
row data; top to bottom; row data row data; top to bottom; row data
is displayed from 1 to 16 and icon is displayed from 16 to 1 and icon
row data is in 17 and 18
Character mode; full display
icon blink disabled
Direct mode disabled
set VA
row data is in 18 and 17
Icon mode; only icons displayed
icon blink enabled
IM
IB
DM
V
Direct mode enabled
set VB
9.1 Clear display
‘Clear display’ writes character code 20h into all DDRAM addresses (the character pattern
for character code 20h must be a blank pattern), sets the DDRAM address counter to 0
and returns the display to its original position, if it was shifted. Thus, the display
disappears and the cursor or blink position goes to the left edge of the display. Sets entry
mode I/D = 1 (increment mode). S of entry mode does not change.
The instruction ‘clear display’ requires extra execution time. This may be allowed by
checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are foreseen, as in some
Chip-On-Glass (COG) applications.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
27 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
9.2 Return home
‘Return home’ sets the DDRAM address counter to 0 and returns the display to its original
position if it was shifted. DDRAM contents do not change. The cursor or blink position
goes to the left of the first display line. I/D and S of entry mode do not change.
9.3 Entry mode set
9.3.1 Bit I/D
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when
data is written into or read from the DDRAM or CGRAM. The cursor or blink position
moves to the right when incremented and to the left when decremented. The cursor
underline and cursor character blink are inhibited when the CGRAM is accessed.
9.3.2 Bit S
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1)
during a DDRAM write. Thus it appears as if the cursor stands still and the display moves.
The display does not shift when reading from the DDRAM, or when writing to or reading
from the CGRAM.
When S = 0, the display does not shift.
9.4 Display control (and partial Power-down mode)
9.4.1 Bit D
The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not
affected and can be displayed immediately by setting D = 1.
When the display is off (D = 0) the chip is in partial Power-down mode:
• The LCD outputs are connected to VSS
• The LCD generator and bias generator are turned off
Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all
outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running
during partial Power-down mode (‘display off’) the chip can still execute instructions. Even
lower current consumption is obtained by inhibiting the oscillator (pin OSC = VSS).
To ensure IDD < 1 µA, pin PD and the parallel bus pins DB7 to DB0 should be connected
to VDD, pins RS and R/W to VDD or left open-circuit.
Recovery from Power-down mode: connect pin PD back to VSS, if necessary pin OSC
back to VDD and send a ‘display control’ instruction with D = 1.
9.4.2 Bit C
The cursor is displayed when C = 1 and inhibited when C = 0. The cursor is displayed
using 5 dots in the 8th line (see Figure 12). Even if the cursor disappears, the display
functions like I/D, remain in operation during display data write.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
28 of 65
PCF2113x
NXP Semiconductors
9.4.3 Bit B
LCD controllers/drivers
The character indicated by the cursor blinks when B = 1. The cursor character blink is
displayed by switching between display characters and all dots on with a period of
f osc
approximately 1 s, with f blink
=
Hz.
-----------------
104448
The cursor underline and the cursor character blink can be set to display simultaneously.
9.5 Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the display to the right or left without
writing or reading display data. This function is used to correct a character or move the
cursor through the display. In 2-line displays, the cursor moves to the next line when it
passes the last position of the line. When the displayed data is shifted repeatedly all lines
shift at the same time; displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the only action performed is shift
display, but increments or decrements with the ‘cursor display shift’.
9.6 Function set
9.6.1 Bit DL (parallel mode only)
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or
in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should
be left open-circuit (internal pull-ups). Hence in the first ‘function set’ instruction after
power-on M, SL and H are set to logic 1. A second ‘function set’ must then be sent
(2 nibbles) to set M, SL and H to their required values.
‘Function set’ from the I2C-bus interface sets the DL bit to logic 1.
9.6.2 Bit M
Selects either 1 line × 24 character display (M = 0) or 2 line × 12 character display (M = 1).
9.6.3 Bit SL
Selects MUX 1:9, 1 line × 12 character display (independent of M and L). Only rows 1 to 8
and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the
same as in the 2 line × 12 character display mode, however, the second line is not
displayed.
9.6.4 Bit H
When H = 0 the chip can be programmed via the standard 11 instruction codes used in
the PCF2116 and other LCD controllers.
When H = 1 the extended range of instructions will be used. These are mainly for
controlling the display configuration and the icons, as shown in Section 10.
9.7 Set CGRAM address
‘Set CGRAM address’ writes bits DB5 to DB0 of the CGRAM address ACG into the
address counter (A5h to A0h). Data can then be written to or read from the CGRAM.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
29 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Remark: the CGRAM address uses the same address register as the DDRAM address
and consists of 7 bits (A6h to A0h). With the ‘set CGRAM address’ command, only
bits DB5 to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command
first, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can
be read using the ‘read busy flag’ and ‘read address’ command.
When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not
set (e.g. by an earlier DDRAM write or read action).
9.8 Set DDRAM address
‘Set DDRAM address’ writes the DDRAM address ADD into the address counter
(A6h to A0h). Data can then be written to or read from the DDRAM.
9.9 Read busy flag and read address
‘Read busy flag and address counter’ reads the Busy Flag (BF) and Address
Counter (AC). BF = 1 indicates that an internal operation is in progress. The next
instruction will not be executed until BF = 0. It is recommended that the BF status is
checked before the next write operation is executed.
At the same time, the value of the address counter (A6h to A0h) is read out, into DB6 to
DB0. The address counter is used by both CGRAM and DDRAM, and its value is
determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set
CGRAM address’ or ‘set DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in accordance with the entry mode. Only
bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are ‘not relevant’.
9.11 Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM.
The most recent ‘set address’ command determines whether the CGRAM or DDRAM is to
be read.
The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while
pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC into the DR.
There are only three instructions that update the DR:
• ‘Set CGRAM address’
• ‘Set DDRAM address’
• ‘Read data’ from CGRAM or DDRAM
Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’)
do not modify the data register content.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
30 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
10. Extended function set instructions and features
10.1 New instructions
H = 1 sets the chip into Extended instruction set mode.
10.2 Icon control
The PCF2113x can drive up to 120 icons. See Figure 18 and Figure 19 for CGRAM to
icon mapping.
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 –
1
2
3
4
5
6
7
8
9
10
56 57 58 59 60
ROW 18 –
61 62 63 64 65
block of 5 columns
66 67 68 69 70
116 117 118 119 120
mge999
Fig 18. CGRAM to icon mapping (a)
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
31 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
icon no.
phase
ROW/COL
character codes
CGRAM address
CGRAM data
icon view
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
4
3
2
1
0
MSB
LSB MSB
LSB MSB
LSB
1-5
6-10
11-15
even
even
even
17/1-5
17/6-10
17/11-15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
56-60
61-65
even
even
17/56-60
18/1-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
116-120
1-5
even
18/56-60
17/1-5
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
odd (blink)
116-120
odd (blink) 18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
mgg001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.
Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is
enabled.
Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when
icon blink is disabled).
Fig 19. CGRAM to icon mapping (b)
10.3 Bit IM
When IM = 0, the chip is in Character mode. In Character mode, characters and icons are
driven (MUX 1:18 or MUX 1:9). The VLCD generator, if used, produces the VLCD voltage
programmed in register VA.
When IM = 1, the chip is in Icon mode. In Icon mode only the icons are driven (MUX 1:2)
and the VLCD generator, if used, produces the VLCD voltage as programmed in register VB.
Table 12. Character/Icon mode operation
IM
0
Mode
VLCD
Character mode
Icon mode
defined in VA
defined in VB
1
10.4 Bit IB
Icon blink control is independent of the cursor/character blink function.
When IB = 0, the icon blink is disabled. Icon data is stored in CGRAM characters 0 to 2
(3 × 8 × 5 = 120 bits for 120 icons).
When IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits.
Blink consists of two half phases (corresponding to the cursor on and off phases called
even and odd phases hereafter).
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
32 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Icon states for the even phase are stored in CGRAM characters 0 to 2
(3 × 8 × 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not
used (see Table 13).
Icon states for the odd phase are stored in CGRAM characters 4 to 6 (another 120 bits for
the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as
normal CGRAM characters.
Table 13. Blink effect for icons and cursor character blink
Parameter
Even phase
Odd phase
Cursor character blink
Icons
block (all on)
normal (display character)
state 2; CGRAM character 4 to 6
state 1; CGRAM character 0 to 2
10.5 Direct mode
When DM = 0, the chip is not in the Direct mode. Either the internal VLCD generator or an
external voltage may be used to achieve VLCD
.
When DM = 1, the chip is in Direct mode. The internal VLCD generator is turned off and the
output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage).
The Direct mode can be used to reduce the current consumption when the required
output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in Icon
mode or in MUX 1:9 (depending on LCD liquid properties).
10.6 Voltage multiplier control
10.6.1 Bits S1 and S0
A software configurable voltage multiplier is incorporated in the VLCD generator and can
be set via the ‘Set HVgen stages’ command.
The voltage multiplier control can be used to reduce current consumption by
disconnecting internal voltage multiplier stages, depending on the required output voltage
VLCD (see Table 14).
Table 14. S1 and S0 control of voltage multiplier
S1
0
S0
0
Description
set VLCD generator stages to 1 (2 × voltage multiplier)
set VLCD generator stages to 2 (3 × voltage multiplier)
set VLCD generator stages to 3 (4 × voltage multiplier)
do not use
0
1
1
0
1
1
10.7 Screen configuration
10.7.1 Bit L
L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61,
2/62 to 60/120; default.
L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120,
2/119 to 60/61. This allows single layer PCB or glass layout.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
33 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
10.8 Display configuration
10.8.1 Bit P
The P bit is used to flip the display left to right by mirroring the column data, as shown in
Figure 20. This allows the display to be viewed from behind instead of front, enhances the
flexibility in the assembly of equipment and avoids complicated data manipulation within
the controller.
P = 0: default.
P = 1: mirrors the column data.
P = 0
P = 1
P = 0
P = 1
001aah714
Fig 20. Use of P bit
10.8.2 Bit Q
The Q bit flips the display top to bottom by mirroring the row data.
Q = 0: default.
Q = 1: mirrors the row data.
A combination of Q and P allows the display to be rotated 180 deg, as shown in Figure 21.
This is useful for viewing the display from the opposite edge.
P = 0
Q = 0
P = 1
Q = 1
001aah715
Fig 21. Use of P and Q bits
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
34 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
10.9 Temperature control
Default is bit TC1 = 0 and bit TC2 = 0. Selects the default temperature coefficient for the
internally generated VLCD (see Table 15).
Table 15. TC1 and TC2 selection of VLCD temperature coefficient
Bit TC1
Bit TC2
VLCD temperature coefficient TC (typical values)
TC = −0.16 %/K
0
1
0
1
0
0
1
1
TC = −0.18 %/K
TC = −0.21 %/K
TC = −0.24 %/K
10.10 Set VLCD
The VLCD value is programmed by instruction. Two on-chip registers, VA and VB hold VLCD
values for the Character mode and the Icon mode respectively. The generated VLCD is
independent of VDD, allowing battery operation of the chip.
10.10.1 VLCD programming
1. Send ‘function set’ instruction with H = 1
2. Send ‘set VLCD’ instruction to write to voltage register:
a. If DB[7:6] = 10, then DB[5:0] represents VLCD of Character mode (VA)
b. If DB[7:6] = 11, then DB[5:0] represents VLCD of Icon mode (VB)
c. DB[5:0] = 00 0000 switches VLCD generator off (when selected)
d. During ‘display off’ and power-down the VLCD generator is also disabled
3. Send ‘function set’ instruction with H = 0 to resume normal programming
Section 8.1 shows the relation between VLCD and registers VA and VB.
10.11 Reducing current consumption
Reducing current consumption can be achieved by one of the options given in Table 16.
When VLCD lies outside the VDD range and must be generated, it is usually more efficient
to use the on-chip generator than an external regulator.
Table 16. Reducing current consumption
Original mode
Character mode
Display on
Alternative mode
Icon mode (control bit M)
display off (control bit D)
Direct mode
VLCD generator operating
Any mode
Power-down mode (PD pin)
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
35 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
11. Interfaces to microcontroller
11.1 Parallel interface
The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can
thus interface to 4-bit or 8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three
further control lines E, RS and R/W are required (see Section 7).
In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the
transaction. The higher order bits (corresponding to bits DB7 to DB4 in 8-bit mode) are
sent in the first cycle and the lower order bits (corresponding to bits DB3 to DB0 in 8-bit
mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It
should be noted that two cycles are also required for the busy flag check. 4-bit operation is
selected by instruction: see Figure 22, Figure 23 and Figure 24 for examples of bus
protocol.
In 4-bit mode, pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD
internally.
RS
R/W
E
DB7
DB6
DB5
DB4
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
BF
AC3
AC2
AC1
AC0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
AC6
AC5
AC4
busy flag and
address counter read
data register
read
instruction
write
mga804
Fig 22. 4-bit transfer example
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
36 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
RS
R/W
E
internal
DB7
internal operation
not
busy
IR7
IR3
AC3
AC3
D7
D3
busy
instruction
write
busy flag
check
busy flag
check
instruction
write
mga805
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
Fig 23. Example of 4-bit data transfer timing sequence
RS
R/W
E
internal
internal operation
not
busy
data
busy
busy
data
DB7
instruction
write
busy flag
check
busy flag
check
busy flag
check
instruction
write
mga806
Fig 24. Example of busy flag checking timing sequence
11.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH
level signal put on the bus by the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
37 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
11.2.1 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the START procedure. The I2C-bus configuration for the different PCF2113x read and
write cycles is shown in Figure 25, Figure 26 and Figure 27. The slow-down feature of the
I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the
PCF2113x.
acknowledgement
from PCF2113x
S
A
0
S
0
1
1
1
0
1
0
A
1 RS CONTROL BYTE
DATA BYTE
A
0 RS CONTROL BYTE
1 byte
A
DATA BYTE
A P
A
slave address
2n ≥ 0 bytes
n ≥ 0 bytes
Co
R/W
Co
update
data pointer
mgg002
S
A
0
0
1
1
1
0
1
0
PCF2113x
slave address
R/W
Fig 25. Master transmits to slave receiver; write mode
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
38 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
acknowledgement
S
A
0
(1)
0
1
1
1
0
1
A
1 RSCONTROL BYTE A
DATA BYTE
0 RSCONTROL BYTE
1 byte
DATA BYTE
A
S
0
A
A
slave address
2n ≥ 0 bytes
n ≥ 0 bytes
R/W
Co
Co
acknowledgement
acknowledgement
no acknowledgement
S
A
0
SLAVE
ADDRESS
1
A
DATA BYTE
A
DATA BYTE
1
P
S
n bytes
last byte
R/W
Co
update
update
data pointer
mgg003
data pointer
(1) Last data byte is a dummy byte (may be omitted).
Fig 26. Master reads after setting word address; write word address; set RS; ‘read data’
acknowledgement
from PCF2113x
acknowledgement
from master
no acknowledgement
from master
S
A
0
SLAVE
ADDRESS
1
A
DATA BYTE
A
DATA BYTE
1
P
S
n bytes
last byte
R/W
Co
update
update
data pointer
data pointer
mgg004
Fig 27. Master reads slave immediately after first byte; read mode (RS previously defined)
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 28. System configuration
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
39 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 29. Bit transfer
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 30. Definition of START and STOP conditions
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
8
SCL from
master
1
2
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 31. Acknowledgement on the I2C-bus
11.2.2 Definitions
• Transmitter: the device that sends the data to the bus
• Receiver: the device that receives the data from the bus
• Master: the device that initiates and terminates a transfer and generates clock signals
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message
• Arbitration: procedure to ensure that if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock signals of two or more devices
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
40 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
12. Internal circuitry
Table 17. Device protection circuits
Symbol
Pad
Internal circuit
VDD1
1
V
V
DD1
SS1
mgu200
VDD2
109
V
V
DD2
SS2
V
SS1
mgu201
VDD3
110
V
V
DD3
SS1
mgu202
VSS1
VSS2
7
8
V
SS2
V
SS1
mgu203
VLCDSENSE
VLCDIN
10
11
9
VLCDOUT
V
SS1
mgu196
SCL
SDA
96
97
V
DD1
SS1
V
mgu198
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
41 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 17. Device protection circuits …continued
Symbol
Pad
Internal circuit
OSC
2
V
DD1
PD
3
T1
5
T2
6
T3
4
E
98
V
SS1
mgu199
RS
99
R/W
100
DB0 to DB7
R1 to R8
R9 to R16
R17
108 to 101
94 to 87
12 to 19
95
V
LCDOUT
R18
20
C1 to C2
C3 to C27
C28 to C52
C53 to C60
86 to 85
82 to 58
55 to 31
28 to 21
V
SS1
mgu197
13. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD1
VDD2
VDD3
VLCD
Vi(n)
Parameter
Conditions
Min
Max
+5.5
+4.0
+4.0
+6.5
+5.5
+6.5
+10
Unit
V
supply voltage 1
logic supply
−0.5
supply voltage 2
VLCD generator supply
analog supply
−0.5
V
supply voltage 3
−0.5
V
LCD supply voltage
voltage on any input
voltage on any output
input current
−0.5
V
VDD related inputs
VLCD related outputs
DC level
−0.5
V
Vo(n)
II
−0.5
V
−10
mA
mA
mA
mA
mA
mW
mW
V
IO
output current
DC level
−10
+10
IDD
supply current
on pins VDD1, VDD2, VDD3
on pins VSS1 and VSS2
-
+50
ISS
ground supply current
LCD supply current
total power dissipation
power dissipation per output
-
−50
IDD(LCD)
Ptot
-
+50
-
400
P/out
Vesd
-
100
[1]
[2]
[3]
[4]
electrostatic discharge
voltage
HBM
MM
-
±2000
±200
±2000
100
-
V
CDM
-
V
Ilu
latch-up current
-
mA
°C
Tstg
storage temperature
−65
+150
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
42 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
[1] HBM: Human Body Model, according to JESD22-A114.
[2] MM: Machine Model, according to JESD22-A115.
[3] CDM: Charged-Device Model, according to JESD22-C101.
[4] Latch-up testing, according to JESD78.
14. Static characteristics
Table 19. Static characteristics
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified.
Symbol
Supplies
VDD1
Parameter
Conditions
Min
Typ
Max
Unit
[1]
supply voltage 1
supply voltage 2
logic supply
1.8
2.2
-
-
5.5
4.0
V
V
VDD2
VLCD generator supply;
internal VLCD generation
(VDD2 and VDD3 < VLCD
)
VDD3
supply voltage 3
analog supply;
2.2
-
4.0
V
internal VLCD generation
(VDD2 and VDD3 < VLCD
)
VLCD
VPOR
ISS
LCD supply voltage
2.2
0.9
-
-
6.5
1.6
V
V
[1][2]
[3]
power-on reset voltage
ground supply current external VLCD; pins VSS1 and VSS2
Character mode; VLCD = 6.5 V;
-
-
-
70
45
25
120
80
µA
µA
µA
V
DD1 = 5.5 V; VDD2 = VDD3 = 4 V
Character mode; VLCD = 5 V;
DD1 = VDD2 = VDD3 = 3 V
Icon mode; VLCD = 2.5 V;
DD1 = VDD2 = VDD3 = 3 V
[4]
[4]
V
45
V
[3][5]
internal VLCD; pins VSS1 and VSS2
Character mode; VLCD = 6.5 V;
-
-
-
-
190
160
120
2
400
400
-
µA
µA
µA
µA
V
DD1 = 5.5 V; VDD2 = VDD3 = 2.2 V
Character mode; VLCD = 5 V;
DD1 = VDD2 = VDD3 = 3 V
Icon mode; VLCD = 2.5 V;
DD1 = VDD2 = VDD3 = 2.5 V
Power-down mode; VLCD = 2.5 V;
DD1 = VDD2 = VDD3 = 3 V;
[4]
[4]
V
V
[3][4]
5
V
pins RS, PD, R/W and DB7 to
DB0 = HIGH; in OSC = LOW
Logic
Vi
input voltage
LOW-level input voltage on pin OSC
on any other pin
on pin OSC
V
SS1 − 0.5
-
-
-
-
-
-
VDD1 + 0.5 V
VIL
VSS1
VSS1
V
DD1 − 1.2
V
0.3VDD1
VDD1
VDD1
+1
V
VIH
HIGH-level input
voltage
VDD1 − 0.1
V
on any other pin
VI = VDD1 or VSS1
0.7VDD1
V
IL
leakage current
−1
µA
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
43 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 19. Static characteristics …continued
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified.
Symbol
Pins DB7 to DB0
IOL LOW-level output
Parameter
Conditions
Min
Typ
Max
Unit
VOL = 0.4 V; VDD1 = 5 V
VOH = 0.4 V; VDD1 = 5 V
VI = VSS1
1.6
−1
4
-
mA
mA
µA
current
IOH
HIGH-level output
current
−8
0.15
-
Ipu
pull-up current
0.04
1
I2C-bus
Input on pins SDA and SCL
VI
input voltage
V
SS1 − 0.5
-
-
-
5.5
V
V
V
VIL
VIH
LOW-level input voltage
0
0.3VDD1
5.5
HIGH-level input
voltage
0.7VDD1
ILI
CI
input leakage current
input capacitance
VI = VDD1 or VSS1
−1
-
+1
-
µA
[6]
-
5
pF
Output on pin SDA
IOL(SDA)
LOW-level output
current on pin SDA
VOL = 0.4 V; VDD1 > 2 V
3
2
-
-
-
-
mA
mA
VOL = 0.2VDD1; VDD1 < 2 V
LCD outputs
[7]
[7]
[8]
[5]
RO
output resistance
row outputs: pins R1 to R18
column outputs: pins C1 to C60
pins R1 to R18 and C1 to C60
Tamb = 25 °C
-
-
-
10
15
20
30
kΩ
kΩ
mV
40
∆Vbias
∆VLCD
bias voltage variation
LCD voltage variation
130
VLCD < 3 V
-
-
-
-
-
-
-
-
160
200
260
340
mV
mV
mV
mV
VLCD < 4 V
VLCD < 5 V
VLCD < 6 V
[1] Spikes on VDD1 or VSS1 which cause (VDD1 − VSS1) ≤ 1.6 V can cause a Power-on reset.
[2] Resets all logic when VDD1 < VPOR; 3 oscillator cycles required.
[3] LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive.
[4] Tamb = 25 °C; fosc = 200 kHz.
[5] LCD outputs are open-circuit; VLCD generator is on; load current IDD(LCD) = 5 µA (at VLCD).
[6] Tested on a sample basis.
[7] Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 µA; outputs measured one at a time; external VLCD = 3 V;
VDD1 = VDD2 = VDD3 = VLCD
.
[8] LCD outputs are open-circuit; external VLCD
.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
44 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
15. Dynamic characteristics
Table 20. Dynamic characteristics
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified
Symbol
ffr(LCD)
fosc
Parameter
Conditions
Min
45
140
140
-
Typ
95
250
-
Max
147
450
450
300
-
Unit
Hz
LCD frame frequency
oscillator frequency
external oscillator frequency
internal clock; VDD = 5.0 V
[1]
[2]
[2]
kHz
kHz
µs
fosc(ext)
td(startup)(OSC) start-up delay time on pin OSC oscillator, after power down
200
-
tw(pd)
power-down pulse width
1
µs
tw(spike)
spike pulse width
on pin PD
-
-
90
ns
Timing characteristics of parallel interface [3]
Write operation (writing data from microcontroller to PCF2113x); see Figure 32
tcy(en)
tw(en)
tsu(A)
th(A)
enable cycle time
500
220
50
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
enable pulse width
address set-up time
address hold time
data input set-up time
data input hold time
25
tsu(D)
th(D)
60
25
Read operation (reading data from PCF2113x to microcontroller); see Figure 33
tcy(en)
tw(en)
tsu(A)
th(A)
enable cycle time
500
220
50
25
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
enable pulse width
address set-up time
address hold time
-
-
-
td(DV)
data input valid delay time
VDD1 > 2.2 V
VDD1 > 1.5 V
150
250
-
-
th(D)
data input hold time
5
Timing characteristics of I2C-bus interface [3]; see Figure 34
fSCL
SCL frequency
-
-
-
-
-
-
-
400
Hz
µs
µs
ns
ns
ns
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
LOW period of the SCL clock
HIGH period of the SCL clock
data set-up time
1.3
-
0.6
-
100
-
data hold time
0
-
[2][4]
[2][4]
[4]
rise time of both SDA and SCL
signals
15 + 0.1Cb
300
tf
fall time of both SDA and SCL
signals
15 + 0.1Cb
-
300
ns
Cb
capacitive load for each bus line
-
-
-
400
-
pF
tSU;STA
set-up time for a repeated
START condition
0.6
µs
tHD;STA
hold time (repeated) START
condition
0.6
-
-
µs
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
45 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 20. Dynamic characteristics …continued
VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified
Symbol
tSU;STO
tSP
Parameter
Conditions
Min
0.6
-
Typ
Max
-
Unit
µs
set-up time for STOP condition
-
-
pulse width of spikes that must on bus
be suppressed by the input filter
50
ns
tBUF
bus free time between a STOP
and START condition
1.3
-
-
µs
[1] Not available at any pin.
[2] Tested on a sample basis.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD
.
[4] Cb = total capacitance of one bus line in pF.
V
V
V
V
IH
IH
RS
IL
IL
t
t
t
su(A)
h(A)
R/W
E
V
V
IL
IL
t
w(en)
h(A)
V
IH
V
IH
V
V
IL
IL
V
IL
t
h(D)
t
su(D)
V
V
V
IH
V
IL
IH
IL
DB0 to DB7
valid data
mbk474
t
cy(en)
Fig 32. Parallel bus write operation sequence; writing data from microcontroller to
PCF2113x
V
V
V
IH
V
IL
IH
RS
IL
t
t
t
su(A)
h(A)
V
V
IH
IH
R/W
E
t
w(en)
h(A)
V
IH
V
IH
V
V
IL
IL
V
IL
t
h(D)
t
d(DV)
V
OH
V
OL
V
OH
V
OL
DB0 to DB7
mbk475
t
cy(en)
Fig 33. Parallel bus read operation sequence; writing data from PCF2113x to
microcontroller
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
46 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 34. I2C-bus timing diagram
16. Application information
16.1 Application diagrams
2
R17, R18
P10
P11
RS
R/W
E
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
16
P12
P80CL51
PCF2113x
C1 to C60
60
P17 to P14
4
DB7 to DB4
mgg006
Fig 35. Direct connection to 8-bit microcontroller; 4-bit bus
2
R17, R18
P20
P21
P22
RS
R/W
E
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
16
P80CL51
PCF2113x
C1 to C60
60
P17 to P10
DB7 to DB0
8
mgg005
Fig 36. Direct connection to 8-bit microcontroller; 8-bit bus
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
47 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
R17, R18
2
OSC
V
DD
V
DD
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
16
PCF2113x
470
nF
V
V
LCD
100
nF
C1 to C60
60
V
SS
SS
8
mgg007
DB7 to DB0
E
RS R/W
Fig 37. Typical application using parallel interface
V
V
V
DD
DD DD
DB3/SA0
2
R17, R18
OSC
V
V
DD
V
DD
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
16
PCF2113x
470
nF
V
V
LCD
100
nF
C1 to C60
60
SS
SS
SCL SDA
V
SS
DB3/SA0
R17, R18
2
OSC
V
V
DD
V
DD
1 × 24 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
R1 to R16
16
PCF2113x
470
nF
V
V
LCD
100
nF
C1 to C60
60
SS
SS
SCL SDA
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
mgg008
Fig 38. Application using I2C-bus interface
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
48 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
16.2 General application information
The required minimum value for the external capacitors in an application with the
PCF2113x are: Cext ≥ 100 nF between VLCD and VSS, and Cext ≥ 470 nF between VDD and
VSS. Higher capacitor values are recommended for ripple reduction.
For COG applications the recommended Indium Tin Oxide (ITO) track resistance is to be
minimized for the I/O and supply connections. Optimized values for these tracks are below
50 Ω for the supply and below 100 Ω for the I/O connections. Higher track resistances
reduce performance and increase current consumption.
To avoid accidental triggering of power-on reset (especially in COG applications), the
supplies must be adequately decoupled. Depending on power supply quality, VDD1 may
have to be risen above the specified minimum.
16.3 4-bit operation, 1-line display using internal reset
The program must set functions prior to a 4-bit operation (see Table 21 ). When power is
turned on, 8-bit operation is automatically selected and the PCF2113x attempts to
perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a
rewrite is then required. However, since one operation is completed in two accesses of
4-bit operation, a rewrite is required to set the functions (see Table 21 step 3). Thus,
DB4 to DB7 of the ‘function set’ are written twice.
Table 21. 4-bit operation, 1-line display example using internal reset
Step Instruction
Display
Operation
1
internal power supply on (PCF2113x
initialized; no display appears
is initialized by the internal reset)
2
function set
sets a 4-bit operation; in this instance
operation is handled as 8-bit by
initialization and only this instruction
completes with one write
RS R/W DB7 DB6 DB5 DB4
0
0
0
0
1
0
3
function set
sets to 4-bit operation, selects 1-line
display and VLCD = VA; 4-bit operation
starts from this point and resetting is
needed
0
0
0
0
0
0
0
0
1
0
0
0
4
5
display control
turns on display and cursor; entire
display is blank after initialization
0
0
0
0
0
1
0
1
0
1
0
0
entry mode set
sets mode to increment address by 1
and to shift the cursor to the right at the
time of write to the DDRAM/CGRAM;
display is not shifted
0
0
0
0
0
0
0
1
0
1
0
0
6
‘write data’ to CGRAM/DDRAM
writes ’P’; the DDRAM has already
been selected by initialization at
power-on; the cursor is incremented by
1 and shifted to the right
1
1
0
0
0
0
1
0
0
0
1
0
P
16.4 8-bit operation, 1-line display using internal reset
Table 22 and Table 23 show an example of a 1-line display in 8-bit operation. The
PCF2113x functions must be set by the ‘function set’ instruction prior to display. Since the
DDRAM can store data for 80 characters, the RAM can be used for advertising displays
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
49 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
when combined with display shift operation. Since the display shift operation changes
display position only and the DDRAM contents remain unchanged, display data entered
first can be displayed when the ‘return home’ operation is performed.
Table 22. 8-bit operation, 1-line display example; using internal reset (character set ‘A’)
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
2
power supply on (PCF2113x is initialized by the internal
reset)
initialized; no display appears
function set
sets to 8-bit operation, selects 1-line
display and VLCD = VA
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
3
4
display control
turns on display and cursor; entire
display is blank after initialization
0
0
0
entry mode set
sets mode to increment the address
by 1 and to shift the cursor to the
right at the time of the write to the
DDRAM/CGRAM; display is not
shifted
0
0
0
5
‘write data’ to CGRAM/DDRAM
writes ‘P’; the DDRAM has already
been selected by initialization at
power-on; the cursor is incremented
by 1 and shifted to the right
1
0
0
1
0
1
0
1
0
0
0
0
0
0
P
6
‘write data’ to CGRAM/DDRAM
writes ‘H’
writes ‘ILIP’
writes ‘S’
1
0
0
1
0
0
:
PH
7 to 10
11
:
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
0
1
PHILIPS
PHILIPS
HILIPS
12
entry mode set
sets mode for display shift at time of
write
0
0
0
0
0
13
‘write data’ to CGRAM/DDRAM
writes space
1
0
0
0
1
14
‘write data’ to CGRAM/DDRAM
writes ‘M’
1
0
0
1
0
0
:
HILIPS M
15 to 19
20
writes ‘ICROK’
writes ‘O’
:
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
MICROKO
MICROKO
MICROKO
ICROCO
21
cursor/display shift
shifts only the cursor position to the
left
0
0
0
22
cursor/display shift
shifts only the cursor position to the
left
0
0
0
23
‘write data’ to CGRAM/DDRAM
writes ‘C’ correction; the display
moves to the left
1
0
0
1
0
24
cursor/display shift
shifts the display and cursor to the
right
0
0
0
0
0
MICROCO
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
50 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 22. 8-bit operation, 1-line display example; using internal reset (character set ‘A’) …continued
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
25
cursor/display shift
shifts only the cursor to the right
writes ‘M’
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
1
0
MICROCO
ICROCOM
PHILIPS M
26
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
27
return home
returns both display and cursor to
the original position (address 0)
0
0
0
0
0
Table 23. 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
power supply on (PCF2113x is initialized by the internal reset)
function set
1
2
initialized; no display appears
sets to 8-bit operation, selects 1-line
display and VLCD = VA
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
3
4
display control
turns on display and cursor; entire
display is blank after initialization
0
0
0
entry mode set
sets mode to increment the address
by 1 and to shift the cursor to the
right at the time of the write to the
DDRAM/CGRAM; display is not
shifted
0
0
0
5
set CGRAM address
sets the CGRAM address to
position of character ‘0’; the
CGRAM is selected
0
0
0
1
0
0
0
1
0
0
0
1
0
0
6
7
8
‘write data’ to CGRAM/DDRAM
writes data to CGRAM for icon even
phase; icon appears
1
0
0
0
0
0
:
:
sets CGRAM address
sets the CGRAM address to
position of character ‘0’; the
CGRAM is selected
0
0
0
1
1
1
0
1
0
0
0
1
0
0
9
‘write data’ to CGRAM/DDRAM
writes data to CGRAM for icon odd
phase
1
0
0
0
0
0
:
10
:
11
function set
sets H = 1: Extended instruction set
icons blink
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
12
icon control
0
0
13
function set
sets H = 0
0
0
14
set DDRAM address
sets the DDRAM to the first position;
DDRAM is selected
0
0
1
0
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
51 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 23. 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’) …continued
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
‘write data’ to CGRAM/DDRAM
15
writes ‘P’; the cursor is incremented
by 1 and shifted to the right
1
0
0
1
0
1
0
0
0
0
P
16
‘write data’ to CGRAM/DDRAM
writes ‘H’
1
0
0
1
0
0
:
1
0
0
0
PH
17
writes ‘ILIPS’
:
22
return home
returns both display and cursor to
the original position (address 0)
0
0
0
0
0
0
0
0
1
0
PHILIPS
16.5 8-bit operation, 2-line display
For a 2-line display the cursor automatically moves from the first to the second line after
the 40th digit of the first line has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the 8th character is completed (see
Table 24). It should be noted that both lines of the display are always shifted together;
data does not shift from one line to the other.
Table 24. 8-bit operation, 2-line display example; using internal reset
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
power supply on (PCF2113x is initialized by the internal reset)
function set
1
2
initialized; no display appears
sets to 8-bit operation, selects
1-line display and VLCD = VA
0
0
0
0
1
1
0
1
0
0
3
4
display control
turns on display and cursor;
entire display is blank after
initialization
0
0
0
0
0
0
1
1
1
0
entry mode set
sets mode to increment the
address by 1 and to shift the
cursor to the right at the time of
the write to the DDRAM/CGRAM;
display is not shifted
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
5
‘write data’ to CGRAM/DDRAM
writes ‘P’; the DDRAM has
already been selected by
initialization at power-on; the
cursor is incremented by 1 and
shifted to the right
1
0
0
1
0
P
6 to 10
11
:
:
writes ‘HILIP’
‘write data’ to CGRAM/DDRAM
writes ‘S’
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
PHILIPS
PHILIPS
12
sets DDRAM address
sets DDRAM to position the
cursor at the start of the 2nd line
0
0
1
1
0
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
52 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 24. 8-bit operation, 2-line display example; using internal reset …continued
Step
Instruction
Display
Operation
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
‘write data’ to CGRAM/DDRAM
13
writes ‘M’
1
0
0
1
0
0
1
1
0
1
PHILIPS
M
14 to 18
19
:
:
writes ‘ICROC’
writes ‘O’
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
PHILIPS
MICROCO
20
21
22
entry mode set
sets mode for display shift at the
time of write
0
0
0
0
0
PHILIPS
MICROCO
‘write data’ to CGRAM/DDRAM
writes ‘M’; display is shifted to the
left; the 1st and 2nd lines shift
together
1
0
0
0
1
0
HILIPS
ICROCOM
return home
returns both the display and
cursor to the original position
(address 0)
0
0
0
0
PHILIPS
MICROCOM
16.6 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 25).
[1]
Table 25. Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS
)
Step
I2C-bus byte
Display
Operation
1
2
I2C-bus start
initialized; no display appears
slave address for write
during the acknowledge cycle SDA is
pulled down by the PCF2113x
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
1
1
1
0
1
0
0
0
3
4
5
6
send a control byte for ‘function set’
control byte sets RS for the following
data bytes
Co
0
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
Ack
1
function set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
selects 1-line display and VLCD = VA;
SCL pulse during acknowledge cycle
starts execution of instruction
0
0
1
X
0
0
0
0
1
display control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
turns on display and cursor; entire
display shows character 20h (blank in
ASCII-like character sets)
0
0
0
0
1
1
1
0
1
entry mode set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
sets mode to increment the address
by 1 and to shift the cursor to the right
at the time of write to the DDRAM or
CGRAM; display is not shifted
0
0
0
0
0
1
1
0
1
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
53 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
[1]
Table 25. Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS
)
…continued
Step
I2C-bus byte
Display
Operation
7
I2C-bus start
to write data to DDRAM, RS must be
set to 1 so a control byte is needed
8
slave address for write
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
1
1
1
0
1
0
0
1
9
send a control byte for ‘write data’
Co
0
RS
1
0
0
0
0
0
0
0
0
0
0
0
0
Ack
1
10
11
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
writes ‘P’; the DDRAM is selected at
power-up; the cursor is incremented
by 1 and shifted to the right
P
0
1
0
1
0
0
0
0
1
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PH
writes ‘H’
0
1
0
0
1
0
:
0
0
1
12 to 15
16
writes ‘ILIP’
writes ‘S’
:
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
1
0
1
0
0
1
1
1
17
18
(optional I2C-bus stop) I2C-bus start + slave address for
write (as step 8)
PHILIPS
control byte
Co
1
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
Ack PHILIPS
1
19
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
sets DDRAM address 0 in address
counter (also returns shifted display
to original position; DDRAM contents
unchanged); this instruction does not
update the Data Register (DR)
0
0
0
0
0
0
1
0
1
20
21
I2C-bus start
slave address for read
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS
PHILIPS
during the acknowledge cycle the
content of DR is loaded into the
internal I2C-bus interface to be shifted
out; in the previous instruction neither
a ‘set address’ nor a ‘read data’ has
been performed, so the content of the
DR was unknown; the R/W has to be
set to 1 while still in the I2C-bus write
mode
0
1
1
1
0
1
0
1
1
22
control byte for read
DDRAM content is read from the
following instructions
Co
0
RS
1
0
1
0
0
0
0
0
0
0
0
0
0
Ack PHILIPS
1
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
54 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
[1]
Table 25. Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS
)
…continued
Step
I2C-bus byte
Display
Operation
23
‘read data’: 8 × SCL + master acknowledge [2]
8 × SCL; content loaded into interface
during previous acknowledge cycle is
shifted out over SDA; MSB is DB7;
during master acknowledge content
of DDRAM address 01 is loaded into
the I2C-bus interface
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
X
X
X
X
X
X
X
X
0
24
25
‘read data’: 8 × SCL + master acknowledge [2]
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
8 × SCL; code of letter ‘H’ is read first;
during master acknowledge, code of
‘I’ is loaded into the I2C-bus interface
0
1
0
0
1
0
0
0
0
‘read data’: 8 × SCL + master acknowledge [2]
no master acknowledge;
-after the content of the I2C-bus
interface register is shifted out no
internal action is performed;
-no new data is loaded into the
interface register;
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
1
0
0
1
0
0
1
1
-data register is not updated;
-address counter is not incremented
and cursor is not shifted
26
I2C-bus stop
PHILIPS
[1] X = not relevant.
[2] SDA is left at high-impedance by the microcontroller during the read acknowledge.
Table 26. Initialization by instruction, 8-bit interface [1]
Step Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
1
internal reset
:
starting from power-on or unknown state
:
2
wait 2 ms
:
:
3
4
0
0
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
function set (interface is 8 bit long). Busy Flag (BF)
cannot be checked before this instruction
wait 2 ms
:
:
5
6
0
0
1
function set (interface is 8 bit long). BF cannot be
checked before this instruction
wait more than 40 µs
:
:
7
8
0
0
0
0
1
function set (interface is 8 bit long). BF cannot be
checked before this instruction
:
:
:
BF can be checked after the following instructions;
when BF is not checked the waiting time between
instructions is the specified instruction time (see
Table 10)
9
0
0
0
0
0
0
0
0
1
0
1
0
1
M
0
0
0
H
0
function set (interface is 8 bit long); specify the
number of display lines
10
0
display off
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
55 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 26. Initialization by instruction, 8-bit interface [1] …continued
Step Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
11
12
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
1
0
1
clear display
I/D
S
entry mode set
13
initialization ends
[1] X = not relevant.
Table 27. Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
Step Instruction Description
1
2
3
4
5
6
7
8
internal reset
:
starting from power-on or unknown state
:
wait 2 ms
:
:
RS
0
R/W
0
DB7
0
DB6
DB5
1
DB4
1
BF cannot be checked before this instruction
function set (interface is 8 bit long)
0
wait 2 ms
:
:
RS
0
R/W
DB7
0
DB6
DB5
1
DB4
1
BF cannot be checked before this instruction
function set (interface is 8 bit long)
0
0
wait more than 40 µs
:
:
RS
0
R/W
0
DB7
0
DB6
DB5
1
DB4
1
BF cannot be checked before this instruction
function set (interface is 8 bit long)
0
:
BF can be checked after the following instructions; when BF is
not checked the waiting time between instructions is the specified
instruction time (see Table 10)
:
9
RS
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
0
function set (set interface to 4 bit long)
interface is 8 bit long
10
11
12
13
0
0
0
0
1
0
function set (interface is 4 bit long)
specify number of display lines
0
0
0
M
0
0
H
0
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
0
0
0
0
0
1
clear display
entry mode set
0
0
0
0
0
0
0
0
0
1
I/D
S
:
14
initialization ends
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
56 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
17. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 14.1 14.1
0.17 0.09 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-01
03-02-20
SOT407-1
136E20
MS-026
Fig 39. Package outline SOT407-1 (LQFP100)
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
57 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
18. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
MOS devices; see JESD625-A and/or IEC61340-5.
19. Packing information
x
A
C
y
D
B
F
E
mgu206
Fig 40. Tray details
Table 28. Tray dimensions (see Figure 40)
Symbol
Description
Value
A
B
C
D
E
F
x
pocket pitch in x direction
pocket pitch in y direction
pocket width in x direction
pocket width in y direction
tray width in x direction
tray width in y direction
6.35 mm
5.59 mm
3.82 mm
3.66 mm
50.8 mm
50.8 mm
7
number of pockets, x direction
number of pockets, y direction
y
8
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
58 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
PCF2113x
mgu207
Fig 41. Tray alignment
The orientation of the IC in a pocket is indicated by the position of the IC type name on the
die surface with respect to the chamfer on the upper left corner of the tray. Refer to the
bonding pad location diagram (Figure 3) for the orientation and position of the type name
on the die surface.
20. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
20.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
20.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
© NXP B.V. 2008. All rights reserved.
PCF2113_FAM_4
Product data sheet
Rev. 04 — 4 March 2008
59 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
20.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
20.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 42) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 29 and 30
Table 29. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
60 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
Table 30. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
260
> 2000
260
< 1.6
1.6 to 2.5
> 2.5
260
250
245
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 42.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 42. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
61 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
21. Revision history
Table 31. Revision history
Document ID
PCF2113_FAM_4
Modifications:
Release date
20080304
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF2113_FAM_3
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Figure 3, Figure 13, Figure 20 and Figure 21: new graphics.
• Table 2 added: marking codes table.
• Table 4: adjusted die size.
• Table 18 and Table 19: adjusted values.
• Table 25: changed byte settings.
PCF2113_FAM_3
(9397 750 06995)
20011219
19970404
19961021
Product specification
Preliminary data sheet
Preliminary specification
-
-
-
PCF2113_FAM_2
PCF2113_FAM_2
(9397 750 01753)
PCF2113_FAM_1
-
PCF2113_FAM_1
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
62 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
22.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
63 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
24. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
9.11
Read data from CGRAM or DDRAM . . . . . . . 30
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10
Extended function set instructions
and features. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
New instructions. . . . . . . . . . . . . . . . . . . . . . . 31
Icon control. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bit IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bit IB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Direct mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage multiplier control . . . . . . . . . . . . . . . . 33
Bits S1 and S0 . . . . . . . . . . . . . . . . . . . . . . . . 33
Screen configuration . . . . . . . . . . . . . . . . . . . 33
Bit L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Display configuration . . . . . . . . . . . . . . . . . . . 34
Bit P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bit Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Temperature control . . . . . . . . . . . . . . . . . . . . 35
Set VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3
10.1
10.2
10.3
10.4
10.5
10.6
10.6.1
10.7
10.7.1
10.8
10.8.1
10.8.2
10.9
10.10
10.10.1
10.11
4
5
6
7
7.1
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Functional description . . . . . . . . . . . . . . . . . . 10
LCD supply voltage generator . . . . . . . . . . . . 10
LCD bias voltage generator . . . . . . . . . . . . . . 10
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Busy flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address counter . . . . . . . . . . . . . . . . . . . . . . . 12
Display data RAM. . . . . . . . . . . . . . . . . . . . . . 12
Character generator ROM . . . . . . . . . . . . . . . 13
Character generator RAM. . . . . . . . . . . . . . . . 18
Cursor control circuit. . . . . . . . . . . . . . . . . . . . 18
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 19
LCD row and column drivers . . . . . . . . . . . . . 19
Power-down mode . . . . . . . . . . . . . . . . . . . . . 23
Reset function. . . . . . . . . . . . . . . . . . . . . . . . . 23
VLCD programming . . . . . . . . . . . . . . . . . . . . . 35
8.8
8.9
Reducing current consumption . . . . . . . . . . . 35
8.10
8.11
8.12
8.13
8.14
8.15
8.16
11
Interfaces to microcontroller . . . . . . . . . . . . . 36
Parallel interface. . . . . . . . . . . . . . . . . . . . . . . 36
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 37
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 38
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1
11.2
11.2.1
11.2.2
12
13
14
15
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 41
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42
Static characteristics . . . . . . . . . . . . . . . . . . . 43
Dynamic characteristics. . . . . . . . . . . . . . . . . 45
9
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clear display. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Return home. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Entry mode set . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit I/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Display control (and partial Power-down
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Cursor or display shift. . . . . . . . . . . . . . . . . . . 29
Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit DL (parallel mode only) . . . . . . . . . . . . . . . 29
Bit M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit SL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bit H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Set CGRAM address . . . . . . . . . . . . . . . . . . . 29
Set DDRAM address . . . . . . . . . . . . . . . . . . . 30
Read busy flag and read address. . . . . . . . . . 30
Write data to CGRAM or DDRAM. . . . . . . . . . 30
9.1
9.2
9.3
9.3.1
9.3.2
9.4
16
Application information . . . . . . . . . . . . . . . . . 47
Application diagrams . . . . . . . . . . . . . . . . . . . 47
General application information . . . . . . . . . . . 49
4-bit operation, 1-line display using
internal reset . . . . . . . . . . . . . . . . . . . . . . . . . 49
8-bit operation, 1-line display using
internal reset . . . . . . . . . . . . . . . . . . . . . . . . . 49
8-bit operation, 2-line display . . . . . . . . . . . . . 52
I2C-bus operation, 1-line display . . . . . . . . . . 53
16.1
16.2
16.3
16.4
9.4.1
9.4.2
9.4.3
9.5
16.5
16.6
9.6
17
18
19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 57
Handling information . . . . . . . . . . . . . . . . . . . 58
Packing information . . . . . . . . . . . . . . . . . . . . 58
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.8
9.9
9.10
20
Soldering of SMD packages . . . . . . . . . . . . . . 59
Introduction to soldering. . . . . . . . . . . . . . . . . 59
Wave and reflow soldering . . . . . . . . . . . . . . . 59
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 60
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 60
20.1
20.2
20.3
20.4
continued >>
PCF2113_FAM_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 March 2008
64 of 65
PCF2113x
NXP Semiconductors
LCD controllers/drivers
21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 62
22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 63
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 63
22.1
22.2
22.3
22.4
23
24
Contact information. . . . . . . . . . . . . . . . . . . . . 63
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 March 2008
Document identifier: PCF2113_FAM_4
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明