PCF2113DU2 [NXP]

LCD controllers/drivers; LCD控制器/驱动器


型号：	PCF2113DU2
厂家：	NXP
描述：	LCD controllers/drivers LCD控制器/驱动器驱动器控制器 CD
文件：	总72页 (文件大小：333K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

PCF2113x

LCD controllers/drivers

Product speciﬁcation

2001 Dec 19

Supersedes data of 1997 Apr 04

File under Integrated Circuits, IC12

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

CONTENTS

9.5

Direct mode

9.6

9.7

9.8

9.9

9.10

9.11

Voltage multiplier control

Screen configuration

Display configuration

Temperature control

Set V_LCD

FEATURES

1.1

Note

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

Reducing current consumption

INTERFACES TO MICROCONTROLLER

10.1

10.2

Parallel interface

I²C-bus interface

FUNCTIONAL DESCRIPTION

LIMITING VALUES

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

LCD supply voltage generator

LCD bias voltage generator

Oscillator

External clock

Power-on reset

Power-down mode

Registers

Busy flag

Address Counter (AC)

Display Data RAM (DDRAM)

Character Generator ROM (CGROM)

Character Generator RAM (CGRAM)

Cursor control circuit

Timing generator

HANDLING INSTRUCTIONS

DC CHARACTERISTICS

AC CHARACTERISTICS

DEVICE PROTECTION CIRCUITS

APPLICATION INFORMATION

16.1

16.2

General application information

4-bit operation, 1-line display using internal

reset

8-bit operation, 1-line display using internal

reset

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

16.3

16.4

16.5

8-bit operation, 2-line display

I²C-bus operation, 1-line display

BONDING PAD INFORMATION

TRAY INFORMATION

PACKAGE OUTLINE

SOLDERING

LCD row and column drivers

Reset function

INSTRUCTIONS

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.11

Clear display

Return home

Entry mode set

Display control (and partial Power-down mode)

Cursor or display shift

Function set

Set CGRAM address

Set DDRAM address

20.1

Introduction to soldering surface mount

packages

Reflow soldering

Wave soldering

Manual soldering

20.2

20.3

20.4

20.5

Suitability of surface mount IC packages for

wave and reflow soldering methods

Read busy flag and read address

Write data to CGRAM or DDRAM

Read data from CGRAM or DDRAM

DATA SHEET STATUS

DEFINITIONS

EXTENDED FUNCTION SET

INSTRUCTIONS AND FEATURES

DISCLAIMERS

BARE DIE DISCLAIMER

PURCHASE OF PHILIPS I²C COMPONENTS

9.1

9.2

9.3

9.4

New instructions

Icon control

Bit IM

Bit IB

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

FEATURES

• Single-chip LCD controller/driver

• 2-line display of up to 12 characters + 120 icons, or

1-line display of up to 24 characters + 120 icons

• 5 × 7 character format plus cursor; 5 × 8 for kana

(Japanese) and user defined symbols

1.1

Note

• Icon mode: reduced current consumption while

displaying

Icon mode is used to save current. When only icons are

displayed, a much lower operating voltage V_LCDcan be

used and the switching frequency of the LCD outputs is

reduced. In most applications it is possible to use V_DDas

• Icon blink function

• On-chip:

– Configurable 4, 3 or 2 voltage multiplier generating

V_LCD

LCD supply voltage, independent of V_DD

programmable by instruction (external supply also

possible)

APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

– Temperature compensation of on-chip generated

V_LCD: −0.16 to −0.24 %/K (programmable by

instruction)

– Generation of intermediate LCD bias voltages

– Oscillator requires no external components

(external clock also possible).

GENERAL DESCRIPTION

The PCF2113x is a low power CMOS LCD controller and

driver, designed to drive a dot matrix LCD display of 2-line

by 12 or 1-line by 24 characters with 5 × 8 dot format.

All necessary functions for the display are provided in a

single chip, including on-chip generation of LCD bias

voltages, resulting in a minimum of external components

and lower system current consumption. The PCF2113x

interfaces to most microcontrollers via a 4 or 8-bit bus or

via the 2-wire I²C-bus. The chip contains a character

generator and displays alphanumeric and kana

• Display data RAM: 80 characters

• Character generator ROM: 240, 5 × 8 characters

• Character generator RAM: 16, 5 × 8 characters;

3 characters used to drive 120 icons, 6 characters used

if icon blink feature is used in application

• 4 or 8-bit parallel bus and 2-wire I²C-bus interface

• CMOS compatible

• 18 row and 60 column outputs

(Japanese) characters. The letter ‘x’ in PCF2113x

characterizes the built-in character set. Various character

sets can be manufactured on request.

• Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for

single line operation) and 1 : 2 (for icon only mode)

• Uses common 11 code instruction set (extended)

• Logic supply voltage range V_DD1− V_SS1= 1.8 to 5.5 V

(chip may be driven with two battery cells)

• V_LCDgenerator supply voltage range

V_DD2− V_SS2= 2.2 to 4.0 V

• Display supply voltage range V_LCD− V_SS2= 2.2 to 6.5 V

• Direct mode to save current consumption for icon mode

and Mux 1 : 9 (depending on V_DD2value and LCD liquid

properties)

• Very low current consumption (20 to 200 µA):

– Icon mode: <25 µA

– Power-down mode: <2 µA.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

PCF2113AU/10/F4

−

chip on ﬂexible ﬁlm carrier

−

PCF2113DU/10/F4

PCF2113DU/F4

PCF2113DH/F4

−

chip on ﬂexible ﬁlm carrier

chip in tray

−

LQFP100

plastic low proﬁle quad ﬂat package; 100 leads;

SOT407-1

body 14 × 14 × 1.4 mm

PCF2113DU/2/F4

PCF2113EU/2/F4

PCF2113WU/2/F4

−

chip with bumps in tray

−

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

BLOCK DIAGRAM

handbook, full pagewidth

C1 to C60

R1 to R18

COLUMN DRIVERS

ROW DRIVERS

BIAS

VOLTAGE

LCD1

GENERATOR

DATA LATCHES

SHIFT REGISTER 18-BIT

LCDSENSE

LCD

GENERATOR

SHIFT REGISTER 5 × 12 BIT

LCD2

OSC

OSCILLATOR

CURSOR AND DATA CONTROL

DD1

CHARACTER

GENERATOR

ROM

DD2

GENERATOR

RAM (128 × 5)

(CGRAM)

DD3

(CGROM)

16 CHARACTERS

240 CHARACTERS

TIMING

GENERATOR

SS1

SS2

DISPLAY DATA RAM

(DDRAM)

80 CHARACTERS/BYTES

DISPLAY

ADDRESS

COUNTER

ADDRESS COUNTER

(AC)

INSTRUCTION

DECODER

PCF2113x

DATA

(DR)

INSTRUCTION

BUSY

FLAG

POWER-ON

RESET

I/O BUFFER

MGE990

SCL

SDA

DB4 to DB7

DB0 to DB3/SA0

R/W

Fig.1 Block diagram.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

PINNING

SYMBOL

PCF2113DH PCF2113XU

PAD⁽¹⁾

TYPE

DESCRIPTION

V_DD1

supply voltage 1 for all except V_LCDgenerator

oscillator/external clock input; note 2

OSC

power-down select input; for normal operation PD is LOW

test pad; open circuit and not user accessible

test pin; must be connected to V_SS1

−

test pad; must be connected to V_SS1

V_SS1

ground 1 for all except V_LCDgenerator

ground 2 for V_LCDgenerator

V_SS2

V_LCD2

V_LCDoutput if V_LCDis generated internally; note 7

input (V_LCD) for voltage multiplier regulation; notes 3 and 7

input for generation of LCD bias levels; note 7

LCD row driver outputs 9 to 16

V_LCDSENSE

V_LCD1

−

R9 to R16

R18

9 to 16

12 to 19

−

LCD row driver output 18

C60 to C53

dummy pad

C52 to C28

dummy pad

C27 to C3

dummy pad

18 to 25

21 to 28

LCD column driver outputs 60 to 53

−

26 to 50

31 to 55

−

LCD column driver outputs 52 to 28

LCD column driver outputs 27 to 3

−

51 to 75

−

58 to 82

−

LCD column driver output 2

LCD column driver output 1

LCD row driver outputs 8 to 1

LCD row driver output 17

I²C-bus serial clock input; note 4

I²C-bus serial data input/output; note 4

data bus clock input; note 4

R8 to R1

R17

78 to 85

87 to 94

SCL

SDA

I/O

R/W

100

101

102

103

104

105

read/write input

DB7

I/O

8-bit bidirectional data bus bit 7; note 5

8-bit bidirectional data bus bit 6

8-bit bidirectional data bus bit 5

8-bit bidirectional data bus bit 4

8-bit bidirectional data bus bit 3 or I²C-bus address pin;

notes 4 and 5

DB6

DB5

DB4

DB3/SA0

DB2

DB1

106

107

I/O

8-bit bidirectional data bus bit 2

8-bit bidirectional data bus bit 1

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

PAD⁽¹⁾

SYMBOL

DB0

TYPE

DESCRIPTION

8-bit bidirectional data bus bit 0

PCF2113DH PCF2113XU

100

−

108

109

110

I/O

V_DD2

V_DD3

supply voltage 2 for V_LCDgenerator; note 6

supply voltage 3 for V_LCDgenerator; notes 3 and 6

Notes

1. Bonding pad location information is given in Chapter 17.

2. When the on-chip oscillator is used this pad must be connected to V_DD1

3. In the LQFP100 version this signal is connected internally and can not be accessed at any pin.

4. When the I²C-bus is used, the parallel interface pin E must be LOW. In the I²C-bus read mode DB7 to DB0 should

be connected to V_DD1or left open-circuit.

When the parallel bus is used, the pins SCL and SDA must be connected to V_SS1or V_DD1; they must not be left

open-circuit.

When the 4-bit interface is used without reading out from the PCF2113x (R/W is set permanently to logic 0), the

unused ports DB0 to DB4 can either be set to V_SS1or V_DD1instead of leaving them open-circuit.

5. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the

four higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I²C-bus operations

(see note 4).

6. V_DD2and V_DD3should always be equal.

7. When V_LCDis generated internally, pins V_LCD1, V_LCD2and V_LCDSENSEmust be connected together. When external

V_LCDis supplied, pin V_LCD2should be left open-circuit to avoid any stray current, pins V_LCD1and V_LCDSENSEmust be

connected together.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

75 C3

DD1

OSC

72 C6

71 C7

SS1

SS2

LCD2

68 C10

67 C11

LCD1

R10 10

C12

C13

R11

R12

R13

64 C14

63 C15

PCF2113x

R14 14

R15 15

C16

C17

R16

60 C18

59 C19

R18 17

C60 18

C59 19

C20

C21

C58

56 C22

55 C23

C57 21

C56 22

C55 23

C54 24

C53 25

C24

C25

C26

51 C27

MGE989

Fig.2 Pin configuration (LQFP100).

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

FUNCTIONAL DESCRIPTION

LCD supply voltage generator

The generated V_LCDis independent of V_DDand is

temperature compensated. When the V_LCDgenerator and

the direct mode are switched off, an external voltage may

be supplied at connected pins V_LCD1and V_LCD2. V_LCD1and

7.1

The LCD supply voltage may be generated on-chip. The

V_LCDgenerator is controlled by two internal 6-bit registers:

V_Aand V_B. The nominal LCD operating voltage at room

temperature is given by the relationship:

V_LCD2may be higher or lower than V_DD2.

During direct mode (program DM register bit) the internal

V_LCDgenerator is turned off and the V_LCD2output voltage

is directly connected to V_DD2. This reduces the current

consumption during icon mode and Mux 1 : 9 (depending

on V_DD2value and LCD liquid properties).

V_OP(nom)= (integer value of register × 0.08) + 1.82

7.1.1

PROGRAMMING RANGES

Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V.

T_ref= 27 °C.

The V_LCDgenerator ensures that, as long as V_DDis in the

valid range (2.2 to 4 V), the required peak voltage

V_OP= 6.5 V can be generated at any time.

Values producing more than 6.5 V at operating

temperature are not allowed. Operation above this

voltage may damage the device. When programming the

operating voltage the V_LCDtolerance and temperature

coefficient must be taken into account.

7.2

LCD bias voltage generator

The intermediate bias voltages for the LCD display are

also generated on-chip. This removes the need for an

external resistive bias chain and significantly reduces the

system current consumption. The optimum value of V_LCD

depends on the multiplex rate, the LCD threshold voltage

(V_th) and the number of bias levels. Using a 5-level bias

scheme for 1 : 18 maximum rate allows V_LCD< 5 V for

most LCD liquids. The intermediate bias levels for the

different multiplex rates are shown in Table 1. These bias

levels are automatically set to the given values when

switching to the corresponding multiplex rate.

Values below 2.2 V are below the specified operating

range of the chip and are therefore not allowed.

Value 0 for V_Aand V_Bswitches the generator off

(i.e. V_A= 0 in character mode, V_B= 0 in icon mode).

Usually register V_Ais programmed with the voltage for

character mode and register V_Bwith the voltage for icon

mode.

When V_LCDis generated on-chip the V_LCDpins should be

decoupled to V_SSwith a suitable capacitor.

Table 1 Bias levels as a function of multiplex rate; note 1

MULTIPLEX

RATE

NUMBER

OF LEVELS

V₁

V₂

V₃

V₄

V₅

V₆

1 : 18

1 : 9

1 : 2

V_LCD

V_SS

Note

1. The values in the table are given relative to V_LCD− V_SS, e.g. ³/₄means ³/₄× (V_LCD− V_SS).

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

7.3

Oscillator

The data register temporarily stores data to be read from

the DDRAM and CGRAM. When reading, data from the

DDRAM or CGRAM corresponding to the address in the

instruction register is written to the data register prior to

being read by the ‘read data’ instruction.

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC pin must be connected to V_DD1

7.4 External clock

7.8

Busy ﬂag

If an external clock is to be used this input is at the OSC

pin. The resulting display frame frequency is given by:

The busy flag indicates the internal status of the

PCF2113x. A logic 1 indicates that the chip is busy and

further instructions will not be accepted. The busy flag is

output to pin DB7 when bit RS = 0 and bit R/W = 1.

Instructions should only be written after checking that the

busy flag is at logic 0 or waiting for the required number of

cycles.

---^O----^S---^C---

3072

f_frame

Only in the Power-down mode is the clock allowed to be

stopped (OSC connected to V_SS), otherwise the LCD is

frozen in a DC state.

7.9

Address Counter (AC)

7.5

Power-on reset

The address counter assigns addresses to the DDRAM

and CGRAM for reading and writing and is set by the

commands ‘set CGRAM address’ and ‘set DDRAM

address’. After a read/write operation the address counter

is automatically incremented or decremented by 1.

The address counter contents are output to the bus

(DB6 to DB0) when bit RS = 0 and bit R/W = 1.

The on-chip Power-on reset block initializes the chip after

power-on or power failure. This is a synchronous reset and

requires 3 oscillator cycles to be executed.

7.6

Power-down mode

The chip can be put into Power-down mode by applying an

external active HIGH level to the PD pin. In Power-down

mode all static currents are switched off (no internal

oscillator, no bias level generation and all LCD outputs are

internally connected to V_SS).

7.10 Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data

represented by 8-bit character codes. RAM locations

which are not used for storing display data can be used as

general purpose RAM. The basic RAM to display

addressing scheme is shown in Fig.3. With no display shift

the characters represented by the codes in the first

24 RAM locations starting at address 00H in line 1 are

displayed. Figures 4 and 5 show the display mapping for

right and left shift respectively.

During power-down, information in the RAMs and the chip

state are preserved. Instruction execution during

power-down is possible when pin OSC is externally

clocked.

7.7

Registers

The PCF2113x has two 8-bit registers, an Instruction

Select (RS) signal determines which register will be

accessed. The instruction register stores instruction codes

such as ‘display clear’, ‘cursor shift’, and address

information for the Display Data RAM (DDRAM) and

Character Generator RAM (CGRAM).The instruction

controller.

When data is written to or read from the DDRAM,

wrap-around occurs from the end of one line to the start of

the next line. When the display is shifted each line wraps

around within itself, independently of the others. Thus all

lines are shifted and wrapped around together.

The address ranges and wrap-around operations for the

various modes are shown in Table 2.

Table 2 Address space and wrap-around operation

MODE

1 × 24

2 × 12

1 × 12

Address space

00 to 4F

4F to 00

00 to 27; 40 to 67

27 to 40; 67 to 00

27 to 00; 67 to 40

00 to 27

27 to 00

Read/write wrap-around (moves to next line)

Display shift wrap-around (stays within line)

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

non-displayed DDRAM addresses

display

handbook, full pagewidth

position

22 23 24

DDRAM

address

00 01 02 03 04

15 16 17 18 19

4C 4D 4E 4F

1-line display

non-displayed DDRAM address

10 11 12

00 01 02 03 04

09 0A 0B 0C 0D

24 25 26 27

line 1

line 2

DDRAM

address

10 11 12

40 41 42 43 44

49 4A 4B 4C 4D

64 65 66 67

MGE991

2-line display

Fig.3 DDRAM to display mapping; no shift.

display

position

handbook, halfpage

22 23 24

14 15 16

4F 00 01 02 03

DDRAM

address

1-line display

10 11 12

08 09 0A

line 1

line 2

27 00 01 02 03

DDRAM

address

10 11 12

48 49 4A

67 40 41 42 43

MGE992

2-line display

Fig.4 DDRAM to display mapping; right shift.

display

position

handbook, halfpage

22 23 24

16 17 18

01 02 03 04 05

DDRAM

address

1-line display

10 11 12

0A 0B 0C

line 1

line 2

01 02 03 04 05

DDRAM

address

10 11 12

4A 4B 4C

41 42 43 44 45

MGE993

2-line display

Fig.5 DDRAM to display mapping; left shift.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

7.11 Character Generator ROM (CGROM)

7.14 Timing generator

The CGROM generates 240 character patterns in a

5 × 8 dot format from 8-bit character codes.

Figures 7, 8, 9 and 10 show the character sets that are

currently implemented.

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data buses.

7.15 LCD row and column drivers

7.12 Character Generator RAM (CGRAM)

The PCF2113x contains 18 row and 60 column drivers,

which connect the appropriate LCD bias voltages in

sequence to the display in accordance with the data to be

displayed. R17 and R18 drive the icon rows.

Up to 16 user defined characters may be stored in the

CGRAM. Some CGRAM characters (see Fig.16) are also

used to drive icons (6 if icons blink and both icon rows are

used in the application; 3 if no blink but both icon rows are

used in the application; 0 if no icons are driven by the icon

rows). The CGROM and CGRAM use a common address

space, of which the first column is reserved for the

CGRAM (see Fig.7). Figure 11 shows the addressing

principle for the CGRAM.

The bias voltages and the timing are selected

automatically when the number of lines in the display is

selected. Figures 12, 13, 14 and 15 show typical

waveforms. Unused outputs should be left unconnected.

7.13 Cursor control circuit

The cursor control circuit generates the cursor underline

and/or cursor blink as shown in Fig.6 at the DDRAM

address contained in the address counter.

When the address counter contains the CGRAM address

the cursor will be inhibited.

MGA801

cursor

5 x 7 dot character font

alternating display

cursor display example

blink display example

Fig.6 Cursor and blink display examples.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MGE994

Fig.7 Character set ‘A’ in CGROM.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MGD688

Fig.8 Character set ‘D’ in CGROM.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MGD689

Fig.9 Character set ‘E’ in CGROM.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MGU204

Fig.10 Character set ‘W’ in CGROM.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

character codes

(DDRAM data)

CGRAM

address

character patterns

(CGRAM data)

character code

(CGRAM data)

handbook, full pagewidth

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

character

pattern

example 1

cursor

position

character

pattern

example 2

MGE995

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with

the cursor. Data in the 8th position will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure.

As shown in Figs 7 and 8, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds

to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in

the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag’ and ‘address

counter’ command.

Fig.11 Relationship between CGRAM addresses, data and display patterns.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

frame n

frame n + 1

state 1 (ON)

state 2 (OFF)

handbook, full pagewidth

LCD

V /V

ROW 1

ROW 9

ROW 2

COL1

LCD

V /V

LCD

V /V

LCD

V /V

LCD

V /V

COL2

0.5V

0.25V

0 V

state 1

−0.25V

−0.5V

−V

0.5V

0.25V

0 V

state 2

−0.25V

−0.5V

−V

MGE996

Fig.12 MUX 1 : 18 LCD waveforms; character mode.

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PCF2113x

handbook, full pagewidth

frame n

frame n + 1

state 1 (ON)

state 2 (OFF)

LCD

V /V

ROW 1

ROW 2

ROW 3

COL1

LCD

V /V

LCD

V /V

LCD

V /V

LCD

V /V

COL2

0.5V

0.25V

0 V

state 1

−0.25V

−0.5V

−V

0.5V

0.25V

0 V

state 2

−0.25V

−0.5V

−V

MGU217

R10 to R18 to be left open.

Fig.13 MUX 1 : 9 LCD waveforms; character mode.

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Product speciﬁcation

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PCF2113x

frame n

frame n + 1

handbook, full pagewidth

only icons are

driven (MUX 1 : 2)

LCD

2/3

1/3

ROW 17

ROW 18

LCD

2/3

1/3

LCD

2/3

1/3

ROW 1 to 16

LCD

2/3

1/3

COL 1

ON/OFF

LCD

2/3

1/3

COL 2

COL 3

COL 4

/ON

OFF

LCD

2/3

1/3

ON/ON

LCD

2/3

1/3

OFF/OFF

MGE997

Fig.14 MUX 1 : 2 LCD waveforms; icon mode.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

frame n

frame n + 1

PIXEL

state 1 (ON)

state 2 (OFF)

2/3 V

1/3 V

R17

state 1

COL 1 -

ROW 17

R18

R1-16

−1/3 V

−2/3 V

−V

state 3 (OFF)

2/3 V

1/3 V

state 2

COL 2 -

ROW 17

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

state 3

COL 1 -

ROW 1 to 16

−1/3 V

−2/3 V

−V

MGE998

V_ON(rms)= 0.745V_OP

V_OFF(rms)= 0.333V_OP

V_ON

D =

= 2.23

-------------

V_OFF

Fig.15 MUX 1 : 2 LCD waveforms; icon mode.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

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PCF2113x

7.16 Reset function

The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, including

a ‘clear display’, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 3.

Table 3 State after reset

STEP

FUNCTION

clear display

CONTROL BIT STATE

CONDITIONS

entry mode set

I/D = 1

+1 (increment)

S = 0

D = 0

C = 0

B = 0

DL = 1

M = 0

H = 0

SL = 0

no shift

display control

display off

cursor off

cursor character blink off

8-bit interface

1-line display

function set

normal instruction set

MUX 1 : 18 mode

default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until

initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software;

see Tables 17 and 18

icon control

IM = 0; IB = 0; DM = 0

icons, icon blink and direct

mode disabled

display/screen conﬁguration

L = 0; P = 0; Q = 0

TC1 = 0; TC2 = 0

V_A= 0; V_B= 0

default conﬁgurations

default temperature coefﬁcient

V_LCDgenerator off

_LCDtemperature coefﬁcient

set V_LCD

I²C-bus interface reset

Set HVgen stages

S1 = 1; S0 = 0

V_LCDgenerator voltage

multiplier set at factor 4

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

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PCF2113x

INSTRUCTIONS

In normal use, category 3 instructions are used most

frequently. However, automatic incrementing by 1

(or decrementing by 1) of internal RAM addresses after

each data write lessens the microcontroller program load.

The display shift in particular can be performed

concurrently with display data write, enabling the designer

to develop systems in minimum time with maximum

programming efficiency.

Only two PCF2113x registers, the Instruction Register (IR)

and the Data Register (DR) can be directly controlled by

the microcontroller. Before internal operation, control

information is stored temporarily in these registers, to

allow interfacing to various types of microcontrollers which

operate at different speeds or to allow interface to

peripheral control ICs.

During internal operation, no instructions other than the

‘read busy flag’ and ‘read address’ instructions will be

executed. Because the busy flag is set to a logic 1 while an

instruction is being executed, check to ensure it is a logic 0

before sending the next instruction or wait for the

maximum instruction execution time, as given in Table 5.

An instruction sent while the busy flag is logic 1 will not be

executed.

The instruction set for I²C-bus commands is given in

Table 4.

The PCF2113x operation is controlled by the instructions

shown in Table 5 together with their execution time.

Details are explained in subsequent sections.

Instructions are of 4 types, those that:

1. Designate PCF2113x functions such as display

format, data length, etcetera.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

Table 4 Instruction set for I²C-bus commands

CONTROL BYTE

COMMAND BYTE

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1

I²C-BUS COMMANDS

Co RS 0

Note

1. R/W is set together with the slave address.

2001 Dec 19

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Table 5 Instruction set with parallel bus commands

REQUIRE

INSTRUCTION

H = 0 or 1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DESCRIPTION

CLOCK

CYCLES

NOP

no operation

Function set

sets interface Data Length (DL), number of display

lines (M), single line/MUX 1 : 9 (SL) and extended

instruction set control (H)

Read busy ﬂag

and address

counter

A_C

reads the Busy Flag (BF) indicating internal

operating is being performed and reads Address

counter (A_C) contents

Read data

Write data

read data

write data

reads data from CGRAM or DDRAM

writes data from CGRAM or DDRAM

H = 0

Clear display

clears entire display and sets DDRAM address 0 in

address counter

165

Return home

Entry mode set

Display control

sets DDRAM address 0 in address counter; also

returns shifted display to original position; DDRAM

contents remain unchanged

I/D

sets cursor move direction (I/D) and speciﬁes shift

of display (S); these operations are performed

during data write and read

sets entire display on/off (D), cursor on/off (C) and

blink of cursor position character (B); D = 0 (display

off) puts chip into the Power-down mode

Cursor/display

shift

S/C R/L

A_CG

moves cursor or shifts display (S/C) to right or left

(R/L) without changing DDRAM contents

Set CGRAM

address

sets CGRAM address; bit DB6 is to be set by the

command ‘set DDRAM address’; look at the

description of the commands

Set DDRAM

address

A_DD

sets DDRAM address

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REQUIRE

INSTRUCTION

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DESCRIPTION

CLOCK

CYCLES

H = 1

Reserved

do not use

−

Screen

set screen conﬁguration (L)

conﬁguration

Display

conﬁguration

set display conﬁguration, columns (P) and rows (Q)

Icon control

DM set Icon Mode (IM), Icon Blink (IB),

Direct Mode (DM)

Temperature

control

TC1 TC2 set Temperature Coefﬁcient (TCx)

Set HVgen stages

S0 set internal V_LCDgenerator voltage multiplier stages

(S1 = 1 and S0 = 1 not allowed)

Set V_LCD

voltage

store V_LCDin register V_Aor V_B(V)

Philips Semiconductors

Product speciﬁcation

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PCF2113x

Table 6 Explanations of symbols used in Tables 4 and 5.

BIT

LOGIC STATE 0

last control byte; see Table 4

4 bits

LOGIC STATE 1

another control byte follows after data/command

8 bits

M (noimpact, 1-line by 24 display

if SL = 1)

2-line by 12 display

MUX 1 : 18 (1 × 24 or 2 × 12 character display)

MUX 1 : 9 (1 × 12 character display)

use extended instruction set

increment

use basic instruction set

decrement

I/D

display freeze

display off

display shift

display on

cursor off

cursor on

cursor character blink off; character at cursor

position does not blink

cursor character blink on; character at cursor

position blinks

S/C

R/L

cursor move

left shift

display shift

right shift

L (no impact, left/right screen: standard connection

if M = 1 or

SL = 1)

left/right screen; mirrored connection

1st 12 characters of 24; columns are from 1 to 60 1st 12 characters of 24; columns are from 1 to 60

2nd 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 60 to 1

column data: left to right; column data is displayed column data; right to left; column data is displayed

from 1 to 60

from 60 to 1

row data; top to bottom; row data is displayed from row data; bottom to top; row data is displayed

1 to 16 and icon row data is in 17 and 18

character mode; full display

icon blink disabled

from 16 to 1 and icon row data is in 18 and 17

icon mode; only icons displayed

icon blink enabled

direct mode disabled

set V_A

direct mode enabled

set V_B

8.1

Clear display

8.2

Return home

‘Clear display’ writes character code 20H into all DDRAM

addresses (the character pattern for character code 20H

must be a blank pattern), sets the DDRAM address

counter to logic 0 and returns the display to its original

position, if it was shifted. Thus, the display disappears and

the cursor or blink position goes to the left edge of the

display. Sets entry mode I/D = 1 (increment mode). S of

entry mode does not change.

‘Return home’ sets the DDRAM address counter to logic 0

and returns the display to its original position if it was

shifted. DDRAM contents do not change. The cursor or

blink position goes to the left of the first display line.

I/D and S of entry mode do not change.

The instruction ‘clear display’ requires extra execution

time. This may be allowed by checking the Busy Flag (BF)

or by waiting until the 165 clock cycles have elapsed.

The latter must be applied where no read-back options are

foreseen, as in some Chip-On-Glass (COG) applications.

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PCF2113x

8.3

Entry mode set

8.4.3

BIT B

8.3.1

BIT I/D

The character indicated by the cursor blinks when B = 1.

The cursor character blink is displayed by switching

between display characters and all dots on with a period of

When I/D = 1 (0) the DDRAM or CGRAM address

increments (decrements) by 1 when data is written into or

read from the DDRAM or CGRAM. The cursor or blink

position moves to the right when incremented and to the

left when decremented. The cursor underline and cursor

character blink are inhibited when the CGRAM is

accessed.

f_OSC

approximately 1 second, with f_blink

----------------

52224

The cursor underline and the cursor character blink can be

set to display simultaneously.

8.5

Cursor or display shift

8.3.2

BIT S

‘Cursor/display shift’ moves the cursor position or the

display to the right or left without writing or reading display

data. This function is used to correct a character or move

the cursor through the display. In 2-line displays, the

cursor moves to the next line when it passes the last

position (40) of the line. When the displayed data is shifted

repeatedly all lines shift at the same time; displayed

characters do not shift into the next line.

When S = 1, the entire display shifts either to the right

(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus

it appears as if the cursor stands still and the display

moves. The display does not shift when reading from the

DDRAM, or when writing to or reading from the CGRAM.

When S = 0, the display does not shift.

8.4

Display control (and partial Power-down mode)

The Address Counter (AC) content does not change if the

only action performed is shift display, but increments or

decrements with the ‘cursor display shift’.

8.4.1

BIT D

The display is on when D = 1 and off when D = 0. Display

data in the DDRAM is not affected and can be displayed

immediately by setting D = 1.

8.6

Function set

8.6.1

BIT DL (PARALLEL MODE ONLY)

When the display is off (D = 0) the chip is in partial

Power-down mode:

Sets interface data width. Data is sent or received in bytes

(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)

when DL = 0. When 4-bit width is selected, data is

transmitted in two cycles using the parallel bus. In a 4-bit

application DB3 to DB0 should be left open-circuit (internal

pull-ups). Hence in the first ‘function set’ instruction after

power-on M, SL and H are set to logic 1. A second

‘function set’ must then be sent (2 nibbles) to set M,

SL and H to their required values.

• The LCD outputs are connected to V_SS

• The LCD generator and bias generator are turned off.

Three oscillator cycles are required after sending the

‘display off’ instruction to ensure all outputs are at V_SS

afterwards the oscillator can be stopped. If the oscillator is

running during partial Power-down mode (‘display off’) the

chip can still execute instructions. Even lower current

consumption is obtained by inhibiting the oscillator

(OSC = V_SS).

‘Function set’ from the I²C-bus interface sets the DL bit to

logic 1.

To ensure I_DD< 1 µA, the parallel bus pins DB7 to DB0

should be connected to V_DD; pins RS and R/W to V_DDor

left open-circuit and pin PD to V_DD. Recovery from

Power-down mode: PD back to V_SS, if necessary pin OSC

back to V_DDand send a ‘display control’ instruction with

D = 1.

8.6.2

BIT M

Selects either 1-line by 24 display (M = 0) or 2-line by

12 display (M = 1).

8.6.3

BIT SL

8.4.2

BIT C

Selects MUX 1 : 9, 1-line by 12 display (independent of

M and L). Only rows 1 to 8 and 17 are to be used. All other

rows must be left open-circuit. The DDRAM map is the

same as in the 2-line by 12 display mode, however, the

second line cannot be displayed.

The cursor is displayed when C = 1 and inhibited when

C = 0. Even if the cursor disappears, the display functions

I/D, etcetera, remain in operation during display data write.

The cursor is displayed using 5 dots in the 8th line (see

Fig.6).

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PCF2113x

8.6.4

BIT H

8.10 Write data to CGRAM or DDRAM

When H = 0 the chip can be programmed via the standard

11 instruction codes used in the PCF2116 and other LCD

controllers.

‘Write data’ writes binary 8-bit data DB7 to DB0 to the

CGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written into is

determined by the previous ‘set CGRAM address’ or ‘set

DDRAM address’ command. After writing, the address

automatically increments or decrements by 1, in

When H = 1 the extended range of instructions will be

used. These are mainly for controlling the display

configuration and the icons.

accordance with the entry mode. Only bits DB4 to DB0 of

CGRAM data are valid, bits DB7 to DB5 are ‘don’t care’.

8.7

Set CGRAM address

‘Set CGRAM address’ sets bits DB5 to 0 of the CGRAM

address A_CGinto the address counter (binary A5 to A0).

Data can then be written to or read from the CGRAM.

8.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data DB7 to DB0 from the

CGRAM or DDRAM.

Attention: the CGRAM address uses the same address

(binary A6 to A0). With the ‘set CGRAM address’

command, only bits DB5 to DB0 are set. Bit DB6 can be

set using the ‘set DDRAM address’ command first, or by

using the auto-increment feature during CGRAM write. All

bits DB6 to DB0 can be read using the ‘read busy flag’ and

‘read address’ command.

The most recent ‘set address’ command determines

whether the CGRAM or DDRAM is to be read.

The ‘read data’ instruction gates the content of the Data

goes LOW again, internal operation increments (or

decrements) the AC and stores RAM data corresponding

to the new AC into the DR.

When writing to the lower part of the CGRAM, ensure that

bit DB6 of the address is not set (e.g. by an earlier DDRAM

write or read action).

There are only three instructions that update the data

• ‘Set CGRAM address’

8.8

Set DDRAM address

• ‘Set DDRAM address’

• ‘Read data’ from CGRAM or DDRAM.

‘Set DDRAM address’ sets the DDRAM address A_DDinto

the address counter (binary A6 to A0). Data can then be

written to or read from the DDRAM.

Other instructions (e.g. ‘write data’, ‘cursor/display shift’,

‘clear display’ and ‘return home’) do not modify the data

8.9

Read busy ﬂag and read address

‘Read busy flag and address counter’ read the Busy Flag

(BF) and Address Counter (AC). BF = 1 indicates that an

internal operation is in progress. The next instruction will

not be executed until BF = 0. It is recommended that the

BF status is checked before the next write operation is

executed.

EXTENDED FUNCTION SET INSTRUCTIONS AND

FEATURES

9.1

New instructions

H = 1 sets the chip into alternate instruction set mode.

9.2 Icon control

At the same time, the value of the address counter

expressed in binary A6 to A0 is read out. The address

counter is used by both CGRAM and DDRAM, and its

value is determined by the previous instruction.

The PCF2113x can drive up to 120 icons. See Fig.16 for

CGRAM to icon mapping.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

display:

COL 1 to 5

COL 6 to 10

COL 56 to 60

handbook, full pagewidth

ROW 17 –

56 57 58 59 60

ROW 18 –

61 62 63 64 65

block of 5 columns

66 67 68 69 70

116 117 118 119 120

MGE999

icon no.

handbook, full pagewidth

phase

ROW/COL

character codes

CGRAM address

CGRAM data

icon view

MSB

LSB MSB

LSB

1-5

6-10

11-15

even

17/1-5

17/6-10

17/11-15

56-60

61-65

even

17/56-60

18/1-5

116-120

1-5

even

18/56-60

17/1-5

odd (blink)

116-120

odd (blink) 18/56-60

MGG001

CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.

Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled.

Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).

Fig.16 CGRAM to icon mapping.

2001 Dec 19

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PCF2113x

9.3

Bit IM

When DM = 1, the chip is in direct mode. The internal V_LCD

generator is turned off and the V_LCD2output is directly

When IM = 0, the chip is in character mode. In the

character mode characters and icons are driven

(MUX 1 : 18). The V_LCDgenerator, if used, produces the

V_LCDvoltage programmed in register V_A.

connected to the V_LCDgenerator supply voltage V_DD2

The direct mode can be used to reduce the current

consumption when the required V_LCD2output voltage is

close to the V_DD2supply voltage. This can be the case in

icon mode or in Mux 1:9 (depending on LCD liquid

properties).

When IM = 1, the chip is in icon mode. In the icon mode

only the icons are driven (MUX 1 : 2) and the V_LCD

generator, if used, produces the V_LCDvoltage as

programmed in register V_B.

9.6

Voltage multiplier control

Table 7 Normal/icon mode operation

Bits S1 and S0

A software configurable voltage multiplier is incorporated

in the V_LCDgenerator and can be set via the ‘Set HVgen

stages’ command.

MODE

V_LCD

character mode

icon mode

generates V_A

generates V_B

The voltage multiplier control can be used to reduce

current consumption by disconnecting internal voltage

multiplier stages, depending on the required V_LCDoutput

voltage (see Table 8).

9.4

Bit IB

Icon blink control is independent of the cursor/character

blink function.

Table 8 S1 and S0 control of voltage multiplier

When IB = 0, the icon blink is disabled. Icon data is stored

in CGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for

120 icons).

DESCRIPTION

set V_LCDgenerator stages to 1

(2 x voltage multiplier)

When IB = 1, the icon blink is enabled. In this case each

icon is controlled by two bits. Blink consists of two half

phases (corresponding to the cursor on and off phases

called even and odd phases hereafter).

set V_LCDgenerator stages to 2

(3 x voltage multiplier)

set V_LCDgenerator stages to 3

(4 x voltage multiplier)

Icon states for the even phase are stored in CGRAM

characters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons).

These bits also define icon state when icon blink is not

used (see Table 9).

do not use

9.7

Bit L

Screen conﬁguration

Icon states for the odd phase are stored in CGRAM

character 4 to 6 (another 120 bits for the 120 icons). When

icon blink is disabled CGRAM characters 4 to 6 may be

used as normal CGRAM characters.

L = 0: the two halves of a split screen are connected in a

standard way i.e. column 1/61, 2/62 to 60/120; default.

L = 1: the two halves of a split screen are connected in a

mirrored way i.e. column 1/120, 2/119 to 60/61. This

allows single layer PCB or glass layout.

9.5

Direct mode

When DM = 0, the chip is not in the direct mode. Either the

internal V_LCDgenerator or an external voltage may be

used to achieve V_LCD

Table 9 Blink effect for icons and cursor character blink

PARAMETER

EVEN PHASE

ODD PHASE

Cursor character blink

Icons

block (all on)

normal (display character)

state 1; CGRAM character 0 to 2

state 2; CGRAM character 4 to 6

2001 Dec 19

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PCF2113x

9.8

Display conﬁguration

V_LCDprogramming:

1. Send ‘function set’ instruction with H = 1

Bit P

2. Send ‘set V_LCD’ instruction to write to voltage register:

P = 0: default.

a) DB7, DB6 = 10: DB5 to DB0 are V_LCDof character

mode (V_A)

P = 1: mirrors the column data.

Bit Q

b) DB7, DB6 = 11: DB5 to DB0 are V_LCDof icon

mode (V_B)

Q = 0: default.

c) DB5 to DB0 = 000000 switches V_LCDgenerator off

(when selected)

Q = 1: mirrors the row data.

d) During ‘display off’ and power-down the V_LCD

generator is also disabled.

9.9

Temperature control

Default is TC1 = 0 and TC2 = 0. Selects the default

temperature coefficient for the internally generated V_LCD

(see Table 10).

3. Send ‘function set’ instruction with H = 0 to resume

normal programming.

The ranges for TC are given in Chapter 13.

9.11 Reducing current consumption

Reducing current consumption can be achieved by one of

the options given in Table 11.

Table 10 TC1 and TC2 selection of V_LCDtemperature

coefﬁcient

When V_LCDlies outside the V_DDrange and must be

generated, it is usually more efficient to use the on-chip

generator than an external regulator.

TC1

TC2

DESCRIPTION

V_LCDtemperature coefﬁcient 0

_LCDtemperature coefﬁcient 1

_LCDtemperature coefﬁcient 2

_LCDtemperature coefﬁcient 3

Table 11 Reducing current consumption

ORIGINAL MODE

Character mode

Display on

_LCDgenerator operating

Any mode

ALTERNATIVE MODE

Icon mode (control bit IM)

Display off (control bit D)

Direct mode

9.10 Set V_LCD

The V_LCDvalue is programmed by instruction. Two on-chip

registers, V_Aand V_Bhold V_LCDvalues for the character

mode and the icon mode respectively. The generated

power-down (PD pin)

V_LCDvalue is independent of V_DD, allowing battery

operation of the chip.

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PCF2113x

10.2 I²C-bus interface

10 INTERFACES TO MICROCONTROLLER

10.1 Parallel interface

The I²C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are the

Serial Data line (SDA) and the Serial Clock Line (SCL).

Both lines must be connected to a positive supply via

pull-up resistors. Data transfer may be initiated only when

the bus is not busy.

The PCF2113x can send data in either two 4-bit operations

or one 8-bit operation and can thus interface to 4-bit or

8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the

8 data lines DB7 to DB0. Three further control lines E,

RS and R/W are required (see Chapter 6).

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH level signal put on the bus

by the transmitter during which time the master generates

an extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte.

In 4-bit mode data is transferred in two cycles of 4 bits

each using pins DB7 to DB4 for the transaction.

The higher order bits (corresponding to DB7 to DB4 in

8-bit mode) are sent in the first cycle and the lower order

bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data

transfer is complete after two 4-bit data transfers. It should

be noted that two cycles are also required for the busy flag

check. 4-bit operation is selected by instruction, see

Figs 17 to 19 for examples of bus protocol.

Also a master receiver must generate an acknowledge

after the reception of each byte that has been clocked out

of the slave transmitter.

The device that acknowledges must pull-down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration).

In 4-bit mode, pins DB3 to DB0 must be left open-circuit.

They are pulled up to V_DDinternally.

R/W

DB7

DB6

DB5

DB4

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

AC3

AC2

AC1

AC0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

AC6

AC5

AC4

busy flag and

address counter read

data register

read

instruction

write

MGA804

Fig.17 4-bit transfer example.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

R/W

internal

internal operation

not

busy

DB7

IR7

IR3

AC3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

MGA805

IR7, IR3: instruction 7th, 3rd bit.

AC3: address counter 3rd bit.

D7, D3: data 7th, 3rd bit.

Fig.18 An example of 4-bit data transfer timing sequence.

R/W

internal

internal operation

not

busy

data

busy

data

DB7

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

MGA806

Fig.19 Example of busy flag checking timing sequence.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

A master receiver must signal an end of data to the

transmitter by not generating an acknowledge bit on the

last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to

enable the master to generate a STOP condition.

10.2.2 DEFINITIONS

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer generates

clock signals and terminates a transfer

10.2.1 I²C-BUS PROTOCOL

Before any data is transmitted on the I²C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

START procedure. The I²C-bus configuration for the

different PCF2113x read and write cycles is shown in

Figs 24 to 26. The slow down feature of the I²C-bus

protocol (receiver holds SCL LOW during internal

operations) is not used in the PCF2113x.

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

MASTER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

TRANSMITTER/

RECEIVER

SDA

SCL

MGA807

Fig.20 System configuration.

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.21 Bit transfer.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

SDA

SCL

STOP condition

START condition

MBC622

Fig.22 Definition of START and STOP conditions.

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

START

condition

MBC602

Fig.23 Acknowledgement on the I²C-bus.

2001 Dec 19

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ahdnbok,uflapegwidt

acknowledgement

from PCF2113x

1 RS CONTROL BYTE

DATA BYTE

0 RS CONTROL BYTE

1 byte

DATA BYTE

A P

slave address

2n ≥ 0 bytes

n ≥ 0 bytes

R/W Co

update

data pointer

MGG002

PCF2113x

slave address

R/W

Fig.24 Master transmits to slave receiver; write mode.

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acknowledgement

(1)

1 RS CONTROL BYTE A

DATA BYTE

0 RS CONTROL BYTE

1 byte

DATA BYTE

slave address

2n 0 bytes

n ≥ 0 bytes

R/W

acknowledgement

no acknowledgement

SLAVE

ADDRESS

DATA BYTE

n bytes

last byte

R/W

update

data pointer

MGG003

data pointer

Last data byte is a dummy byte (may be omitted).

Fig.25 Master reads after setting word address; writes word address, set RS; ‘read data’.

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

acknowledgement

from PCF2113x

acknowledgement

from master

no acknowledgement

from master

SLAVE

DATA BYTE

last byte

ADDRESS

n bytes

R/W

update

data pointer

MGG004

Fig.26 Master reads slave immediately after first byte; read mode (RS previously defined).

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_DD1

_DD2, V_DD3

PARAMETER

logic supply voltage

CONDITIONS

MIN.

−0.5

MAX.

+5.5

UNIT

V_LCDgenerator supply voltages

LCD supply voltage

−0.5

V_LCD

V_i/o(n)

+6.5

voltage on

any V_DDrelated input or output

any V_LCDrelated input or output

DC input current

−0.5

−10

−50

−

V_DD+ 0.5

V_LCD+ 0.5

+10

I_I

I_O

DC output current

+10

_DD, I_SSand I_LCDV_DD, V_SSor V_LCDsupply current

+50

P_tot

P_O

total power dissipation

400

power dissipation per output

electrostatic handling voltage

−

100

V_es

human body model;

−

2000

C = 100 pF; R = 1.5 kΩ

electrostatic handling voltage

storage temperature

machine model;

C = 200 pF; L = 0.75 µH

−

150

T_stg

−65

+150

°C

12 HANDLING INSTRUCTIONS

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

13 DC CHARACTERISTICS

V_DD1= 1.8 to 5.5 V; V_DD2= V_DD3= 2.2 to 4.0 V; V_SS= 0 V; V_LCD= 2.2 to 6.5 V; T_amb= −40 to +85 °C; unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

V_DD1

logic supply voltage

note 1

internal V_LCDgeneration

1.8

2.2

−

5.5

V_DD2, V_DD3V_LCDgenerator supply

−

4.0

voltages

(V_DD2and V_DD3< V_LCD

)

V_LCD

V_POR

LCD supply voltage

Power-on reset voltage

2.2

0.9

−

6.5

1.6

note 1 and 2

GROUND SUPPLY CURRENT; EXTERNAL V_LCD; note 3

I_SS1

I_SS3

I_SS4

ground supply current 1

ground supply current 3

ground supply current 4

−

120

µA

V_DD= 3 V; V_LCD= 5 V; note 4

icon mode; V_DD= 3 V;

V_LCD= 2.5 V; note 4

I_SS5

ground supply current 5

Power-down mode;

−

µA

V_DD= 3 V; V_LCD= 2.5 V;

DB7 to DB0,RS and R/W = 1;

OSC = 0; PD = 1

GROUND SUPPLY CURRENT; INTERNAL V_LCD; notes 3 and 5

I_SS6

I_SS8

I_SS9

ground supply current 6

ground supply current 8

ground supply current 9

−

190

160

120

400

−

µA

V_DD= 3 V; V_LCD= 5 V; note 4

icon mode; V_DD= 2.5 V;

V_LCD= 2.5 V; note 4

Logic

V_IL

LOW-level input voltage

HIGH-level input voltage

V_SS1

−

0.3V_DD1

V_DD1

V_IH

0.7V_DD1

V_SS1

V_IL(OSC)

LOW-level input voltage on

pin OSC

V_DD1− 1.2

V_IH(OSC)

I_OL(DB)

HIGH-level voltage pin OSC

_DD1− 0.1

−

V_DD1

LOW-level output current on

pins DB7 to DB0

V_OL= 0.4 V; V_DD1= 5 V

V_OH= 4 V; V_DD1= 5 V

V_I= V_SS1

1.6

−

I_OH(DB)

I_pu

HIGH-level output current on

pins DB7 to DB0

−1

−8

0.15

−

µA

pull-up current at

pins DB7 to DB0

0.04

−1

I_L

leakage current

V_I= V_DD1or V_SS1

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I²C-bus; pins SDA and SCL

V_IL

LOW-level input voltage

−

0.3V_DD1

V_IH

HIGH-level input voltage

input leakage current

input capacitance

0.7V_DD1

−

5.5

−

I_LI

V_I= V_DD1or V_SS1

−1

−

µA

C_i

note 6

I_{OL (SDA)}

LOW-level output current on

pin SDA

V_OL= 0.4 V; V_DD1> 2 V

−

V_OL= 0.2 V_DD1; V_DD1< 2 V

−

LCD outputs

R_O(ROW)

R_O(COL)

V_bias(tol)

V_LCD2(tol)

row output resistance of

pins R1 to R18

note 7

−

kΩ

column output resistance of

pins C1 to C60

note 7

bias voltage tolerance on

pins R1 to R18 and C1 to C60

note 8

130

V_LCDvoltage tolerance

T_amb= 25 °C; note 5

V_LCD< 3 V

V_LCD< 4 V

V_LCD< 5 V

V_LCD< 6 V

−

160

200

260

340

−

TC0

TC1

TC2

TC3

V_LCDtemperature coefﬁcient 0

V_LCDtemperature coefﬁcient 1

V_LCDtemperature coefﬁcient 2

V_LCDtemperature coefﬁcient 3

−0.16

−0.18

−0.21

−0.24

%/K

−

Notes

1. Spikes on V_DD1or V_SS1which cause V_DD1− V_SS1≤ 1.6 V can cause a Power-on reset.

2. Resets all logic when V_DD1< V_POR; 3 OSC cycles required.

3. LCD outputs are open-circuit; inputs at V_DD1or V_SS1; bus inactive.

4. T_amb= 25 °C; f_OSC= 200 kHz.

5. LCD outputs are open-circuit; V_LCDgenerator is on; load current I_VLCD= 5 µA (at V_LCD).

6. Tested on sample basis.

7. Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 µA; outputs measured one at a time;

external V_LCD= 3 V, V_{DD1, 2, 3}= 3 V.

8. LCD outputs open-circuit; external V_LCD

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

14 AC CHARACTERISTICS

V_DD1= 1.8 to 5.5 V; V_DD2= V_DD3= 2.2 to 4.0 V; V_SS= 0 V; V_LCD= 2.2 to 6.5 V; T_amb= −40 to +85 °C; unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

147

UNIT

f_FR

LCD frame frequency (internal clock)

oscillator frequency (not available at any pin)

external clock frequency

V_DD= 5.0 V

140

−

f_osc

250

−

450

300

−

kHz

µs

f_OSC(ext)

t_osc(st)

t_W(PD)

t_SW(PD)

oscillator start-up time after power-down

power-down HIGH-level pulse width

tolerable spike width on PD pin

note 1

200

−

µs

−

Timing characteristics of parallel interface; note 2

WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X); see Fig.27

T_cy(en)

t_W(en)

t_su(A)

t_h(A)

enable cycle time

enable pulse width

address set-up time

address hold time

data set-up time

data hold time

500

220

−

t_su(D)

t_h(D)

READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER); see Fig.28

T_cy(en)

t_W(en)

t_su(A)

t_h(A)

enable cycle time

enable pulse width

address set-up time

address hold time

data delay time

500

220

−

t_d(D)

V_DD1> 2.2 V

_DD1> 1.5 V

150

250

100

−

t_h(D)

data hold time

Timing characteristics of I²C-bus interface; see Fig.29; note 2

f_SCL

SCL clock frequency

−

400

−

kHz

µs

t_LOW

t_HIGH

t_SU;DAT

t_HD;DAT

t_r

SCL clock LOW period

SCL clock HIGH period

data set-up time

1.3

0.6

−

100

−

data hold time

−

SCL and SDA rise time

SCL and SDA fall time

capacitive bus line load

set-up time for a repeated START condition

START condition hold time

note 1 and 3

15 + 0.1 C_b

300

400

−

t_f

15 + 0.1 C_b

C_b

−

t_SU;STA

t_HD;STA

0.6

−

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

µs

t_SU;STO

t_SW

set-up time for STOP condition

tolerable spike width on bus

0.6

−

t_BUF

bus free time between STOP and START

condition

1.3

−

µs

Notes

1. Tested on sample base.

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

V_ILand V_IHwith an input voltage swing of V_SSto V_DD

3. C_b= total capacitance of one bus line in pF.

handbook, full pagewidth

IH1

IL1

IH1

IL1

h(A)

su(A)

R/W

IL1

h(A)

W(en)

IH1

IL1

h(D)

su(D)

IH1

IL1

valid data

DB0 to DB7

IL1

MBK474

cy(en)

Fig.27 Parallel bus write operation sequence; writing data from microcontroller to PCF2113x.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

IH1

IL1

IH1

IL1

su(A)

IH1

h(A)

IH1

R/W

h(A)

W(en)

IH1

IL1

h(D)

d(D)

OH1

OL1

DB0 to DB7

OL1

MBK475

cy(en)

Fig.28 Parallel bus read operation sequence; writing data from PCF2113x to microcontroller.

handbook, full pagewidth

SDA

SCL

SDA

LOW

BUF

SU;DAT

HD;STA

HIGH

HD;DAT

SU;STA

MGA728

SU;STO

Fig.29 I²C-bus timing diagram.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

15 DEVICE PROTECTION CIRCUITS

SYMBOL

PAD

INTERNAL CIRCUIT

V_DD1

DD1

SS1

MGU200

V_DD2

109

DD2

SS2

SS1

MGU201

V_DD3

110

DD3

SS1

MGU202

V_SS1

V_SS2

SS2

SS1

MGU203

V_LCDSENSE

V_LCD1

V_LCD2

SS1

MGU196

SCL

SDA

DD1

SS1

MGU198

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

SYMBOL

PAD

INTERNAL CIRCUIT

OSC

DD1

SS1

MGU199

R/W

100

DB0 to DB7

R1 to R8

R9 to R16

R17

108 to 101

94 to 87

12 to 19

LCD2

R18

C1 to C2

C3 to 27

C28 to C52

C53 to C60

86 to 85

82 to 58

55 to 31

28 to 21

SS1

MGU197

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

16 APPLICATION INFORMATION

handbook, full pagewidth

P10

R17, R18

R/W

P11

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

P12

P80CL51

PCF2113x

C1 to C60

P17 to P14

DB7 to DB4

MGG006

Fig.30 Direct connection to 8-bit microcontroller; 4-bit bus.

handbook, full pagewidth

R17, R18

P20

P21

P22

R/W

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

P80CL51

PCF2113x

C1 to C60

P17 to P10

DB7 to DB0

MGG005

Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus.

handbook, full pagewidth

R17, R18

OSC

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

PCF2113x

100

LCD

100

C1 to C60

MGG007

DB7 to DB0

RS R/W

Fig.32 Typical application using parallel interface.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

DD DD

handbook, full pagewidth

DB3/SAO

R17, R18

OSC

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

PCF2113x

100

LCD

100

C1 to C60

SCL SDA

DB3/SAO

R17, R18

OSC

1 × 24 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

PCF2113x

470

LCD

100

C1 to C60

SCL SDA

MASTER TRANSMITTER

PCF84C81A; P80CL410

MGG008

Fig.33 Application using I²C-bus interface.

16.1 General application information

Optimized values for these tracks are below 50 Ω for the

supply and below 100 Ω for the I/O connections. Higher

track resistance reduce performance and increase current

consumption.

The required minimum value for the external capacitors in

an application with the PCF2113x are: C_Extfor

V_LCD/V_SS= 100 nF min., for V_DD/V_SS= 470 nF. Higher

capacitor values are recommended for ripple reduction.

To avoid accidental triggering of Power-on reset

(especially in COG applications), the supplies must be

adequately decoupled. Depending on power supply

quality, V_DD1may have to be risen above the specified

minimum.

For COG applications the recommended ITO track

resistance is to be minimized for the I/O and supply

connections.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

16.2 4-bit operation, 1-line display using internal

reset

16.4 8-bit operation, 2-line display

For a 2-line display the cursor automatically moves from

the first to the second line after the 40th digit of the first line

has been written. Thus, if there are only 8 characters in the

first line, the DDRAM address must be set after the 8th

character is completed (see Table 15). It should be noted

that both lines of the display are always shifted together;

data does not shift from one line to the other.

The program must set functions prior to a 4-bit operation

(see Table 12). When power is turned on, 8-bit operation

is automatically selected and the PCF2113x attempts to

perform the first write as an 8-bit operation. Since nothing

is connected to DB0 to DB3, a rewrite is then required.

However, since one operation is completed in two

accesses of 4-bit operation, a rewrite is required to set the

functions (see Table 12 step 3). Thus, DB4 to DB7 of the

‘function set’ are written twice.

16.5 I²C-bus operation, 1-line display

A control byte is required with most commands

(see Table 16).

16.3 8-bit operation, 1-line display using internal

reset

Tables 13 and 14 show an example of a 1-line display in

8-bit operation. The PCF2113x functions must be set by

the ‘function set’ instruction prior to display. Since the

DDRAM can store data for 80 characters, the RAM can be

used for advertising displays when combined with display

shift operation. Since the display shift operation changes

display position only and the DDRAM contents remain

unchanged, display data entered first can be displayed

when the ‘return home’ operation is performed.

Table 12 4-bit operation, 1-line display example using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2113x is initialized by

the internal reset)

initialized; no display appears

function set

R/W DB7 DB6 DB5 DB4

sets to 4-bit operation; in this instance operation

is handled as 8-bits by initialization and only this

instruction completes with one write

function set

sets to 4-bit operation, selects 1-line display and

V_LCD= V₀; 4-bit operation starts from this point

and resetting is needed

display control

turns on display and cursor; entire display is

blank after initialization

entry mode set

sets mode to increment the address by 1 and to

shift the cursor to the right at the time of write to

the DD/CGRAM; display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected

by initialization at power-on; the cursor is

incremented by 1 and shifted to the right

2001 Dec 19

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Table 13 8-bit operation, 1-line display example; using internal reset (character set ‘A’)

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2113x is initialized by the internal

reset)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

sets to 8-bit operation, selects 1-line display and

V_LCD= V₀

display control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the

DD/CGRAM; display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1

and shifted to the right

‘write data’ to CGRAM/DDRAM

PH_

writes ‘H’

7 to 10

writes ‘ILIP’

‘write data’ to CGRAM/DDRAM

PHILIPS_

HILIPS _

writes ‘S’

entry mode set

sets mode for display shift at the time of write

writes space

‘write data’ to CGRAM/DDRAM

ILIPS M_

writes ‘M’

15 to 19

writes ‘ICROK’

‘write data’ to CGRAM/DDRAM

MICROKO_

writes ‘O’

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STEP

INSTRUCTION

DISPLAY

OPERATION

cursor/display shift

MICROKO

ICROCO

shifts only the cursor position to the left

writes ‘C’ correction; the display moves to the left

shifts the display and cursor to the right

shifts only the cursor to the right

writes ‘M’

cursor/display shift

‘write data’ to CGRAM/DDRAM

cursor/display shift

MICROCO

MICROCO_

ICROCOM_

PHILIPS M

cursor/display shift

‘write data’ to CGRAM/DDRAM

return home

returns both display and cursor to the original position

(address 0)

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Table 14 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2113x is initialized by the internal

reset)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

sets to 8-bit operation, selects 1-line display and

V_LCD= V₀

display mode on/off control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the

DD/CGRAM; display is not shifted

set CGRAM address

sets the CGRAM address to position of character 0;

the CGRAM is selected

‘write data’ to CGRAM/DDRAM

writes data to CGRAM for icon even phase; icons appears

set CGRAM address

sets the CGRAM address to position of character 4;

the CGRAM is selected

‘write data’ to CGRAM/DDRAM

writes data to CGRAM for icon odd phase

function set

sets H = 1

icons blink

sets H = 0

icon control

function set

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STEP

INSTRUCTION

DISPLAY

OPERATION

set DDRAM address

sets the DDRAM address to the ﬁrst position; DDRAM is

selected

‘write data’ to CGRAM/DDRAM

writes ‘P’; the cursor is incremented by 1 and shifted to

the right

‘write data’ to CGRAM/DDRAM

PH_

writes ‘H’

17 to 21

writes ‘ILIPS’

return home

PHILIPS

returns both display and cursor to the original position

(address 0)

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Table 15 8-bit operation, 2-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2113x is initialized by the internal

reset)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

sets to 8-bit operation; selects 2-line display and V_LCD

generator off

display on/off control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of write to the CG/DDRAM;

display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1

and shifted to the right

6 to 10

writes ‘HILIP’

‘write data’ to CGRAM/DDRAM

PHILIPS_

writes ‘S’

set DDRAM address

PHILIPS

sets DDRAM address to position the cursor at the head of

the 2nd line

‘write data’ to CGRAM/ DDRAM

PHILIPS

writes ‘M’

14 to 18

writes ‘ICROC’

‘write data’ to CGRAM/DDRAM

PHILIPS

writes ‘O’

MICROCO_

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STEP

INSTRUCTION

‘write data’ to CGRAM/DDRAM

DISPLAY

OPERATION

PHILIPS

MICROCO_

sets mode for display shift at the time of write

‘write data’ to CGRAM/DDRAM

HILIPS

ICROCOM_

writes ‘M’; display is shifted to the left; the ﬁrst and second

lines shift together

return home

PHILIPS

MICROCOM

returns both display and cursor to the original position

(address 0)

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Table 16 Example of I²C-bus operation; 1-line display (using internal reset, assuming SA0 = V_SS; note 1)

STEP

I²C-BUS BYTE

DISPLAY

OPERATION

initialized; no display appears

I²C-bus start

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

during the acknowledge cycle SDA will be pulled-down by the

PCF2113x

send a control byte for ‘function set’

Co RS

Ack

control byte sets RS for following data bytes

function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

selects 1-line display and V_LCD= V₀; SCL pulse during

acknowledge cycle starts execution of instruction

display on/off control

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

turns on display and cursor; entire display shows character 20H

(blank in ASCII-like character sets)

entry mode set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

sets mode to increment the address by 1 and to shift the cursor

to the right at the time of write to the DDRAM or CGRAM; display

is not shifted

I²C-bus start

for writing data to DDRAM, RS must be set to 1; therefore a

control byte is needed

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

send a control byte for ‘write data’

Co RS

Ack

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack P_

writes ‘P’; the DDRAM has been selected at power-up; the

cursor is incremented by 1 and shifted to the right

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PH_

writes ‘H’

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STEP

I²C-BUS BYTE

DISPLAY

OPERATION

12 to 15

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS_

writes ‘S’

(optional I²C-bus stop) I²C-bus start start + slave

address for write (as step 8)

PHILIPS_

control byte

Co RS

Ack PHILIPS_

return home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

sets DDRAM address 0 in address counter (also returns shifted

display to original position; DDRAM contents unchanged); this

instruction does not update the Data Register (DR)

I²C-bus start

slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS

PHILIPS

during the acknowledge cycle the content of the DR is loaded

into the internal I²C-bus interface to be shifted out; in the

previous instruction neither a ‘set address’ nor a ‘read data’ has

been performed; therefore the content of the DR was unknown;

the R/W has to be set to 1 while still in I²C-write mode

control byte for read

Co RS

Ack PHILIPS

DDRAM content will be read from following instructions

‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

8 × SCL; content loaded into interface during previous

acknowledge cycle is shifted out over SDA; MSB is DB7; during

master acknowledge content of DDRAM address 01 is loaded

into the I²C-bus interface

‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

8 × SCL; code of letter ‘H’ is read ﬁrst; during master

acknowledge code of ‘I’ is loaded into the I²C-bus interface

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STEP

I²C-BUS BYTE

DISPLAY

OPERATION

‘read data’: 8 × SCL + no master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

no master acknowledge; after the content of the I²C-bus

interface register is shifted out no internal action is performed;

no new data is loaded to the interface register, data register is

not updated, address counter is not incremented and cursor is

not shifted

I²C-bus stop

PHILIPS

Notes

1. X = don’t care.

2. SDA is left at high-impedance by the microcontroller during the read acknowledge.

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Table 17 Initialization by instruction, 8-bit interface (note 1)

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after internal reset has been applied

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

wait 2 ms

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

wait more than 40 µs

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

BF can be checked after the following instructions; when BF is not checked,

the waiting time between instructions is the speciﬁed instruction time

(see Table 3)

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines

display off

clear display

entry mode set

I/D

Initialization ends

Note

1. X = don’t care.

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Table 18 Initialization by instruction, 4-bit interface; not applicable for I²C-bus operation

STEP

power-on or unknown state

DESCRIPTION

Wait 2 ms after internal reset has been applied

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction

function set (interface is 8 bits long)

Wait 2 ms

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction

function set (interface is 8 bits long)

Wait 40 µs

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction

function set (interface is 8 bits long)

BF can be checked after the following instructions; when BF is not checked, the waiting time

between instructions is the speciﬁed instruction time (see Table 3)

R/W

DB7

DB6

DB5

DB4

function set (set interface to 4 bits long)

interface is 8 bits long

function set (interface is 4 bits long)

specify number of display lines

display off

clear display

entry mode set

I/D

Initialization ends

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

17 BONDING PAD INFORMATION

COORDINATES⁽¹⁾

SYMBOL

C40

PAD

COORDINATES⁽¹⁾

SYMBOL

V_DD1

PAD

+1630

+1435

+1335

+1225

+1115

+1005

+765

+65

C39

+165

−1345

−1155

−1 055

−845

−1550

−1395

−1255

−1155

−1055

−955

C38

+265

OSC

C37

+365

C36

+465

C35

+565

−765

C34

+665

−665

C33

+765

V_SS1

V_SS2

V_LCD2

V_LCDSENSE

V_LCD1

−525

C32

+865

−455

C31

+965

−295

C30

+1065

+1165

+1265

+1335

+1550

+1355

+1255

−145

C29

+15

C28

+175

dummy pad 3

dummy pad 4

C27

R10

+245

R11

+315

R12

+385

C26

R13

+455

C25

R14

+525

C24

R15

+595

C23

R16

+665

C22

+665

R18

+735

C21

+565

C60

+805

C20

+465

C59

+875

C19

+365

C58

+995

C18

+265

C57

+1065

+1135

+1205

+1275

+1345

+1435

+1630

C17

+165

C56

C16

+65

C55

C15

−35

C54

C14

−135

C53

C13

−235

dummy pad 1

dummy pad 2

C52

C12

−335

C11

−435

C10

−535

C51

−635

C50

−735

C49

−835

C48

−735

−965

C47

−635

−1065

−1165

−1265

−1465

−1630

C46

−535

C45

−435

C44

−335

dummy pad 5

dummy pad 6

C43

−235

C42

−135

C41

−35

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

COORDINATES⁽¹⁾

SYMBOL

PAD

SYMBOL

DB7

PAD

100

−1630

+1185

+1115

+1045

+975

+905

+835

+765

+695

+625

+555

+375

+305

+85

101

102

103

104

105

106

107

108

109

110

111

112

−1630

−1465

−215

−315

DB6

DB5

−415

DB4

−515

DB3

−615

DB2

−715

DB1

−815

DB0

−915

V_DD2

−1015

−1235

−1395

−1550

R17

SCL

SDA

V_DD3

dummy pad 7

dummy pad 8

Note

−15

1. All x and y coordinates are referenced to centre of chip

R/W

−115

and dimensions are in µm (see Fig.34).

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

handbook, full pagewidth

56 dummy pad 3

dummy pad 6

R17

C28

C29

C30

C31

C32

C33

C34

C35

PC2113x

C36

SCL

SDA

C37

C38

C39

C40

3.36

C41

100

101

102

103

104

105

106

107

108

109

C42

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

C43

C44

C45

C46

C47

C48

C49

DD2

C50

C51

110

111

DD3

C52

dummy pad 7

dummy pad 2

3.52 mm

MGU205

Fig.34 Bonding pad locations.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

18 TRAY INFORMATION

handbook, full pagewidth

MGU206

For dimensions see Table 19.

Fig.35 Tray details.

Table 19 Tray dimensions

DIMENSION

DESCRIPTION

pocket pitch x direction

VALUE

6.35 mm

5.59 mm

3.82 mm

3.66 mm

50.8 mm

pocket pitch y direction

pocket width x direction

pocket width y direction

tray width x direction

tray width y direction

pockets in x direction

pockets in y direction

handbook, halfpage

PC2113x

Table 20 Bump size

PARAMETER

Type

VALUE

UNIT

MGU207

galvanic pure Au

50 ±6

−

Bump width

Bump length

Bump height

µm

90 ±6

17.5 ±5

The orientation of the IC in a pocket is indicated by the position of the

IC type name on the die surface with respect to the chamfer on the

upper left corner of the tray. Refer to the bonding pad location

diagram for the orientating and position of the type name on the die

surface.

Height difference in one die <2

Convex deformation

Pad size, aluminium

Passivation opening CBB

Wafer thickness

62 × 100

36 × 76

380 ±25

Fig.36 Tray alignment.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

19 PACKAGE OUTLINE

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

(1)

(A )

w M

pin 1 index

detail X

100

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 14.1 14.1

0.17 0.09 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

1.6

0.25

0.5

1.0

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

00-01-19

00-02-01

SOT407-1

136E20

MS-026

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

20 SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

20.1 Introduction to soldering surface mount

packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

20.2 Reﬂow soldering

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

20.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

20.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

20.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

BGA, LFBGA, SQFP, TFBGA

WAVE

not suitable

REFLOW⁽¹⁾

suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

PLCC⁽³⁾, SO, SOJ

not suitable⁽²⁾

suitable

LQFP, QFP, TQFP

not recommended⁽³⁾⁽⁴⁾suitable

not recommended⁽⁵⁾

suitable

SSOP, TSSOP, VSO

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

21 DATA SHEET STATUS

PRODUCT

STATUS

DATA SHEET STATUS

DEFINITIONS ⁽¹⁾

Objective speciﬁcation

Development This data sheet contains the design target or goal speciﬁcations for

product development. Speciﬁcation may change in any manner without

notice.

Preliminary speciﬁcation Qualiﬁcation

This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to

make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation

Production

This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

22 DEFINITIONS

23 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

the use of any of these products, conveys no licence or title

under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

Application information

Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

24 BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of

ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately

indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors

has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips

Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing,

handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in

which the die is used.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

25 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

NOTES

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

NOTES

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

NOTES

2001 Dec 19

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA73

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

403502/03/pp72

Date of release: 2001 Dec 19

Document order number: 9397 750 06995

PCF2113DU2 [NXP]

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