PCF2119FU/2/F2Z_技术文档

PCF2119x

LCD controllers/drivers

Rev. 05 — 13 August 2009

Product data sheet

1. General description

The PCF2119x is a low power CMOS¹LCD controller and driver, designed to drive a dot

matrix LCD display of 2-lines by 16 characters or 1-line by 32 characters with 5 × 8 dot

format. All necessary functions for the display are provided in a single chip, including

on-chip generation of LCD bias voltages, resulting in a minimum of external components

and lower system current consumption. The PCF2119x interfaces to most

microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I²C-bus. The chip contains a

character generator and displays alphanumeric and kana (Japanese) characters.

The letter ‘x’ in PCF2119x characterizes the built-in character set. Various character sets

can be manufactured on request. In addition 16 user deﬁned symbols (5 × 8 dot format)

are available.

2. Features

I Single-chip LCD controller and driver

I 2-line display of up to 16 characters plus 160 icons or 1-line display of up to

32 characters plus 160 icons

I 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user deﬁned

symbols

I Reduced current consumption while displaying icons only

I Icon blink function

I On-chip:

N Conﬁgurable 4, 3 or 2 times voltage multiplier generating LCD supply voltage,

independent of V_DD, programmable by instruction (external supply also possible)

N Temperature compensation of on-chip generated V_LCDOUT: −0.16 %/K to

−0.24 %/K (programmable by instruction)

N Generation of intermediate LCD bias voltages

N Oscillator requires no external components (external clock also possible)

I Display Data RAM (DDRAM): 80 characters

I Character Generator ROM (CGROM): 240 characters (5 × 8)

I Character Generator RAM (CGRAM): 16 characters (5 × 8); 4 characters used to drive

160 icons, 8 characters used if icon blink feature is used in application

I 4-bit or 8-bit parallel bus and 2-wire I²C-bus interface

I CMOS compatible

I 18 row and 80 column outputs

I Multiplex rates 1:18 (2-line display or 1-line display), 1:9 (for 1-line display of up to

16 characters and 80 icons) and 1:2 (for icon only mode)

1. The deﬁnition of the abbreviations and acronyms used in this data sheet can be found in Section 20.

PCF2119x

NXP Semiconductors

LCD controllers/drivers

I Uses common 11 code instruction set (extended)

I Logic supply voltage: V_DD1− V_SS1= 1.5 V to 5.5 V (chip may be driven with two

battery cells)

I LCD supply voltage: V_LCDOUT− V_SS2= 2.2 V to 6.5 V

I V_LCDgenerator supply voltage: V_DD2− V_SS2= 2.2 V to 4 V and

V

_DD3− V_SS2= 2.2 V to 4 V

I Direct mode to save current consumption for icon mode and multiplex drive mode 1:9

(depending on V_DD2value and LCD liquid properties)

I Very low current consumption (20 µA to 200 µA):

N Icon mode: < 25 µA

N Power-down mode: < 2 µA

I Icon mode is used to save current. When only icons are displayed, a much lower LCD

operating voltage can be used and the switching frequency of the LCD outputs is

reduced; in most applications it is possible to use V_DDas LCD supply voltage

3. Applications

I Telecom equipment

I Portable instruments

I Point-of-sale terminals

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF2119AU/2DA/2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm

PCF2119x

PCF2119DU/2/2

PCF2119FU/2/F2

PCF2119RU/2/F2

PCF2119SU/2/F2

PCF2119VU/2/F2

PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm

5. Marking

Table 2.

Marking codes

Type number

Marking code

PC2119-2

PCF2119AU/2DA/2

PCF2119DU/2/2

PCF2119FU/2/F2

PCF2119RU/2/F2

PCF2119SU/2/F2

PCF2119VU/2/F2

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

2 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

6. Block diagram

C1 to C80

R17DUP

100

R1 to R18

60 to 99,

101 to 140

51 to 59,

141 to 149

80

18

COLUMN DRIVERS

80

ROW DRIVERS

BIAS

VOLTAGE

GENERATOR

44 to 49

V

LCDIN

18

DATA LATCHES

SHIFT REGISTER 18-BIT

37 to 43

36

80

V

LCDOUT

V

LCD

GENERATOR

SHIFT REGISTER 5 × 12 BIT

V

LCDSENSE

5

168

OSC

OSCILLATOR

CURSOR AND DATA CONTROL

5

1 to 6

V

DD1

7 to 14

V

DD2

CHARACTER

GENERATOR

ROM

15 to 18

DD3

GENERATOR

RAM (128 × 5)

(CGRAM)

(CGROM)

16 CHARACTERS

240 CHARACTERS

22 to 29

30 to 35

TIMING

GENERATOR

V

SS1

8

SS2

20

T1

T2

T3

DISPLAY DATA RAM

(DDRAM)

80 CHARACTERS/BYTES

7

155

PD

21

153

7

DISPLAY

ADDRESS

COUNTER

ADDRESS COUNTER

(AC)

7

INSTRUCTION

DECODER

8

DATA

REGISTER

(DR)

INSTRUCTION

REGISTER

BUSY

FLAG

PCF2119X

154

8

POR

8

163

DB3/SA0

I/O BUFFER

156,

157

151,

152

160 to 162

164 to 167

19

158

159

E

RS

SCL

SDA

DB4 to DB7

DB0 to DB2

mgw571

R/W

Fig 1. Block diagram

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

3 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

7. Pinning information

7.1 Pinning

49

44

dummy

R8

50

60

V

LCDIN

R1

R17

C80

LCDOUT

37

35

V

LCDSENSE

SS2

34

30

V

SS2

SS1

C66

C65

74

75

22

21

T2

T1

E

20

19

V

DD3

DD2

15

V

7

C41

R17DUP

C40

100

DD1

1

168

OSC

DB7

DB6

DB5

DB4

DB3/SA0

DB2

DB1

DB0

RS

C16

C15

125

126

158

R/W

PC2119

C1

R18

R9

SDA

PD

142

POR

T3

R16

149

150

SCL

dummy

151

mgw572

Top view. For mechanical details, see Figure 49.

Fig 2. Pinning diagram of PCF2119x (bare die)

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

4 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

7.2 Pin description

Table 3.

Symbol

V_DD1

Pin description

Description

1 to 6

supply voltage 1 (logic)

[1]

[2]

V_DD2

7 to 14

15 to 18

19

supply voltage 2 (for high voltage generator)

supply voltage 3 (for high voltage generator)

data bus clock input

V_DD3

E

• set HIGH to signal the start of a read or write operation

• data is clocked in or out of the chip on the negative edge

of the clock

T1 and T2

V_SS1

20 and 21

22 to 29

30 to 35

36

test pins

• must be connected to V_SS1

ground supply voltage 1

[3]

• for all circuits, except of high voltage generator

ground supply voltage 2

V_SS2

• for high voltage generator

input for voltage multiplier regulation circuitry and for the bias

level generation

V_LCDSENSE

• if V_LCDis generated internally then this pin must be

connected to V_LCDOUTand V_LCDIN

• if V_LCDis generated externally then this pin must be

connected to V_LCDINonly

V_LCDOUT

37 to 43

V_LCDoutput

• if V_LCDis generated internally then this pin must be

connected to V_LCDINand to V_LCDSENSE

• if V_LCDis generated externally then this pin must be left

open-circuit

V_LCDIN

44 to 49

50

input for LCD bias level generator

-

[4]

dummy

R8 to R1,

R17,

R17DUP,

R18,

51 to 58,

59,

100

LCD row driver output

• R17 has two pins: R17 and R17DUP

• R17 and R18 drive the icons

141,

R9 to R16

142 to 149

C80 to C41,

C40 to C1

dummy

SCL

60 to 99,

101 to 140

150

LCD column driver output

[4]

[5]

-

151 and 152

153

I²C-bus serial clock input

T3

test pin

• open-circuit

• not user accessible

external Power-On Reset (POR) input

power-down mode select

• for normal operation pin PD must be LOW

I²C-bus serial data input/output

POR

PD

154

155

[5]

SDA

156 and 157

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

5 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 3.

Pin description …continued

Symbol

Description

read/write input

R/W

158

• pin R/W = HIGH selects the read operation

• pin R/W = LOW selects the write operation

• this pin has an internal pull-up resistor

register select pin;

RS

159

• this pin has an internal pull-up resistor

8 bit bidirectional data bus (bit 0 to bit 7)

[6][7

]

DB0 to DB2, 160 to 162,

DB3/SA0,

163,

• the 8-bit bidirectional data bus (3-state) transfers data

DB4 to DB7

164 to 167

between the microcontroller and the PCF2119x

• pin DB7 may be used as the busy ﬂag, signalling that

internal operations are not yet completed

• 4-bit operations the 4 higher order lines DB7 to DB4 are

used, DB3 to DB0 must be left open-circuit

• data bus line DB3 has an alternative function (SA0) as the

I²C-bus address pin

• each data line has its own internal pull-up resistor

OSC

168

oscillator or external clock input

• when the on-chip oscillator is used this pin must be

connected to V_DD1

[1] Always put V_DD2= V_DD3

.

[2] When the I²C-bus is used, the parallel interface pin E must be LOW.

[3] The substrate (rear side of the die) is wired to V_SSbut should not be electrically connected.

[4] On the device connected to V_SS1

.

[5] When the parallel bus is used, the pins SCL and SDA must be connected to V_SS1or V_DD1; they must not be

left open-circuit.

[6] In the I²C-bus read mode, ports DB7 to DB4 and DB2 to DB0 should be connected to V_DD1or left

open-circuit.

[7] When the 4-bit interface is used without reading out from the PCF2119x (bit R/W is set permanently to

logic 0), the unused ports DB4 to DB0 can either be set to V_SS1or V_DD1instead of leaving them

open-circuit.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

6 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

8. Functional description

8.1 Oscillator and timing generator

The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency

f_clkwhich equals either the built in oscillator frequency f_oscor an external clock frequency

f_clk(ext)

.

8.1.1 Timing generator

The timing generator produces the various signals required to drive the internal circuitry.

Internal chip operation is not disturbed by operations on the data buses.

8.1.2 Internal clock

To use the on-chip oscillator, pin OSC must be connected to V_DD1. The on-chip oscillator

provides the clock signal for the display system. No external components are required.

8.1.3 External clock

If an external clock will be used, the input is at pin OSC. The resulting display frame

frequency is given by:

f _osc

f _fr

=

(1)

-----------

3072

Remark: Only in the power-down mode the clock is allowed to be stopped (pin OSC

connected to V_SS), otherwise the LCD is frozen in a DC state, which is not suitable for the

liquid crystals.

8.2 Reset function and Power-On Reset (POR)

The PCF2119x must be reset externally when power is turned on. If no external reset is

performed, the chip might start-up in an unwanted state.

For the external reset, pin POR has to be active HIGH. The reset has to be active for at

least 3 oscillator periods in order for the reset to be executed. If the internal oscillator is

used, the minimum reset activity time follows from the lowest possible oscillator frequency

(f_osc= 140 kHz, T_osc~ 71 µs, 3 × T_osc~ 215 µs). The internal oscillator start-up time is

200 µs (typ) up to 300 µs (max) after power-on. In case that an external oscillator is used,

T_oscis dependent from f_osc(ext)

.

Afterwards the chip executes the Clear_display instruction, which requires 165 oscillator

cycles. After the reset the chip has the state shown in Table 4 and is then ready for use.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

7 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 4.

State after reset

Step Function

Control bit and

register state

Description

Reference

1

2

Clear_display

Table 16

Entry_mode_set

bit I_D = 1

bit S = 0

bit D = 0

bit C = 0

bit B = 0

bit DL = 1

bit M = 0

bit SL = 0

incremental cursor move direction

no display shift

Table 18

3

4

Display_ctl

display off

Table 19

cursor off

cursor character blink off

8-bit interface

Function_set

Table 12

1-line display

1:18 multiplex drive mode

normal instruction set

bit H = 0

[1]

5

6

default address pointer to DDRAM

Icon_ctl

Table 22

Table 25

bit IM = 0

character mode, full display

icon blink disabled

bit IB = 0

7

Screen_conf

Disp_conf

Temp_ctl

bit L = 0

default conﬁguration

default conﬁgurations

Table 23

Table 24

Table 28

Table 32

bit P = 0; bit Q = 0

8

9

bit TC1 = 0; bit TC2 = 0 default temperature coefﬁcient

VLCD_set

register V_A= 0;

register V_B= 0

V_LCDgenerator off

10

11

I²C-bus interface reset

HV_gen

bit S1 = 1; bit S0 = 0

V_LCDgenerator set to 3 internal stages

(4 voltage multipliers)

Table 30

[1] The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be

initialized by software (see Table 43 and Table 44).

8.3 Power-down mode

The chip can be put into power-down mode by applying a HIGH-level to pin PD. In

power-down mode all static currents are switched off (no internal oscillator, no bias level

generation and all LCD outputs are internally connected to V_SS).

During power-down, information in the RAMs and the chip state are preserved. Instruction

execution during power-down is possible when pin OSC is externally clocked.

8.4 LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The V_LCDgenerator is controlled by

two internal 6-bit registers: V_Aand V_B. Register V_Ais programmed with the voltage for

character mode and register V_Bwith the voltage for icon mode.

The nominal LCD operating voltage at room temperature is given by Equation 2:

V_LCD(nom)= V_x× 0.08 + 1.82

(2)

Where V_xis the integer value of the register V_Aor V_B.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage (V_oper).

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

8 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

8.4.1 Programming ranges

Possible values for V_Aand V_Bare between 0 to 63.

Remarks:

• Values producing more than 6.5 V at operating temperature are not allowed.

Operation above this voltage may damage the device. When programming the

operating voltage the temperature coefﬁcient of V_LCDOUTmust be taken into account.

• Values below 2.2 V are below the speciﬁed operating range of the chip and are

therefore not allowed.

Table 5.

Values of V_Aand V_Band the corresponding V_LCDvalues

All values at T_ref= 27 °C; allowed values are highlighted.

Integer values Corresponding Integer values Corresponding

Integer values Corresponding

of V_Aand V_B

value of V_LCDin V

of V_Aand V_B

value of V_LCDin V

3.58

of V_Aand V_B

value of V_LCDin V

0

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

5.34

V_LCDswitched off

1.90

1

3.66

5.42

2

1.98

3.74

5.50

3

2.06

3.82

5.58

4

2.14

3.90

5.66

5

2.22

3.98

5.74

6

2.30

4.06

5.82

7

2.38

4.14

5.90

8

2.46

4.22

5.98

9

2.54

4.30

6.06

10

11

12

13

14

15

16

17

18

19

20

21

2.62

4.38

6.14

2.70

4.46

6.22

2.78

4.54

6.30

2.86

4.62

6.38

2.94

4.70

6.46

3.02

4.78

6.54

3.10

4.86

6.62

3.18

4.94

6.70

3.26

5.02

6.78

3.34

5.10

6.86

3.42

5.18

3.50

5.26

When the LCD supply voltage is generated on-chip, the V_LCDpins should be decoupled to

V_SSwith a suitable capacitor. The generated V_LCDOUTis independent of V_DDand is

temperature compensated.

In Equation 2 the internal charge pump is not considered. However, if the supplied voltage

to V_DD2and V_DD3is below the required V_LCDit is necessary to use the internal charge

pump. The multiplication factor has to be set such, that V_DD2and V_DD3(which are equal)

multiplied with the programmed multiplication factor exceeds the required V_LCDunder all

circumstances (i.e. at low temperatures and along with the temperature compensation -

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

9 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

see Section 10.2.3.4). If still a higher multiplication factor is chosen, V_LCDwill not increase

(it is set by Equation 2) but the current that can be delivered will be higher. Also current

consumption increases (see Section 16.6).

When the V_LCDgenerator and the direct mode are switched off, an external voltage may

be supplied at connected pins V_LCDINand V_LCDOUT. V_LCDINand V_LCDOUTmay be higher or

lower than V_DD2

.

In direct mode (see Icon_ctl instruction, Section 10.2.3.3) the internal V_LCDgenerator is

turned off and the V_LCDOUToutput voltage is directly connected to V_DD2. This reduces the

current consumption depending on V_DD2value and LCD liquid properties.

The V_LCDgenerator ensures that, as long as V_DDis in the valid range (2.2 V to 4 V), the

required peak voltage V_LCD= 6.5 V can be generated at any time.

8.5 LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This

removes the need for an external resistive bias chain and signiﬁcantly reduces the system

current consumption. The optimum value of V_LCDdepends on the multiplex rate, the LCD

threshold voltage (V_th) and the number of bias levels. Using a 5-level bias scheme for the

1:18 multiplex rate allows V_LCD< 5 V for most LCD liquids.

The intermediate bias levels for the different multiplex rates are shown in Table 6. These

bias levels are automatically set to the given values when switching to the corresponding

multiplex rate.

Table 6.

Bias levels as a function of multiplex rate

Multiplex

rate

Number of

bias levels

Bias voltages

V₁

V₂

V₃

V₄

V₅

V₆

1:18

5

4

V_LCD

V_SS

3

4

1

2

1

2

1

4

(V_LCD– V_SS

)

(V_LCD– V_SS

)

(V_LCD– V_SS

)

(V_LCD– V_SS

)

--

1:9

V_LCD

V_SS

3

--

4

1

--

2

1

--

2

1

--

4

(V_LCD– V_SS

1:2

V_LCD

2

--

3

2

--

3

1

--

3

1

--

3

(V_LCD– V_SS

8.6 LCD row and column drivers

The PCF2119x contains 18 row and 80 column drivers, which drive the appropriate LCD

bias voltages in sequence to the display in accordance with the data to be displayed. R17

and R18 drive the icon rows. Unused outputs should be left open.

The bias voltages and the timing are selected automatically when the number of lines in

the display is selected. Figure 3 to Figure 5 show typical waveforms.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

10 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

frame n

frame n +1

state 1 (on)

state 2 (off)

V

LCD

2

3/V4

5

R1

R2

R3

R4

R5

R6

R7

R8

ROW 17

ROW 18

ROW 1

ROW 9

ROW 2

ROW 10

SS

V

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

R9

SS

R10

V

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

R17

R18

SS

V

C1 C2 C3 C4 C5

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

COL 1

COL 2

SS

V

LCD

2

3/V4

5

SS

V

LCD

0.5V

state 1

0.25V

LCD

0

−0.25V

−0.5V

LCD

−V

LCD

V

0.5V

LCD

state 2

0.25V

LCD

0

−0.25V

−0.5V

LCD

−V

LCD

013aaa140

1 2 3

18 1 2 3

18

V_state(t) = V_COL(t) − V_ROW(t).

Fig 3. Waveforms for the 1:18 multiplex drive mode; character mode

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

11 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

frame n

frame n +1

state 1 (off)

state 2 (on)

V

LCD

2

3/V4

5

R1

R2

R3

R4

R5

R6

R7

R8

ROW 17

ROW 1

ROW 2

ROW 3

ROW 4

SS

V

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

R17

SS

V

C1 C2 C3 C4 C5

LCD

2

3/V4

5

SS

V

LCD

2

3/V4

5

COL 1

COL 2

SS

V

LCD

2

3/V4

5

SS

V

LCD

0.5V

state 1

0.25V

LCD

0

−0.25V

−0.5V

LCD

−V

LCD

V

0.5V

LCD

state 2

0.25V

LCD

0

−0.25V

−0.5V

LCD

−V

LCD

013aaa141

1

2

3

9

1

2

3

9

V_state(t) = V_COL(t) − V_ROW(t).

Fig 4. Waveforms for the 1:9 multiplex drive mode; character mode, R9 to R16 and R18 open

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

12 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

frame n

frame n +1

only icons are

driven (MUX 1: 2)

V

LCD

2/3

1/3

SS

ROW 17

V

LCD

2/3

1/3

SS

ROW 18

V

LCD

2/3

1/3

SS

ROW 1 to 16

V

LCD

2/3

1/3

SS

COL 1

COL 2

COL 3

COL 4

ON/OFF

V

LCD

2/3

1/3

V

SS

V

LCD

2/3

1/3

V

SS

V

LCD

2/3

1/3

V

SS

V

0.66V

0.33V

LCD

state 1 (ON)

state 2 (OFF)

LCD

0

state 1

COL 1 - ROW 17

−0.33V

−0.66V

−V

LCD

state 3 (OFF)

V

0.66V

0.33V

LCD

COL 2

COL 1

LCD

0

state 2

COL 2 - ROW 17

−0.33V

−0.66V

−V

LCD

V

0.66V

0.33V

LCD

0

state 3

COL 3 - ROW 1 to ROW 16

−0.33V

−0.66V

−V

LCD

013aaa142

V_state(t) = V_COL(t) − V_ROW(t).

V_on(RMS)= 0.745V_LCD

.

V_off(RMS)= 0.333V_LCD

V_on

D =

= 2.23

----------

V_off

Fig 5. Waveforms for the 1:2 multiplex drive mode; icon mode

PCF2119X_5

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PCF2119x

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9. Display data RAM and ROM

9.1 DDRAM

The Display Data RAM (DDRAM) stores up to 80 characters of display data represented

by 8-bit character codes. RAM locations which are not used for storing display data can be

used as general purpose RAM.

The basic RAM to display addressing scheme is shown in Figure 6, Figure 7 and Figure 8.

With no display shift the characters represented by the codes in the ﬁrst 32 RAM locations

starting at address 00h are displayed in line 1.

non-displayed DDRAM addresses

display

position

1

2

3

4

5

30 31 32

DDRAM

address

00 01 02 03 04

1D 1E 1F 20 21

4C 4D 4E 4F

1-line display

non-displayed DDRAM address

1

2

3

4

5

14 15 16

00 01 02 03 04

0D 0E 0F 10 11

24 25 26 27 line 1

DDRAM

address

1

2

3

4

5

14 15 16

40 41 42 43 44

4D 4E 4F 50 51

64 65 66 67 line 2

mgk892

2-line display/MUX 1 : 9 mode

All addresses are shown in hex.

Fig 6. DDRAM to display mapping: no shift

1

2

3

4

5

14 15 16

0C 0D 0E

line 1

27 00 01 02 03

DDRAM

address

1

2

3

4

5

14 15 16

4C 4D 4E

67 40 41 42 43

line 2

mgl536

2-line display/MUX 1 : 9 mode

All addresses are shown in hex.

Fig 7. DDRAM to display mapping: right shift

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

display

position

1

2

3

4

5

30 31 32

1E 1F 20

01 02

04 05

03

DDRAM

address

1-line display

1

2

3

4

5

14 15 16

0E 0F 10

line 1

01 02 03 04 05

DDRAM

address

1

2

3

4

5

14 15 16

4E 4F 50

41 42 43 44 45

line 2

2-line display/MUX 1 : 9 mode

mgk894

All addresses are shown in hex.

Fig 8. DDRAM to display mapping: left shift

When data is written to or read from the DDRAM, wrap-around occurs from the end of one

line to the start of the next line. When the display is shifted each line wraps around within

itself, independently of the others. Thus all lines are shifted and wrapped around together.

The address ranges and wrap-around operations for the various modes are shown in

Table 7.

Address space and wrap-around operation

Mode

1 × 32

2 × 16

1 × 16

Address space

00h to 4Fh

00h to 27h;

40h to 67h

00h to 27h

Read/write wrap-around

(moves to next line)

4Fh to 00h

27h to 40h;

67h to 00h

27h to 00h

Display shift wrap-around

(stays within line)

27h to 00h;

67h to 40h

9.2 CGROM

The Character Generator ROM (CGROM) contains 240 character patterns in a 5 × 8 dot

format from 8-bit character codes. Figure 9 to Figure 14 show the character sets that are

currently implemented.

PCF2119X_5

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PCF2119x

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upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

3

4

5

6

7

8

9

10

11

12

13

14

15

16

mce190

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 9. Character set ‘A’ in CGROM

PCF2119X_5

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NXP Semiconductors

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upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

3

4

5

6

7

8

9

10

11

12

13

14

15

16

mce173

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 10. Character set ‘D’ in CGROM

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

3

4

5

6

7

8

9

10

11

12

13

14

15

16

mgu552

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 11. Character set ‘F’ in CGROM

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

3

4

5

6

7

8

9

10

11

12

13

14

15

16

mgl535

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 12. Character set ‘R’ in CGROM

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

3

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

4

5

6

7

8

9

10

11

12

13

14

15

16

mgl534

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 13. Character set ‘S’ in CGROM

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

1

2

3

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

4

5

6

7

8

9

10

11

12

13

14

15

16

mgl597

The ﬁrst column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.

Fig 14. Character set ‘V’ in CGROM

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NXP Semiconductors

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9.3 CGRAM

Up to 16 user deﬁned characters may be stored in the Character Generator RAM

(CGRAM). Some CGRAM characters (see Figure 21) are also used to drive icons:

• 6 CGRAM characters if icons blink and both icon rows are used in the application

• 3 CGRAM characters if no icons blink but both icon rows are used in the application

• 0 CGRAM characters if no icons are driven by the icon rows

When the icons blink option is enabled, double the number of CGRAM characters are

used since both the on and off state of an icon is deﬁned.

The CGROM and CGRAM use a common address space, of which the ﬁrst column is

reserved for the CGRAM (see Figure 9 to Figure 14).

Figure 15 shows the addressing principle for the CGRAM.

character codes

(DDRAM data)

CGRAM

address

character patterns

(CGRAM data)

character code

(CGRAM data)

7

0

6

5

4

3

2

1

0

6

0

5

4

3

2

1

0

4

3

2

1

0

4

3

2

1

0

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

character

pattern

example 1

(4)

0

(2)

0

cursor

position

(3)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

character

pattern

example 2

(1)

0

(5)

1

0

1

coa072

0

1

0

1

0

1

0

1

(1) Character code bit 0 to bit 3 correspond to CGRAM address bit 3 to bit 6.

(2) CGRAM address bit 0 to bit 2 designate the character pattern line position. The 8th line is the cursor position and display is

performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Lines are numbered from 0 to 7.

(3) Character pattern column positions correspond to CGRAM data bit 0 to bit 4, as shown in Figure 9 to Figure 14.

(4) As shown in Figure 9 to Figure 14, CGRAM character patterns are selected when character code bit 4 to bit 7 are all logic 0.

CGRAM data = logic 1 corresponds to selection for display.

(5) Only bit 0 to bit 5 of the CGRAM address are set by the Set_CGRAM command. Bit 6 can be set using the Set_DDRAM

command in the valid address range or by using the auto-increment feature during CGRAM write. All bits from bit 0 to bit 6 can

be read using the BF_AC instruction.

Fig 15. Relationship between CGRAM addresses, data and display patterns

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PCF2119x

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9.4 Cursor control circuit

The cursor control circuit generates the cursor underline and/or cursor blink as shown in

Figure 16 at the DDRAM address contained in the address counter.

cursor

013aaa139

5 × 7 dot character font

alternating display

cursor display example

blink display example

Fig 16. Cursor and blink display examples

row 18

icon 1

icon 5

row 17

row 8

row 17

row 8

row 2

row 1

row 2

row 1

cursor

013aaa156

Fig 17. Example of a displays with icons

PCF2119X_5

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PCF2119x

NXP Semiconductors

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10. Registers

The PCF2119x has two 8-bit registers, an instruction register and a data register. Only

these two registers can be directly controlled by the microcontroller. Before an internal

operation, the control information is stored temporarily in these registers, to allow

interfacing to various types of microcontrollers which operate at different speeds or to

allow interface to peripheral control ICs.

The instruction set for the parallel interface is shown in Table 11 together with their

execution time. Details about the parallel interface can be found in Section 11.1.

Examples of operations on a 4-bit bus are given in Table 38, on a 8-bit bus in Table 39,

Table 40 and Table 41.

When using the I²C-bus, the instruction has to be commenced with a control byte as

shown in Table 8. Details about the I²C-bus interface can be found in Section 11.2. An

example of operations on the I²C-bus is given in Table 42.

Table 8.

Control byte

Instruction set for I²C-bus commands

Command byte

I²C-bus

command

[1]

CO RS

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

[1] R/W is set together with the slave address (see Figure 30).

Table 9.

Control byte bit description

Bit

Symbol

Value

Description

7

CO

0

1

0

1

0

last control byte

another control byte follows after data/command

instruction register selected

data register selected

6

RS

4 to 0

-

default logic 0

Instructions are of 4 types, those that:

1. Designate PCF2119x functions like display format, data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others, like read ‘busy ﬂag’ and read ‘address counter’

In normal use, type 3 instructions are used most frequently. However, automatic

incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write

lessens the microcontroller program load. The display shift in particular can be performed

concurrently with display data write, enabling the designer to develop systems in minimum

time with maximum programming efﬁciency.

During internal operation, no instructions other than the BF_AC instruction will be

executed. Because the busy ﬂag is set to logic 1 while an instruction is being executed,

check to ensure it is logic 0 before sending the next instruction or wait for the maximum

instruction execution time, as given in Table 11. An instruction sent while the busy ﬂag is

logic 1 will not be executed.

PCF2119X_5

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PCF2119x

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The RS bit determines which register will be accessed and the R/W bit indicates if it is a

read or a write operation (see Table 10).

Table 10. Register access selection

Symbol

Value

Description

RS

register select

instruction register^[1]

data register^[2]

read/write

0

1

R/W

0

1

write operation

read operation

[1] There is only write access to the instruction register, but read access to the busy ﬂag (BF) and the address

counter (AC) of the BF_AC instruction (see Section 10.2.1.2).

[2] Write and read access.

Details of the instructions are explained in subsequent sections.

10.1 Data register

The data register temporarily stores data to be read from the DDRAM and CGRAM. Prior

to being read by the Read_data instruction, data from the DDRAM or CGRAM,

corresponding to the address in the instruction register, is written to the data register.

10.2 Instruction register

The instruction register stores instruction codes such as Clear_display, Curs_disp_shift,

and address information for the Display Data RAM (DDRAM) and Character Generator

RAM (CGRAM). The instruction register can be written to but not read from by the system

controller.

The instruction register is sectioned into basic, standard and extended instructions. Bit

H = 1 of the Function_set instruction (see Section 10.2.1.1) sets the chip into extended

instruction set mode.

PCF2119X_5

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PCF2119x

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Table 11. Instruction register overview

Instruction

Bits^[1]

Required

Reference

clock

cycles^[2]

RS

R/W

7

6

5

4

3

2

1

0

Basic instructions (bit H = 0 or 1)

[3]

NOP

0

1

0

1

0

1

0

3

0

3

-

Function_set

BF_AC

0

DL

M

SL

H

Section 10.2.1.1

Section 10.2.1.2

Section 10.2.1.3

Section 10.2.1.4

BF

AC

Read_data

Write_data

READ_DATA

WRITE_DATA

Standard instructions (bit H = 0)

Clear_display

Return_home

Entry_mode_set

Display_ctl

0

1

0

1

0

1

0

S

B

0

165

3

Section 10.2.2.1

Section 10.2.2.2

Section 10.2.2.3

Section 10.2.2.4

Section 10.2.2.5

Section 10.2.2.6

Section 10.2.2.7

0

1

0

1

I_D

C

0

3

0

1

D

RL

3

Curs_disp_shift

Set_CGRAM

Set_DDRAM

0

SC

3

1

ACG

3

ADD

3

Extended instructions (bit H = 1)

[4]

Reserved

Screen_conf

Disp_conf

Icon_ctl

0

1

0

1

V

0

1

0

1

0

1

-

0

1

L

3

Section 10.2.3.1

Section 10.2.3.2

Section 10.2.3.3

Section 10.2.3.4

Section 10.2.3.5

Section 10.2.3.6

1

P

IB

Q

IM

0

DM

Temp_ctl

HV_gen

TC1 TC2

S1 S0

0

VLCD_set

VA or VB

[1] The bits 0 to 7 correspond with the data bus lines DB0 to CB7.

[2] f_osccycles.

[3] No operation.

[4] Do not use.

PCF2119X_5

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PCF2119x

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LCD controllers/drivers

10.2.1 Basic instructions (bit H = 0 or 1)

10.2.1.1 Function_set

Table 12. Function_set bit description

Bit

Symbol

Value

0

Description

RS

-

see Table 10

R/W

7 to 5

4

-

0

-

001

ﬁxed value

DL

interface data length (for parallel mode only)

2 × 4 bits (DB7 to DB4)

8 bits (DB7 to DB0)

[1]

[2]

0

1

0

3

2

-

unused

[3]

[4]

M

number of display lines

1 line × 32 characters

2 line × 16 characters

multiplex mode

0

1

0

SL

H

0

1

1:18 multiplex drive mode, 1 × 32 or 2 × 16

character display

[4][5]

[4]

1:9 multiplex drive mode, 1 × 16 character display

instruction set control

0

1

basic instruction set plus standard instruction set

basic instruction set plus extended instruction set

[1] When 4-bit width is selected, data is transmitted in two cycles using the parallel-bus. In a 4-bit application

ports DB3 to DB0 should be left open-circuit (internal pull-ups).

[2] Default value after power-on in I²C-bus mode.

[3] No impact if SL = 1.

[4] Due to the internal pull-ups on DB3 to DB0 in a 4-bit application, the ﬁrst Function_set after power-on sets

bits M, SL and H to logic 1. A second Function_set must be sent to set bits M, SL and H to the required

values.

[5] Independent of bit M and bit L of the Screen_conf instruction (see Section 10.2.3.1). Only row 1 to row 8

and row 17 are used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2 × 16

character display mode, however, the second line cannot be displayed.

10.2.1.2 BF_AC instructions

Table 13. BF_AC bit

Bit

RS

R/W

7

Symbol

Value

Description

-

0

1

see Table 10

-

[1]

BF

read busy ﬂag

0

1

next instruction will be executed

internal operation is in progress;

next instruction will not be executed until BF = 0

6 to 0

AC

0000000 to

1111111

read address counter

[1] It is recommended that the BF status is checked before the next write operation is started.

PCF2119X_5

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PCF2119x

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Busy ﬂag: The busy ﬂag indicates the internal status of the PCF2119x. A logic 1

indicates that the chip is busy and further instructions will not be accepted. The busy ﬂag

is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be started

after checking that the busy ﬂag is at logic 0 or after waiting for the required number of

cycles.

Address counter: The address counter is used by both CGRAM and DDRAM, and its

value is determined by the previous Set_CGRAM and Set_DDRAM instruction. After a

read/write operation the address counter is automatically incremented or decremented

by 1. The address counter value is output to the bus (DB6 to DB0) when bit RS = 0 and bit

R/W = 1.

10.2.1.3 Read_data

Table 14. Read_data bit description

Bit

Symbol

Value

Description

RS

-

1

see Table 10

R/W

7 to 0

READ_DATA 00000000 to

11111111

read data from CGRAM or DDRAM

Read_data from CGRAM or DDRAM: Read_data reads binary 8-bit data from the

CGRAM or DDRAM. The most recent ‘set address’ command (Set_CGRAM or

Set_DDRAM) determines whether the CGRAM or DDRAM is to be read.

The Read_data instruction gates the content of the data register to the bus while pin E is

HIGH. After pin E goes LOW again, internal operation increments (or decrements) the

address counter and stores RAM data corresponding to the new address counter into the

data register.

There are only three instructions that update the data register:

• Set_CGRAM

• Set_DDRAM

• Read_data from CGRAM or DDRAM

Other instructions (e.g. Write_data, Curs_disp_shift, Clear_display and Return_home) do

not modify the value of the data register.

10.2.1.4 Write_data

Table 15. Write_data bit description

Bit

Symbol

Value

Description

RS

-

1

0

see Table 10

R/W

7 to 0

WRITE_DATA 00000000 to

11111111

write data to CGRAM or DDRAM

Write_data to CGRAM or DDRAM: Write_data writes binary 8-bit data to the CGRAM or

the DDRAM.

PCF2119X_5

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PCF2119x

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The previous Set_CGRAM or Set_DDRAM command determines if data is written into

CGRAM or DDRAM. After writing, the address counter automatically increments or

decrements by 1, in accordance with the Entry_mode_set (see Section 10.2.2.3). Only bit

4 to bit 0 of CGRAM data are valid, bit 7 to bit 5 are ‘don’t care’.

10.2.2 Standard instructions (bit H = 0)

10.2.2.1 Clear_display

Table 16. Clear_display bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 0

0

00000001

ﬁxed value

Clear_display: writes usually the character code 20h (blank pattern) into all DDRAM

addresses except for the character sets ‘R’ and ‘V’ where the character code 20h is not a

blank pattern.

In addition Clear_display

• sets the DDRAM address counter to logic 0

• returns the display to its original position, if it was shifted. Thus, the display

disappears and the cursor or blink position goes to the left edge of the display

• sets entry mode bit I_D = 1 (increment mode); bit S of entry mode does not change

The instruction Clear_display requires extra execution time. This may be allowed by

checking the busy ﬂag bit BF or by waiting until the 165 clock cycles have elapsed. The

latter must be applied where no read-back options are foreseen, as in some

Chip-On-Glass (COG) applications.

Remark: When using the character sets ‘R’ or ‘V’, where the character code 20h is not the

blank pattern, the following alternative instruction set has to be used:

1. Switch display off (Display_ctl, bit D = 0).

2. Write a blank pattern into all DDRAM addresses (Write_data).

3. Switch display on (Display_ctl, bit D = 1).

10.2.2.2 Return_home

Table 17. Return_home bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 0

0

00000010

ﬁxed value

Return_home: Sets the DDRAM address counter to logic 0 and switches a shifted

display back to an unshifted state. The DDRAM content remain unchanged. The cursor or

blink position goes to the left of the ﬁrst display line. Bit I_D and bit S of the

Entry_mode_set instruction remain unchanged.

PCF2119X_5

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PCF2119x

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10.2.2.3 Entry_mode_set

Table 18. Entry_mode_set bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 2

1

-

0

-

000001

ﬁxed value

I_D

address increment or decrement

0

1

DDRAM or CGRAM address decrements by 1,

cursor moves to the left

DDRAM or CGRAM address increments by 1,

cursor moves to the right

0

S

shift display to the left or right

display does not shift

display shifts

0

1

Bit I_D: When bit I_D = 1 the DDRAM or CGRAM address increments by 1 when data is

written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the

right.

When bit I_D = 0 the DDRAM or CGRAM address decrements by 1 when data is written

into or read from the DDRAM or CGRAM. The cursor or blink position moves to the left.

The cursor underline and cursor character blink are inhibited when the CGRAM is

accessed.

Bit S: When bit S = 0, the display does not shift.

During DDRAM write, when bit S = 1 and bit I_D = 0, the entire display shifts to the right;

when bit S = 1 and bit I_D = 1, the entire display shifts to the left.

Thus it appears as if the cursor stands still and the display moves. The display does not

shift when reading from the DDRAM, or when writing to or reading from the CGRAM.

10.2.2.4 Display_ctl instructions

Table 19. Display_ctl bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 3

2

0

00001

ﬁxed value

D

C

B

display on or off

display is off; chip is in power-down mode

display is on

0

1

0

cursor on or off

0

1

cursor is off

cursor is on

character blink on or off

character blink is off

character blink is on

0

1

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

Bit D: The display is on when bit D = 1 and off when bit D = 0. Display data in the DDRAM

is not affected and can be displayed immediately by setting bit D = 1.

When the display is off (bit D = 0) the chip is in partial power-down mode:

• The LCD outputs are connected to V_SS

• The V_LCDgenerator and bias generator are turned off

Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all

outputs are at V_SS, afterwards the oscillator can be stopped. If the oscillator is running

during partial power-down mode (‘display off’) the chip can still execute instructions. Even

lower current consumption is obtained by inhibiting the oscillator (pin OSC to V_SS).

To ensure I_DD< 1 µA:

• the parallel bus ports DB7 to DB0 should be connected to V_DD

• pins RS and R/W should be connected to V_DDor left open-circuit

• pin PD should be connected to V_DD

Recovery from power-down mode:

• pin PD should be connected back to V_SS

• if necessary pin OSC should be connected back to V_DD

• a Display_ctl instruction with bit D = 1 should be sent

Bit C: The cursor is displayed when bit C = 1 and inhibited when bit C = 0. Even if the

cursor disappears, bit I_D and bit S (see Section 10.2.2.3) remain in operation during

display data write. The cursor is displayed using 5 dots in the 8th line (see Figure 16).

Bit B: The character indicated by the cursor blinks when bit B = 1. The character blink is

displayed by switching between display characters and all dots on with a period of

f _osc

approximately 1 second, with f _blink

=

--------------

52224

10.2.2.5 Curs_disp_shift

Table 20. Curs_disp_shift bit description

Bit

Symbol

Value

0

Description

RS

-

see Table 10

R/W

7 to 4

3

0

0001

ﬁxed value

SC

RL

-

cursor move or display shift

move cursor

0

1

shift display

2

shift or move to the right or left

left shift or move

right shift or move

ﬁxed value

0

1

1 to 0

00

PCF2119X_5

Product data sheet

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PCF2119x

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LCD controllers/drivers

Bits SC and RL: Curs_disp_shift moves the cursor position or the display to the right or

left without writing or reading display data. This function is used to correct a character or

move the cursor through the display.

In 2-line displays, the cursor moves to the next line when it passes the last position (40) of

the line. When the displayed data is shifted repeatedly all lines shift at the same time;

displayed characters do not shift into the next line.

The address counter content does not change if the only action performed is shift display

(SC = 1) but increments or decrements with the shift cursor (SC = 0).

10.2.2.6 Set_CGRAM

Table 21. Set_CGRAM bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 6

5 to 0

-

0

-

01

ﬁxed value

ACG

000000 to

111111

set CGRAM address

Set_CGRAM: Sets the CGRAM address bits ACG[5:0] into the address counter. Data can

then be written to or read from the CGRAM.

Remark: The CGRAM address uses the same address register as the DDRAM address.

This register consists of 7 bits. But with the Set_CGRAM command, only bit 5 to bit 0 are

set. Bit 6 can be set using the Set_DDRAM command ﬁrst, or by using the auto-increment

feature during CGRAM write. All bits 6 to 0 can be read using the BF_AC instruction.

When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set

(e.g. by an earlier DDRAM write).

10.2.2.7 Set_DDRAM

Table 22. Set_DDRAM bit description

Bit

Symbol

Value

Description

RS

-

0

1

see Table 10

R/W

7

-

ﬁxed value

6 to 0

ADD

0000000 to

1111111

set DDRAM address

Set_DDRAM: Sets the DDRAM address bits ADD[6:0] into the address counter. Data can

then be written to or read from the DDRAM.

PCF2119X_5

Product data sheet

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32 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

10.2.3 Extended instructions (bit H = 1)

10.2.3.1 Screen_conf

Table 23. Screen_conf bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 1

0

0000001

ﬁxed value

L

screen conﬁguration

0

1

split screen standard connection

split screen mirrored connection

Screen_conf:

• If bit L = 0, then the two halves of a split screen are connected in a standard way i.e.

column 1/81, 2/82 to 80/160.

• If bit L = 1, then the two halves of a split screen are connected in a mirrored way i.e.

column 1/160, 2/159 to 80/81. This allows single layer PCB or glass layout.

10.2.3.2 Disp_conf

Table 24. Disp_conf bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 2

1

0

000001

ﬁxed value

P

display column conﬁguration

column data: left to right;

0

1

column data is displayed from column 1 to column

80

column data: right to left;

column data is displayed from column 80 to

column 1

0

Q

display row conﬁguration

0

1

row data: top to bottom;

row data is displayed from row 1 to row 16 and

icon row data in row 17 and row 18

in single line mode (SL = 1) row data is displayed

from row 1 to row 8 and icon row data in row 17

row data: bottom to top;

row data is displayed from row 16 to row 1 and

icon row data in row 18 and row 17

in single line mode (SL = 1) row data is displayed

from row 8 to row 1 and icon row data in row 17

Bit P: The P bit is used to ﬂip the display left to right by mirroring the column data, as

shown in Figure 18. This allows the display to be viewed from behind instead of front and

enhances the ﬂexibility in the assembly of equipment and avoids complicated data

manipulation within the controller.

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

P = 0

Q = 0

P = 1

Q = 0

013aaa122

Fig 18. Use of bit P

Bit Q: The Q bit ﬂips the display top to bottom by mirroring the row data, as shown in

Figure 19.

P = 0

Q = 0

P = 0

Q = 1

013aaa113

Fig 19. Use of bit Q

Combination of bit P and bit Q: A combination of P and Q allows the display to be

rotated horizontally and vertically by 180 degree, as shown in Figure 20. This is useful for

viewing the display from the opposite edge.

P = 0

Q = 0

P = 1

Q = 1

013aaa123

Fig 20. Use of bit P and bit Q

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

10.2.3.3 Icon_ctl

Table 25. Icon_ctl bit description

Bit

Symbol

Value

Description

RS

-

0

see Table 10

R/W

7 to 3

2

-

0

-

00001

ﬁxed value

IM

icon mode

0

1

character mode, full display

icon mode, only icons displayed

1

0

IB

icon blink

icon blink disabled

icon blink enabled

direct mode

off

0

1

DM

0

1

on

The PCF2119x can drive up to 160 icons. See Figure 21 and Figure 22 for CGRAM to

icon mapping.

Bit IM: When bit IM = 0, the chip is in character mode. In the character mode characters

and icons are driven (multiplex drive mode 1:18 or 1:9). The V_LCDgenerator, if used,

produces the V_LCDOUTvoltage programmed with register V_A.

When bit IM = 1, the chip is in icon mode. In the icon mode only the icons are driven

(multiplex drive mode 1:2). The V_LCDgenerator, if used, produces the V_LCDOUTvoltage as

programmed with register V_B.

Table 26. Normal/icon mode operation

Bit IM

Mode

V_LCDOUT

0

1

character mode

icon mode

generated from V_A

generated from V_B

Bit IB: Icon blink control is independent of the cursor/character blink function.

When bit IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 3

(4 × 8 × 5 = 160 bits for 160 icons).

When bit IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits.

Blink consists of two half phases (corresponding to the cursor on and off phases called

even and odd phases hereafter).

Icon states for the even phase are stored in CGRAM characters 0 to 3

(4 × 8 × 5 = 160 bits for 160 icons). These bits also deﬁne icon state when icon blink is not

used (see Table 27).

Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for

the 160 icons). When icon blink is disabled CGRAM characters 4 to 7 may be used as

normal CGRAM characters.

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 27. Blink effect for icons and cursor character blink

Parameter Even phase Odd phase

cursor character blink block (all on)

icons state 1; CGRAM character 0 to 3

normal (display character)

state 2; CGRAM character 4 to 7

display:

COL 1 to 5

COL 6 to 10

COL 76 to 80

ROW 17 –

1

2

3

4

5

6

7

8

9

10

76 77 78 79 80

ROW 18 –

81 82 83 84 85

block of 5 columns

86 87 88 89 90

156 157 158 159 160

mgl249

Fig 21. CGRAM to icon mapping (a)

icon no.

phase

ROW/COL

character codes

CGRAM address

CGRAM data

icon view

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

4

3

2

1

0

MSB

LSB MSB

LSB

1-5

6-10

11-15

even

17/1-5

17/6-10

17/11-15

0

1

0

1

0

1

0

1

0

1

0

1

0

76-80

81-85

even

17/76-80

18/1-5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

156-160

1-5

even

18/76-80

17/1-5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

odd (blink)

156-160

odd (blink) 18/76-80

0

1

0

1

0

1

0

mgk999

CGRAM data: logic 1 of a data bit turns the icon on and logic 0 turns the icon off.

Character codes: bits 0 to 3 deﬁne the icon state when icon blink is disabled or during the even phase when icon blink is

enabled. Bits 4 to 7 deﬁne the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is

disabled)

Fig 22. CGRAM to icon mapping (b)

Bit DM: When DM = 0, the chip is not in the direct mode. Either the internal V_LCD

generator or an external voltage may be used to achieve V_LCD

.

When DM = 1, the chip is in direct mode. The internal V_LCDgenerator is turned off and the

output V_LCDOUTis directly connected V_DD2(i.e. the V_LCDgenerator supply voltage).

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

Remark: In direct mode, no external V_LCDis possible.

The direct mode can be used to reduce the current consumption when the required output

voltage V_LCDOUTis close to the V_DD2supply voltage. This can be the case in icon mode or

in MUX 1:9 (depending on LCD liquid properties).

10.2.3.4 Temp_ctl

Table 28. Temp_ctl bit description

Bit

Symbol

Value

0

Description

RS

-

see Table 10

R/W

7 to 2

1 to 0

-

0

-

000100

00 to 11

TC[1:0]

temperature coefﬁcient

The bit-ﬁeld TC[1:0] selects the temperature coefﬁcient for the internally generated

V_LCDOUT(see Table 29).

Table 29. TC[1:0] selection of V_LCDtemperature coefﬁcient

TC[1:0]

00

Typical value

−0.16 %/K

−0.18 %/K

−0.21 %/K

−0.24 %/K

Description

V_LCDtemperature coefﬁcient 0 (default value)

V_LCDtemperature coefﬁcient 1

V_LCDtemperature coefﬁcient 2

V_LCDtemperature coefﬁcient 3

10

01

11

10.2.3.5 HV_gen

Table 30. HV_gen bit description

Bit

Symbol

Value

0

Description

RS

-

see Table 10

R/W

7 to 2

1 to 0

-

0

-

010000

00 to 11

ﬁxed value

S[1:0]

voltage multiplier

A software conﬁgurable voltage multiplier is incorporated in the V_LCDgenerator and can

be set via the HV_gen command. The voltage multiplier control can be used to reduce

current consumption by disconnecting internal voltage multiplier stages, depending on the

required V_LCDOUToutput voltage (see Table 31).

Table 31. Voltage multiplier control bits

S[1:0]

00

Description

set V_LCDgenerator stages to 1 (2 × voltage multiplier)

set V_LCDgenerator stages to 2 (3 × voltage multiplier)

set V_LCDgenerator stages to 3 (4 × voltage multiplier)

do not use

01

10

11

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

10.2.3.6 VLCD_set

Table 32. VLCD_set bit description

Bit

RS

R/W

7

Symbol

Value

Description

-

0

1

see Table 10

-

ﬁxed value

6

V

set register V_Aor V_B

set register V_A

set register V_B

0

1

5 to 0

V_Aor V_B

000000 to

111111

factor for calculating V_LCD

The V_LCDvalue is calculated with the Equation 2 on page 8. The multiplication factor is

programmed by instruction. Two on-chip registers (V_Aand V_B) hold the multiplication

factor for the character mode and the icon mode, respectively. The generated V_LCDOUT

value is independent of V_DD, allowing battery operation of the chip.

V_xprogramming:

1. Send Function_set instruction with bit H = 1.

2. Send VLCD_set instruction to write to the voltage register:

a. Bit 7 = 1 and bit 6 = 0: bit 5 to bit 0 are the multiplication factor for V_LCDof character

mode (V_A).

b. Bit 7 = 1 and bit 6 = 1: bit 5 to bit 0 are the multiplication factor for V_LCDof icon

mode (V_B).

c. Bit 5 to bit 0 = 0 switches V_LCDgenerator off (when selected).

d. During ‘display off’/power-down the V_LCDgenerator is also disabled.

3. Send Function_set instruction with bit H = 0 to resume normal programming.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

38 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

11. Basic architecture

11.1 Parallel interface

The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can

thus interface to 4-bit or 8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the 8 ports DB7 to DB0. Three

further control lines E, RS and R/W are required.

In 4-bit mode data is transferred in two cycles of 4 bits each using ports DB7 to DB4 for

the transaction. The higher order bits (corresponding to range of bit 7 to bit 4 in 8-bit

mode) are sent in the ﬁrst cycle and the lower order bits (bit 3 to bit 0 in 8-bit mode) in the

second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted

that two cycles are also required for the busy ﬂag check. 4-bit operation is selected by

instruction (see Figure 23 to Figure 25 for examples of bus protocol).

In 4-bit mode, ports DB3 to DB0 must be left open-circuit. They are pulled up to V_DD

internally.

RS

R/W

E

DB7

DB6

DB5

DB4

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

BF

AC3

AC2

AC1

AC0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

AC6

AC5

AC4

busy flag and

address counter read

data register

read

instruction

write

mga804

Fig 23. 4-bit transfer example

PCF2119X_5

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

RS

R/W

E

internal

DB7

internal operation

not

busy

IR7

IR3

AC3

D7

D3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

mga805

IR7, IR3: instruction 7th, 3rd bit.

AC3: address counter 3rd bit.

D7, D3: data 7th, 3rd bit.

Fig 24. An example of 4-bit data transfer timing sequence

RS

R/W

E

internal

internal operation

not

busy

data

busy

data

DB7

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

mga806

Fig 25. Example of busy ﬂag checking timing sequence

PCF2119X_5

Product data sheet

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40 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

11.2 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines

must be connected to a positive supply via pull-up resistors. Data transfer may be initiated

only when the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is

addressed must generate an acknowledge after the reception of each byte.

Also a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge

related clock pulse (set-up and hold times must be taken into consideration).

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge bit on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 26. System conﬁguration

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mbc621

Fig 27. Bit transfer

SDA

SCL

S

P

STOP condition

START condition

mbc622

Fig 28. Deﬁnition of START and STOP conditions

Rev. 05 — 13 August 2009

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

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data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

8

SCL from

master

1

2

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 29. Acknowledgement on the I²C-bus

11.2.1 I²C-bus protocol

One I²C-bus slave address is reserved for the PCF2119x (see Figure 30).

S

A

0

1

0

1

0

slave address

R/W

013aaa143

Fig 30. PCF2119x I²C-bus slave address

Before any data is transmitted on the I²C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the START procedure.

The I²C-bus conﬁguration for the different PCF2119x read and write cycles is shown in

Figure 31 to Figure 33.

The slow down feature of the I²C-bus protocol (receiver holds SCL line LOW during

internal operations) is not used in the PCF2119x.

11.2.2 I²C-bus deﬁnitions

Deﬁnitions:

• Transmitter: the device which sends the data to the bus.

• Receiver: the device which receives the data from the bus.

• Master: the device which initiates a transfer, generates clock signals and terminates a

transfer.

• Slave: the device addressed by a master.

• Multi-master: more than one master can attempt to control the bus at the same time

without corrupting the message.

PCF2119X_5

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PCF2119x

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• Arbitration: procedure to ensure that if more than one master simultaneously tries to

control the bus, only one is allowed to do so and the message is not corrupted.

• Synchronization: procedure to synchronize the clock signals of two or more devices.

acknowledgement

from PCF2119x

S

A

0

S

0

1

0

1

0

A

1 RS CONTROL BYTE

DATA BYTE

A

0 RS CONTROL BYTE

1 byte

A

DATA BYTE

A P

A

slave address

2n ≥ 0 bytes

n ≥ 0 bytes

R/W Co

Co

update

data pointer

mgk899

Fig 31. Master transmits to slave receiver; write mode

acknowledgement

S

A

0

(1)

0

1

0

1

A

1 RSCONTROL BYTE A

DATA BYTE

0 RSCONTROL BYTE

1 byte

DATA BYTE

S

0

A

slave address

2n ≥ 0 bytes

n ≥ 0 bytes

R/W

Co

acknowledgement

no acknowledgement

S

A

0

SLAVE

ADDRESS

1

A

DATA BYTE

A

DATA BYTE

1

P

S

n bytes

last byte

R/W

Co

update

data pointer

mgg003

data pointer

Last data byte is a dummy byte (may be omitted).

Fig 32. Master reads after setting word address; writes word address, set RS; Read_data

PCF2119X_5

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PCF2119x

NXP Semiconductors

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acknowledgement

from PCF2119x

acknowledgement

from master

no acknowledgement

from master

S

A

0

SLAVE

ADDRESS

DATA BYTE

1

A

1

P

S

n bytes

last byte

update

R/W

Co

data pointer

013aaa155

Fig 33. Master reads slave immediately after ﬁrst byte; read mode (RS previously

deﬁned)

PCF2119X_5

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PCF2119x

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12. Internal circuitry

Table 33. Device protection circuits

Symbol

Internal circuit

V_DD1

1 to 6

V

DD1

SS1

013aaa169

V_DD2

7 to 14

V

DD2

SS2

V

SS1

013aaa170

V_DD3

15 to 18

V

DD3

SS1

013aaa171

V_SS1

V_SS2

22 to 29

30 to 35

V

SS2

SS1

013aaa172

V_LCDSENSE

V_LCDIN

V_LCDOUT

SCL

36

44 to 49

37 to 43

151 to 152

156 to 157

168

V

SS1

013aaa173

SDA

OSC

V

DD1

PD

155

POR

154

T1

20

V

SS1

T2

21

013aaa174

T3

153

E

19

RS

159

R/W

158

DB0 to DB7

R1 to R18

160 to 167

58, 57 to 51,

142 to 149,

59, 100, 141

V

LCDIN

C1 to C80

140 to 101,

99 to 60

SS1

013aaa175

PCF2119X_5

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PCF2119x

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LCD controllers/drivers

13. Limiting values

Table 34. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD1

Parameter

Conditions

logic

Min

−0.5

Max

+6.5

+4.5

Unit

V

supply voltage 1

supply voltage 2

supply voltage 3

LCD supply voltage

V_DD2

V_LCDgenerator

V

V_DD3

V_LCD

−0.5

−10

−50

-

+7.5

V

V_I/O(n)

input/output voltage on any

other pin

V_DDrelated

V_LCDrelated

DC level

V_DD+ 0.5

V_LCD+ 0.5 V

I_I

input current

+10

+50

400

100

mA

I_O

output current

DC level

mA

mW

I_DD

I_SS

supply current

ground supply current

LCD supply current

total power dissipation

output power

I_DD(LCD)

P_tot

P_o

dissipation per

output

-

[1]

[2]

[3]

[4]

V_ESD

electrostatic discharge voltage HBM

MM

-

±3000

±300

200

V

-

V

I_lu

latch-up current

-

mA

°C

T_stg

storage temperature

−65

+150

[1] Pass level; Human Body Model (HBM) according to Ref. 5 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”.

[3] Pass level; latch-up testing, according to Ref. 7 “JESD78”.

[4] According to the NXP store and transport conditions (see Ref. 9 “SNW-SQ-623”) the devices have to be

stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

46 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

14. Static characteristics

Table 35. Static characteristics

V_DD1= 1.5 V to 5.5 V; V_DD2= V_DD3= 2.2 V to 4.0 V; V_SS= 0 V; V_LCD= 2.2 V to 6.5 V; T_amb= −40 °C to +85 °C;

unless otherwise speciﬁed.

Symbol

Supplies

V_DD1

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage 1

supply voltage 2

supply voltage 3

LCD supply voltage

logic

1.5

2.2

-

5.5

4.0

V

V_DD2

internal V_LCDgeneration;

V_LCD> V_DD2= V_DD3

V_DD3

V_LCD

2.2

-

6.5

V

[1]

Ground supply current using external V_LCD

I_SSground supply current

-

70

35

25

120

80

µA

[2]

V_DD= 3 V; V_LCD= 5 V

icon mode; V_DD= 3 V;

45

V

_LCD= 2.5 V

power-down mode; V_DD= 3 V;

_LCD= 2.5 V;

-

0.5

5

µA

V

DB7 to DB0, RS and R/W = 1;

OSC = 0; PD = 1

[1][3]

Ground supply current using internal V_LCD

I_SS

ground supply current

-

190

135

85

400

-

µA

[2]

V_DD= 3 V; V_LCD= 5 V

icon mode; V_DD= 2.5 V;

V_LCD= 2.5 V

Logic

V_IL

LOW-level input voltage

HIGH-level input voltage

V_SS1

-

0.3V_DD1

V_DD1

V

V_IH

0.7V_DD1

Oscillator input; pin OSC

V_IL

LOW-level input voltage

V_SS1

-

V

2

_DD1− 1.

V

V_IH

HIGH-level input voltage

V_DD1− 0.

V_DD1

1

Data bus; pins DB7 to DB0

I_OLLOW-level output current V_OL= 0.4 V; V_DD1= 5 V

I_OH

1.6

4

-

mA

HIGH-level output

current

V_OH= 4 V; V_DD1= 5 V

−1

−8

I_pu

I_L

pull-up current

leakage current

V_I= V_SS1

0.04

0.15

-

1

µA

V_I= V_{DD1, 2, 3}or V_{SS1, 2}

−1

+1

I²C-bus; pins SDA and SCL

Inputs: pins SDA and SCL

V_IL

V_IH

I_LI

LOW-level input voltage

0

-

0.3V_DD1

V

HIGH-level input voltage

input leakage current

input capacitance

0.7V_DD1

-

5.5

+1

-

V

V_I= V_{DD1, 2, 3}or V_{SS1, 2}

−1

-

µA

pF

C_i

-

5

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

47 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 35. Static characteristics …continued

V_DD1= 1.5 V to 5.5 V; V_DD2= V_DD3= 2.2 V to 4.0 V; V_SS= 0 V; V_LCD= 2.2 V to 6.5 V; T_amb= −40 °C to +85 °C;

unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output: pin SDA

I_OL

LOW-level output current V_OL= 0.4 V; V_DD1> 2 V

V_OL= 0.2 V_DD1; V_DD1< 2 V

3

2

-

mA

LCD outputs

[4]

[5]

R_O

output resistance

row output, pins R1 to R18

-

10

15

20

30

kΩ

mV

column output, pins C1 to C80

40

∆V_bias

∆V_LCD

bias voltage variation

LCD voltage variation

on pins R1 to R18 and

C1 to C80

130

[3]

T_amb= 25 °C

V_LCD< 3 V

V_LCD< 4 V

V_LCD< 5 V

V_LCD< 6 V

-

160

200

260

340

mV

[1] LCD outputs are open-circuit; inputs at V_DDor V_SS; bus inactive.

[2] T_amb= 25 °C; f_osc= 200 kHz.

[3] LCD outputs are open-circuit; V_LCDgenerator is on; load current I_LCD= 5 µA.

[4] Resistance of output pins (R1 to R18 and C1 to C80) with a load current of 10 µA; outputs measured one at a time; external LCD supply

V_LCD= 3 V; V_DD1= V_DD2= V_DD3= 3 V.

[5] LCD outputs open-circuit; external LCD supply.

PCF2119X_5

Product data sheet

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48 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

15. Dynamic characteristics

Table 36. Dynamic characteristics

V_DD1= 1.5 V to 5.5 V; V_DD2= V_DD3= 2.2 V to 4.0 V; V_SS= 0 V; V_LCD= 2.2 V to 6.5 V; T_amb= −40 °C to +85 °C; unless

otherwise speciﬁed.

Symbol

Clock and oscillator

f_fr(LCD)LCD frame frequency

f_osc

Parameter

Conditions

Min

Typ

Max

Unit

internal clock; V_DD= 5.0 V

not available at any pin

45

140

-

95

250

-

147

450

300

Hz

oscillator frequency

kHz

µs

f_osc(ext)

external oscillator frequency

[1]

t_{d(startup)(OSC)}start-up delay time on pin OSC oscillator, after power-down

Timing characteristics of parallel interface^[2]

200

Write operation (writing data from microcontroller to PCF2119x); see Figure 34

t_cy(en)

t_w(en)

t_su(A)

t_h(A)

enable cycle time

500

220

50

-

ns

enable pulse width

address set-up time

address hold time

data input set-up time

data input hold time

25

t_su(D)

t_h(D)

60

25

Read operation (reading data from PCF2119x to microcontroller); see Figure 35

t_cy(en)

t_w(en)

t_su(A)

t_h(A)

enable cycle time

500

220

50

25

-

ns

enable pulse width

address set-up time

address hold time

-

t_d(DV)

data input valid delay time

V_DD1> 2.2 V

V_DD1> 1.5 V

150

250

100

-

t_h(D)

data input hold time

20

Timing characteristics of I²C-bus interface^[2]; see Figure 36

f_SCL

SCL clock frequency

LOW period of the SCL clock

HIGH period of the SCL clock

data set-up time

-

400

kHz

µs

ns

t_LOW

t_HIGH

t_SU;DAT

t_HD;DAT

t_r

1.3

-

0.6

-

100

-

data hold time

0

-

ns

[1][3]

rise time of both SDA and SCL

signals

15 + 0.1 C_b

300

ns

t_f

fall time of both SDA and SCL

signals

15 + 0.1 C_b

-

300

ns

pF

µs

C_b

capacitive load for each bus

line

-

400

t_SU;STA

t_HD;STA

set-up time for a repeated

START condition

0.6

-

hold time (repeated) START

condition

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

49 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 36. Dynamic characteristics …continued

V_DD1= 1.5 V to 5.5 V; V_DD2= V_DD3= 2.2 V to 4.0 V; V_SS= 0 V; V_LCD= 2.2 V to 6.5 V; T_amb= −40 °C to +85 °C; unless

otherwise speciﬁed.

Symbol

t_SU;STO

t_SP

Parameter

Conditions

Min

0.6

-

Typ

Max

-

Unit

µs

set-up time for STOP condition

-

pulse width of spikes that must

be suppressed by the input

ﬁlter

50

ns

t_BUF

bus free time between a STOP

and START condition

1.3

-

µs

[1] Tested on sample base.

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

[3] C_b= total capacitance of one bus line in pF.

V

IH

RS

IL

t

su(A)

h(A)

R/W

E

V

IL

t

w(en)

h(A)

V

IH

V

IH

V

IL

V

IL

t

h(D)

t

su(D)

V

IH

V

IL

IH

IL

DB0 to DB7

valid data

mbk474

t

cy(en)

Fig 34. Parallel bus write operation sequence; writing data from microcontroller to

PCF2119x

V

IH

V

IL

IH

RS

IL

t

su(A)

h(A)

V

IH

R/W

E

t

w(en)

h(A)

V

IH

V

IH

V

IL

V

IL

t

h(D)

t

d(DV)

V

OH

V

OL

V

OH

V

OL

DB0 to DB7

mbk475

t

cy(en)

Fig 35. Parallel bus read operation sequence; writing data from PCF2119x to

microcontroller

PCF2119X_5

Product data sheet

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50 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 36. I²C-bus timing diagram

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

51 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16. Application information

16.1 General application information

The required minimum value for the external capacitors in an application with the

PCF2119x are: C_extfrom pins V_LCDto V_SS= 100 nF and for pins V_DDto V_SS= 470 nF.

Higher capacitor values are recommended for ripple reduction.

For COG applications the recommended ITO track resistance is to be minimized for the

I/O and supply connections. Optimized values for these tracks are below 50 Ω for the

supply and below 100 Ω for the I/O connections. Higher track resistance reduce

performance and increase current consumption. To avoid accidental triggering of

Power-On Reset (POR) (especially in COG applications), the supplies must be

adequately decoupled. Depending on power supply quality, V_DD1may have to be risen

above the speciﬁed minimum.

When external LCD supply voltage is supplied, V_LCDOUTshould be left open-circuit to

avoid any stray current, and V_LCDINmust be connected to V_LCDSENSE

.

16.2 Power supply connections for internal V_LCDgeneration

V

1.5 V to 5.5 V

2.2 V to 4.0 V

GND

V

DD1

V

DD2

DD3

DD2

DD3

2.2 V to 4.0 V

GND

V

SS1

SS2

SS1

SS2

013aaa114

013aaa115

Decoupling capacitors are not shown in the drawings.

Fig 37. Recommended V_DDconnections for internal V_LCDgeneration

V

LCDIN

LCDOUT

LCDSENSE

V

SS2

013aaa116

Fig 38. Recommended V_LCDconnections for internal V_LCDgeneration

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

52 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.3 Power supply connections for external V_LCDgeneration

V

1.5 V to 5.5 V

2.2 V to 4.0 V

GND

2.2 V to 4.0 V

V

DD1

V

DD2

DD3

DD2

DD3

V

SS1

SS2

SS1

SS2

GND

013aaa114

013aaa117

Decoupling capacitors are not shown in the drawings.

Remark: When using an external V_LCD, the internal V_LCDgenerator must never be switched on

otherwise damages will occur.

Fig 39. Recommended V_DDconnections for external V_LCDgeneration

V

LCDIN

n.c.

LCDOUT

V

SS2

LCDSENSE

013aaa118

Fig 40. Recommended V_LCDconnections for external V_LCDgeneration

16.4 Information about V_LCDconnections

V_LCDIN— This input is used for generating the 5 LCD bias levels. It is the power supply for

the bias level buffers.

V_LCDOUT— This is the V_LCDoutput if V_LCDis generated internally. In this case pin V_LCDOUT

must be connected to V_LCDINand to V_LCDSENSE

.

V_LCDSENSE— This input is used for the voltage multiplier’s regulation circuitry. When using

the internal V_LCDgeneration, this pin must be connected to V_LCDOUTand V_LCDIN. When

using an external V_LCDsupply it must be connected to V_LCDINonly.

16.5 Reducing current consumption

Reducing current consumption can be achieved by one of the options given in Table 37.

When V_LCDlies outside the V_DDrange and must be generated, it is usually more efﬁcient

to use the on-chip V_LCDgenerator than an external regulator.

Table 37. Reducing current consumption

Original mode

character mode

display on

Alternative mode

icon mode (control bit IM)

display off (control bit D)

direct mode

V_LCDgenerator operating

any mode

power-down mode (pin PD)

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

53 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.6 Charge pump characteristics

Typical graphs of the total power consumption of the PCF2119x using the internal charge

pump are illustrated in Figure 41, Figure 42 and Figure 43.

The graphs were obtained under the following conditions:

• T_amb= 25 °C

• V_DD1= V_DD2= V_DD3= 2.2 V (minimum), 2.7 V (typical) and 4.0 V (maximum)

• Normal mode

• f_osc= internal oscillator

• multiplex drive mode 1:18

• Typical current load for I_LCD= 10 µA.

For each multiplication factor there is a separate line. The line ends where it is not

possible to get a higher voltage under its conditions (a higher multiplication factor is

needed to get higher voltages).

Connecting different displays may result in different current consumption. This affects the

efﬁciency and the optimum multiplication factor to be used to generate a certain output

voltage.

mgw573

400

I

DD

(µA)

300

(2)

200

100

0

(3)

(1)

1.25

2.75

4.25

5.75

7.25

V

(V)

LCD

(1) 2 × multiplication factor.

(2) 3 × multiplication factor.

(3) 4 × multiplication factor.

Fig 41. Typical charge pump characteristics (a), V_DD= 2.2 V

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

54 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

mgw574

300

I

DD

(µA)

(3)

(2)

200

(1)

100

0

1.25

2.75

4.25

5.75

7.25

V

(V)

LCD

(1) 2 × multiplication factor.

(2) 3 × multiplication factor.

(3) 4 × multiplication factor.

Fig 42. Typical charge pump characteristics (b), V_DD= 2.7 V

mgw575

300

I

DD

(µA)

(3)

(2)

(1)

200

100

0

1.25

2.75

4.25

5.75

7.25

V

(V)

LCD

(1) 2 × multiplication factor.

(2) 3 × multiplication factor.

(3) 4 × multiplication factor.

Fig 43. Typical charge pump characteristics (c), V_DD= 4.0 V

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

55 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.7 Interfaces

OSC

R17, R18

V

DD

2 × 16 CHARACTER

LCD DISPLAY

PLUS 160 ICONS

2

R1 to R16

16

PCF2119X

470

nF

V

LCD

100

nF

C1 to C80

V

80

SS

4,8

013aaa119

DB7 to DB4

DB3 to DB0

E

RS R/W

Fig 44. Typical application using parallel interface, 4 or 8 bit bus possible

V

DD DD

DD

2

DB3/SAO

R17, R18

OSC

V

DD

V

DD

2 × 16 CHARACTER

LCD DISPLAY

PLUS 160 ICONS

R1 to R16

16

PCF2119X

100

nF

V

LCD

100

nF

80

C1 to C80

SS

SCL SDA

V

SS

DB3/SAO

2

R17, R18

OSC

V

DD

V

DD

1 × 32 CHARACTER

LCD DISPLAY

PLUS 160 ICONS

R1 to R16

16

PCF2119X

100

nF

V

LCD

100

nF

80

C1 to C80

SS

SCL SDA

2

I C MASTER,

MICROCONTROLLER

mgk898

Fig 45. Application using I²C-bus interface

Rev. 05 — 13 August 2009

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.8 Connections with LCD modules

R17

Icons

8

R1 to R8

Character row 1

Character row 2

PCF2119X

C1 to C80 80

8

R9 to R16

R18

013aaa120

Fig 46. Connecting PCF2119x with 2 × 16 character LCD

C1 to C80

R17

Icons

8

R1 to R8

Character row 1

PCF2119X

C1 to C80 80

8

R9 to R16

R18

013aaa121

Fig 47. Connecting PCF2119x with 1 × 32 character LCD

PCF2119X_5

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57 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.9 4-bit operation, 1-line display using external reset

The program must set functions prior to a 4-bit operation (see Table 38). When power is

turned on, 8-bit operation is automatically selected and the PCF2119x attempts to

perform the ﬁrst write as an 8-bit operation. Since nothing is connected to ports

DB0 to DB3, a rewrite is then required. However, since one operation is completed in two

accesses of 4-bit operation, a rewrite is required to set the functions (see Table 38 step 3).

Thus, DB4 to DB7 of the Function_set are written twice.

Table 38. 4-bit operation, 1-line display example; using external reset (character set ‘A’)

Step

Instruction

Display

Operation

RS R/W DB7 DB6 DB5 DB4

power supply on

1

2

initialized by the external reset; no display appears

Function_set

sets to 4-bit operation; in this instance operation is handled as

8-bit by initialization and only this instruction completes with

one write

0

1

0

3

4

5

6

Function_set

sets to 4-bit operation, selects 1-line display and V_LCD= V₀;

4-bit operation starts from this point and resetting is needed

0

1

0

Display_ctl

turns display and cursor on; entire display is blank after

initialization

0

1

0

1

0

1

0

Entry_mode_set

sets mode to increment the address by 1 and to shift the cursor

to the right at the time of write to the DDRAM or CGRAM;

display is not shifted

0

1

0

1

0

Write_data to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1 and

shifted to the right

1

0

1

0

1

0

P

16.10 8-bit operation, 1-line display using external reset

Table 39 and Table 40 show an example of a 1-line display in 8-bit operation. The

PCF2119x functions must be set by the Function_set instruction prior to display. Since the

DDRAM can store data for 80 characters, the RAM can be used for advertising displays

when combined with display shift operation. Since the display shift operation changes

display position only and the DDRAM contents remain unchanged, display data entered

ﬁrst can be displayed when the Return_home operation is performed.

Table 39. 8-bit operation, 1-line display example; using external reset (character set ‘A’)

Step

Instruction

Display

Operation

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

2

power supply on

initialized by the external reset; no

display appears

Function_set

sets to 8-bit operation, selects 1-line

display and V_LCD= V₀

0

1

0

1

0

1

0

1

0

1

0

3

Display_ctl

turns on display and cursor; entire

display is blank after initialization

0

PCF2119X_5

Product data sheet

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58 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 39. 8-bit operation, 1-line display example; using external reset (character set ‘A’) …continued

Step

Instruction

Display

Operation

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

4

Entry_mode_set

sets mode to increment the address

by 1 and to shift the cursor to the right

at the time of the write to the

0

1

0

1

0

DDRAM/CGRAM; display is not shifted

5

6

Write_data to CGRAM/DDRAM

writes ‘P’; the DDRAM has already

been selected by initialization at

power-on; the cursor is incremented

by 1 and shifted to the right

1

0

1

0

1

P

Write_data to CGRAM/DDRAM

writes ‘H’

1

0

1

0

:

PH

7 to 10

11

PHILIP

writes ‘ILIP’

writes ‘S’

Write_data to CGRAM/DDRAM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PHILIPS

HILIPS

12

13

14

Entry_mode_set

sets mode for display shift at the time

of write

0

Write_data to CGRAM/DDRAM

writes space

1

0

1

0

Write_data to CGRAM/DDRAM

writes ‘M’

1

0

1

0

:

ILIPS

M

15 to 19

20

MICROK

writes ‘ICROK’

writes ‘O’

Write_data to CGRAM/DDRAM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

MICROKO

ICROCO

21

22

23

24

25

26

27

Curs_disp_shift

shifts only the cursor position to the left

0

Curs_disp_shift

0

Write_data to CGRAM/DDRAM

writes ‘C’ correction; display moves to

the left

1

0

1

0

1

Curs_disp_shift

shifts the display and cursor to the

right

0

MICROCO

ICROCOM

PHILIPS M

Curs_disp_shift

shifts only the cursor to the right

0

Write_data to CGRAM/DDRAM

writes ‘M’

1

0

1

0

Return_home

returns both display and cursor to the

original position (address 0)

0

PCF2119X_5

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59 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 40. 8-bit operation, 1-line display and icon example; using external reset (character set ‘A’)

Step

Instruction

Display

Operation

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

2

power supply on

initialized by the external reset; no

display appears

Function_set

sets to 8-bit operation, selects 1-line

display and V_LCD= V₀

0

1

0

1

0

1

0

1

0

1

0

3

4

Display_ctl

turns on display and cursor; entire

display is blank after initialization

0

Entry_mode_set

sets mode to increment the address

by 1 and to shift the cursor to the right

at the time of the write to the

0

DD/CGRAM; display is not shifted

5

6

Set_CGRAM

sets the CGRAM address to position of

character 0; the CGRAM is selected

0

1

0

1

0

1

0

Write_data to CGRAM/DDRAM

writes data to CGRAM for icon even

phase; icons appears

1

0

:

7

8

Set_CGRAM

sets the CGRAM address to position of

character 4; the CGRAM is selected

0

1

0

1

0

1

0

9

Write_data to CGRAM/DDRAM

writes data to CGRAM for icon odd

phase

1

0

:

10

11

Function_set

sets bit H = 1

icons blink

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

12

13

14

15

16

Icon_ctl

0

Function_set

sets bit H = 0

0

Set_DDRAM

sets the DDRAM address to the ﬁrst

position; DDRAM is selected

0

1

Write_data to CGRAM/DDRAM

writes ‘P’; the cursor is incremented

by 1 and shifted to the right

1

0

1

0

1

P

Write_data to CGRAM/DDRAM

writes ‘H’

1

0

1

0

:

PH

17 to 21

22

PHILIPS

writes ‘ILIPS’

Return_home

returns both display and cursor to the

original position (address 0)

0

1

0

PHILIPS

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

60 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.11 8-bit operation, 2-line display

For a 2-line display the cursor automatically moves from the ﬁrst to the second line after

the 40th digit of the ﬁrst line has been written. Thus, if there are only 8 characters in the

ﬁrst line, the DDRAM address must be set after the 8th character is completed

(see Table 41). It should be noted that both lines of the display are always shifted

together; data does not shift from one line to the other.

Table 41. 8-bit operation, 2-line display example; using external reset (character set ‘A’)

Instruction

Step

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display

Operation

1

power supply on

initialized by the external reset; no

display appears

2

3

4

Function_set

sets to 8-bit operation; selects 2-line

display and V_LCDgenerator off

0

1

0

1

0

1

0

1

0

display mode on/off control

turns on display and cursor; entire

display is blank after initialization

0

Entry_mode_set

sets mode to increment the address

by 1 and to shift the cursor to the right

at the time of write to the CG/DDRAM;

display is not shifted

0

5

Write_data to CGRAM/DDRAM

writes ‘P’; the DDRAM has already

been selected by initialization at

power-on; the cursor is incremented

by 1 and shifted to the right

1

0

1

0

1

0

P

6 to 10

11

:

PHILIP

writes ‘HILIP’

writes ‘S’

Write_data to CGRAM/DDRAM

1

0

1

0

1

0

1

0

1

0

PHILIPS

12

13

Set_DDRAM

sets DDRAM address to position the

cursor at the head of the 2nd line

0

1

0

Write_data to CGRAM/ DDRAM

writes ‘M’

1

0

1

0

1

0

1

PHILIPS

M

14 to 18

19

:

PHILIPS

MICROC

writes ‘ICROC’

writes ‘O’

Write_data to CGRAM/DDRAM

1

0

1

0

1

0

1

0

1

PHILIPS

MICROCO

20

21

Write_data to CGRAM/DDRAM

sets mode for display shift at the time

of write

0

PHILIPS

MICROCO

Write_data to CGRAM/DDRAM

writes ‘M’; display is shifted to the left;

the ﬁrst and second lines shift

together

1

0

1

0

HILIPS

ICROCOM

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

61 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 41. 8-bit operation, 2-line display example; using external reset (character set ‘A’) …continued

Instruction

Step

22

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display

Operation

:

23

Return_home

returns both display and cursor to the

original position (address 0)

0

1

0

PHILIPS

MICROCOM

16.12 I²C-bus operation, 1-line display

A control byte is required with most commands (see Table 42).

[1]

Table 42. Example of I²C-bus operation; 1-line display (using external reset, assuming pin SA0 = V_SS

)

Step

I²C-bus byte

Display

Operation

1

2

I²C-bus start

initialized; no display appears

slave address for write

during the acknowledge cycle SDA will be

pulled-down by the PCF2119x

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

0

1

0

1

0

1

3

4

5

6

send a control byte for Function_set

control byte sets RS for following data bytes

CO RS

0

Ack

1

0

Function_set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

selects 1-line display and V_LCD= V₀; SCL

pulse during acknowledge cycle starts

execution of instruction

0

1

X

0

1

Display_ctl

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

turns on display and cursor; entire display

shows character code 20h (blank in

ASCII-like character sets)

0

1

0

1

Entry_mode_set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

sets mode to increment the address by 1

and to shift the cursor to the right at the time

of write to the DDRAM or CGRAM; display

is not shifted

0

1

0

1

7

8

I²C-bus start

for writing data to DDRAM, RS must be set

to 1; therefore a control byte is needed

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

0

1

0

1

0

1

9

send a control byte for Write_data

CO RS

0

Ack

1

0

1

10

11

Write_data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

writes ‘P’; the DDRAM has been selected at

power-on; the cursor is incremented by 1

and shifted to the right

P

0

1

0

1

0

1

Write_data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PH

writes ‘H’

0

1

0

1

:

0

1

12 to 15

PHILIP

writes ‘ILIP’

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

62 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

[1]

Table 42. Example of I²C-bus operation; 1-line display (using external reset, assuming pin SA0 = V_SS

)

…continued

Step

I²C-bus byte

Display

Operation

16

Write_data to DDRAM

writes ‘S’

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

0

1

0

1

0

1

17

18

19

optional l²C-bus STOP

I²C-bus start

PHILIPS

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS

0

1

0

1

0

1

20

21

control byte

CO RS

0

Ack PHILIPS

1

0

1

Return_home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

sets DDRAM address 0 in address counter

(also returns shifted display to original

position; DDRAM contents unchanged); this

instruction does not update the data register

0

1

0

1

22

23

I²C-bus start

slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS

PHILIPS

during the acknowledge cycle the content of

the data register is loaded into the internal

I²C-bus interface to be shifted out; in the

previous instruction neither a ‘set address’

nor a Read_data has been performed;

therefore the content of the data register

was unknown; bit R/W has to be set to logic

1 while still in I²C-write mode

0

1

0

1

0

1

24

25

control byte for read

DDRAM content will be read from following

instructions

CO RS

0

Ack PHILIPS

0

1

0

1

Read_data: 8 × SCL + master acknowledge^[2]

8 × SCL; content loaded into interface

during previous acknowledge cycle is

shifted out over SDA; MSB is DB7; during

master acknowledge content of DDRAM

address 01 is loaded into the I²C-bus

interface

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

X

0

26

27

Read_data: 8 × SCL + master acknowledge^[2]

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

8 × SCL; code of letter ‘H’ is read ﬁrst;

during master acknowledge code of ‘I’ is

loaded into the I²C-bus interface

0

1

0

1

0

Read_data: 8 × SCL + no master acknowledge^[2]

no master acknowledge; after the content of

the I²C-bus interface register is shifted out

no internal action is performed; no new data

is loaded to the interface register, data

register is not updated, address counter is

not incremented and cursor is not shifted

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS

0

1

0

1

0

1

28

I²C-bus STOP

PHILIPS

[1] X = don’t care.

[2] SDA is left at high-impedance by the microcontroller during the read acknowledge.

PCF2119X_5

Product data sheet

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63 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.13 Initialization

Table 43. Initialization by instruction, 8-bit interface (^[1]

)

Step

Instruction

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

2

3

power-on or unknown state

wait 2 ms

after internal reset has been applied

Function_set

interface is 8 bits long; BF cannot be checked before

this instruction

0

1

X

4

5

wait 2 ms

Function_set

interface is 8 bits long; BF cannot be checked before

this instruction

0

6

7

wait more than 40 µs

Function_set

interface is 8 bits long; BF cannot be checked before

this instruction

0

BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the

speciﬁed instruction time (see Table 11)

8

Function_set (interface is 8 bits long)

specify number of display lines

0

1

0

1

0

1

0

M

0

H

0

9

Display_ctl

display off

0

10

11

12

Clear_display

0

1

Entry_mode_set

0

1

I_D

S

initialization ends

[1] X = don’t care.

PCF2119X_5

Product data sheet

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64 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 44. Initialization by instruction, 4-bit interface; not applicable for I²C-bus operation

Step

Instruction

Description

RS R/W DB7 DB6 DB5 DB4

power-on or unknown state

1

2

3

wait 2 ms after internal reset has been applied

Function_set interface is 8 bits long; BF cannot be checked

before this instruction

0

1

4

5

wait 2 ms

Function_set

interface is 8 bits long; BF cannot be checked

before this instruction

0

6

7

wait more than 40 µs

Function_set

interface is 8 bits long; BF cannot be checked

before this instruction

0

BF can be checked after the following instructions; when BF is not checked, the waiting time

between instructions is the speciﬁed instruction time (see Table 11)

8

Function_set

0

1

0

set interface to 4 bit long

interface is 8 bit long

9

Function_set

0

1

0

set interface to 4 bits long

M

H

specify number of display line

10

11

12

Display_ctl

0

1

0

display off

Clear_display

0

1

Entry_mode_set

0

1

:

0

I_D

S

13

Initialization ends

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

65 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

16.14 User deﬁned characters and symbols

Up to 16 user deﬁned characters may be stored in the CGRAM. The content of the

CGRAM is lost during power-down, therefore the CGRAM has to be rewritten after every

power-on.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

013aaa144

Fig 48. User deﬁned euro currency sign

Below some source code is printed, which shows how a user deﬁned character is deﬁned

- in this case the euro currency sign. The display used is a 2 lines by 16 characters display

and the interface is the I²C-bus:

// Write

a user defined character into the CGRAM

startI2C();

// PCF2119 slave address for write, SA0 is connected to Vdd

SendI2CAddress(0x70);

// MSB (Continuation bit Co)

// is command byte

= 0, more than one byte may follow. Bit6, RS=0, next byte

i2c_write(0x00);

//

2 lines x 16, 1/18 duty, basic instruction set. Next byte will be another command.

i2c_write(0x24);

// Set CGRAM address to

i2c_write(0x40);

0

// Repeated Start condition

startI2C();

SendI2CAddress(0x70);

// RS=1, next byte is

i2c_write(0x40);

a data byte

// Here the data bytes to define the character

// Behind the write commands the 5x8 dot matrix is shown, the

1 represents a on pixel.

// The Euro currency character can be recognized by the 0/1 pattern (see Figure 48

)

i2c_write(0x06); // 00110

i2c_write(0x09); // 01001

i2c_write(0x08); // 01000

i2c_write(0x1E); // 11110

i2c_write(0x08); // 01000

i2c_write(0x09); // 01001

PCF2119X_5

Product data sheet

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PCF2119x

NXP Semiconductors

LCD controllers/drivers

i2c_write(0x06); // 00110

i2c_stop();

// Until here the definition of the character and writing it into the CGRAM. Now it

// still needs to be displayed. See below.

// PCF2119, setting of proper display modes

startI2C();

// PCF2119 slave address for write, SA0 is connected to Vdd

SendI2CAddress(0x70);

// MSB (Continuation bit Co)

// is command byte

= 0, more than one byte may follow. Bit6, RS=0, next byte

i2c_write(0x00);

//

2 lines x 16, 1/18 duty, extended instruction set. Next byte will be another

// command.

i2c_write(0x25);

// Set display configuration to right to left, column 80 to 1. Row data displ. top to

// bottom,1 to 16.

i2c_write(0x06);

// Set to character mode, full display, icon blink disabled

i2c_write(0x08);

// Set voltage multiplier to

i2c_write(0x40);

2

// Set Vlcd and store in register VA

i2c_write(0xA0);

// Change from extended instruction set to basic instruction set

i2c_write(0x24);

// Display control: set display on, cursor off, no blink

i2c_write(0x0C);

// Entry mode set, increase DDRAM after access, no shift

i2c_write(0x06);

// Return home, set DDRAM address

i2c_write(0x02);

0 in address counter

// Clear entire display, set DDRAM address to

i2c_write(0x01);

0 in address counter

// Repeated Start condition because RS needs to be changed from

0 to 1

startI2C();

SendI2CAddress(0x70);

// RS=1, next byte is data

i2c_write(0x40);

// Write the character at address 0, which is the previously defined Euro currency

// character

i2c_write(0x00);

i2c_stop();

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

67 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

17. Bare die outline

Bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm

PCF2119X

D

Z

x

y

E

0

PC2119-2

Y

X

e

b

A

1

e

b

A

1

L

detail X

detail Y

detail Z

0

2.5

scale

5 mm

Dimensions

(1)

A

(1)

Unit

max

A

b

1

D

E

e

1

L

1

0.0225

mm nom 0.380 0.0175 0.050 0.100 7.59 1.71 0.070 0.350 0.090

min 0.0125

Note

1. Dimension not drawn to scale

pcf2119x_do

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

09-07-16

09-08-03

PCF2119X

Fig 49. Bare die outline of PCF2119x

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

68 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 45. Pin location

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

V_DD1

V_DD2

V_DD3

E

1

X

Y

Description

+745

−274

logic supply voltage 1

2

−204

3

−134

4

−64

5

+6

6

+76

7

+146

V_LCDgenerator supply voltage 2

8

+216

9

+286

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

+356

+426

+496

+566

+636

+706

+776

+846

+916

+986

data bus clock input

test pin 1

T1

+1196

+1406

+1616

+1686

+1756

+1826

+1896

+1966

+2036

+2106

+2176

+2246

+2316

+2386

+2456

+2666

+2736

+2806

+2876

+2946

+3016

T2

test pin 2

V_SS1

ground 1

V_SS1

V_SS2

ground 2

V_SS2

V_LCDSENSE

V_LCDOUT

input for voltage multiplier regulation

V_LCDoutput

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

69 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 45. Pin location …continued

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

V_LCDOUT

V_LCDIN

41

42

43

44

45

46

47

48

49

X

Y

Description

+745

−745

+3086

+3156

+3226

+3296

+3366

+3436

+3506

+3576

+3646

+3576

+3506

+3436

+3366

+3296

+3226

+3156

+3086

+3016

+2946

+2876

+2806

+2736

+2666

+2596

+2526

+2456

+2386

+2316

+2246

+2176

+2106

+2036

+1966

+1896

+1756

+1686

+1616

+1546

+1476

+1406

V_LCDoutput

input for generation of LCD bias levels

V_LCDIN

dummy (V_SS1) 50

dummy

R8

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

LCD row driver output

R7

R6

R5

R4

R3

R2

R1

R17

C80

C79

C78

C77

C76

C75

C74

C73

C72

C71

C70

C69

C68

C67

C66

C65

C64

C63

C62

C61

C60

LCD column driver output

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

70 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 45. Pin location …continued

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

C59

C58

C57

C56

C55

C54

C53

C52

C51

C50

C49

C48

C47

C46

C45

C44

C43

C42

C41

R17DUP

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

81

X

Y

Description

−745

+1336

+1266

+1196

+1126

+1056

+986

+916

+846

+776

+706

+636

+566

+496

+426

+356

+286

+216

+146

+76

LCD column driver output

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

+6

LCD row driver output

−64

LCD column driver output

−134

−204

−274

−344

−414

−484

−554

−624

−694

−764

−834

−904

−974

−1044

−1114

−1184

−1254

−1324

−1394

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

71 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 45. Pin location …continued

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

X

Y

Description

−745

+745

−1464

−1534

−1604

−1674

−1744

−1884

−1954

−2024

−2094

−2164

−2234

−2304

−2374

−2444

−2514

−2584

−2654

−2724

−2794

−2864

−2934

−3004

−3074

−3144

−3214

−3284

−3354

−3424

−3494

−3704

−3634

−3494

−3424

−3214

−3004

−2934

−2584

−2374

−2164

LCD column driver output

C8

C7

C6

C5

C4

C3

C2

C1

R18

R9

LCD row driver output

R10

R11

R12

R13

R14

R15

R16

dummy (V_SS1) 150

dummy

I²C-bus serial clock input

SCL

T3

151

152

153

154

155

156

157

158

159

160

test pin 3

POR

PD

external Power-On Reset (POR) input

power-down mode select input

I²C-bus serial data input/output

SDA

R/W

RS

read/write input

register select input

DB0

8-bit bidirectional data bus; bit 0

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

72 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

Table 45. Pin location …continued

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

DB1

161

162

163

164

165

166

167

168

X

Y

Description

+745

−1954

−1744

−1534

−1324

−1114

−904

−694

−484

8-bit bidirectional data bus; bit 1

8-bit bidirectional data bus; bit 2

8-bit bidirectional data bus; bit 3

8-bit bidirectional data bus; bit 4

8-bit bidirectional data bus; bit 5

8-bit bidirectional data bus; bit 6

8-bit bidirectional data bus; bit 7

oscillator or external clock input

DB2

DB3/SA0

DB4

DB5

DB6

DB7

OSC

Table 46. Alignment mark location

All X and Y coordinates are referenced to the center of the chip (dimensions in µm).

Symbol

AM1

X

Y

-

+745

−745

−2689

+2561

+3681

−3599

AM2

AM3

AM4

18. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

73 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

19. Packing information

A

C

1.1

1.2

1.3

2.1

2.2

3.1

x.1

D

F

1.y

B

y

E

x

001aai624

For dimensions see Table 47.

Fig 50. Tray details

Table 47. Tray dimensions

Dimension

Description

Value

A

B

C

D

E

F

x

pocket pitch x direction

pocket pitch y direction

pocket width x direction

pocket width y direction

tray width x direction

tray width y direction

pockets in x direction

pockets in y direction

10.16 mm

4.45 mm

7.74 mm

1.91 mm

50.8 mm

4

y

10

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

74 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

marking code

001aaj623

The orientation of the IC in a pocket is indicated by the position of the IC type name on the die

surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pin

location diagram for the orientating and position of the type name on the die surface.

Fig 51. Tray alignment

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

75 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

20. Abbreviations

Table 48. Abbreviations

Acronym

CGRAM

CGROM

CMOS

COG

DC

Description

Character Generator RAM

Character Generator ROM

Complementary Metal Oxide Semiconductor

Chip-On-Glass

Direct Current

DDRAM

HBM

I²C

Display Data RAM

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

ITO

Indium Tin Oxide

LCD

Liquid Crystal Display

Least Signiﬁcant Bit

Machine Model

LSB

MM

MSB

MSL

Most Signiﬁcant Bit

Moisture Sensitivity Level

Multiplexer

MUX

PCB

Printed-Circuit Board

Power-On Reset

POR

RAM

RMS

ROM

SCL

Random Access Memory

Root Mean Square

Read Only Memory

Serial Clock Line

SDA

Serial Data Line

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

76 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

21. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10706 — Handling bare die

[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] SNW-SQ-623 — NXP store and transport conditions

[10] UM10204 — I²C-bus speciﬁcation and user manual

22. Revision history

Table 49. Revision history

Document ID

PCF2119X_5

Modiﬁcations:

Release date

20090813

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF2119X_4

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• The entire data sheet has been reworked for better readability and understandability

PCF2119X_4

PCF2119X_3

PCF2119X_2

PCF2119X_1

20030130

20020116

19990302

19971121

Product speciﬁcation

Objective speciﬁcation

-

PCF2119X_3

PCF2119X_2

PCF2119X_1

-

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

77 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

23. Legal information

23.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Limiting values — Stress above one or more limiting values (as deﬁned in

23.2 Deﬁnitions

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

23.3 Disclaimers

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Bare die — All die are tested on compliance with their related technical

speciﬁcations as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

I²C-bus — logo is a trademark of NXP B.V.

24. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

78 of 79

PCF2119x

NXP Semiconductors

LCD controllers/drivers

25. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

10.2.3.5 HV_gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.2.3.6 VLCD_set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

11

Basic architecture . . . . . . . . . . . . . . . . . . . . . . 39

Parallel interface. . . . . . . . . . . . . . . . . . . . . . . 39

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 41

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 42

I²C-bus deﬁnitions . . . . . . . . . . . . . . . . . . . . . 42

11.1

11.2

11.2.1

11.2.2

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

12

13

14

15

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 45

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 46

Static characteristics . . . . . . . . . . . . . . . . . . . 47

Dynamic characteristics. . . . . . . . . . . . . . . . . 49

8

8.1

8.1.1

8.1.2

8.1.3

8.2

8.3

8.4

8.4.1

8.5

8.6

Functional description . . . . . . . . . . . . . . . . . . . 7

Oscillator and timing generator. . . . . . . . . . . . . 7

Timing generator. . . . . . . . . . . . . . . . . . . . . . . . 7

Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Reset function and Power-On Reset (POR) . . . 7

Power-down mode . . . . . . . . . . . . . . . . . . . . . . 8

LCD supply voltage generator . . . . . . . . . . . . . 8

Programming ranges . . . . . . . . . . . . . . . . . . . . 9

LCD bias voltage generator . . . . . . . . . . . . . . 10

LCD row and column drivers . . . . . . . . . . . . . 10

16

16.1

16.2

Application information . . . . . . . . . . . . . . . . . 52

General application information . . . . . . . . . . . 52

Power supply connections for internal

V

_LCDgeneration . . . . . . . . . . . . . . . . . . . . . . . 52

Power supply connections for external

_LCDgeneration . . . . . . . . . . . . . . . . . . . . . . . 53

16.3

V

16.4

16.5

16.6

16.7

16.8

16.9

Information about V_LCDconnections . . . . . . . 53

Reducing current consumption . . . . . . . . . . . 53

Charge pump characteristics . . . . . . . . . . . . . 54

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Connections with LCD modules. . . . . . . . . . . 57

4-bit operation, 1-line display using external

9

Display data RAM and ROM . . . . . . . . . . . . . . 14

DDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Cursor control circuit. . . . . . . . . . . . . . . . . . . . 23

9.1

9.2

9.3

9.4

reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8-bit operation, 1-line display using external

16.10

reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8-bit operation, 2-line display . . . . . . . . . . . . . 61

I²C-bus operation, 1-line display . . . . . . . . . . 62

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 64

User deﬁned characters and symbols . . . . . . 66

10

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data register . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Instruction register . . . . . . . . . . . . . . . . . . . . . 25

Basic instructions (bit H = 0 or 1) . . . . . . . . . . 27

16.11

16.12

16.13

16.14

10.1

10.2

10.2.1

10.2.1.1 Function_set . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.2.1.2 BF_AC instructions. . . . . . . . . . . . . . . . . . . . . 27

10.2.1.3 Read_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.2.1.4 Write_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

17

18

19

20

21

22

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 68

Handling information . . . . . . . . . . . . . . . . . . . 73

Packing information . . . . . . . . . . . . . . . . . . . . 74

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 76

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Revision history . . . . . . . . . . . . . . . . . . . . . . . 77

10.2.2

Standard instructions (bit H = 0). . . . . . . . . . . 29

10.2.2.1 Clear_display . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2.2.2 Return_home . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2.2.3 Entry_mode_set . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.2.4 Display_ctl instructions . . . . . . . . . . . . . . . . . . 30

10.2.2.5 Curs_disp_shift. . . . . . . . . . . . . . . . . . . . . . . . 31

10.2.2.6 Set_CGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2.2.7 Set_DDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32

23

Legal information . . . . . . . . . . . . . . . . . . . . . . 78

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 78

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 78

23.1

23.2

23.3

23.4

10.2.3

Extended instructions (bit H = 1) . . . . . . . . . . 33

24

25

Contact information . . . . . . . . . . . . . . . . . . . . 78

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.2.3.1 Screen_conf . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2.3.2 Disp_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2.3.3 Icon_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.2.3.4 Temp_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 August 2009

Document identifier: PCF2119X_5


型号：	PCF2119FU/2/F2Z
厂家：	NXP
描述：	PCF2119x - LCD controllers/drivers DIE 168-Pin 驱动器控制器 CD
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中文：	中文翻译
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