PCF85116-3D [NXP]
IC 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, PLASTIC, SOT-96-1, SO-8, Programmable ROM;
| 型号： | PCF85116-3D |
| 厂家： | 
NXP |
| 描述： | IC 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, PLASTIC, SOT-96-1, SO-8, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总21页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF85116-3
2048 × 8-bit CMOS EEPROM with I2C-bus interface
Rev. 03 — 19 August 2002
Product data
1. Description
The PCF85116-3 is an 16 kbits (2048 × 8-bit) floating gate Electrically Erasable
Programmable Read Only Memory (EEPROM). By using redundant EEPROM cells it
is fault tolerant to single bit errors. In most cases multi bit errors are also covered.
This feature dramatically increases reliability compared to conventional EEPROM
memories. Power consumption is low due to the full CMOS technology used. The
programming voltage is generated on-chip, using a voltage multiplier.
As data bytes are received and transmitted via the serial I2C-bus, a package using
eight pins is sufficient. Only one PCF85116-3 device is required to support all eight
blocks of 256 × 8-bit each.
Timing of the E/W cycle is carried out internally, thus no external components are
required. A write-protection input at pin 7 (WP) allows disabling of write-commands
from the master by a hardware signal. When pin 7 is HIGH, data in the EEPROM are
protected. The data bytes received will not be acknowledged by the PCF85116-3 and
the EEPROM contents are not changed.
Remark: The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family.
The PCF85116-3 covers the whole address space of 16 kbits; address inputs are no
longer needed. Therefore, pins 1 to 3 are not connected. The write-protection input
(WP) is on pin 7.
2. Features
■ Low power CMOS:
◆ maximum operating current 1.0 mA
◆ maximum standby current 10 µA (at 5.5 V), typical 4 µA
■ Non-volatile storage of 16 kbits organized as eight blocks of 256 × 8-bit each
■ Single supply with full operation down to 2.7 V
■ On-chip voltage multiplier
■ Serial input/output I2C-bus (100 kbits/s standard-mode and 400 kbits/s fast-mode)
■ Write operations: multi byte write mode up to 32 bytes
■ Write-protection input
■ Read operations:
◆ sequential read
◆ random read
■ Internal timer for writing (no external components)
■ Power-on-reset
■ High reliability by using redundant EEPROM cells
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
■ Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 °C
■ 20 years non-volatile data retention time (minimum)
■ Pin and address compatible to the PCx85xxC-2 family
■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
■ Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA
■ Offered in DIP and SO packages
3. Quick reference data
Table 1:
Symbol
VDD
Quick reference data
Parameter
Conditions
Min
Typ
Max
5.5
1.0
1.0
6
Unit
V
supply voltage
2.7
-
-
-
-
-
IDDR
supply current read
supply current E/W
standby supply current
fSCL = 400 kHz; VDD = 5.5 V
fSCL = 400 kHz; VDD = 5.5 V
VDD = 2.7 V
-
-
-
-
mA
mA
µA
µA
IDDW
Istb
VDD = 5.5 V
10
4. Ordering information
Table 2:
Ordering information
Type number
Package
North America Name
Description
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT97-1
SOT96-1
PCF85116-3P
PCF85116-3T
PCF85116-3N
PCF85116-3D
DIP8
SO8
9397 750 10249
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 19 August 2002
2 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
5. Block diagram
WP
7
PCF85116-3
6
SCL
SDA
INPUT
FILTER
2
I C-BUS CONTROL LOGIC
5
n
TEST MODE
REGISTER
ADDRESS
COMPARATOR
SHIFT
REGISTER
ADDRESS
POINTER
SEQUENCER
5
COLUMN DECODER
PAGE REGISTER
HV
GENERATOR
DIVIDER
6
ROW
DEC
EEPROM ARRAY
(8 × 256 × 8)
8
V
DD
POWER-ON-RESET
OSCILLATOR
4
002aaa338
V
SS
Fig 1. Block diagram.
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© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 19 August 2002
3 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
6. Pinning information
6.1 Pinning
V
1
2
3
4
8
7
6
5
n.c.
n.c.
n.c.
DD
WP
PCF85116-3
SCL
V
SDA
SS
002aaa284
Fig 2. Pin configuration.
6.2 Pin description
Table 3:
Symbol
n.c.
Pin description
Pin
1
Description
not connected
not connected
not connected
n.c.
2
n.c.
3
VSS
4
negative supply voltage
SDA
SCL
WP
5
serial data input/output (I2C-bus)
serial clock input (I2C-bus)
active HIGH write-protection input
positive supply voltage
6
7
VDD
8
7. Device selection
Table 4:
Selection
Bit
Device selection code
Device code
Chip enable
R/W
B0
B7[1]
B6
0
B5
1
B4
0
B3
B2
B1
Device
1
MEM SEL 2 MEM SEL 1 MEM SEL 0
R/W
[1] The Most Significant Bit (MSB) ‘B7’ is sent first.
9397 750 10249
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 19 August 2002
4 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
8. Functional description
8.1 I2C-bus protocol
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
8.1.1 Bus conditions
The following bus conditions have been defined:
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.1.2 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes transferred between the START and STOP
conditions is limited to 32 bytes in the E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within the I2C-bus specifications a low-speed mode (2 kHz clock rate), a high-speed
mode (100 kHz clock rate) and a fast speed mode (400 kHz clock rate) are defined.
The PCF85116-3 operates in all three modes.
By definition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signal is called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
put on the bus by the transmitter. The master generates an extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
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Product data
Rev. 03 — 19 August 2002
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PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3 Device addressing
Following a START condition, the bus master must output the address of the slave it
is accessing. The four MSBs of the slave address are the device type identifier (see
Figure 3). For the PCF85116-3 this is fixed to ‘1010’.
Fig 3. Slave address.
The next three significant bits of the slave address field (B3, B2, B1) are the block
selection bits. It is used by the host to select one out of eight blocks
(1 block = 256 bytes of memory). These are, in effect, the three most significant bits
of the word address.
The last bit of the slave address (R/W) defines the operation to be performed. When
R/W is set to logic 1, a read operation is selected.
8.1.4 Write operations
Byte/word write: For a write operation, the PCF85116-3 requires a second address
field. This address field is a word address providing access to any one of the eight
blocks of memory. Upon receipt of the word address, the PCF85116-3 responds with
an acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is a maximum of 10 ms.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I2C-bus.
Page write: The PCF85116-3 is capable of a 32-byte page write operation. It is
initiated in the same manner as the byte write operation. The master can transmit up
to 32 data bytes within one transmission. After receipt of each byte, the PCF85116-3
will respond with an acknowledge. The master terminates the transfer by generating a
STOP condition. The maximum total E/W time in this mode is 10 ms.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
6 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
After the receipt of each data byte, the six high-order bits of the memory address
providing access to one of the 64 pages of the memory remain unchanged. The five
low-order bits of the memory address will be incremented only (see Figure 4). By
these five bits a single byte within the page in access is selected. By an increment the
memory address may change from 31 to 0, from 63 to 32, etc. If the master transmits
more than 32 bytes prior to generating the STOP condition, data within the addressed
page may be overwritten and unpredictable results may occur. As in the byte write
operation, all inputs are disabled until completion of the internal write cycles.
read: auto increment
B3 B2 B1
WORD ADDRESS
write: unchanged
write: auto increment
002aaa288
Fig 4. Auto-increment of memory address.
Remark: Write accesses to the EEPROM are enabled if the pin WP is LOW. When
WP is HIGH the EEPROM is write-protected and no acknowledge will be given by the
PCF85116-3 when data is sent. However, an acknowledge will be given after the
slave address and the word address.
Fig 5. Auto increment memory address; two byte write.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
7 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
Fig 6. Page write operation; 32 bytes.
8.1.5 Read operations
Read operations are initiated in the same manner as write operations with the
exception that the LSB of the slave address (R/W) is set to logic 1.
There are three basic read operations: current address read, random read, and
sequential read.
Remark: During read operations all bits of the memory address are incremented
after each transmission of a data byte. Contrary to write operations, an overflow of the
memory address occurs from 2047 to 0 (see Figure 8).
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
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PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
Fig 7. Master reads PCF85116-3 slave after setting word address (write word address; read data);
sequential read.
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
1
0
1
0 B3 B2 B1 1
A
A
DATA
1
P
S
DATA
n bytes
last bytes
R/W
SLAVE ADDRESS
auto increment
word address
auto increment
word address
002aaa294
Fig 8. Master reads PCF85116-3 immediately after first byte (read mode); current address read.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
9 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
9. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Vi
Parameter
Conditions
Min
Max
+6.5
+6.5
1
Unit
V
supply voltage
−0.3
input voltage on any input pin
input current on any input pin
output current
|Zi| > 500 Ω
VSS − 0.8
V
Ii
-
mA
mA
°C
°C
kV
Io
-
10
Tstg
Tamb
Vesd
storage temperature
−65
−40
2
+150
+85
-
operating ambient temperature
electrostatic discharge voltage
[1]
[1] ESD human body model Q22 at Tamb = 22 °C; discharge procedure according to MIL-STD-883C Method 3015.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
10 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
10. Characteristics
Table 6:
Characteristics
VDD = 2.7 to 3.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
2.7
-
-
-
5.5
1.0
V
IDDR
supply current read
fSCL = 400 kHz;
VDD = 5.5 V
mA
IDDW
supply current E/W
fSCL = 400 kHz;
VDD = 5.5 V
-
-
1.0
mA
IDD(stb)
standby supply current
VDD = 2.7 V
VDD = 5.5 V
-
-
-
-
6
µA
µA
10
SDA input/output (pin 5)
VIL
LOW level input voltage
−0.8
-
-
-
-
-
0.3VDD
+6.5
0.4
V
VIH
HIGH level input voltage
LOW level output voltage
0.7VDD
V
VOL1
VOL2
ILO
IOL = 3 mA; VDD(min)
IOL = 6 mA; VDD(min)
VOH = VDD
-
-
-
V
0.6
V
output leakage current
1
µA
[1]
to(f)
output fall time from VIHmin to VILmax
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
20 + 0.1Cb
20 + 0.1Cb
0
-
-
-
250
250
100
ns
ns
ns
tSP
Ci
pulse width of spikes suppressed by
filter
input capacitance
VI = VSS
-
-
10
pF
SCL input (pin 6)
VIL
VIH
ILI
LOW level input voltage
−0.8
-
-
-
-
-
0.3VDD
+6.5
±1
V
HIGH level input voltage
input leakage current
clock input frequency
0.7VDD
V
VI = VDD or VSS
-
µA
kHz
ns
fSCL
tSP
0
0
400
pulse width of spikes suppressed by
filter
100
Ci
input capacitance
VI = VSS
-
-
7
pF
WP input (pin 7)
VIL
VIH
LOW level input voltage
HIGH level input voltage
−0.8
-
-
0.1VDD
V
V
0.9VDD
VDD + 0.8
Data retention time
tS data retention time
Tamb = 55 °C
20
-
-
years
[1] The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF).
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
11 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
11. I2C-bus characteristics
Table 7:
I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Standard mode
Fast mode
Unit
Min
0
Max
100
-
Min
0
Max
400
-
fSCL
tBUF
clock frequency
kHz
time the bus must be free before
new transmission can start
4.7
1.3
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
-
0.6
-
µs
tLOW
LOW level clock period
HIGH level clock period
set-up time for START condition
data hold time
4.7
4.0
4.7
-
-
-
1.3
0.6
0.6
-
-
-
µs
µs
µs
tHIGH
tSU;STA
tHD;DAT
repeated start
for CBUS compatible masters
for I2C-bus devices
5
-
-
-
µs
ns
ns
µs
ns
µs
[1]
0
-
0
-
tSU;DAT
data set-up time
250
-
100
-
[2]
tr
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
-
1000
300
-
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
-
[2]
tf
-
tSU;STO
4.0
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
[2] Cb = total capacitance of one bus line in pF.
SDA
t
t
t
f
t
BUF
LOW
HD;STA
SCL
P
S
S
P
t
t
HIGH
HD;STA
t
t
t
t
t
SU;STO
r
HD;DAT
SU;DAT
SU;STA
MBA705
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
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Product data
Rev. 03 — 19 August 2002
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PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
12. Write cycle limits
Table 8:
The power-on-reset circuit resets the I2C-bus logic with a set-up time of ≤10 µs. Enabling the chip is achieved by connecting
the WP input to VSS
Symbol Parameter
E/W cycle timing
Write cycle limits
.
Conditions
Min
Typ
Max
Unit
tE/W
E/W cycle time
-
-
10
ms
Endurance
NE/W
E/W cycle per byte
Tamb = −40 to +85 °C
Tamb = 22 °C
100000
-
-
-
-
cycles
cycles
1000000
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Product data
Rev. 03 — 19 August 2002
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PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT96-1
076E03
MS-012
Fig 10. SO8 (SOT96-1).
9397 750 10249
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 19 August 2002
14 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D
M
E
A
2
A
A
1
L
c
w M
Z
b
1
e
(e )
1
M
H
b
b
2
8
5
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
1.15
0.068 0.021 0.042 0.014
0.045 0.015 0.035 0.009
0.39
0.36
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.045
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT97-1
050G01
MO-001
SC-504-8
Fig 11. DIP8 (SOT97-1).
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
15 of 21
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
14. Soldering
14.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended.
14.2 Surface mount packages
14.2.1 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 220 °C for thick/large
packages, and below 235 °C for small/thin packages.
14.2.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
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• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
14.2.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
14.3 Through-hole mount packages
14.3.1 Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 °C; solder at this
temperature must not be in contact with the joints for more than 5 seconds. The total
contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (Tstg(max)).
If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
14.3.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit
temperature is between 300 and 400 °C, contact may be up to 5 seconds.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
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Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
14.4 Package related soldering information
Table 9:
Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Soldering method
Wave
Reflow[2] Dipping
Through-hole
mount
DBS, DIP, HDIP, SDIP, SIL suitable[3]
−
suitable
Surface mount
BGA, LBGA, LFBGA,
SQFP, TFBGA, VFBGA
not suitable
suitable
suitable
−
−
HBCC, HBGA, HLQFP,
HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
PLCC[5], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
−
−
−
not recommended[5][6] suitable
not recommended[7]
suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
9397 750 10249
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Product data
Rev. 03 — 19 August 2002
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2048 × 8-bit CMOS EEPROM with I2C-bus interface
15. Revision history
Table 10: Revision history
Rev Date
CPCN
-
Description
03 20020819
Product data (9397 750 10249); Engineering Change Notice 853-2356 28772;
supersedes data in data sheet PCF85116-3_2 dated 1997 Apr 02 (9397 750 01994).
Modifications:
• The format of this specification has been redesigned to comply with Philips
Semiconductors’ new presentation and information standard.
• Table 2 on page 2: North America type numbers added.
• Figure 1 on page 3: modified.
• Table 3 on page 4: description for pin 7 (WP) adjusted.
• Figures 3, 4, 5, 6, 7, 8: modified to display fixed and software-selectable slave addresses.
9397 750 10249
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
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Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
16. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
18. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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Product data
Rev. 03 — 19 August 2002
PCF85116-3
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus interface
Contents
1
2
3
4
5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Device selection. . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Functional description . . . . . . . . . . . . . . . . . . . 5
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 5
Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device addressing . . . . . . . . . . . . . . . . . . . . . . 6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . 6
Read operations . . . . . . . . . . . . . . . . . . . . . . . . 8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C-bus characteristics . . . . . . . . . . . . . . . . . . 12
Write cycle limits . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
10
11
12
13
14
14.1
14.2
14.2.1
14.2.2
14.2.3
14.3
14.3.1
14.3.2
14.4
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Surface mount packages . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
Through-hole mount packages. . . . . . . . . . . . 17
Soldering by dipping or by solder wave . . . . . 17
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
Package related soldering information . . . . . . 18
15
16
17
18
19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2002.
Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 19 August 2002
Document order number: 9397 750 10249
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