PCF85132U/2DA/1 [NXP]
LIQUID CRYSTAL DISPLAY DRIVER;型号: | PCF85132U/2DA/1 |
厂家: | NXP |
描述: | LIQUID CRYSTAL DISPLAY DRIVER 驱动 接口集成电路 |
文件: | 总62页 (文件大小:773K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCF85132
LCD driver for low multiplex rates
Rev. 3 — 15 July 2013
Product data sheet
1. General description
The PCF85132 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 160 segments. It can easily
be cascaded for larger LCD applications. The PCF85132 is compatible with most
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremental addressing, by
hardware subaddressing, and by display memory switching (static and duplex drive
modes).
2. Features and benefits
Single-chip LCD controller and driver for up to 640 elements
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
160 segment drives:
Up to 80 7-segment numeric characters
Up to 40 14-segment alphanumeric characters
Any graphics of up to 640 elements
May be cascaded for large LCD applications (up to 5120 elements possible)
160 4-bit RAM for display data storage
Software programmable frame frequency in steps of 5 Hz in the range of 60 Hz to
90 Hz; factory calibrated
Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
Internal LCD bias generation with voltage-follower buffers
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Wide power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption, typical: IDD = 4 A, IDD(LCD) = 30 A
400 kHz I2C-bus interface
Auto-incremental display data loading across device subaddress boundaries
Versatile blinking modes
Compatible with Chip-On-Glass (COG) technology
No external components required
Two sets of backplane outputs for optimal COG configurations of the application
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17 on page 55.
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
197 bumps; 6.5 1.16 0.40 mm
Version
PCF85132U
bare die
PCF85132U
3.1 Ordering options
Table 2.
Ordering options
Product type number
IC
revision
Sales item (12NC)
Delivery form
chips with bumps in tray
PCF85132U/2DA/1
1
935293465026
4. Marking
Table 3.
Marking codes
Product type number
PCF85132U/2DA/1
Marking code
PC85132/232-1
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
5. Block diagram
BP0 BP1 BP2 BP3
S0 to S159
160
V
LCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
V
SS
DISPLAY
RAM
PCF85132
CLK
BLINKER
CLOCK SELECT
TIMEBASE
AND TIMING
SYNC
COMMAND
DECODE
DATA POINTER AND
AUTO INCREMENT
WRITE DATA
CONTROL
POWER-ON
RESET
OSC
OSCILLATOR
SCL
SDA
2
SUBADDRESS
COUNTER
INPUT
FILTERS
I C-BUS
CONTROLLER
T1 T2 T3
A0 A1
SA0
SDAACK
V
DD
013aaa360
Fig 1. Block diagram of PCF85132
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
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6. Pinning information
6.1 Pinning
+y
PCF85132
+x
0
0
013aaa361
Viewed from active side. For mechanical details, see Figure 37 on page 49.
Fig 2. Pinning diagram of PCF85132
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
6.2 Pin description
Table 4.
Symbol
SDAACK[1]
SDA[1]
SCL
Pin description
Pin
Description
1 to 3
4 to 6
7 to 9
10
I2C-bus acknowledge output
I2C-bus serial data input
I2C-bus serial clock input
CLK
clock input and output
VDD
11 to 13
14
supply voltage
SYNC
OSC
cascade synchronization input and output
selection of internal or external clock
15
T1, T2, and T3
16, 17, and 18 to 20 dedicated testing pins; to be tied to VSS in
application mode
A0 and A1
SA0
21, 22
subaddress inputs
23
I2C-bus slave address input
ground supply voltage
LCD supply voltage
[2]
VSS
24 to 26
27 to 29
30, 31
VLCD
BP2 and BP0
S0 to S79
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
32 to 111
112 to 115
116 to 195
196, 197
BP0, BP2, BP1, and BP3
S80 to S159
BP3 and BP1
[1] For most applications SDA and SDAACK are shorted together (see Section 14.3 on page 44).
[2] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7. Functional description
The PCF85132 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays. It can directly
drive any static or multiplexed LCD containing up to four backplanes and up to
160 segments.
7.1 Commands of PCF85132
The commands available to the PCF85132 are defined in Table 5.
Table 5.
Definition of PCF85132 commands
Operation code
Command
Reference
Bit
7
1
0
0
1
1
1
1
6
1
0
1
1
1
1
1
5
0
0
0
1
1
1
1
4
0
0
0
0
1
1
0
3
2
1
0
mode-set
E
B
M[1:0]
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
load-data-pointer-MSB
load-data-pointer-LSB
device-select
bank-select
blink-select
P[7:4]
P[3:0]
0
1
0
1
0
A[1:0]
I
0
O
AB
BF[1:0]
frequency-ctrl
F[2:0]
7.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 6.
Bit
Mode-set - command bit description
Symbol
Value
Description
7 to 4
3
-
1100
fixed value
E
display status[1]
disabled (blank)[3]
enabled
0[2]
1
2
B
LCD bias configuration[4]
1⁄3 bias
1⁄2 bias
0[2]
1
1 to 0
M[1:0]
LCD drive mode selection
static; BP0
01
10
1:2 multiplex; BP0, BP1
1:3 multiplex; BP0, BP1, BP2
1:4 multiplex; BP0, BP1, BP2, BP3
11
00[2]
[1] The possibility to disable the display allows implementation of blinking under external control. The enable
bit determines also whether the internal clock signal is available at the CLK pin (see Section 7.1.6.2 on
page 9).
[2] Default value.
[3] The display is disabled by setting all backplane and segment outputs to VLCD
.
[4] Not applicable for static drive mode.
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data will be sent to.
Table 7.
Load-data-pointer-MSB - command bit description
See Section 7.5.1 on page 24.
Bit
Symbol
-
Value
Description
7 to 4
3 to 0
0000
0000[1] to
1001
fixed value
P[7:4]
defines the first 4 (most significant) bits of the
data-pointer
the data-pointer indicates one of the 160 display RAM
addresses
[1] Default value.
Table 8.
Load-data-pointer-LSB - command bit description
See Section 7.5.1 on page 24.
Bit
Symbol
-
Value
Description
7 to 4
3 to 0
0100
0000[1] to
1111
fixed value
P[3:0]
defines the last 4 (least significant) bits of the
data-pointer
the data-pointer indicates one of the 160 display RAM
addresses
[1] Default value.
7.1.3 Command: device-select
The device-select command allows defining the subaddress counter value.
Table 9.
Device-select - command bit description
See Section 7.5.2 on page 24.
Bit
Symbol
-
Value
Description
7 to 2
1 to 0
111000
00[1] to 11
fixed value
A[1:0]
defines one of four hardware subaddresses
(see Table 23 on page 44)
[1] Default value.
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
Table 10. Bank-select - command bit description
See Section 7.5.4 on page 25.
Bit
Symbol Value
Description
Static
1:2 multiplex[1]
7 to 2
1
-
I
111110
fixed value
input bank selection; storage of arriving display data
0[2]
1
RAM row 0
RAM row 2
RAM rows 0 and 1
RAM rows 2 and 3
0
O
output bank selection; retrieval of LCD display data
0[2]
1
RAM row 0
RAM row 2
RAM rows 0 and 1
RAM rows 2 and 3
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2] Default value.
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 11. Blink-select - command bit description
See Section 7.1.6.6 on page 10.
Bit
7 to 3
2
Symbol Value
Description
-
11110
fixed value
AB
blink mode selection
0[1]
1
normal blinking[2]
alternate RAM bank blinking[3]
1 to 0
BF[1:0]
blink frequency selection
00[1]
01
off
1
10
2
11
3
[1] Default value.
[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.1.6 Clock frequency and timing
The timing of the PCF85132 organizes the internal data flow of the device. The timing
includes the transfer of display data from the display RAM to the display segment outputs
and therefore the frame frequency.
7.1.6.1 Clock source selection
The PCF85132 can be configured to use either the built-in oscillator or an external clock
as clock source:
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Internal clock — To enable the internal oscillator, pin OSC has to be connected to VSS
.
Pin CLK then becomes an output. For further information on the internal clock, see
Section 7.1.6.2.
External clock — To enable the use of an external clock, pin OSC has to be connected to
VDD. Pin CLK then becomes an input for the external clock frequency fclk(ext). For further
information on the external clock, see Section 7.1.6.3.
Figure 3 illustrates the frequency generation of the PCF85132.
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Fig 3. Frequency generation of the PCF85132
Remark: A clock signal must always be supplied to the device. Removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.1.6.2 Internal clock
If the internal oscillator is used, the timing of the PCF85132 is derived from the built-in
oscillator by a pre-scaler which can be configured with the frequency-ctrl command (see
Table 12).
The internal oscillator is calibrated within an accuracy of ±3.9 % (at VDD = 5.0 V;
Tamb = 30 °C).
The frequency-ctrl command determines the division factor between the oscillator
frequency fosc and the internal clock frequency fclk(int). If the internal oscillator is used, the
frame frequency is derived from the internal clock frequency fclk(int) by the fixed division
shown in Equation 1 on page 10.
If the display is enabled (see bit E in Table 6), fclk(int) on pin CLK provides the clock signal
for cascaded LCD drivers in the system. For further information about cascading, see
Section 14.4 on page 44. The value range of fosc is specified in Table 22 on page 38.
7.1.6.3 External clock
If the external clock source is selected, the timing frequency of the PCF85132 is the
external clock frequency. In this case, the frequency-ctrl command has no influence on
the clock frequency nor the frame frequency. The frame frequency is derived from the
external clock frequency fclk(ext) by the fixed division as shown in Equation 1.
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.1.6.4 Frame frequency
Sourced by the internal oscillator or an external clock, the frame frequency is derived from
the clock frequency fclk by Equation 1.
fclk
-------
ffr
=
(1)
24
7.1.6.5 Command: frequency-ctrl
Table 12. Frequency-ctrl - command bit description
Bit
Symbol
Value
Description
Equation
Nominal
clock
Nominal
frame
frequency[1] frequency[1]
7 to 4
-
11101
000
fixed value
3 to 0 F[2:0]
defines the division factor
1440 Hz
60 Hz
65 Hz
70 Hz
64
80
-----
fclkint
fclkint
fclkint
=
=
=
fosc
fosc
fosc
001
1557 Hz
1694 Hz
64
-----
74
010
64
-----
68
011[2], 111
100
1800 Hz
1920 Hz
75 Hz
80 Hz
fclkint = fosc
64
-----
fclkint
fclkint
fclkint
=
=
=
fosc
fosc
fosc
60
101
110
2057 Hz
2174 Hz
85 Hz
90 Hz
64
-----
56
64
-----
53
[1] Calculated with the oscillator frequency of fosc = 1.800 Hz. The frame frequency is derived from the internal
clock frequency by Equation 1.
[2] Default value.
7.1.6.6 Blinking
The display blinking capabilities of the PCF85132 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 11). The blink
frequencies are derived from the clock frequency (fclk). The ratios between the clock and
blink frequencies depend on the blink mode in which the device is operating (see
Table 13).
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Table 13. Blink frequencies
Assuming that fclk = 1.800 kHz.
Blink mode
Operating mode ratio
Blink frequency
blinking off
off
1
-
~2.34 Hz
fclk
--------
768
fblink
fblink
fblink
=
=
2
3
~1.17 Hz
~0.59 Hz
fclk
-----------
1536
fclk
-----------
3072
=
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads: With the output bank selector, the displayed RAM banks are
exchanged (see Section 7.5.4 on page 25) with alternate RAM banks at the blink
frequency. This mode can also be specified by the blink-select command (see Table 11 on
page 8).
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD elements can blink selectively by changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blinking frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 6).
7.2 Power-On Reset (POR)
At power-on, the PCF85132 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled (bit E = 0, see Table 6 on page 6)
• If internal oscillator is selected (pin OSC connected to VSS), then there is no clock
signal on pin CLK
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.3 Possible display configurations
The display configurations possible with the PCF85132 depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 14.
All of the display configurations given in Table 14 can be implemented in a typical system
as shown in Figure 5.
PCF85132
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 15 July 2013
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 4. Example of displays suitable for PCF85132
Table 14. Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
Dot matrix/
Elements
7-segment
14-segment
4
3
2
1
640
480
320
160
80
60
40
20
40
30
20
10
640 dots (4 160)
480 dots (3 160)
320 dots (2 160)
160 dots (1 160)
V
DD
t
r
SDAACK
R ≤
2C
B
V
DD
V
LCD
160 segment drives
4 backplanes
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
LCD PANEL
PCA85132
(up to 640
elements)
OSC
CONTROLLER
A0 A1 SA0 V
SS
013aaa061
V
SS
Fig 5. Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF85132.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application.
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.3.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
7.3.2 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.3.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command. The biasing configurations that apply to the preferred modes of
operation, together with the biasing characteristics as functions of VLCD and the resulting
discrimination ratios (D) are given in Table 15.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 15. Biasing characteristics
LCD drive
mode
Number of:
LCD bias
configuration
VoffRMS VonRMS
------------------------ ----------------------- D = ------------------------
VLCD VLCD VoffRMS
VonRMS
Backplanes Levels
static
1
2
2
3
4
2
3
4
4
4
static
0
1
1
⁄
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off)
.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------ , where the values for a are
1 + a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 2:
a2 + 2a + n
n 1 + a2
VonRMS
=
-----------------------------
(2)
V
LCD
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
PCF85132
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Product data sheet
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PCF85132
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LCD driver for low multiplex rates
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 3:
a2 – 2a + n
n 1 + a2
VoffRMS
=
-----------------------------
(3)
(4)
V
LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 4:
a2 + 2a + n
VonRMS
----------------------
D =
=
---------------------------
a2 – 2a + n
VoffRMS
Using Equation 4, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21
1⁄2 bias is ---------- = 1.528 .
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): VLCD
• 1:4 multiplex (1⁄2 bias): VLCD
=
=
6 VoffRMS = 2.449VoffRMS
4 3
---------------------
= 2.309VoffRMS
3
These compare with VLCD = 3VoffRMS when 1⁄3 bias is used.
LCD is sometimes referred as the LCD operating voltage.
V
7.3.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltages, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
V
V
onRMS Vthon
offRMS Vthoff
(5)
(6)
V
on(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a (see Equation 2), n (see Equation 4), and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat
.
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
90 %
10 %
V
[V]
RMS
V
th(off)
V
th(on)
OFF
SEGMENT
GREY
SEGMENT
ON
SEGMENT
013aaa494
Fig 6. Electro-optical characteristic: relative transmission curve of the liquid
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.3.4 LCD drive mode waveforms
7.3.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 7.
T
fr
LCD segments
V
LCD
BP0
Sn
V
SS
state 1
(on)
state 2
(off)
V
LCD
V
SS
V
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = VLCD
V
.
Vstate2(t) = V(Sn+1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 7. Static drive mode waveforms
PCF85132
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LCD driver for low multiplex rates
7.3.4.2 1:2 multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF85132 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 8 and
Figure 9.
T
fr
V
LCD
LCD segments
V
V
/2
BP0
BP1
Sn
LCD
SS
state 1
V
LCD
state 2
V
V
/2
LCD
SS
V
LCD
V
V
SS
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
V
LCD
/2
LCD
0 V
−V
state 1
/2
LCD
−V
LCD
V
V
LCD
/2
LCD
0 V
state 2
−V
/2
LCD
LCD
−V
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD
.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD
.
Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF85132
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NXP Semiconductors
LCD driver for low multiplex rates
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
Sn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 1
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 9. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCF85132
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LCD driver for low multiplex rates
7.3.4.3 1:3 multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 10.
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
BP2
Sn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+2
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V /3
LCD
V
/3
LCD
state 1
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V /3
LCD
V
/3
LCD
state 2
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.638VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 10. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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LCD driver for low multiplex rates
7.3.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 11.
T
fr
V
2V
LCD segments
LCD
LCD
/3
BP0
BP1
BP2
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
/3
LCD
BP3
Sn
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+1
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+2
Sn+3
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
/3
LCD
V
LCD
state 1
state 2
0 V
LCD
-V
/3
/3
-2V
LCD
LCD
-V
V
LCD
2V
LCD
/3
/3
V
LCD
0 V
-V
/3
LCD
-2V
LCD
/3
LCD
-V
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD
.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
.
Fig 11. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF85132
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LCD driver for low multiplex rates
7.4 Backplane and segment outputs
7.4.1 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive capabilities.
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In
applications, it is possible to use either the pins for the backplanes
• on the top pin bar
• on the bottom pin bar
• or both of them to increase the driving strength of the device.
When using all backplanes available they may be connected to the respective sibling
(BP0 on the top pin bar with BP0 on the bottom pin bar, and so on).
7.4.2 Segment outputs
The LCD drive section includes 160 segment outputs (S0 to S159) which must be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data resident in the display register.
When less than 160 segment outputs are required, the unused segment outputs must be
left open-circuit.
7.5 Display RAM
The display RAM is a static 160 4 bit RAM which stores LCD data. There is a one-to-one
correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
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LCD driver for low multiplex rates
The display RAM bitmap, Figure 12, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the
segment outputs S0 to S159. In multiplexed LCD applications the segment data of the
first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
columns
display RAM addresses/segment outputs (S)
0
1
2
3
4
155 156 157 158 159
rows
0
1
2
3
display RAM rows/
backplane outputs
(BP)
013aaa220
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs; and between the bits in a RAM word and the backplane outputs.
Fig 12. Display RAM bitmap
When display data is transmitted to the PCF85132, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for the acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples, or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 13. The RAM filling organization depicted
applies equally to other LCD types.
The following applies to Figure 13:
• In static drive mode the eight transmitted data bits are placed in row 0 as 1 byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as 2 successive 4-bit RAM words.
• In 1:3 multiplex drive mode the 8 bits are placed in triples into row 0, 1, and 2 as 3
successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not
recommended to use this bit in a display because of the difficult addressing. This last
bit may, if necessary, be controlled by an additional transfer to this address but care
should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.5.3 on page 25).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as 2 successive 4-bit RAM words.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
S
S
S
S
S
a
n+2
n+3
n+4
n+5
n+6
b
BP0
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
S
f
n+1
rows
static
display RAM
rows/backplane
outputs (BP)
MSB
LSB
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
S
S
n
x
x
x
e
n+7
c
b
a
f
g
e
d
DP
c
x
d
DP
x
columns
display RAM address/segment outputs (s)
byte1 byte2
BP0
a
S
S
n
1:2
b
n
n + 1 n + 2 n + 3
f
n+1
rows
MSB
LSB
DP
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP
x
multiplex
g
x
x
BP1
a
b
f
g
e c d
e
S
S
n+2
n+3
c
d
DP
x
columns
display RAM address/segment outputs (s)
BP0
BP1
byte1
byte2
byte3
S
S
n+1
n+2
a
1:3
b
n
n + 1 n + 2
S
f
n
rows
MSB
LSB
e
display RAM
rows/backplane
outputs (BP)
0
1
2
3
b
DP
c
a
d
g
x
f
g
multiplex
b
DP
c
a
d
g
f
e
x
x
BP2
e
c
d
DP
x
columns
display RAM address/segment outputs (s)
byte2 byte3 byte4
byte1
byte5
a
S
S
n
1:4
b
BP2
BP3
n
n + 1
BP0
BP1
f
rows
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
c
f
MSB
LSB
d
multiplex
e
g
d
e
c
b
a
c
b
DP
f
e
g
d
DP
DP
n+1
001aaj646
x = data bit unchanged
Fig 13. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
7.5.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see 7 on page 7 and Table 8 on page 7).
Following this command, an arriving data byte is stored at the display RAM address
indicated by the data pointer. The filling order is shown in Figure 13.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early, then the state of the data pointer is
unknown. The data pointer should be re-written before further RAM accesses.
7.5.2 Subaddress counter
The storage of display data is conditioned by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined by
the device-select command (see Table 9 on page 7). If the content of the subaddress
counter and the hardware subaddress do not match then data storage is inhibited but the
data pointer is incremented as if data storage had taken place. The subaddress counter is
also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF85132 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
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LCD driver for low multiplex rates
7.5.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 16 (see Figure 13 as
well).
Table 16. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1
a0
-
b7
b6
b5
-
b4
b3
b2
-
b1
b0
-
c7
c6
c5
-
c4
c3
c2
-
c1
c0
-
d7
d6
d5
-
:
:
:
:
-
-
-
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 17.
Table 17. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1/b7 b4
a0/b6 b3
b1/c7 c4
b0/c6 c3
c1/d7 d4
c0/d6 d3
d1/e7 e4
d0/e6 e3
:
:
:
:
b5
-
b2
-
c5
-
c2
-
d5
-
d2
-
e5
-
e2
-
In the case described in Table 17 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8, and so on, have to be connected to elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written
• The data-pointer (see Section 7.1.2 on page 7) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.5.4 Bank selection
7.5.4.1 Output bank selector
The output bank selector (see Table 10 on page 8) selects one of the four rows per display
RAM address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
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PCF85132
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LCD driver for low multiplex rates
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the
contents of row 1, row 2, and then row 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
7.5.4.2 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded by using the bank-select
command (see Table 10). The input bank selector functions independently to the output
bank selector.
7.5.4.3 RAM bank switching
The PCF85132 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. A bank can be thought of as one RAM row or a collection of RAM rows (see
Figure 14). The RAM bank switching gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it is complete.
GLVSOD\ꢂ5$0ꢂDGGUHVVHVꢂꢃFROXPQVꢄꢍVHJPHQWꢂRXWSXWVꢂꢃ6ꢄ
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ꢆ
ꢅ
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EDQNꢂꢅ
ꢆ
ꢅ
ꢀ
ꢇ
PXOWLSOH[ꢂGULYHꢂPRGHꢂꢅꢎꢀ
ꢆ
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ꢅꢈꢈ ꢅꢈꢉ ꢅꢈꢊ ꢅꢈꢋ ꢅꢈꢌ
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Fig 14. RAM banks in static and multiplex driving mode 1:2
There are two banks; bank 0 and bank 1. Figure 14 shows the location of these banks
relative to the RAM map. Input and output banks can be set independently from one
another with the Bank-select command (see Table 10 on page 8). Figure 15 shows the
concept.
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
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Fig 15. Bank selection
In the static drive mode, the bank-select command may request the contents of row 2 to
be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
In Figure 16 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
FROXPQV
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ꢆ
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Fig 16. Example of the Bank-select command with multiplex drive mode 1:2
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF85132, the SDA line becomes fully
I2C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence, it may be possible that the acknowledge generated by the PCF85132
cannot be interpreted as logic 0 by the master. In COG applications where the
acknowledge cycle is required, it is therefore necessary to minimize the track resistance
from the SDAACK pin to the system SDA line to guarantee a valid LOW level (see
Section 14.2 on page 42).
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I2C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 17).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 17. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 18.
2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.
PCF85132
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LCD driver for low multiplex rates
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 18. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 19.
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 19. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 20.
PCF85132
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LCD driver for low multiplex rates
data output
by transmitter
not acknowledge
acknowledge
data output
by receiver
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 20. Acknowledgement on the I2C-bus
8.4 I2C-bus controller
The PCF85132 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF85132 is
the acknowledge signal. Device selection depends on the I2C-bus slave address, on the
transferred command data, and on the hardware subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to VSS which defines the hardware subaddress 0. In multiple device applications
A0 and A1 are tied to VSS or VDD in accordance with a binary coding scheme. No two
devices with a common I2C-bus slave address must have the same hardware
subaddress.
8.5 Input filters
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85132.
The entire I2C-bus slave address byte is shown in Table 18.
Table 18. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
0
1
1
1
0
0
SA0
The PCF85132 is a write-only device and does not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF85132 responds
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
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LCD driver for low multiplex rates
Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 8 PCF85132 on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex drive modes on the same I2C-bus
The I2C-bus protocol is shown in Figure 21. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF85132
slave addresses available. All PCF85132 with the corresponding SA0 level acknowledge
in parallel to the slave address, but all PCF85132 with the alternative SA0 level ignore the
whole I2C-bus transfer.
R/W = 0
slave address
control byte
RAM/command byte
S
A
0
M
S
B
L
S
B
C
O
R
S
S
0
1
1
1
0
0
0
A
P
A
EXAMPLES
a) transmit two bytes of RAM data
S
S
0
1
1
1
0
0
A
0
0
A
0
1
1
0
RAM DATA
COMMAND
COMMAND
RAM DATA
A
A
A
A
A
A
P
A
A
A
b) transmit two command bytes
S
A
0
0
0
1
S
0
1
1
1
0
0
A
0
0
COMMAND
RAM DATA
A
A
P
c) transmit one command byte and two RAM date bytes
S
A
S
0
1
1
1
0
0
A
0
0
1
0
RAM DATA
A
P
mgl752
Fig 21. I2C-bus protocol
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information.
Table 19. Control byte description
Bit
Symbol Value
Description
7
CO
continue bit
0
last control byte
control bytes continue
register selection
command register
data register
1
6
RS
0
1
5 to 0
-
-
not relevant
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LCD driver for low multiplex rates
MSB
LSB
7
6
5
4
3
2
1
0
CO RS
not relevant
mgl753
Fig 22. Control byte format
In this way, it is possible to configure the device and then fill the display RAM with little
overhead.
The command bytes and control bytes are also acknowledged by all addressed
PCF85132 connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter; see Section 7.5.1 and Section 7.5.2.
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCF85132. After the last (display) byte, the I2C-bus master issues a STOP condition (P).
Alternatively a repeated START may be asserted to restart an I2C-bus access.
PCF85132
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LCD driver for low multiplex rates
9. Internal circuitry
V
V
DD
LCD
S0 to S159,
BP0 to BP3
V
V
V
SS
SS
DD
SDAACK, SCL,
SDA, T3, V
LCD
SYNC, T1,
T2, A0, A1,
OSC, CLK,
SA0
V
V
SS
SS
013aaa221
Fig 23. Device protection diagram
10. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF85132
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NXP Semiconductors
LCD driver for low multiplex rates
11. Limiting values
Table 20. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter
Conditions
Min
0.5
50
0.5
50
0.5
Max
+6.5
+50
Unit
V
VDD
IDD
supply voltage
supply current
mA
V
VLCD
LCD supply voltage
+9.0
+50
IDD(LCD) LCD supply current
mA
V
Vi
input voltage
on pins CLK, SYNC,
SA0, OSC, SDA, SCL,
A0, A1, T1, T2, and T3
+6.5
II
input current
10
+10
mA
V
VO
output voltage
on pins S0 to S159 and 0.5
+9.0
BP0 to BP3
on pins SDAACK,
CLK, SYNC
0.5
+6.5
V
IO
output current
10
+10
mA
mA
mW
mW
V
ISS
ground supply current
total power dissipation
power dissipation per output
50
+50
Ptot
P/out
VESD
-
400
-
100
[2]
[3]
[4]
[5]
electrostatic discharge
voltage
HBM
MM
-
4500
300
200
-
V
Ilu
latch-up current
-
mA
C
Tstg
Tamb
storage temperature
ambient temperature
65
40
+150
+85
operating device
C
[1] Stresses above these values listed may cause permanent damage to the device.
[2] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[3] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
PCF85132
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NXP Semiconductors
LCD driver for low multiplex rates
12. Static characteristics
Table 21. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
-
-
-
-
-
5.5
8.0
20
60
70
70
V
VLCD
IDD
LCD supply voltage
supply current
1.8
V
[1][2][3]
[1][3]
fclk(ext) = 1.800 kHz
-
-
-
-
A
A
A
A
with internal oscillator running
fclk(ext) = 1.800 kHz
[1][2][4]
[1][4]
IDD(LCD) LCD supply current
with internal oscillator running
Logic[5]
VI
input voltage
on pins SDA and SCL
all other input pins
0.5
-
-
-
+5.5
V
0.5
VDD + 0.5 V
VIH
VIL
VO
HIGH-level input voltage
LOW-level input voltage
output voltage
on pins CLK, SYNC, OSC, A0, A1,
SA0, SCL, and SDA
0.7VDD
-
V
on pins CLK, SYNC, OSC, A0, A1,
SA0, SCL, and SDA
-
-
0.3VDD
V
on pins CLK and SYNC
on pin SDAACK
0.5
0.5
0.8VDD
VSS
-
-
-
-
-
VDD + 0.5 V
+5.5
VDD
0.2VDD
-
V
VOH
VOL
IOH
HIGH-level output voltage on pin SYNC, CLK
V
LOW-level output voltage on pin SYNC, CLK, SDAACK
V
HIGH-level output current output source current;
1.5
mA
VOH = 4.6 V;
VDD = 5 V;
on pin CLK
IOL
LOW-level output current output sink current;
on pins CLK and SYNC
VOL = 0.4 V;
VDD = 5 V
1.5
-
-
mA
on pin SDAACK
VDD 2 V;
3
3
6
-
-
-
-
-
-
mA
mA
mA
VOL = 0.2VDD
2 V < VDD < 3 V;
VOL = 0.4 V
VDD 3 V;
VOL = 0.4 V
VPOR
IL
power-on reset voltage
leakage current
1.0
1.3
-
1.6
+1
V
VI = VDD or VSS
;
1
A
on pin OSC, CLK, A0, A1, SA0,
SDA, and SCL
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LCD driver for low multiplex rates
Table 21. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
LCD outputs
Conditions
Min
Typ
Max
Unit
[6][7]
VO
output voltage variation
output resistance
on pins BP0 to BP3 and S0 to S159
VLCD = 5 V
30
-
+30
mV
RO
on pins BP0 to BP3
on pins S0 to S159
-
-
1.5
2.0
5
5
k
k
[1] LCD outputs are open-circuit; inputs at VSS or VDD; I2C-bus inactive; VLCD = 8.0 V, VDD = 5.0 V and RAM written with all logic 1.
[2] External clock with 50 % duty factor.
[3] For typical values, see Figure 24.
[4] For typical values, see Figure 25.
[5] The I2C-bus interface of PCF85132 is 5 V tolerant.
[6] Variation between any 2 backplanes on a given voltage level; static measured.
[7] Variation between any 2 segments on a given voltage level; static measured.
001aal014
20
I
DD
(μA)
16
I
internal
DD
12
8
4
I
external
DD
0
1
2
3
4
5
6
V
(V)
DD
IDD internal is measured with the internal oscillator.
IDD external is measured with an external clock.
Tamb = 30 C; 1:4 multiplex; VLCD = 8 V; all RAM written with logic 1; no display connected.
Fig 24. IDD with respect to VDD
PCF85132
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LCD driver for low multiplex rates
001aal111
40
I
DD(LCD)
(μA)
30
20
10
0
1
3
5
7
9
V
(V)
LCD
Tamb = 30 C; 1:4 multiplex; all RAM written with logic 1; no display connected; external clock with
clk = 1.800 Hz or fclk(ext) = 1.800 Hz.
f
Fig 25. IDD(LCD) with respect to VLCD
PCF85132
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LCD driver for low multiplex rates
13. Dynamic characteristics
Table 22. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Unit
[1][2][3]
fclk(int)
internal clock frequency
on pin CLK;
1600 1800 2060 Hz
display enabled;
VDD = 5 V 0.5 V
[4]
fclk(ext)
tclk(H)
tclk(L)
ffr
external clock frequency
HIGH-level clock time
LOW-level clock time
frame frequency variation
700
100
100
-
-
-
5000 Hz
external clock source used
external clock source used
VDD = 5 V 0.5 V
-
-
s
s
ffr = 75 Hz;
10
15
15
-
-
-
+10
+15
+15
%
%
%
T
amb = 30 C
ffr = 71 Hz;
Tamb = 85 C
ffr = 80 Hz;
Tamb = 40 C
tPD(SYNC_N) SYNC propagation delay
-
30
-
-
-
-
ns
s
s
tSYNC_NL
SYNC LOW time
100
-
tPD(drv)
driver propagation delay
VLCD = 5 V
10
Timing characteristics: I2C-bus[5]
fSCL
tBUF
SCL clock frequency
-
-
-
400 kHz
bus free time between a STOP and START
condition
1.3
-
s
tHD;STA
tSU;STA
tVD;ACK
tLOW
tHIGH
tf
hold time (repeated) START condition
set-up time for a repeated START condition
data valid acknowledge time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time
0.6
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
s
s
s
s
s
s
s
-
0.9
-
1.3
0.6
-
-
of both SDA and SCL signals
of both SDA and SCL signals
0.3
0.3
tr
rise time
-
Cb
capacitive load for each bus line
data set-up time
-
400 pF
tSU;DAT
tHD;DAT
tSU;STO
tSP
200
0
-
ns
ns
s
ns
data hold time
-
set-up time for STOP condition
0.6
-
-
pulse width of spikes that must be
suppressed by the input filter
50
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] For the respective frame frequency ffr, see Table 12.
[3] For the characteristics of VDD at a fixed temperature or of the temperature at a fixed VDD, see Figure 26 and Figure 27.
[4] For fclk(ext) > 4 kHz, it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor
should be between 100 k and 1 M.
[5] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD
.
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LCD driver for low multiplex rates
001aak109
1860
f
clk
(Hz)
1820
1780
1740
1700
1
2
3
4
5
6
V
(V)
DD
Tamb = 30 C.
Fig 26. Typical clock frequency (fclk) with respect to VDD
013aaa395
95
f
fr
(Hz)
max
typ
15 %
15 %
85
10 %
10 %
15 %
15 %
75
65
55
min
−60
−40
−20
0
20
40
60
80
Temperature (°C)
100
Condition: VDD = 5 V 0.5 V; frame-frequency-prescaler = 011; 75 Hz typical.
The frame frequency is derived from the internal or external clock frequency by Equation 1.
Fig 27. Frame frequency variation
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LCD driver for low multiplex rates
1 / f
CLK
t
t
clk(L)
clk(H)
0.7 V
0.3 V
DD
DD
CLK
0.7 V
0.3 V
DD
DD
SYNC
t
PD(SYNC_N)
t
SYNC_NL
0.5 V
BP0 to BP3,
and S0 to S159
(V
= 5 V)
DD
0.5 V
t
001aah848
PD(drv)
Fig 28. Driver timing waveforms
t
t
t
SU;DAT
f
r
70 %
30 %
70 %
30 %
SDA
SCL
cont.
cont.
t
t
HD;DAT
VD;ACK
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
013aaa110
Fig 29. I2C-bus timing waveforms when SDA and SDAACK are connected
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14. Application information
14.1 Pull-up resistor sizing on I2C-bus
14.1.1 Max value of pull-up resistor
The bus capacitance (Cb) is the total capacitance of wire, connections, and pins. This
capacitance on pin SDA limits the maximum value of the pull-up resistor (RPU) due to the
specified rise time.
According to the I2C-bus specification the rise time (tr) is defined between the VDD-related
input threshold of VIL = 0.3VDD and VIH = 0.7VDD. The value for tr(max) is 300 ns.
tr is calculated with Equation 7:
tr = t2 – t1
(7)
whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are
derivatives of the functions V(t1) and V(t2):
C
Vt1 = 0.3VDD = VDD1 – e-t1 R b
(8)
(9)
PU
C
Vt2 = 0.7VDD = VDD1 – e-t2 R b
PU
with the results of
t1 = –RPUCb ln(0.7)
(10)
(11)
(12)
t2 = –RPUCb ln(0.3)
tr = –RPUCb ln(0.3) + RPUCb ln(0.7)
R
PU(max) is a function of the rise time (tr) and the bus capacitance (Cb) and is calculated
with Equation 13:
300 10–9
tr
---------------------- -------------------------
RPUmax
=
=
(13)
0.8473Cb 0.8473Cb
14.1.2 Min value of pull-up resistor
The supply voltage limits the minimum value of resistor RPU due to the specified minimum
sink current (see value of IOL on pin SDAACK in Table 21 on page 35). RPU(min) as a
function of VDD is calculated with Equation 14:
VDD – VOL
--------------------------
RPUmin
=
(14)
IOL
The designer now has the minimum and maximum value of RPU. The values for RPU(max)
and RPU(min) are shown in Figure 30 and Figure 31.
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
41 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
001aak441
6
R
PU(max)
(kΩ)
5
4
3
2
1
0
20
60
100
140
180
220
260
300
340
380
420
460
500
(pF)
C
b
Fig 30. Values for RPU(max)
001aak440
6
R
PU(min)
(kΩ)
5
4
3
2
1
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
6
(V)
DD
Fig 31. Values for RPU(min)
14.2 ITO track resistance
If an application requires to have a low VDD supply voltage compared to the VLCD supply
voltage, it is recommended to increase the ITO resistance on the VLCD supply track in
order to reduce the noise induced on the VSS line when display is enabled. A low VDD
voltage supply and noise peaks on VSS induced by display activities may introduce
disturbances into the I2C communication with the microcontroller.
Figure 32 shows that, when the ITO resistance of the VSS pin has a certain value, it is
indicated to have a higher ITO resistance on the VLCD track, especially if VLCD (for
example, 9 V) is sharply higher than VDD (for example, 1.8 V). With a higher ITO
resistance on the VLCD track, the noise spikes induced to the VSS of the PCF85132 are
getting smaller and the functionality is less affected.
PCF85132
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Product data sheet
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42 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
DDDꢀꢁꢁꢂꢃꢃꢆ
ꢅꢆ
ꢋ
9
/&'
ꢃꢇꢄ
ꢃ9ꢄ
ꢃꢀꢄ
ꢃꢅꢄ
ꢉ
RSHUDWLQJꢂUDQJHꢂRIꢂꢂ
3&)ꢋꢈꢅꢇꢀ
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ꢆ
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ꢀꢏꢇ
ꢀꢏꢌ
ꢇꢏꢁ
ꢇꢏꢌ
ꢁꢏꢁ
ꢈꢏꢆ
ꢈꢏꢈ
ꢂꢃ9ꢄ
ꢉꢏꢆ
9
''
Tamb = 25 C; RITO(VSS) = 25 ; RITO(VDD) = 50 .
RITO(VLCD) = 50 .
(1)
(2) RITO(VLCD) = 100 .
(3) RITO(VLCD) = 150 .
a. Operating range of the PCF85132 with RITO(VSS) = 25
DDDꢀꢁꢁꢂꢃꢃꢇ
ꢅꢆ
9
/&'
ꢃꢉꢄ
ꢃꢈꢄ
ꢃꢁꢄ
ꢃꢇꢄ
ꢃꢅꢄ
ꢃ9ꢄ
ꢃꢀꢄ
ꢋ
ꢉ
ꢁ
ꢀ
ꢆ
RSHUDWLQJꢂUDQJHꢂRIꢂꢂ
3&)ꢋꢈꢅꢇꢀ
ꢅꢏꢋ
ꢀꢏꢇ
ꢀꢏꢌ
ꢇꢏꢁ
ꢇꢏꢌ
ꢁꢏꢁ
ꢈꢏꢆ
ꢈꢏꢈ
ꢂꢃ9ꢄ
ꢉꢏꢆ
9
''
Tamb = 25 C; RITO(VSS) = 50 ; RITO(VDD) = 50 .
(1) RITO(VLCD) = 50 .
(2) ITO(VLCD) = 75 .
R
(3) RITO(VLCD) = 100 .
(4) RITO(VLCD) = 150 .
(5)
RITO(VLCD) = 200 .
(6) RITO(VLCD) = 300 .
b. Operating range of the PCF85132 with RITO(VSS) = 50
Fig 32. Operating range of the PCF85132 with respect to the ITO track resistance
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
43 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
14.3 SDA and SDAACK configuration
The Serial DAta line (SDA) and the I2C-bus acknowledge line (SDAACK) are split. Both
lines can be connected together to facilitate a single-line SDA.
SDA
SDA
SDAACK
SDAACK
two wire mode
single wire mode
013aaa111
Fig 33. SDA, SDAACK configurations
14.4 Cascaded operation
In large display configurations, up to 8 PCF85132 can be distinguished on the same
I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable
I2C-bus slave address (SA0).
Table 23. Addressing cascaded PCF85132
Cluster
Bit SA0
Pin A1
Pin A0
Device
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
1
When cascaded PCF85132 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF85132 of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see Figure 34
on page 46).
For display sizes that are not multiple of 640 elements, a mixed cascaded system can be
considered containing only devices like PCF85132 and PCA85133. Depending on the
application, one must take care of the software commands compatibility and pin
connection compatibility.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85132. This synchronization is guaranteed after the Power-On Reset (POR). The
only time that SYNC is likely to be needed is if synchronization is accidentally lost (for
example, by noise in adverse electrical environments, or by the definition of a multiplex
mode when PCF85132 with different SA0 levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an open-drain driver with an
internal pull-up resistor. A PCF85132 asserts the SYNC line at the onset of its last active
backplane signal and monitors the SYNC line at all other times. Should synchronization in
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
44 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
the cascade be lost, it is restored by the first PCF85132 to assert SYNC. The timing
relationship between the backplane waveforms and the SYNC signal for the various drive
modes of the PCF85132 are shown in Figure 36 on page 48.
When using an external clock signal with high frequencies (fclk(ext) > 4 kHz), it is
recommended to have an external pull-up resistor between pin SYNC and pin VDD (see
Table 22 on page 38). This resistor should be present even when no cascading
configuration is used! When using it in a cascaded configuration, care must be taken not
to route the SYNC signal to close to noisy signals.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high, the device is not able to synchronize properly. This is
particularly applicable to COG applications. Table 24 shows the limiting values for contact
resistance.
Table 24. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
2200
1200
3 to 5
6 to 8
In the cascaded applications, the OSC pin of the PCF85132 with subaddress 0 is
connected to VSS so that this device uses its internal clock to generate a clock signal at
the CLK pin. The other PCF85132 devices are having the OSC pin connected to VDD
,
meaning that these devices are ready to receive external clock, the signal being provided
by the device with subaddress 0.
If the master is providing the clock signal to the slave devices, care must be taken that the
sending of display enable or disable is received by both, the master and the slaves at the
same time. When the display is disabled, the output from pin CLK is disabled too. The
disconnection of the clock may result in a DC component for the display.
Alternatively, the schematic can be also constructed such that all the devices have OSC
pin connected to VDD and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
A configuration where SYNC is connected but all PCF85132 are using their internal clock
(OSC pin tied to VSS) should not be used and may lead to display artifacts!
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
45 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
V
DD
V
LCD
SDA
SCL
segments
PCF85132
SYNC
CLK
(2)
OSC
backplanes
(open-circuit)
A0
V
A1
SA0 V
SS
LCD PANEL
V
V
LCD
DD
t
r
R ≤
V
2C
B
DD
LCD
SDA
SCL
HOST
MICRO-
segments
PROCESSOR/
MICRO-
PCF85132
SYNC
(1)
backplanes
CONTROLLER
CLK
OSC
013aaa363
A0
A1
SA0 V
SS
V
SS
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 34. Cascaded configuration with two PCF85132 using the internal clock of the master
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
46 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
V
DD
V
LCD
SDA
SCL
segments
PCF85133
SYNC
CLK
(2)
OSC
backplanes
(open-circuit)
A0 A1 A2 SA0 V
SS
LCD PANEL
V
V
LCD
t
DD
r
R ≤
V
V
LCD
2C
DD
B
SDA
SCL
segments
HOST
MICRO-
CONTROLLER
PCF85132
SYNC
(1)
backplanes
CLK
OSC
013aaa364
A0
A1
SA0 V
SS
V
SS
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 35. Cascaded configuration with one PCF85132 and one PCF85133 using the internal
clock of the master
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
47 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
1
T
=
fr
f
fr
BP0
SYNC
(a) static drive mode
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode
BP2
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode
BP3
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode
001aaj498
Fig 36. Synchronization of the cascade for the various PCF85132 drive modes
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
48 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
15. Bare die outline
Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm
PCF85132U
X
D
166
61
+y
+x
E
0
C1
S1
0
Marking code: PC85132/232-1
167
197 1
60
Y
A
b
A
2
e
e
A
1
1
L
detail Y
detail X
0
1
2 mm
scale
Dimensions
(1)
(1)
(1)
(1)
(1)
(1)
(1)
L
Unit
max
A
A
A
b
D
E
e
e
1
1
2
0.018
mm nom 0.40 0.015 0.380 0.0338 6.5
min 0.012
1.16 0.054 0.2025 0.090
Note
1. Dimension not drawn to scale.
pcf85132_do
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-10-14
12-03-22
PCF85132U
Fig 37. Bare die outline of PCF85132
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
49 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Table 25. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 37.
Symbol
SDAACK
SDAACK
SDAACK
SDA
SDA
SDA
SCL
SCL
SCL
CLK
VDD
VDD
VDD
SYNC
OSC
T1
Bump
1
X (m)
1165.3
1111.3
1057.3
854.8
800.8
746.8
575.8
521.8
467.8
316.2
204.1
150.1
96.1
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
Symbol
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
BP0
BP2
BP1
BP3
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
Bump
100
101
102
103
104
105
106
107
108
109
110
111
X (m)
750.2
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
2
696.2
3
642.2
4
588.2
5
534.2
6
480.2
7
426.2
8
372.2
9
318.2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
264.2
210.2
156.2
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
86.8
6.9
32.8
119.4
21.2
203.1
75.2
T2
286.8
190.7
244.7
298.7
352.7
406.7
460.7
514.7
568.7
622.7
676.7
730.7
784.7
838.7
892.7
946.7
1000.7
1054.7
1108.7
1224.2
1278.2
1332.2
1386.2
1440.2
T3
389.9
T3
443.9
T3
497.9
A0
640.5
A1
724.2
SA0
VSS
807.9
893.0
VSS
947.0
VSS
1001.0
1107.2
1161.2
1215.2
1303.4
1357.4
1411.4
1465.4
1519.4
1573.4
1627.4
1681.4
1735.4
1789.4
VLCD
VLCD
VLCD
BP2
BP0
S0
S1
S2
S3
S4
S5
S6
S7
PCF85132
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Product data sheet
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50 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Table 25. Bump locations …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 37.
Symbol
S8
Bump
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
X (m)
1843.4
1897.4
1951.4
2005.4
2059.4
2113.4
2167.4
2221.4
2363.9
2417.9
2471.9
2525.9
2579.9
2633.9
2687.9
2741.9
2795.9
2849.9
2903.9
2957.9
3011.9
3067.7
3013.7
2959.7
2905.7
2851.7
2797.7
2743.7
2689.7
2635.7
2520.2
2466.2
2412.2
2358.2
2304.2
2250.2
2196.2
2142.2
2088.2
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
Symbol
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
Bump
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
X (m)
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
1494.2
1548.2
1602.2
1656.2
1710.2
1764.2
1818.2
1872.2
1926.2
1980.2
2034.2
2088.2
2142.2
2284.7
2338.7
2392.7
2446.7
2500.7
2554.7
2608.7
2662.7
2716.7
2770.7
2824.7
2878.7
2932.7
2986.7
3040.7
3025.2
2971.2
2917.2
2863.2
2809.2
2755.2
2701.2
2647.2
2593.2
2539.2
2485.2
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
PCF85132
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Product data sheet
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51 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Table 25. Bump locations …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 37.
Symbol
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
Bump
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
X (m)
2034.2
1891.7
1837.7
1783.7
1729.7
1675.7
1621.7
1567.7
1513.7
1459.7
1405.7
1351.7
1297.7
1243.7
1189.7
1135.7
1081.7
1027.7
973.7
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
Symbol
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
BP3
Bump
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
X (m)
Y (m)
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
481.5
2431.2
2377.2
2234.7
2180.7
2126.7
2072.7
2018.7
1964.7
1910.7
1856.7
1802.7
1748.7
1694.7
1640.7
1586.7
1532.7
1478.7
1424.7
1370.7
1316.7
858.2
BP1
804.2
The dummy pins are connected to the pins shown (see Table 26) but are not tested.
Table 26. Dummy bumps
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 37 on page 49.
Symbol
D1
Connected to pin
X (m)
3079.2
3065.9
3121.7
3094.7
Y (m)
481.5
481.5
481.5
S131
S28
D2
D3
S29
D4
S130
481.5
PCF85132
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
The alignment marks are shown in Table 27.
a
a
a
a
3
a
1
2
b
b
b
1
2
3
b
b
REF
REF
S1
C1
013aaa680
Fig 38. Alignment marks
Table 27. Alignment marks
All x/y coordinates represent the position of the REF point (see Figure 38) with respect to the center
(x/y = 0) of the chip; see Figure 37 on page 49.
a
a1
a2
a3
b
b1
b2
b3
Coordinates
Unit
X
Y
Alignment mark S1
121.5
-
-
-
121.5
-
-
-
2733.75 47.25 m
Alignment mark C1
121.5 36.45 48.6
36.45 121.5 36.45 48.6
36.45 2603.7
47.25 m
PCF85132
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
16. Packing information
16.1 Tray information
-
$
+
%
$
$
[ꢏꢅ
ꢅꢏꢅ
;
GLH
.
)
(
GHWDLOꢂ;
'
ꢅꢏ\
\
*
)
[
(
&
1
/
0
6(&7,21ꢀ$ꢁ$
<
GHWDLOꢂ<
'LPHQVLRQVꢂLQꢂPP
DDDꢀꢁꢁꢈꢈꢂꢄ
Fig 39. Tray details
Table 28. Description of tray details
Tray details are shown in Figure 39.
Tray details
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
O
Unit
mm
8.50
2.40
6.596 1.259 50.8
45.72 34.0
5.0
8.40
40.80 3.96
2.18
2.49
0.5
Number of pockets
x direction
5
y direction
18
PCF85132
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Product data sheet
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54 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
marking code
001aaj643
Fig 40. Tray alignment
17. Abbreviations
Table 29. Abbreviations
Acronym
COG
DC
Description
Chip-On-Glass
Direct Current
HBM
Human Body Model
Integrated Circuit
Inter-Integrated Circuit
Indium Tin Oxide
Liquid Crystal Display
Least Significant Bit
Machine Model
IC
I2C
ITO
LCD
LSB
MM
MSB
POR
RC
Most Significant Bit
Power-On Reset
Resistance and Capacitance
Random Access Memory
Root Mean Square
Serial CLock line
Serial DAta line
RAM
RMS
SCL
SDA
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Product data sheet
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
18. References
[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2] AN10706 — Handling bare die
[3] AN11267 — EMC and system level ESD design guidelines for LCD drivers
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8] JESD78 — IC Latch-Up Test
[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] UM10204 — I2C-bus specification and user manual
[11] UM10569 — Store and transport requirements
PCF85132
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Product data sheet
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56 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
19. Revision history
Table 30. Revision history
Document ID
PCF85132 v.3
Modifications:
PCF85132 v.2
PCF85132 v.1
Release date
20130715
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF85132 v.2
• Changed tray information (Section 16.1)
20120905
Product data sheet
-
-
PCF85132 v.1
-
20101123
Product data sheet
PCF85132
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PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
20.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
58 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
59 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
22. Tables
Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 5. Definition of PCF85132 commands . . . . . . . . . .6
Table 6. Mode-set - command bit description . . . . . . . . .6
Table 7. Load-data-pointer-MSB - command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 8. Load-data-pointer-LSB - command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 9. Device-select - command bit description . . . . . .7
Table 10. Bank-select - command bit description . . . . . . .8
Table 11. Blink-select - command bit description . . . . . . .8
Table 12. Frequency-ctrl - command bit description . . . .10
Table 13. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .11
Table 14. Selection of possible display configurations . . .12
Table 15. Biasing characteristics . . . . . . . . . . . . . . . . . . .13
Table 16. Standard RAM filling in 1:3 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 17. Entire RAM filling by rewriting
in 1:3 multiplex drive mode. . . . . . . . . . . . . . . .25
Table 18. I2C slave address byte . . . . . . . . . . . . . . . . . . .30
Table 19. Control byte description . . . . . . . . . . . . . . . . . .31
Table 20. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 21. Static characteristics . . . . . . . . . . . . . . . . . . . .35
Table 22. Dynamic characteristics . . . . . . . . . . . . . . . . . .38
Table 23. Addressing cascaded PCF85132 . . . . . . . . . .44
Table 24. SYNC contact resistance . . . . . . . . . . . . . . . . .45
Table 25. Bump locations . . . . . . . . . . . . . . . . . . . . . . . .50
Table 26. Dummy bumps . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 27. Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .53
Table 28. Description of tray details . . . . . . . . . . . . . . . . .54
Table 29. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 30. Revision history . . . . . . . . . . . . . . . . . . . . . . . .57
PCF85132
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Product data sheet
Rev. 3 — 15 July 2013
60 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
23. Figures
Fig 1. Block diagram of PCF85132 . . . . . . . . . . . . . . . . .3
Fig 2. Pinning diagram of PCF85132. . . . . . . . . . . . . . . .4
Fig 3. Frequency generation of the PCF85132 . . . . . . . .9
Fig 4. Example of displays suitable for PCF85132 . . . .12
Fig 5. Typical system configuration . . . . . . . . . . . . . . . .12
Fig 6. Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .15
Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .16
Fig 8. Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 9. Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Fig 10. Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 11. Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 12. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .22
Fig 13. Relationships between LCD layout, drive mode,
display RAM filling order, and display data
transmitted over the I2C-bus . . . . . . . . . . . . . . . .23
Fig 14. RAM banks in static and multiplex driving
mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 15. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Fig 16. Example of the Bank-select command with
multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .27
Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Fig 18. Definition of START and STOP conditions. . . . . .29
Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .29
Fig 20. Acknowledgement on the I2C-bus . . . . . . . . . . . .30
Fig 21. I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .31
Fig 22. Control byte format . . . . . . . . . . . . . . . . . . . . . . .32
Fig 23. Device protection diagram. . . . . . . . . . . . . . . . . .33
Fig 24. IDD with respect to VDD . . . . . . . . . . . . . . . . . . . .36
Fig 25. IDD(LCD) with respect to VLCD . . . . . . . . . . . . . . . .37
Fig 26. Typical clock frequency (fclk) with respect
to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fig 27. Frame frequency variation. . . . . . . . . . . . . . . . . .39
Fig 28. Driver timing waveforms . . . . . . . . . . . . . . . . . . .40
Fig 29. I2C-bus timing waveforms when SDA and
SDAACK are connected . . . . . . . . . . . . . . . . . . .40
Fig 30. Values for RPU(max). . . . . . . . . . . . . . . . . . . . . . . .42
Fig 31. Values for RPU(min) . . . . . . . . . . . . . . . . . . . . . . . .42
Fig 32. Operating range of the PCF85132 with
respect to the ITO track resistance . . . . . . . . . . .43
Fig 33. SDA, SDAACK configurations . . . . . . . . . . . . . . .44
Fig 34. Cascaded configuration with two PCF85132
using the internal clock of the master . . . . . . . . .46
Fig 35. Cascaded configuration with one PCF85132
and one PCF85133 using the internal clock of the
master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Fig 36. Synchronization of the cascade for the various
PCF85132 drive modes . . . . . . . . . . . . . . . . . . . .48
Fig 37. Bare die outline of PCF85132 . . . . . . . . . . . . . . .49
Fig 38. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . .53
Fig 39. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Fig 40. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .55
PCF85132
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 15 July 2013
61 of 62
PCF85132
NXP Semiconductors
LCD driver for low multiplex rates
24. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
8.1
8.1.1
8.2
8.3
8.4
8.5
8.6
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
START and STOP conditions. . . . . . . . . . . . . 28
System configuration . . . . . . . . . . . . . . . . . . . 29
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 30
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 30
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
9
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 33
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34
Static characteristics . . . . . . . . . . . . . . . . . . . 35
Dynamic characteristics. . . . . . . . . . . . . . . . . 38
10
11
12
13
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 6
Commands of PCF85132. . . . . . . . . . . . . . . . . 6
Command: mode-set . . . . . . . . . . . . . . . . . . . . 6
Command: load-data-pointer . . . . . . . . . . . . . . 7
Command: device-select . . . . . . . . . . . . . . . . . 7
Command: bank-select. . . . . . . . . . . . . . . . . . . 8
Command: blink-select. . . . . . . . . . . . . . . . . . . 8
Clock frequency and timing . . . . . . . . . . . . . . . 8
Clock source selection . . . . . . . . . . . . . . . . . . . 8
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Frame frequency . . . . . . . . . . . . . . . . . . . . . . 10
Command: frequency-ctrl . . . . . . . . . . . . . . . . 10
Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 11
Possible display configurations . . . . . . . . . . . 11
LCD bias generator . . . . . . . . . . . . . . . . . . . . 13
Display register. . . . . . . . . . . . . . . . . . . . . . . . 13
LCD voltage selector . . . . . . . . . . . . . . . . . . . 13
Electro-optical performance . . . . . . . . . . . . . . 14
LCD drive mode waveforms . . . . . . . . . . . . . . 16
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 16
1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 17
1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 19
1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 20
Backplane and segment outputs . . . . . . . . . . 21
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 21
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 21
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Subaddress counter . . . . . . . . . . . . . . . . . . . . 24
RAM writing in 1:3 multiplex drive mode. . . . . 25
Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 25
Output bank selector . . . . . . . . . . . . . . . . . . . 25
Input bank selector . . . . . . . . . . . . . . . . . . . . . 26
RAM bank switching. . . . . . . . . . . . . . . . . . . . 26
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.6.1
7.1.6.2
7.1.6.3
7.1.6.4
7.1.6.5
7.1.6.6
7.2
14
Application information . . . . . . . . . . . . . . . . . 41
Pull-up resistor sizing on I2C-bus. . . . . . . . . . 41
Max value of pull-up resistor . . . . . . . . . . . . . 41
Min value of pull-up resistor. . . . . . . . . . . . . . 41
ITO track resistance. . . . . . . . . . . . . . . . . . . . 42
SDA and SDAACK configuration . . . . . . . . . . 44
Cascaded operation. . . . . . . . . . . . . . . . . . . . 44
14.1
14.1.1
14.1.2
14.2
14.3
14.4
15
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 49
Packing information . . . . . . . . . . . . . . . . . . . . 54
Tray information . . . . . . . . . . . . . . . . . . . . . . . 54
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 55
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision history . . . . . . . . . . . . . . . . . . . . . . . 57
16
16.1
17
18
7.3
19
7.3.1
7.3.2
7.3.3
7.3.3.1
7.3.4
7.3.4.1
7.3.4.2
7.3.4.3
7.3.4.4
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 58
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 58
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 59
20.1
20.2
20.3
20.4
21
22
23
24
Contact information . . . . . . . . . . . . . . . . . . . . 59
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8
Characteristics of the I2C-bus . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 July 2013
Document identifier: PCF85132
相关型号:
PCF85134HL/1,118
PCF85134 - Universal 60 x 4 LCD segment driver for multiplex rates up to 1:4 QFP 80-Pin
NXP
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