PCF8536AT/1,118_技术文档

PCF8536

Universal LCD driver for low multiplex rates including a 6

channel PWM generator

Rev. 2 — 21 February 2012

Product data sheet

1. General description

The PCF8536 is a peripheral device which interfaces to almost any Liquid Crystal Display

(LCD)¹with low multiplex rates. It generates the drive signals for any multiplexed LCD

containing up to eight backplanes, up to 44 segments, and up to 320 elements. The

PCF8536 is compatible with most microcontrollers and communicates via the two-line

bidirectional I²C-bus (PCF8536AT) or a three line unidirectional SPI-bus (PCF8536BT).

Communication overheads are minimized using a display RAM with auto-incremented

addressing.

The PCF8536 features an on-chip PWM controller for LED illumination. Up to six

independent channels can be configured. Each channel has 128 levels allowing the

possibility for two RGB controllers. Each of them provides over 2 million colors. Each

channel can also be used for static drive.

2. Features and benefits

 Single-chip 320 segment LCD controller and driver with 6 channel PWM generator

 6 channel PWM generator for backlight LED illumination

 Selectable display bias configuration

 Wide range for digital power supply: from 1.8 V to 5.5 V

 Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high

threshold twisted nematic LCDs

 Low power consumption

 Selectable backplane drive configuration: 4, 6, or 8 backplane multiplexing

 LCD and logic supplies may be separated

 320-bit RAM for display data storage

 6 PWM outputs with a 7-bit resolution (128 steps) and drivers for external transistors

 Programmable PWM frame frequency to avoid LCD backlight flickering

 400 kHz I²C-bus interface (PCF8536AT)

 5 MHz SPI-bus interface (PCF8536BT)

 Programmable frame frequency in the range of 60 Hz to 300 Hz in steps of 10 Hz;

factory calibrated

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

 320 segments driven allowing:

 up to 40 7-segment alphanumeric characters

 up to 20 14-segment alphanumeric characters

 any graphics of up to 320 elements

 Manufactured in silicon gate CMOS process

3. Applications

 White goods and consumer products

4. Ordering information

Table 1.

Ordering information

Type number

Interface Package

type

Name

Description

Version

PCF8536AT/1

PCF8536BT/1

I²C-bus

TSSOP56 plastic thin shrink small outline

package; 56 leads; body width 6.1 mm

SOT364-1

SPI-bus

TSSOP56 plastic thin shrink small outline

package; 56 leads; body width 6.1 mm

SOT364-1

5. Marking

Table 2.

Marking codes

Type number

PCF8536AT/1

PCF8536BT/1

Marking code

PCF8536AT

PCF8536BT

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

2 of 74

PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

6. Block diagram

S0/GP0 to

S5/GP5

BP4 to BP7/

S40 to S43

V

BP0 to BP3

S6 to S39

DD

V

LCD

GPO/PWM

GENERATOR

BACKPLANE

OUTPUTS

DISPLAY SEGMENT

OUTPUTS

LCD

VOLTAGE

SELECTOR

DISPLAY REGISTER

LCD BIAS

GENERATOR

V

SS

DISPLAY RAM

AND

PWM REGISTERS

OSCILLATOR

AND CLOCK

SELECTION

PCF8536AT

PRESCALER

AND TIMING

OSCCLK

RESET

DATA POINTER,

AUTO INCREMENT

COMMAND

DECODER

WRITE DATA

CONTROL

POWER-ON

RESET

2

SCL

SDA

I C-BUS

INPUT

FILTERS

CONTROLLER

013aaa419

A0

Fig 1. Block diagram of PCF8536AT

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

S0/GP0 to

S5/GP5

BP4 to BP7/

S40 to S43

V

BP0 to BP3

S6 to S39

DD

V

LCD

GPO/PWM

GENERATOR

BACKPLANE

OUTPUTS

DISPLAY SEGMENT

OUTPUTS

LCD

VOLTAGE

SELECTOR

DISPLAY REGISTER

LCD BIAS

GENERATOR

V

SS

DISPLAY RAM

AND

PWM REGISTERS

OSCILLATOR

AND CLOCK

SELECTION

PCF8536BT

PRESCALER

AND TIMING

OSCCLK

RESET

DATA POINTER,

AUTO INCREMENT

COMMAND

DECODER

WRITE DATA

CONTROL

POWER-ON

RESET

SCL

SDI

SPI-BUS

CONTROLLER

013aaa429

CE

Fig 2. Block diagram of PCF8536BT

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

7.2 Pin description

Table 3.

Pin description of PCF8536AT and PCF8536BT

Symbol

Type

Description

1 to 11

S9 to S19

output

input

LCD segment

20 to 31 S20 to S31

LCD segment

43

44

45

46

RESET

V_SS

active LOW reset input

ground supply voltage

supply voltage

supply

V_DD

OSCCLK

input/output external clock input/internal oscillator

output

[1]

47

V_LCD

supply

output

LCD supply voltage

48 to 53 S0/GP0 to S5/GP5

LCD segment/GPO (PWM) output

54 to 56 S6 to S8

LCD segment

Pin layout depending on backplane swap configuration^[2]

BPS = 0

BP0

BPS = 1^[3]

12

13

14

15

16

17

18

19

32

33

34

35

36

37

38

39

S32

output

LCD backplane/LCD segment

BP1

S33

BP2

S34

BP3

S35

BP4/S43

BP5/S42

BP6/S41

BP7/S40

S32

S36

S37

S38

S39

BP7/S40

BP6/S41

BP5/S42

BP4/S43

BP3

S33

S34

S35

S36

S37

BP2

S38

BP1

S39

BP0

Pin layout depending on product and bus type

PCF8536AT PCF8536BT

40

41

42

A0

input

I²C-bus slave address selection

SPI-bus chip enable - active LOW

I²C-bus serial clock

CE

SCL

SDA

SCL

SDI

SPI-bus serial clock

input/output I²C-bus serial data

input

.

SPI-bus data input

[1] V_LCDmust be equal to or greater than V_DD

[2] Effect of backplane swapping is illustrated in Figure 5 on page 10.

[3] Bit BPS is explained in Section 8.1.4 on page 9.

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

6 of 74

PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8. Functional description

The PCF8536 is a versatile peripheral device designed to interface any microcontroller to

a wide variety of LCDs and 6 backlight LEDs. It can directly drive any multiplexed LCD

containing up to eight backplanes and up to 44 segments.

8.1 Commands of PCF8536

The PCF8536 is controlled by 15 commands, which are defined in Table 4. Any other

combinations of operation code bits that are not mentioned in this document may lead to

undesired operation modes of PCF8536.

Table 4.

Commands of PCF8536

Command name

Register

selection

RS[1:0]^[1]

Bits

7

Reference

6

5

4

3

2

1

0

initialize

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Section 8.1.1

Section 8.1.2

OTP-refresh

1

0

PWM-inversion

mode-settings

oscillator-control

GPO-output-config

0

1

0

1

0

PWMI Section 8.1.3

0

1

BPS

1

INV

EFR

PD

COE

E

Section 8.1.4

Section 8.1.5

Section 8.1.6

OSC

0

1

0

GPM1[1:0]

GPM3[1:0]

GPM5[1:0]

GPM0[1:0]

GPM2[1:0]

GPM4[1:0]

M[1:0]

1

0

1

0

set-MUX-mode

0

1

Section 8.1.7

Section 8.1.8

Section 8.1.9

Section 8.1.10

set-bias-mode

0

B[1:0]

frame-frequency-LCD

frame-frequency-PWM

GPO-static-data

0

1

FD[4:0]

0

FP[3:0]

0

1

0

1

GPO2 GPO1 GPO0 Section 8.1.11

GPO5 GPO4 GPO3

0

1

load-data-pointer-LCD

load-data-pointer-PWM

write-RAM-data

1

DP[5:0]

1

Section 8.1.12

0

1

0

PP[2:0]

Section 8.1.13

Section 8.1.14

Section 8.1.15

D[7:0]

0

write-PWM-data

P[6:0]

[1] Information about control byte and register selection see Section 9.1 on page 46.

8.1.1 Command: initialize

This command generates a chip-wide reset. It has the same function as the RESET pin.

Reset takes 1 ms to complete.

Table 5.

Bit

Initialize - initialize command bit description

Symbol

Value

Description

fixed value

7 to 0

-

00010110

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.1.2 Command: OTP-refresh

During production and testing of the device, each IC is calibrated to achieve the specified

accuracy of the frame frequency. This calibration is performed on EPROM cells called

One Time Programmable (OTP) cells. The device reads these cells every time the

OTP-refresh command is sent. This instruction has to be sent after a reset has been

made and before the display is enabled.

This command will be completed after a maximum of 30 ms and requires either the

internal or external clock to run. If the internal oscillator is not used, then a clock must be

supplied to the OSCCLK pin. If the OTP-refresh instruction is sent and no clock is present,

then the request is stored until a clock is available.

Remark: It is recommended not to enter power-down mode during the OTP refresh cycle.

Table 6.

Bit

OTP-refresh - OTP-refresh command bit description

Symbol

Value

Description

7 to 0

-

11110000

fixed value

8.1.3 Command: PWM-inversion

It is possible to invert the output of the PWM generators. This function may be useful for

counteracting EMC issues. The description of this mode can be found in Section 8.11.2 on

page 45.

Table 7.

Bit

PWM-inversion - PWM inversion command bit description

Symbol

-

Value

Description

7 to 1

0

0001010

fixed value

PWMI

PWM inversion mode

PWM inversion mode on

PWM inversion mode off

1

0^[1]

[1] Default value.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.1.4 Command: mode-settings

Table 8.

Mode-settings - mode settings command bit description

Bit

7 to 4

3

Symbol

Value

Description

-

0101

fixed value

BPS

backplane swapping

0^[1]

1

backplane configuration 0

backplane configuration 1

set inversion mode

2

1

INV

PD

0^[1][2]

1

Driving scheme A: LCD line inversion mode

Driving scheme B: LCD frame inversion mode

set power mode

1

power-down mode; backplane and segment

outputs are connected to V_SSand the internal

oscillator is switched off

0^[1]

power-up mode

0

E

display switch

0^[1]

1

display disabled; backplane and segment

outputs are connected to V_SS

display enabled

[1] Default value.

[2] See Section 8.1.4.2.

8.1.4.1 Backplane swapping

Backplane swapping can be configured with the BPS bit (see Table 8). It moves the

location of the backplane and the associated segment outputs from one side of the

PCF8536 to the other. Backplane swapping is sometimes desirable to aid with the routing

of PCBs that do not use multiple layers.

The BPS bit has to be set to the required value before enabling the display. Failure to do

so does not damage the PCF8536 or the display, however unexpected display content

may appear.

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

BP0

BP1

S32

S33

S34

S35

S36

S37

S38

S39

S20

S21

S22

S23

S24

S25

S26

S27

S28

BP2

BP3

BP4/S43

BP5/S42

BP6/S41

BP7/S40

S20

39

38

37

36

35

34

33

32

31

30

29

39

38

37

36

35

34

33

32

31

30

29

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

BP0

BP1

BP2

S21

BP3

S22

BP4/S43

BP5/S42

BP6/S41

BP7/S40

S31

S23

S24

S25

S26

S27

S30

S28

S29

BPS = 1

BPS = 0

013aaa432

Fig 5. Effect of backplane swapping

8.1.4.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)

The DC offset of the voltage across the LCD is compensated over a certain period:

line-wise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode

(driving scheme B). With the INV bit (see Table 8), the compensation mode can be

switched.

In frame inversion mode, the DC value is compensated across two frames and not within

one frame. Changing the inversion mode to frame inversion reduces the power

consumption; therefore it is useful when power consumption is a key point in the

application.

Frame inversion may not be suitable for all applications. The RMS voltage across a

segment is better defined; however, since the switching frequency is reduced, there is

possibility for flicker to occur.

The waveforms of Figure 15 on page 29 to Figure 18 on page 32 are showing line

inversion mode. Figure 19 on page 33 shows an example of frame inversion.

8.1.4.3 Power-down mode

The power-down bit (PD) allows the PCF8536 to be put in a minimum power

configuration. In order to avoid display artefacts, it is recommended to enter power-down

only after the display has been switched off by setting bit E to logic 0.

During power-down, the internal oscillator is switched off and any selected PWM output is

revert to the static value stored in bits GPO0 to GPO5. These bits may be programmed to

give a static logic 0 or static logic 1 on selected GP0 to GP5 pins.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

Table 9.

Effect of the power-down bit (PD)

Effect on function

Mode settings

Effect of setting PD

0

1

backplane output

segment output

internal oscillator

OSCCLK pin

E = 1

normal function

on

V_SS

off

E = 1

OSC = 0, COE = 1

output of internal

V_DD

oscillator frequency

OSCCLK pin

OSC = 1

input clock

clock input, can be

logic 0, logic 1, or left

floating

GPO

static drive

PWM drive

static drive

PWM drive

static drive

With the following sequence, the PCF8536 can be set to a state of minimum power

consumption, called power-down mode.

START

Disable display

by setting bit E

logic 0

External clock

can be

removed now

Enable power-

down mode

with PD = 1

STOP

013aaa447

Fig 6. Recommended power-down sequence

Remarks:

• It is necessary to run the power-down sequence before removing the supplies.

Depending on the application, care must be taken that no other signals are present at

the chip input or output pins when removing the supplies (see Section 10). Otherwise

it may cause unwanted display artifacts. In case of an uncontrolled removal of supply

voltages, the PCF8536 will not be damaged.

• Static voltages across the liquid crystal display can build up when the external LCD

supply voltage (V_LCD) is on while the IC supply voltage is off, or vice versa. This may

cause unwanted display artifacts. To avoid such artifacts, V_LCDand V_DDmust be

applied or removed together.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

• A clock signal must always be supplied to the device when the display is active.

Removing the clock may freeze the LCD in a DC state, which is not suitable for the

liquid crystal. It is recommended to disable the display first and afterwards to remove

the clock signal.

8.1.4.4 Display enable

The display enable bit (E) is used to enable and disable the display. When the display is

disabled, all LCD outputs go to V_SS. This function is implemented to ensure that no

voltage can be induced on the LCD outputs as it may lead to unwanted displays of

segments.

Recommended start-up sequences are found in Section 8.2.3

Remarks:

• The state of display enable has no effect on the GPO outputs.

• Display enable is not synchronized to an LCD frame boundary. Therefore using this

function to flash a display for prolonged periods is not recommended due to the

possible build-up of DC voltages on the display.

8.1.5 Command: oscillator-control

The oscillator-control command switches between internal and external oscillator and

enables or disables the pin OSCCLK. It is also used to define what the external frequency

will be.

Table 10. Oscillator-control - oscillator control command bit description

Bit

7 to 3

2

Symbol

Value

Description

-

00011

fixed value

EFR

external clock frequency applied on pin

OSCCLK

0^[1]

1

9.6 kHz

230 kHz

1

0

COE

OSC

clock output enable for pin OSCCLK

0^[1]

1

clock signal not available on pin OSCCLK;

pin OSCCLK is in 3-state

clock signal available on pin OSCCLK

oscillator source

0^[1]

1

internal oscillator running

external oscillator used;

pin OSCCLK becomes an input;

used in combination with EFR to determine

input frequency

[1] Default value.

The bits OSC, COE, and EFR control the source and frequency of the clock used to

generate the LCD and PWM signals (see Figure 7). Valid combinations are shown in

Table 11.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

COE (1)

EFR (2)

0

OSCCLK

LCD waveform

generator

1

Programmable

divider

1

Internal oscillator

230 kHz

0

9.6 kHz (3)

LCD frame frequency

selection, q

OSC

0

1

Programmable

divider

PWM waveform

generator

PWM frame frequency

selection, p

013aaa448

(4)

(1) Can only be used with the internal oscillator (OSC = 0).

(2) Can only be used with an external oscillator (OSC = 1).

(3) Nominal value for divide factor q is 24; source clock is 230 kHz (see Section 8.1.9).

(4) PWM requires an external or internal 230 kHz clock.

Fig 7. Oscillator selection

Table 11. Valid combinations of bits OSC, EFR, and COE

OSC

COE

EFR

OSCCLK pin

Clock source

0

not used

inactive;

internal oscillator used

may be left floating

0

1

not used

output of internal oscillator

frequency (prescaler)

internal oscillator used

1

not used

0

1

9.6 kHz input

230 kHz input

OSCCLK pin

Table 12. Typical use of bits OSC, EFR, and COE

Usage

OSC

CDE

EFR

LCD and/or PWM with internal oscillator

LCD and PWM with external oscillator

LCD with external oscillator

0

1

0

not used

1

0

8.1.5.1 Oscillator

The internal logic and LCD drive signals of the PCF8536 are timed either by the built-in

oscillator or from an external clock.

Internal clock: When the internal oscillator is used, all LCD and PWM signals are

generated from it. The oscillator runs at nominal 230 kHz. The relationship between this

frequency and the LCD frame frequency is detailed in Section 8.1.9. The relationship

between this frequency and the PWM frame frequency is detailed in Section 8.1.10.

Control over the internal oscillator is made with the OSC bit (see Section 8.1.5). The

internal oscillator is also switched on or off under certain combinations of modes which

are described in Table 13.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

Table 13. Internal oscillator on/off table

PD

OSC

PWM

EFR

Internal

oscillator state^[1]

power-down

power-up

n.a.

off

internal oscillator n.a.

n.a.

on

external oscillator off

n.a.

off

on

9.6 kHz

230 kHz

on^[2]

off

[1] When RESET is active, the internal oscillator is off.

[2] Special case. The PWM generator needs 230 kHz and must be enabled when PWM is enabled.

It is possible to make the internal oscillator signal available on pin OSCCLK by using the

oscillator-control command (see Table 10) and configuring the clock output enable (COE)

bit. If not required, the pin OSCCLK should be left open or connected to V_SS. At power-on

the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state.

Clock output is only valid when using the internal oscillator. The signal will appear on the

OSCCLK pin.

An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this

clock varies with the chosen divide ratio.

Table 14. OSCCLK table

PD

OSC

n.a.

COE

off

EFR

OSCCLK pin^[1]

3-state^[2]

power-down

power-up

n.a.

on

n.a.

V_DD

internal oscillator off

on

n.a.

3-state

n.a.

9.6 kHz output^[3]

9.6 kHz input

230 kHz input

external oscillator n.a.

9.6 kHz

230 kHz

[1] When RESET is active, the pin OSCCLK is in 3-state.

[2] In this state, an external clock may be applied, but it is not a requirement.

[3] 9.6 kHz is the nominal frequency with q = 24, see Table 15.

External clock: In applications where an external clock must be applied to the PCF8536,

bit OSC (see Table 10) has to be set logic 1. In this case pin OSCCLK becomes an input.

The OSCCLK signal must switch between the V_SSand the V_DDvoltage supplied to the

chip.

The system is designed for a 230 kHz clock or alternatively for using a 9.6 kHz clock. The

EFR bit determines the external clock frequency. The clock frequency (f_clk(ext)) in turn

determines the LCD frame frequency, see Table 15.

The PWM generator requires a 230 kHz clock to operate. If PWM is enabled and an

external clock of 9.6 kHz is selected, then the internal oscillator will automatically start and

be used for the PWM signal generation.

PCF8536

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Product data sheet

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

Remark: If an external clock is used, then this clock signal must always be supplied to the

device when the display is on. Removing the clock may freeze the LCD in a DC state

which will damage the LCD material.

8.1.5.2 Timing and frame frequency

The timing of the PCF8536 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. The

timing also generates the LCD frame frequency which it derives as an integer division of

the clock frequency (see Table 15). The frame frequency is a fixed division of the internal

clock or of the frequency applied to pin OSCCLK when an external clock is used.

Table 15. LCD frame frequencies

Frame frequency

Typical external Nominal frame

EFR bit

Value of q^[1]

frequency (Hz)

9600

200

0

-

f_clkext

48

f_frLCD

=

-----------------

230000

200

1

24

f_clkext

-----------------

48  q

f_frLCD

[1] Other values of the frame frequency prescaler see Table 21.

When the internal clock is used, or an external clock with EFR = 1, the LCD frame

frequency can be programmed by software in steps of approximately 10 Hz in the range of

60 Hz to 300 Hz (see Table 21). Furthermore the internal oscillator is factory calibrated,

see Table 44 on page 59.

8.1.6 Command: GPO-output-config

The behavior of the combined LCD and GPO outputs S5/GP5 to S0/GP0 is configured

with the bits described in Table 16.

Table 16. GPO-output-config - output mode config command for S5/GP5 to S0/GP0

Bit

GPM0 and GPM1

7 to 4

Symbol

Value

Description

-

1100

fixed value

3 to 2 GPM1[1:0]

1 to 0 GPM0[1:0]

GPM2 and GPM3

see Table 17

output mode for S1/GP1

output mode for S0/GP0

7 to 4

-

1101

fixed value

3 to 2 GPM3[1:0]

1 to 0 GPM2[1:0]

GPM4 and GPM5

see Table 17

output mode for S3/GP3

output mode for S2/GP2

7 to 4

-

1110

fixed value

3 to 2 GPM5[1:0]

1 to 0 GPM4[1:0]

see Table 17

output mode for S5/GP5

output mode for S4/GP4

Each output can be individually configured to be either an LCD segment output, a PWM

output or a static general-purpose output (GPO), see Table 17.

Remark: Even if using GPO only, V_LCDmust still be applied to the device.

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Table 17. GPMO mode definition

GPM0[1:0] to GPM5[1:0]

00^[1], 01

Mode

LCD

Description

output is an LCD segment

output is static GPO

output is PWM GPO

10

static

PWM

11

[1] Default value.

8.1.7 Command: set-MUX-mode

The multiplex drive mode is configured with the bits described in Table 18.

Table 18. Set-MUX-mode - set multiplex drive mode command bit description

Bit

Symbol

Value

000000

00^[1], 01

10

Description

7 to 2

-

fixed value

1 to 0 M[1:0]

1:8 multiplex drive mode; eight backplanes

1:6 multiplex drive mode; 6 backplanes

1:4 multiplex drive mode; 4 backplanes

11

[1] Default value.

8.1.8 Command: set-bias-mode

The set-bias-mode command allows setting the bias level.

Table 19. Set-bias-mode - set bias mode command bit description

Bit

Symbol

Value

000001

00^[1]. 01

11

Description

fixed value

¹⁄₄bias

7 to 2

-

1 to 0 B[1:0]

¹⁄₃bias

10

¹⁄₂bias

[1] Default value.

8.1.9 Command: frame-frequency-LCD

With the frame-frequency-LCD command, the frame frequency for the display can be

configured. The clock frequency determines the frame frequency.

Table 20. Frame-frequency-LCD - frame frequency and output clock frequency command

bit description

Bit

Symbol

Value

Description

7 to 5

-

001

fixed value

4 to 0 FD[4:0]

see Table 21

frequency prescaler

The system is designed for a 230 kHz clock. It is either internally generated or externally

provided. Alternatively a 9.6 kHz clock signal can be provided as well. The EFR bit (see

Table 10) has to be set according to the external clock frequency.

When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1:

f_clkext

48

f_frLCD

=

(1)

-----------------

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When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation 2:

f_clkext

48  q

f_frLCD

=

(2)

-----------------

where q is the frequency divide factor (see Table 21).

Remark: f_clk(ext)is the external input clock frequency to pin OSCCLK.

When the internal oscillator is used, the intermediate frequency may be output on the

OSCCLK pin. Its frequency is given in Table 21.

Table 21. Frame frequency prescaler values for 230 kHz clock operation

FD[4:0]

Nominal LCD frame

frequency (Hz)^[1]

Divide factor, q

Intermediate clock

frequency (Hz)

00000

00001

00010

00011

00100

00101

00110

00111

59.9

80

68

60

53

48

44

40

37

34

32

30

28

27

25

24

23

22

21

20

19

18

17

16

2875

3382

3833

4340

4792

5227

5750

6216

6765

7188

7667

8214

8519

9200

9583

10000

10455

10952

11500

12105

12778

13529

14375

70.5

79.9

90.4

99.8

108.9

119.8

129.5

140.9

149.7

159.7

171.1

177.5

191.7

199.7

208.3

217.8

228.3

239.6

252.2

266.2

281.9

299.5

not used

01000

01001

01010

01011

01100

01101

01110^[2]

01111

10000

10001

10010

10011

10100

10101

10110

10111 to 11111

[1] Nominal frame frequency calculated for the default clock frequency of 230 kHz.

[2] Default value.

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8.1.10 Command: frame-frequency-PWM

With the frame-frequency-PWM command, the frame frequency for the PWM signal can

be set.

The PWM system requires a clock of 230 kHz either internally generated or externally

supplied. Using a slower clock may result in visible flickering of LEDs driven with the PWM

signal.

When EFR is set to 230 kHz, then the PWM frame frequency will be calculated with

Equation 3:

f_clkext

128  p

f_PWM

=

(3)

-----------------

where p is the frequency divide factor (see Table 23).

Table 22. Frame-frequency-PWM - PWM frame frequency command bit description

Bit

Symbol

Value

Description

7 to 4

-

0100

fixed value

3 to 0 FP[3:0]

see Table 23

frequency prescaler

Table 23. PWM frame frequency prescaler values for 230 kHz clock operation

FP[3:0]

0000

0001

0010

0011

0100

0101

0110

0111^[2]

1000

1001

1010

1011

1100

1101

1110

Nominal PWM frame frequency (Hz)^[1]

Divide factor, p

59.9

30

26

22

20

18

16

15

14

13

12

11

10

9

69.1

81.7

89.8

99.8

112.3

119.8

128.3

138.2

149.7

163.4

179.7

199.7

224.6

256.7

299.5

8

7

1111

6

[1] Nominal frame frequency calculated for the default clock frequency of 230 kHz.

[2] Default value.

In order to avoid flickering caused by the interaction of the backlight LED and the LCD

frame frequency, the PWM frame frequency should be programmed to be more than

50 Hz different from LCD frame frequency or multiples of the LCD frame frequency (see

Figure 8 and Table 49 on page 68).

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In general, the higher the PWM frame

frequency, the less flickering will be visible

Intensity of

visible flickering

Flickering is most

visible when f

PWM

and f

are within

fr(LCD)

10 Hz of each other

Flickering is also visible at multiples

of the fundamental frequency;

however, the visibility is lower

Flickering will not be

visible when f

PWM

and f

are more

fr(LCD)

than 50 Hz apart

f

2f

1

f

1

0

This will repeat for 3 , 4 , etc.

f1 f1

013aaa449

Where f₀= f_PWMand f₁= f_fr(LCD)or f₁= f_PWMand f₀= f_fr(LCD)

.

Fig 8. Flicker avoidance for LED backlighting

8.1.11 Command: GPO-static-data

When static GPOs are selected instead of PWM, then the value for the output is taken

from these register bits. The output is a static level.

Table 24. GPO-static-data - write GPO data for GP0 to GP5 command bit description

Bit

Symbol

Value

Description

GPO0 to GPO2

7 to 3

2

-

01100

0^[1]

1

fixed value

GPO2

0 level output on pin GP2

1 level output on pin GP2

0 level output on pin GP1

1 level output on pin GP1

0 level output on pin GP0

1 level output on pin GP0

1

0

GPO1

GPO0

0^[1]

1

0^[1]

1

GPO3 to GPO5

7 to 3

2

-

01101

0^[1]

1

fixed value

GPO5

0 level output on pin GP5

1 level output on pin GP5

0 level output on pin GP4

1 level output on pin GP4

0 level output on pin GP3

1 level output on pin GP3

1

0

GPO4

GPO3

0^[1]

1

0^[1]

1

[1] Default value.

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8.1.12 Command: load-data-pointer-LCD

The load-data-pointer-LCD command defines the start address of the display RAM. The

data pointer is auto incremented after each RAM write. The size of the display RAM is

dependent on the current multiplex drive mode setting, see Table 25.

Table 25. Load-data-pointer-LCD - load data pointer command bit description

Bit

Symbol

Value

Description

7 to 6

-

10

fixed value

Multiplex drive mode 1:8

5 to 0 DP[5:0]

000000^[1]to

100111

6-bit binary value of 0 to 39

6-bit binary value of 0 to 41

6-bit binary value of 0 to 43

Multiplex drive mode 1:6

5 to 0 DP[5:0]

000000^[1]to

101001

Multiplex drive mode 1:4

5 to 0 DP[5:0]

000000^[1]to

101011

[1] Default value.

Remark: Data pointer values outside of the valid range will be ignored and no RAM

content will be transferred until a valid data pointer value is set.

Filling of the display RAM is described in Section 8.9.

8.1.13 Command: load-data-pointer-PWM

The load-data-pointer-PWM command defines one of the 6 PWM addresses.

Table 26. Load-data-pointer-PWM - load data pointer command bit description

Bit

Symbol

Value

Description

7 to 3

-

01110

fixed value

2 to 0 PP[2:0]

[1] Default value.

000^[1]to 101

3-bit binary value of 0 to 5

Remark: Data pointer values outside of the valid range will be ignored and no PWM

content will be transferred until a valid data pointer value is set.

8.1.14 Command: write-RAM-data

This command will initiate the transfer of data to the display RAM. Data will be written into

the address defined by the load-data-pointer-LCD command. RAM filling is described in

Section 8.9.

Table 27. Write-RAM-data - write RAM data command bit description^[1]

Bit

Symbol

Value

Description

7 to 0 D[7:0]

00000000 to

11111111^[2]

writing data byte-wise to RAM

[1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 01, see Table 36 on

page 46.

[2] After Power-On Reset (POR), the RAM content is random and should be brought to a defined status by

writing meaningful content otherwise unexpected display content may appear.

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8.1.15 Command: write-PWM-data

This command will initiate the transfer of data to the PWM registers. Data will be written

into the address defined by the load-data-pointer-PWM command. PWM register filling is

described in Section 8.10

Table 28. Write-PWM-data - write PWM data command bit description^[1]

Bit

Symbol

Value

Description

7

-

0

fixed value

6 to 0 P[6:0]

0000000^[2]to writing data byte-wise to PWM registers

1111111

[1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 10, see Table 36 on

page 46.

[2] Default value. After Power-On Reset (POR) the PWM content is set to 0.

8.2 Start-up and shut-down

8.2.1 Reset and Power-On Reset (POR)

After a reset and at power-on the PCF8536 resets to starting conditions as follows:

1. The display is disabled.

2. All backplane outputs are set to V_SS

.

3. All segment outputs are set to V_SS

.

4. All GPO outputs are disabled.

5. Selected drive mode is: 1:8 with ¹⁄₄bias.

6. The data pointers are cleared (set logic 0).

7. PWM values are all reset to zero.

8. RAM data is not initialized. Its content can be considered to be random.

9. The internal oscillator is running; no clock signal is available on pin OSCCLK; pin

OSCCLK is in 3-state.

The reset state is as shown in Table 29.

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Table 29. Reset state

Reset state of configurable bits shown in the command table format for clarity.

Associated command Bits

7

6

5

4

3

2

1

0

PWM-inversion

mode-settings

PWMI = 0

E = 0

-

BPS = 0

-

INV = 0

EFR = 0

PD = 0

OSC = 0

oscillator-control

GPO-output-config

COE = 0

GPM1[1:0] = 00

GPM3[1:0] = 00

GPM5[1:0] = 00

GPM0[1:0] = 00

GPM2[1:0] = 00

GPM4[1:0] = 00

M[1:0] = 00

set-MUX-mode

-

set-bias-mode

B[1:0] = 00

frame-frequency-LCD

frame-frequency-PWM

GPO-static-data

FD[4:0] = 01110

-

FP[3:0] = 0111

-

GPO2 = 0 GPO1 = 0 GPO0 = 0

GPO5 = 0 GPO4 = 0 GPO3 = 0

load-data-pointer-LCD

load-data-pointer-PWM

DP[5:0] = 000000

-

PP[2:0] = 000

The first command sent to the device after the power-on event must be the initialize

command (see Section 8.1.1).

After Power-On Reset (POR) and before enabling the display, the RAM content should be

brought to a defined state by writing meaningful content (e.g. a graphic) otherwise

unwanted display artifacts may appear on the display.

8.2.2 RESET pin function

The RESET pin of the PCF8536 will reset all the registers to their default state. The reset

state is given in Table 29. The RAM contents will remain unchanged. After the reset signal

is removed, the PCF8536 will behave in the same manner as after Power-On Reset

(POR). See Section 8.2.1 for details.

8.2.3 Recommended start-up sequences

This chapter describes how to proceed with the initialization of the chip in different

application modes.

In general, the sequence should always be:

1. Power-on the device,

2. set the display and functional modes,

3. fill the display memory and then

4. turn on the display.

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START

Power-on V

DD

LCD

and V

together

If using GPO outputs, set

- GPO data

- PWM data

- PWM frame frequency

Toggle RESET

(1)

Send display

content

Wait minimum

1 ms

Enable

the display

Send

OTP-refresh

STOP

Set:

- mode settings: BPS and INV

- LCD/GPO output mode

- multiplex driver mode

- bias mode

013aaa452

- LCD frame frequency

(1) Alternatively, it is possible to send the initialize command.

Fig 9. Recommended start-up sequence when using the internal oscillator

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START

Power-on V

DD

LCD

and V

together

If using GPO outputs, set

- GPO data

- PWM data

- PWM frame frequency

Toggle RESET

(1)

Send display

content

Wait minimum

1 ms

External clock

must be

applied by now

External clock

can be applied

now

Enable

the display

Send

OTP-refresh

STOP

Set:

- Mode settings: BPS and INV

- Select external clock

- GPO output mode

013aaa453

- Multiplex driver mode

- Bias mode

- LCD frame frequency

(1) Alternatively, it is possible to send the initialize command.

Fig 10. Recommended start-up sequence when using an external clock signal

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8.3 Possible display configurations

The PCF8536 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 11). It

can drive multiplexed LCD with 4, 6, or 8 backplanes and up to 44 segments.

The display configurations possible with the PCF8536 depend on the number of active

backplane outputs required. A selection of possible display configurations is given in

Table 30.

dot matrix

7-segment with dot

14-segment with dot and accent

013aaa312

Fig 11. Example of displays suitable for PCF8536

Table 30. Selection of display configurations

Number of

Digits/Characters

7 segment^[1]14 segment^[2]

Dot matrix/

Elements

Backplanes

Segments

Icons

No GPO or PWM outputs enabled

8

6

4

40

42

44

320

252

176

40

31

22

20

15

11

320

252

176

With 6 GPO or PWM outputs enabled

8

6

4

34

36

38

272

216

152

34

27

19

17

13

9

272

216

152

[1] 7 segment display has 8 elements including the decimal point.

[2] 14 segment display has 16 elements including decimal point and accent dot.

All of the display configurations in Table 30 can be implemented in the typical systems

shown in Figure 12 and Figure 13.

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V

DD

t

r

R=

2C

b

40 to 44 segment

drives

V

DD

SDA

SCL

HOST

PROCESSOR/

MICRO-

LCD PANEL

(up to 320

elements)

PCF8536AT

4 to 8 backplanes

CONTROLLER

A0

V

SS

013aaa450

V

SS

Fig 12. Typical system configuration for the I²C-bus

V

DD

40 to 44 segment

drives

V

DD

SDI

SCL

CE

HOST

PROCESSOR/

MICRO-

LCD PANEL

(up to 320

elements)

PCF8536BT

4 to 8 backplanes

CONTROLLER

V

SS

013aaa451

V

SS

Fig 13. Typical system configuration for the SPI-bus

The host microcontroller maintains the two line I²C-bus or a three line SPI-bus

communication channel with the PCF8536. The appropriate biasing voltages for the

multiplexed LCD waveforms are generated internally. The only other connections required

to complete the system are the power supplies (V_DD, V_SS, V_LCD) and the LCD panel

selected for the application.

The minimum recommended values for external capacitors on V_DDand V_LCDare 100 nF

respectively. Decoupling of V_LCDwill help to reduce display artifacts. The decoupling

capacitors should be placed close to the IC with short connections to the respective

supply pin and V_SS

.

8.4 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

set-bias-mode command (see Table 19) and the set-MUX-mode command (see

Table 18).

Fractional LCD biasing voltages are obtained from an internal voltage divider. The biasing

configurations that apply to the preferred modes of operation, together with the biasing

characteristics as functions of V_LCDand the resulting discrimination ratios (D), are given in

Table 31.

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Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 31. Preferred LCD drive modes: summary of characteristics

[2]

LCD multiplex Number of:

LCD bias

configuration

V_LCD

V_offRMS

----------------------

V_LCD

V_onRMS

----------------------

V_LCD

V_onRMS

---------------------- ^[1]

V_offRMS

D =

drive mode

Backplanes

Levels

1

⁄

1:4 ^[3]

1:4

1:4 ^[3]

1:6 ^[3]

1:6

4

6

8

3

4

5

3

4

5

3

4

5

0.433

0.333

0.331

0.456

0.333

0.306

0.467

0.333

0.293

0.661

0.577

0.545

0.612

0.509

0.467

0.586

0.471

0.424

1.527

1.732

1.646

1.341

1.527

1.254

1.414

1.447

2.309V_off(RMS)

3.0V_off(RMS)

2

1

⁄

3

1

⁄

3.024V_off(RMS)

2.191V_off(RMS)

3.0V_off(RMS)

4

1

⁄

2

1

⁄

3

1

⁄

1:6

3.266V_off(RMS)

2.138V_off(RMS)

3.0V_off(RMS)

4

1

⁄

1:8 ^[3]

1:8

2

1

⁄

3

1

⁄

3.411V_off(RMS)

4

[1] Determined from Equation 6.

[2] Determined from Equation 5.

[3] In these examples, the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a

reduction of the LCD voltage V_LCD

.

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

a = 3 for ¹⁄₄bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 4

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(4)

V

LCD

where V_LCDis the resultant voltage at the LCD segment and where the values for n are

n = 4 for 1:4 multiplex drive

n = 6 for 1:6 multiplex drive

n = 8 for 1:8 multiplex drive

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 5:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(5)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 6:

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a²+ 2a + n

a²– 2a + n

V_onRMS

----------------------

V_offRMS

D =

=

---------------------------

(6)

It should be noted that V_LCDis sometimes referred to as the LCD operating voltage.

8.4.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 14. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(7)

(8)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 4 to Equation 6) and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes just named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

100 %

90 %

10 %

V

[V]

RMS

V

th(off)

V

th(on)

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

013aaa494

Fig 14. Electro-optical characteristic: relative transmission curve of the liquid

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8.5 LCD drive mode waveforms

8.5.1 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 15. This drawing is also showing the case of line inversion (see

Section 8.1.4.2).

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

/3

LCD

BP3

Sn

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

Sn+3

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

LCD

/3

V

/3

LCD

state 1

0 V

-V

/3

LCD

-2V

/3

LCD

-V

LCD

V

LCD

2V

LCD

/3

V

/3

LCD

0 V

-V

state 2

/3

LCD

-2V

/3

LCD

-V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa211

V_state1(t) = V_Sn(t)  V_BP0(t). V_state2(t) = V_Sn(t)  V_BP1(t).

_on(RMS)(t) = 0.577V_LCD. V_off(RMS)(t) = 0.333V_LCD

V

.

Fig 15. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias and line inversion

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.5.2 1:6 Multiplex drive mode

When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The

PCF8536 allows use of ¹⁄₃bias or ¹⁄₄bias in this mode as shown in Figure 16 and

Figure 17. These waveforms are drawn for the case of line inversion (see

Section 8.1.4.2).

T

fr

LCD segments

state 2

V

LCD

state 1

2V

V

/ 3

LCD

BP0

BP1

LCD

V

SS

V

LCD

/ 3

2V

V

LCD

V

SS

V

LCD

2V

V

/ 3

LCD

BP2

LCD

V

SS

V

LCD

2V

V

/ 3

LCD

BP3

LCD

V

SS

V

LCD

2V

V

/ 3

LCD

BP4

V

SS

V

LCD

2V

V

/ 3

LCD

BP5

LCD

V

SS

V

LCD

2V

V

/ 3

LCD

Sn

LCD

V

SS

V

LCD

2V

V

/ 3

LCD

Sn + 1

state 1

LCD

V

SS

(a) Waveforms at driver

V

LCD

/ 3

2V

V

LCD

V

SS

/ 3

-V

-2V

LCD

-V

LCD

V

LCD

2V

V

/ 3

LCD

state 2

LCD

V

SS

/ 3

-V

-2V

LCD

(b) Resultant waveforms at LCD segment

-V

LCD

001aal399

V_state1(t) = V_Sn(t)  V_BP0(t). V_state2(t) = V_{Sn +1}(t)  V_BP0(t). V_on(RMS)(t) = 0.509V_LCD. V_off(RMS)(t) = 0.333V_LCD

.

Fig 16. Waveforms for 1:6 multiplex drive mode with bias ¹⁄₃and line inversion

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

T

fr

LCD segments

state 2

V

LCD

/ 4

3V

V

LCD

state 1

BP0

BP1

BP2

BP3

BP4

BP5

Sn

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

V

/ 2

LCD

V

SS

V

LCD

Sn + 1

V

LCD

/ 2

V

SS

(a) Waveforms at driver

V

LCD

3V

V

/ 4

LCD

/ 4

LCD

state 1

V

SS

/ 4

-V

LCD

-3V

/ 4

LCD

-V

V

LCD

3V

V

/ 4

/ 2

/ 4

LCD

state 2

V

SS

/ 4

/ 2

/ 4

-V

-3V

LCD

(b) Resultant waveforms at LCD segment

-V

LCD

001aal400

V_state1(t) = V_Sn(t)  V_BP0(t). V_state2(t) = V_{Sn + 1}(t)  V_BP0(t).

_on(RMS)(t) = 0.467V_LCD. V_off(RMS)(t) = 0.306V_LCD

V

.

Fig 17. Waveforms for 1:6 multiplex drive mode with bias ¹⁄₄and line inversion

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Universal LCD low multiplex driver with 6 channel PWM generator

8.5.3 1:8 Multiplex drive mode

T

fr

V

LCD segments

state 2

LCD

/ 4

3V

V

LCD

state 1

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

Sn

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

3

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

/ 4

3V

V

LCD

/ 4

SS

LCD

V

LCD

V

/ 2

LCD

V

SS

V

LCD

Sn + 1

/ 2

LCD

V

SS

(a) Waveforms at driver

V

LCD

3V

V

/ 4

LCD

/ 4

LCD

state 1

V

SS

/ 4

-V

LCD

-3V

/ 4

LCD

-V

V

LCD

3V

V

/ 4

/ 2

/ 4

LCD

state 2

V

SS

/ 4

/ 2

/ 4

-V

-3V

LCD

(b) Resultant waveforms at LCD segment

-V

LCD

001aal398

V_state1(t) = V_Sn(t)  V_BP0(t). V_state2(t) = V_{Sn + 1}(t)  V_BP0(t). V_on(RMS)(t) = 0.424V_LCD. V_off(RMS)(t) = 0.293V_LCD

.

Fig 18. Waveforms for 1:8 multiplex drive mode with bias ¹⁄₄and line inversion

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

T

fr

frame n

fr

frame n+1

V

3/4 V

LCD

LCD segments

state 2

state 1

BP0

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

BP1

BP2

1/4 V

LCD

V

SS

V

3/4 V

LCD

1/4 V

LCD

V

SS

V

3/4 V

LCD

BP3

BP4

BP5

BP6

1/4 V

LCD

V

SS

V

3/4 V

LCD

1/4 V

LCD

V

SS

V

3/4 V

LCD

1/4 V

LCD

V

SS

V

3/4 V

LCD

1/4 V

LCD

V

SS

V

3/4 V

LCD

BP7

Sn

1/4 V

LCD

V

SS

V

LCD

1/2 V

V

SS

V

LCD

Sn + 1

1/2 V

V

SS

(a) Waveforms at driver

V

LCD

3/4 V

1/2 V

1/4 V

state 1

V

SS

1/4 V

LCD

1/2 V

3/4 V

V

3/4 V

1/2 V

1/4 V

LCD

V

state 2

SS

1/4 V

LCD

1/2 V

3/4 V

V

001aam359

(b) Resultant waveforms at LCD segment

V_state1(t) = V_Sn(t)  V_BP0(t). V_state2(t) = V_{Sn + 1}(t)  V_BP0(t). V_on(RMS)(t) = 0.424V_LCD. V_off(RMS)(t) = 0.293V_LCD

.

Fig 19. Waveforms for 1:8 multiplex drive mode with bias ¹⁄₄and frame inversion

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

8.6 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

8.7 Backplane outputs

The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane

output signals are generated based on the selected LCD multiplex drive mode.

• In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD.

• In 1:6 multiplex drive mode: BP0 to BP5 must be connected directly to the LCD.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

8.8 Segment outputs

The LCD drive section includes up to 44 segment outputs (S0 to S43) which must be

connected directly to the LCD. The segment output signals are generated based on the

multiplexed backplane signals and with data resident in the display register. When less

segment outputs are required, the unused segment outputs must be left open-circuit.

The number of available segments depends on the multiplex drive mode selected and the

number of GPOs used. The table shows consecutive GPOs selected, but this is just for

simplicity of explanation. Any combination of GPOs may be used.

Table 32. Backplane and active segment combinations

Basic examples. GPO pins may be configured in any combination. Other LCD segment and GPO combinations are possible.

Multiplex

drive mode

Active BPs Active GPOs

None

GP0 only

S1 to S39

S1 to S41

S1 to S43

GP0 to GP1 GP0 to GP2 GP0 to GP3 GP0 to GP4 GP0 to GP5

1:8

1:6

1:4

BP0 to BP7 S0 to S39

BP0 to BP5 S0 to S41

BP0 to BP3 S0 to S43

S2 to S39

S2 to S41

S2 to S43

S3 to S39

S3 to S41

S3 to S43

S4 to S39

S4 to S41

S4 to S43

S5 to S39

S5 to S41

S5 to S43

S6 to S39

S6 to S41

S6 to S43

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.9 Display RAM

The display RAM stores the LCD data. Depending on the multiplex drive mode, the

arrangement of the RAM is changed.

• multiplex drive 1:8: RAM is 40  8 bit

• multiplex drive 1:6: RAM is 42  6 bit

• multiplex drive 1:4: RAM is 44  4 bit

Display RAM addresses (columns)/segment outputs (S)

S35 S36 S37 S38 S39

Multiplex 1:8 drive mode

BP0

S0 S1 S2 S3 S4

BP1

BP2

BP3

BP4

BP5

BP6

BP7

Multiplex 1:6 drive mode

S35 S36 S37 S38 S39 S40 S41

S0 S1 S2 S3 S4

BP0

BP1

BP2

BP3

BP4

BP5

S35 S36 S37 S38 S39 S40 S41 S42 S43

S0 S1 S2 S3 S4

Multiplex 1:4 drive mode

BP0

BP1

BP2

BP3

013aaa454

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs and between the bits in a RAM row and the backplane outputs.

Fig 20. Display RAM bitmap

Logic 1 in the RAM bit map indicates the on-state (V_on(RMS)) of the corresponding LCD

element; similarly, logic 0 indicates the off-state (V_off(RMS)). For more information on

V

_on(RMS)and V_off(RMS), see Section 8.4.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements,

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

• the RAM columns and the segment outputs,

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 20, shows row 0 to row 7 which correspond with the

backplane outputs BP0 to BP7, and column 0 to column 43 which correspond with the

segment outputs S0 to S43. In multiplexed LCD applications, the data of each row of the

display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1

with BP1, and so on).

When display data is transmitted to the PCF8536, the display bytes received are stored in

the display RAM in accordance with the selected LCD multiplex drive mode. The data is

stored as it arrives and depending on the current multiplex drive mode, data is stored in

quadruples, sextuples or bytes.

8.9.1 Data pointer (LCD part)

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer-LCD command (see Table 25).

Following this command, an arriving data byte is stored starting at the display RAM

address indicated by the data pointer.

The data pointer is automatically incremented in accordance with the chosen LCD

multiplex drive mode configuration. That is, after each byte is stored, the contents of the

data pointer are incremented

• by two (1:4 multiplex drive mode),

• by one or two (1:6 multiplex drive mode),

• by one (1:8 multiplex drive mode).

Multiplex drive 1:6 is a special case and is described later on.

When the address counter reaches the end of the RAM, it stops incrementing after the last

byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are

discarded until the pointer is reset. To send new RAM data, the data pointer must be reset.

If an I²C-bus or SPI-bus data access is terminated early then the state of the data pointer

is unknown. The data pointer must then be re-written prior to further RAM accesses.

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.9.2 RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the RAM is organized in four rows and 44 columns. The

eight transmitted data bits are placed in two successive display RAM columns of four rows

(see Figure 21). In order to fill the whole four RAM rows, 22 bytes need to be sent to the

PCF8536. After the last byte sent, the data pointer must be reset before the next RAM

content update. Additional data bytes sent and any data bits that spill over the RAM will be

discarded.

Columns

Display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

5

6

7

39 40 41 42 43

0

1

b7 b3

b6 b2

Rows

b5

b1

2

3

Display RAM

bits (rows)/

b4 b0

backplane outputs

(BP)

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

Transmitted data byte

013aaa455

Fig 21. Display RAM filling order in 1:4 multiplex drive mode

Depending on the start address of the data pointer, there is the possibility for a boundary

condition. This will occur when more data bits are sent than fit into the remaining RAM.

The additional data bits are discarded. See Figure 22.

Columns

Display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

5

6

7

39 40 41 42 43

0

1

b7

b6

Rows

b5

b4

2

3

Display RAM

bits (rows)/

backplane outputs

(BP)

Discarded

b7 b6 b5 b4 b3 b2 b1 b0

MSB

LSB

Transmitted data byte

013aaa456

Fig 22. Boundary condition in 1:4 multiplex drive mode

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.9.3 RAM filling in 1:6 multiplex drive mode

In the 1:6 multiplex drive mode the RAM is organized in six rows and 42 columns. The

eight transmitted data bits are placed in such a way, that a column is filled up (see

Figure 23).

Columns

Display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

5

6

7

37 38 39 40 41

0

1

2

3

4

5

a7 a1 b3 c5

a6 a0 b2 c4

a5 b7 b1 c3

a4 b6 b0 c2

a3 b5 c7 c1

a2 b4 c6 c0

Rows

Display RAM

bits (rows)/

backplane outputs

(BP)

MSB

LSB

a7 a6 a5 a4 a3 a2 a1 a0

b7 b6 b5 b4 b3 b2 b1 b0

c7 c6 c5 c4 c3 c2 c1 c0

Transmitted data bytes

013aaa457

Fig 23. Display RAM filling order in 1:6 multiplex drive mode

The remaining bits are wrapped over into the next column. In order to fill the whole RAM,

31 and a half bytes need to be sent to the PCF8536. After the last byte sent, the data

pointer must be reset before the next RAM content update. Additional data bytes sent and

any data bits that spill over the RAM will be discarded. Depending on the start address of

the data pointer, there are three possible boundary conditions. See Figure 24.

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

Columns

Display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

5

6

7

37 38 39 40 41

0

1

2

3

4

5

b7

b6

b5

b4

b3

b2

Discarded

b7 b6 b5 b4 b3 b2 b1 b0

MSB

LSB

Transmitted data byte

37 38 39 40 41

0

1

2

3

4

5

b7

b6

b5

b4

Discarded

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

Transmitted data byte

37 38 39 40 41

0

1

2

3

4

5

b7

b6

Discarded

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

Transmitted data byte

013aaa458

Fig 24. Boundary condition in 1:6 multiplex drive mode

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

8.9.4 RAM filling in 1:8 multiplex drive mode

In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The

eight transmitted data bits are placed into eight rows of one display RAM column (see

Figure 25). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8536. After

the last byte sent, the data pointer must be reset before the next RAM content update.

Additional data bytes sent will be discarded.

Columns

Display RAM columns/segment outputs (S)

0

1

2

3

4

5

6

7

35 36 37 38 39

0

b7

1 b6

2 b5

3 b4

4 b3

5 b2

6 b1

7 b0

Rows

Display RAM rows/

backplane outputs

(BP)

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

Transmitted data byte

013aaa459

Fig 25. Display RAM filling order in 1:8 multiplex drive mode

There are no boundary conditions in 1:8 multiplex drive mode.

8.10 PWM registers and data pointer (PWM part)

There are six PWM generators which can be independently configured. The values used

to define the PWM output are stored here.

The addressing mechanism for the PWM register is realized using the PWM data pointer.

This allows the loading of an individual PWM data byte, or a series of data bytes, into any

location of the PWM registers. The sequence commences with the initialization of the data

pointer by the load-data-pointer-PWM command (see Table 26).

Following this command, an arriving data byte is stored starting at the PWM register

address indicated by the PWM data pointer. The data pointer is automatically

incremented. That is, after each byte is stored, the contents of the data pointer are

incremented. The data pointer will wrap around continuously as long as data is

transmitted.

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

Columns

Display RAM columns/segment outputs (S)

0

1

2

3

4

5

6

7

35 36 37 38 39

0

b7

1 b6

2 b5

3 b4

4 b3

5 b2

6 b1

7 b0

Rows

Display RAM rows/

backplane outputs

(BP)

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

Transmitted data byte

013aaa460

Fig 26. PWM register filling

8.11 GPO output

The PCF8536 contains six independently configured GPO pins (GP0 to GP5). These

outputs, when enabled, will replace the function of the corresponding LCD segment

outputs.

Each GPO output can supply either a logic 1, a logic 0, or a PWM signal. The PWM signal

can be used to control the brightness of an LED.

The PWM generator has 128 possible levels allowing for an output with a variable duty

cycle between 0 % and 99.7 %. 100 % can only be achieved by a static 1 output.

The period of the PWM frame frequency described in Section 8.1.10 is divided into

128 time slots. The value in the PWM register determines for how many of these time

slots the PWM output is at logic 1.

Table 33. PWM generator

PWM register value

Percentage of

ON time (%)

Time slots at 1

Time slots at 0

0

128

127

126

:

1

0.78

1.56

:

1

2

:

126

127

98.4

99.2

126

127

2

1

PWM duty cycle may be calculated by:

PWMvalue

----------------------------

DutyCycle =

 100

(9)

128

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PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

PWMI

PWM generator

0

230 kHz

GP0

1 0

1 1

0 1

0 0

channel 0

S0/GP0

S1/GP1

S2/GP2

S3/GP3

S4/GP4

1

segment 0

LCD data

PWM value 0

GP0M[1:0]

PWM generator

channel 1

0

1

GP1

1 0

1 1

0 1

0 0

segment 1

LCD data

PWM value 1

GP1M[1:0]

PWM generator

channel 2

0

1

GP2

1 0

1 1

0 1

0 0

segment 2

LCD data

PWM value 2

GP2M[1:0]

PWM generator

channel 3

0

1

GP3

1 0

1 1

0 1

0 0

segment 3

LCD data

PWM value 3

GP3M[1:0]

PWM generator

channel 4

0

1

GP4

1 0

1 1

0 1

0 0

segment 4

LCD data

PWM value 4

GP4M[1:0]

PWM generator

channel 5

0

1

GP5

1 0

1 1

0 1

0 0

S5/GP5

segment 5

LCD data

PWM value 5

GP5M[1:0]

001aan567

There are six independently configured GPO outputs.

Fig 27. General-purpose output block diagram

An example of the PWM waveforms is given in Figure 28.

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

f

PWM

0.00 %

0.78 %

PWM register 0 = 0

PWM register 1 = 1

PWM register 2 = 32

24.96 %

PWM register 3 = 64

PWM register 4 = 96

49.92 %

74.88 %

PWM register 5 = 127

99.20 %

1

t =

128 x f

PWM

001aan569

Fig 28. PWM example waveforms for PWMI = 0

8.11.1 RGB color driving

There are six PWM channels that can be arranged as two RGB channels. There are no

explicit settings for this feature, only ways of utilizing the PWM channels.

Table 34 gives an example of how two RGB clusters can be configured.

Table 34. Combining PWM channels for RGB

RGB cluster

PWM channel

Component color

0

1

2

3

4

5

red

green

blue

red

1

green

blue

Figure 29 gives an example of how two RGB clusters can be connected.

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

LED supply voltage

R

G

B

R

G

B

cluster 0

cluster 1

S0/GP0

S1/GP1

S2/GP2

S3/GP3

S4/GP4

S5/GP5

001aan568

There are six independently configured GPO outputs.

Fig 29. Configuration for two RGB clusters

Table 35 gives some examples of programming values for the PWM channels in order to

achieve the given colors. By using three PWM channels for one RGB cluster it is possible

to generate two million colors.

Table 35. Example PWM values

PWM channel

Component

color

PWM channel

value

Resultant color

0

1

2

3

4

5

0

1

2

3

4

5

red

127

0

yellow

green

blue

red

127

82

orange

aqua

gold

green

blue

red

0

green

blue

red

127

108

0

green

blue

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Universal LCD low multiplex driver with 6 channel PWM generator

8.11.2 PWM inversion mode

The PWM inversion mode can be enabled by setting the PWMI bit to logic 1 (see Table 7

on page 8). The PWMI mode will invert the PWM waveform.

By default, all PWM outputs will switch HIGH at the same time. If the PWM output is used

to drive external LEDs then this could cause a voltage dip on the power supply of the

LEDs. With the PWMI mode, it is possible to prevent multiple outputs switching HIGH at

the same time by ensuring that the PWM values are not identical.

In the example in Figure 30, none of the six PWM outputs switch HIGH together. All PWM

channels instead switch off together; however this will not cause any power supply

disturbances.

f

PWM

100.00 %

PWM register 0 = 0

PWM register 1 = 1

99.20 %

75.00 %

50.00 %

25.00 %

PWM register 2 = 32

PWM register 3 = 64

PWM register 4 = 96

0.78 %

PWM register 5 = 127

1

t =

128 x f

PWM

001aan570

Fig 30. PWM example waveforms for PWMI = 1

When PWM inversion mode is used, the PWM duty cycle can be calculated with:

128 – PWMvalue

-------------------------------------------

DutyCycle =

 100

(10)

128

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

9. Bus interfaces

9.1 Control byte and register selection

After initiating the communication over the bus and sending the slave address (I²C-bus,

see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The

purpose of this byte is to indicate both, the content for the following data bytes (RAM,

command, or PWM data) and to indicate that more control bytes will follow.

Typical sequences could be:

• Slave address/subaddress - control byte - command byte - command byte - command

byte - end

• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end

• Slave address/subaddress - control byte - command byte - control byte - RAM byte -

end

In this way, it is possible to send a mixture of RAM, PWM and command data in one

access or alternatively, to send just one type of data in one access.

Table 36. Control byte description

Bit

Symbol

Value

Description

continue bit

last control byte

control bytes continue

register selection

command register

RAM data

7

CO

0

1

6 to 5 RS[1:0]

00

01

10

11

-

PWM data

unused

4 to 0

-

unused

MSB

LSB

7

6

5

4

3

2

1

0

CO RS[1:0]

not relevant

013aaa461

Fig 31. Control byte format

9.2 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 32).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 32. Bit transfer

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START

condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P).

The START and STOP conditions are shown in Figure 33.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 33. Definition of START and STOP conditions

9.2.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 34.

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 34. System configuration

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Universal LCD low multiplex driver with 6 channel PWM generator

9.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is shown in Figure 35.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 35. Acknowledgement on the I²C-bus

9.2.5 I²C-bus controller

The PCF8536 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. Device selection depends on the I²C-bus

slave address.

9.2.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

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Universal LCD low multiplex driver with 6 channel PWM generator

9.2.7 I²C-bus slave address

Device selection depends on the I²C-bus slave address. Two different I²C-bus slave

addresses can be used to address the PCF8536 (see Table 37).

Table 37. I²C slave address

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

A0

The least significant bit of the slave address byte is bit R/W. Bit 1 of the slave address is

defined by connecting the input A0 to either V_SS(logic 0) or V_DD(logic 1). Therefore, two

instances of PCF8536 can be distinguished on the same I²C-bus.

9.2.8 I²C-bus protocol

The I²C-bus protocol is shown in Figure 36. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the two PCF8536 slave

addresses available. All PCF8536 with the corresponding A0 level acknowledge in

parallel to the slave address, but any PCF8536 with the alternative A0 level ignore the

whole I²C-bus transfer.

After acknowledgement, a control byte follows (see Section 9.1 on page 46).

The display bytes are stored in the display RAM at the address specified by the RAM data

pointer and PWM data is stored at the address pointed to by the PWM data pointer.

The acknowledgement after each byte is made only by the addressed PCF8536. After the

last data byte, the I²C-bus master issues a STOP condition (P). Alternatively a START

may be issued to RESTART an I²C-bus access.

R/W = 0

slave address

control byte

RAM/command byte

M

A S

B

L

S P

B

R R

S S

1 0

A

0

C

O

S 0 1 1 1 0 0

0 A

EXAMPLES

a) transmit two byte of RAM data

A

S 0 1 1 1 0 0

0 A 0 0

1

A

RAM DATA

COMMAND

A

RAM DATA

A P

0

b) transmit two command bytes

A

0

S 0 1 1 1 0 0

0 A 1 0 0

0 0 0

COMMAND

RAM DATA

A

A P

c) transmit one command byte and two RAM date bytes

A A

S 0 1 1 1 0

0 A 1 0 0

A

COMMAND

0 0 1

RAM DATA

A

A P

1 0

013aaa462

Fig 36. I²C-bus protocol write mode

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Universal LCD low multiplex driver with 6 channel PWM generator

9.2.8.1 Status read out

Status read out for I²C-bus operation only. This command will initiate the read out of a

fixed value plus the slave address bit A0 from the PCF8536. This read out function will

allow the I²C master to confirm the existence of the device on the I²C-bus.

Table 38. Status read out value

Bit

7 to 1

0

Symbol

Value

Description

-

0101010

fixed value

A0

0

1

read back value is 01010100

read back value is 01010101

If a readout is made, the R/W bit must be logic 1 and then the next data byte following is

provided by the PCF8536 as shown in Figure 37.

R/W = 1

readout byte

slave address

A

0

A

0

S

0

1

0

1

A

0

1

0

1

0

1

0

A

P

(1)

acknowledge

from master

013aaa463

(1) From PCF8536.

Fig 37. I²C-bus protocol read mode

In the unlikely case that the chip has entered the internal test mode, detection of this state

is possible by using the modified status read out detailed in Table 39. The read out value

is modified to indicate that the chip has entered an internal test mode.

Table 39. Modified status read out value

Bit

7 to 1

0

Symbol

Value

Description

-

1111000

fixed value

A0

0

1

read back value is 1111 0000

read back value is 1111 0001

EMC detection: The PCF8536 is ruggedized against EMC susceptibility; however it is not

possible to cover all cases. To detect if a severe EMC event has occurred, it is possible to

check the responsiveness of the device by reading its register.

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Universal LCD low multiplex driver with 6 channel PWM generator

9.3 SPI-bus interface

Data transfer to the device is made via a 3 line SPI-bus (see Table 40). There is no output

data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive.

Table 40. Serial interface

Symbol

CE

Function

chip enable input^[1]; active LOW

Description

when HIGH, the interface is reset

input may be higher than V_DD

SCL

serial clock input

SDI

serial data input

input may be higher than V_DD; input data is

sampled on the rising edge of SCL

[1] The chip enable must not be wired permanently LOW.

9.3.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a byte

with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the subaddress byte.

data bus

CE

SUBADDRESS

DATA

013aaa464

Fig 38. Data transfer overview

The subaddress byte opens the communication with a read/write bit and a subaddress.

The subaddress is used to identify multiple devices on one SPI-BUS.

Table 41. Subaddress byte definition

Bit

Symbol

Value

Description

7

R/W

data read or write selection

write data

0

1

read data

6 to 5 SA

4 to 0

01

subaddress; other codes will cause the device

to ignore data transfer

-

unused

After the subaddress byte, a control byte follows (see Section 9.1 on page 46).

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

R/W = 0

subaddress

control byte

RAM/command byte

R R

S S

M

S

B

L

S

B

C

0 0 1

O

1

0

EXAMPLES

a) transmit two bytes of display RAM data

0 0 1 0 0

1

RAM DATA

COMMAND

RAM DATA

b) transmit two command bytes

0 0 1 1 0 0

0 0 0

COMMAND

RAM DATA

c) transmit one command byte and two display RAM date bytes

COMMAND

0 0 1 1 0 0 0 0 1

RAM DATA

013aaa465

Data transfers are terminated by de-asserting CE (set CE to logic 1).

Fig 39. SPI-bus write example

R/W

SA

unused

command byte

Bias sytem = 1/3 B[1:0] = 11

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

1

0

1

0

1

SCL

SDI

CE

013aaa466

In this example, the bias system is set to ¹⁄₃. The transfer is terminated by CE returning to logic 1. After the last bit is

transmitted, the state of the SDI line is not important.

Fig 40. SPI-bus example

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Universal LCD low multiplex driver with 6 channel PWM generator

10. Internal circuitry

V

DD

A0, RESET,

OSCCLK

V , V ,

LCD DD

SCL, SDA

V

SS

LCD

V

SS

BP0 to BP7,

S0/GP0 to S5/GP5

S6 to S39

V

SS

013aaa472

Fig 41. Device protection diagram for PCF8536AT

V

DD

CE, RESET,

OSCCLK

SDI, SCL

V

,V

LCD DD

V

SS

LCD

V

SS

BP0 to BP7,

S0/GP0 to S5/GP5

S6 to S39

V

013aaa473

SS

Fig 42. Device protection diagram for PCF8536BT

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Universal LCD low multiplex driver with 6 channel PWM generator

11. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 42. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

0.5

50

0.5

50

Max

+6.5

+50

+10

+50

Unit

V

supply voltage

supply current

LCD supply voltage

LCD supply current

input voltage

I_DD

mA

V

V_LCD

I_DD(LCD)

V_I

mA

PCF8536AT

on pins SDA,

OSCCLK, SCL, A0,

RESET

0.5

+6.5

V

PCF8536BT

on pins CE,

0.5

+6.5

OSCCLK, SCL,

SDI, RESET

I_I

input current

10

+10

mA

V

V_O

output voltage

on pins S0/GP0 to

S5/GP5, S6 to S39,

BP0 to BP7

0.5

on pin SDA

0.5

+6.5

+10

V

I_O

output current

10

mA

mW

V

I_SS

ground supply current

total power dissipation

power dissipation per output

electrostatic discharge voltage

50

+50

P_tot

P/out

V_ESD

-

400

-

100

[1]

[2]

[3]

[4]

HBM

CDM

-

3500

1250

200

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

+150

+85

operating device

[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.

[2] Pass level; Charge Device Model (CDM), according to Ref. 6 “JESD22-C101”.

[3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be stored at a temperature of

+8 C to +45 C and a humidity of 25 % to 75 %. For long-term storage products deviant conditions are described in that document.

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PCF8536

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Universal LCD low multiplex driver with 6 channel PWM generator

12. Static characteristics

Table 43. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 9.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

2.5

-

5.5

9.0

2

V

V_LCD

LCD supply voltage

power-down mode supply current

supply current

V_LCD V_DD

-

V

[1]

I_DD(pd)

I_DD

0.5

A

see Figure 43

[2]

[3]

external 9.6 kHz clock

-

10

20

25

40

A

external 230 kHz

clock with PWM

[2]

[3]

internal oscillator

-

30

60

A

internal oscillator with

PWM

130

I_DD(LCD)

LCD supply current

[1][4]

[5]

power-down, see

Figure 44

-

7

15

A

display active, see

Figure 45

55

140

Logic

V_I

input voltage

V_SS 0.5

-

V_DD+ 0.5

0.3V_DD

V

V_IL

LOW-level input voltage

on pins OSCCLK,

A0 and RESET

-

V_IH

HIGH-level input voltage

on pins OSCCLK,

A0 and RESET

0.7V_DD

-

V

V_O

output voltage

0.5

-

V_DD+ 0.5

-

V

V_OH

HIGH-level output voltage

driving load of 50 A

on pins OSCCLK and

GP0 to GP5

0.8V_DD

V_OL

LOW-level output voltage

HIGH-level output current

driving load of 50 A

on pins OSCCLK and

GP0 to GP5

-

0.2V_DD

V

I_OH

output source current;

V

_OH= V_DD 0.4 V

on pin OSCCLK

V_DD= 1.8 V

0.7

1.5

1.6

4.0

-

mA

V_DD 3.3 V

on pins GP0 to GP5

V_DD= 1.8 V;

V_LCD= 2.5 V

0.7

1.5

1.1

2.8

-

mA

V

_DD= 3.3 V;

V_LCD 5.5 V

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Universal LCD low multiplex driver with 6 channel PWM generator

Table 43. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 9.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_OL

LOW-level output current

output sink current;

V_OL= 0.4 V

on pin OSCCLK

V_DD= 1.8 V

3

5

4

-

mA

V_DD 3.3 V

10

on pins GP0 to GP5

V_DD= 1.8 V;

0.7

1.5

1

1.1

2.4

-

mA

A

V

_LCD= 2.5 V

V_DD= 3.3 V;

V_LCD 5.5 V

-

I_L

leakage current

V_i= V_DDor V_SS; on

pin OSCCLK and GP0

to GP5

+1

I²C-bus^[6]

On pins SCL and SDA

V_I

input voltage

V_SS 0.5

-

5.5

V

V_IL

LOW-level input voltage

HIGH-level input voltage

output voltage

0.3V_DD

-

V

V_IH

0.7V_DD

0.5

V

V_O

+5.5

+1

V

I_L

leakage current

V_I= V_DDor V_SS

1

A

On pin SDA

I_OL

LOW-level output current

input voltage

output sink current

V_DD= 1.8 V

3

5

5.5

9

-

mA

V_DD= 3.3 V

SPI-bus

V_I

on pin SCL

V_SS 0.5

-

5.5

V

on pins CE and SDI

V_DD+ 0.5

On pins SCL, CE and SDI

V_IL

V_IH

I_L

LOW-level input voltage

-

0.3V_DD

V

HIGH-level input voltage

leakage current

0.7V_DD

-

V

V_I= V_DDor V_SS

1

+1

A

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Table 43. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 9.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

LCD outputs

V_O

output voltage variation

[7]

[8]

on pins BP0 to BP7

on pins S0 to S43

-

2.5

+10

mV

R_O

output resistance

[9]

V_LCD= 7 V;

on pins BP0 to BP7

-

0.9

1.5

5.0

6.0

k

V_LCD= 7 V;

on pins S0 to S43

[1] Power-down mode is enabled; I²C-bus or SPI-bus inactive.

[2] 1:8 multiplex drive mode; ¹⁄₄bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at V_SSor V_DD

;

default display prescale factor; I²C-bus or SPI-bus inactive.

[3] 1:8 multiplex drive mode; ¹⁄₄bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at V_SSor V_DD

;

default display prescale factor; I²C-bus or SPI-bus inactive; six PWM channels active at 50 % duty.

[4] Strongly linked to V_LCDvoltage. See Figure 44.

[5] 1:8 multiplex drive mode; ¹⁄₄bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; default display prescale

factor.

[6] The I²C-bus interface of PCF8536 is 5 V tolerant.

[7] Variation between any two backplanes on a given voltage level; static measured.

[8] Variation between any two segments on a given voltage level; static measured.

[9] Outputs measured one at a time.

013aaa503

60

I

DD

(µA)

40

20

0

-45

-10

25

60

95

T

(ºC)

amb

1:8 multiplex drive mode; ¹⁄₄bias; internal oscillator; display enabled; LCD outputs are open circuit;

RAM is all written with logic 1; inputs at V_SSor V_DD; default display prescale factor; I²C-bus or

SPI-bus inactive. Typical is defined at V_DD= 3.3 V, 25 C.

Fig 43. Typical I_DDwith respect to temperature

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Universal LCD low multiplex driver with 6 channel PWM generator

013aaa505

15

I

DD(LCD)

(µA)

V

= 9.0 V

= 5.5 V

LCD

10

5

0

-45

-10

25

60

95

T

(ºC)

amb

Power-down mode is enabled; I²C-bus or SPI-bus inactive. Typical is defined at 25 C.

Fig 44. Typical I_DD(LCD)in power-down mode with respect to temperature

013aaa507

120

I

DD(LCD)

(µA)

V

= 9.0 V

LCD

80

40

0

= 5.5 V

LCD

-45

-10

25

60

95

T

(ºC)

amb

1:8 multiplex drive mode; ¹⁄₄bias; display enabled; LCD outputs are open circuit; RAM is all written

with logic 1; default display prescale factor. Typical is defined at 25 C.

Fig 45. Typical I_DD(LCD)when display is active with respect to temperature

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13. Dynamic characteristics

Table 44. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 9.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

f_clk

clock frequency

output on pin

7800

9600

11040

Hz

OSCCLK;V_DD= 3.3 V

f_clk(ext)

external clock frequency

EFR = 0

-

250000

-

Hz

ns

t_{(RESET_N)}RESET_N pulse width

LOW time

400

External clock source used on pin OSCCLK

t_clk(H)

t_clk(L)

clock HIGH time

clock LOW time

33

-

s

[1] Frequency present on OSCCLK with default display frequency division factor.

013aaa501

15

f

clk

(kHz)

(3)

(1)

(2)

10

5

0

1

3

5

7

V

(V)

DD

(1) 40 C.

(2) 25 C.

(3) 85 C.

Fig 46. Typical clock frequency with respect to V_DDand temperature

1/f

clk(ext)

t

clk(L)

clk(H)

0.7V

DD

OSCCLK

0.3V

013aaa474

External clock source used on pin OSCCLK.

Fig 47. Driver timing waveforms

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Universal LCD low multiplex driver with 6 channel PWM generator

t

RESET(L)

RESET

0.3V

DD

013aaa475

Fig 48. RESET timing

Table 45. Timing characteristics: I²C-bus

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 9.0 V; T_amb= 40 C to +85 C; unless otherwise specified. All timing values

are valid within the operating supply voltage and temperature range and referenced to V_ILand V_IHwith an input voltage swing

of V_SSto V_DD. Timing waveforms see Figure 49.

Symbol

Pin SCL

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

[1]

SCL clock frequency

-

400

kHz

s

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP

1.3

-

s

and START condition

t_SU;STO

t_HD;STA

set-up time for STOP condition

0.6

-

s

hold time (repeated) START

condition

t_SU;STA

t_r

set-up time for a repeated START

condition

0.6

-

s

rise time of both SDA and SCL

signals

f_SCL= 400 kHz

f_SCL= 100 kHz

-

0.3

1.0

0.3

s

t_f

fall time of both SDA and SCL

signals

[2]

[3]

t_VD;ACK

t_VD;DAT

C_b

data valid acknowledge time

data valid time

0.6

-

s

pF

ns

-

capacitive load for each bus line

400

50

[4]

t_SP

pulse width of spikes that must be

suppressed by the input filter

-

[1] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL

is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.

[2] t_VD;ACK= time for acknowledgement signal from SCL LOW to SDA output LOW.

[3]

t_VD;DAT= minimum time for valid SDA output following SCL LOW.

[4] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

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Universal LCD low multiplex driver with 6 channel PWM generator

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 0 acknowledge

(R/W) (A)

protocol

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

013aaa417

HD;STA

SU;DAT

Fig 49. I²C-bus timing waveforms

Table 46. Timing characteristics: SPI-bus

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C. All timing values are valid within the operating supply voltage and

temperature range and referenced to V_ILand V_IHwith an input voltage swing of V_SSto V_DD. Timing waveforms see Figure 50.

Symbol

Parameter

Conditions

V_DD< 2.7 V

V_DD 2.7 V

Unit

Min

-

Max

Min

-

Max

f_clk(SCL)

t_SCL

SCL clock frequency

SCL time

2

5

MHz

ns

500

200

-

200

80

-

t_clk(H)

t_clk(L)

t_r

clock HIGH time

clock LOW time

rise time

-

for SCL signal

100

t_f

fall time

-

100

-

100

t_{su(CE_N)}

t_{h(CE_N)}

t_{rec(CE_N)}

t_su

CE_N set-up time

CE_N hold time

CE_N recovery time

set-up time

150

0

-

80

0

-

100

10

100

5

set-up time for

SDI data

t_h

hold time

hold time for SDI

data

25

-

10

-

ns

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CE

t

SCL

t

su(CE_N)

t

rec(CE_N)

t

r

t

clk(H)

t

h(CE_N)

f

70%

SCL

SDI

30%

t

clk(L)

t

su

t

h

b7

b6

b0

013aaa476

Fig 50. SPI-bus timing

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14. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 51. Package outline SOT364-1 (TSSOP56)

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15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

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16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 52) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 47 and 48

Table 47. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 48. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 52.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 52. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Footprint information for reflow soldering

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Footprint information for reflow soldering of TSSOP56 package

SOT364-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 8.900 6.100 1.400 0.280 0.400 14.270 7.000 16.600 9.150

sot364-1_fr

Fig 53. Footprint information for reflow soldering of SOT364-1 (TSSOP56) package

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19. Abbreviations

Table 50. Abbreviations

Acronym

Description

CDM

CMOS

DC

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Direct Current

EMC

EPROM

ESD

HBM

I²C

ElectroMagnetic Compatibility

Erasable Programmable Read-Only Memory

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit bus

Integrated Circuit

IC

LCD

LED

LSB

MSB

MSL

MUX

OTP

PCB

POR

PWM

RC

Liquid Crystal Display

Light-Emitting Diode

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Multiplexer

One Time Programmable

Printed-Circuit Board

Power-On Reset

Pulse-Width Modulation

Resistance-Capacitance

Random Access Memory

Red Green Blue

RAM

RGB

RMS

SCL

SDA

SPI

Root Mean Square

Serial CLock line

Serial DAta line

Serial Peripheral Interface

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20. References

[1] AN10365 — Surface mount reflow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface-Mount Devices

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] NX3-00092 — NXP store and transport requirements

[10] SNV-FA-01-02 — Marking Formats Integrated Circuits

[11] UM10204 — I²C-bus specification and user manual

21. Revision history

Table 51. Revision history

Document ID

PCF8536 v.2

Modifications:

PCF8536 v.1

Release date

Data sheet status

Change notice

Supersedes

20120221

Product Data Sheet

-

PCF8536 v.1

• Fixed typos

20111006

Product Data Sheet

-

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

22.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Universal LCD low multiplex driver with 6 channel PWM generator

24. Contents

1

2

3

4

5

6

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.9

Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data pointer (LCD part) . . . . . . . . . . . . . . . . . 36

RAM filling in 1:4 multiplex drive mode . . . . . 37

RAM filling in 1:6 multiplex drive mode . . . . . 38

RAM filling in 1:8 multiplex drive mode . . . . . 40

PWM registers and data pointer (PWM part) . 40

GPO output . . . . . . . . . . . . . . . . . . . . . . . . . . 41

RGB color driving. . . . . . . . . . . . . . . . . . . . . . 43

PWM inversion mode. . . . . . . . . . . . . . . . . . . 45

8.9.1

8.9.2

8.9.3

8.9.4

8.10

8.11

8.11.1

8.11.2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

9

9.1

9.2

Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 46

Control byte and register selection . . . . . . . . 46

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . 46

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

START and STOP conditions. . . . . . . . . . . . . 47

System configuration . . . . . . . . . . . . . . . . . . . 47

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 48

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 48

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

I²C-bus slave address . . . . . . . . . . . . . . . . . . 49

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 49

Status read out. . . . . . . . . . . . . . . . . . . . . . . . 50

SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 51

Data transmission . . . . . . . . . . . . . . . . . . . . . 51

8

8.1

Functional description . . . . . . . . . . . . . . . . . . . 7

Commands of PCF8536. . . . . . . . . . . . . . . . . . 7

Command: initialize . . . . . . . . . . . . . . . . . . . . . 7

Command: OTP-refresh . . . . . . . . . . . . . . . . . . 8

Command: PWM-inversion. . . . . . . . . . . . . . . . 8

Command: mode-settings . . . . . . . . . . . . . . . . 9

Backplane swapping. . . . . . . . . . . . . . . . . . . . . 9

Line inversion (driving scheme A) and frame

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.8.1

9.3

8.1.1

8.1.2

8.1.3

8.1.4

8.1.4.1

8.1.4.2

inversion (driving scheme B) . . . . . . . . . . . . . 10

Power-down mode . . . . . . . . . . . . . . . . . . . . . 10

Display enable . . . . . . . . . . . . . . . . . . . . . . . . 12

Command: oscillator-control . . . . . . . . . . . . . 12

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Timing and frame frequency. . . . . . . . . . . . . . 15

Command: GPO-output-config. . . . . . . . . . . . 15

Command: set-MUX-mode. . . . . . . . . . . . . . . 16

Command: set-bias-mode . . . . . . . . . . . . . . . 16

Command: frame-frequency-LCD. . . . . . . . . . 16

Command: frame-frequency-PWM. . . . . . . . . 18

Command: GPO-static-data . . . . . . . . . . . . . . 19

Command: load-data-pointer-LCD . . . . . . . . . 20

Command: load-data-pointer-PWM . . . . . . . . 20

Command: write-RAM-data . . . . . . . . . . . . . . 20

Command: write-PWM-data . . . . . . . . . . . . . . 21

Start-up and shut-down. . . . . . . . . . . . . . . . . . 21

Reset and Power-On Reset (POR). . . . . . . . . 21

RESET pin function . . . . . . . . . . . . . . . . . . . . 22

Recommended start-up sequences . . . . . . . . 22

Possible display configurations . . . . . . . . . . . 25

LCD voltage selector . . . . . . . . . . . . . . . . . . . 26

Electro-optical performance . . . . . . . . . . . . . . 28

LCD drive mode waveforms . . . . . . . . . . . . . . 29

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 29

1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 30

1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 32

Display register. . . . . . . . . . . . . . . . . . . . . . . . 34

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 34

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 34

8.1.4.3

8.1.4.4

8.1.5

8.1.5.1

8.1.5.2

8.1.6

8.1.7

8.1.8

8.1.9

8.1.10

8.1.11

8.1.12

8.1.13

8.1.14

8.1.15

8.2

8.2.1

8.2.2

8.2.3

8.3

8.4

8.4.1

8.5

9.3.1

10

11

12

13

14

15

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 53

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 54

Static characteristics . . . . . . . . . . . . . . . . . . . 55

Dynamic characteristics. . . . . . . . . . . . . . . . . 59

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 63

Handling information . . . . . . . . . . . . . . . . . . . 64

16

Soldering of SMD packages. . . . . . . . . . . . . . 64

Introduction to soldering. . . . . . . . . . . . . . . . . 64

Wave and reflow soldering. . . . . . . . . . . . . . . 64

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 65

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 65

16.1

16.2

16.3

16.4

17

18

Footprint information for reflow soldering. . 66

Appendix: possible PWM and LCD frame

frequency combinations to avoid flicker . . . 68

19

20

21

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 69

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Revision history . . . . . . . . . . . . . . . . . . . . . . . 70

8.5.1

8.5.2

8.5.3

8.6

8.7

8.8

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 71

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 71

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 72

22.1

22.2

22.3

22.4

continued >>

PCF8536

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 February 2012

73 of 74

PCF8536

NXP Semiconductors

Universal LCD low multiplex driver with 6 channel PWM generator

23

24

Contact information. . . . . . . . . . . . . . . . . . . . . 72

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 February 2012

Document identifier: PCF8536


型号：	PCF8536AT/1,118
厂家：	NXP
描述：	PCF8536 - Universal LCD driver for low multiplex rates including a 6 channel PWM generator TSSOP 56-Pin PC CD
文件：	总74页 (文件大小：2614K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF8536AT/1,118 [NXP]

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