PCF8548U/9_技术文档

INTEGRATED CIRCUITS

DATA SHEET

PCF8548

65 × 102 pixels matrix LCD driver

Product speciﬁcation

1999 Aug 16

Supersedes data of 1999 Mar 22

File under Integrated Circuits, IC12

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

CONTENTS

12

INSTRUCTIONS

12.1

12.2

External reset (RES)

Function set

Power-Down (PD)

V

H

MX

1

FEATURES

2

APPLICATIONS

GENERAL DESCRIPTION

Packages

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.3

12.3.1

12.4

12.4.1

12.4.2

12.5

12.6

12.7

12.7.1

12.8

12.9

3

3.1

4

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

MY

5

Display control

D and E

Display configuration

TRS

6

7

PIN FUNCTIONS

7.1

7.2

7.3

7.4

7.5

7.6

7.7

R0 to R64: row driver outputs

BRS

C0 to C101: column driver outputs

V_SS1and V_SS2: negative power supply rails

V_DD1to V_DD3: positive power supply rails

Set Y address of RAM

Set X address of RAM

Set HV generator stages

S[1:0]

Temperature control

Bias system

Set V_OPvalue

V_LCDIN: LCD power supply

V_LCDOUT: LCD power supply

V_LCDSENSE: voltage multiplier regulation input

(V_LCD

)

12.10

7.8

7.9

7.10

7.11

7.12

7.13

T1 to T12: test pads

SDAIN and SDAOUT: I²C-bus data lines

SCL: I²C-bus clock signal

SA0: slave address

OSC: oscillator

RES: reset

13

14

15

16

17

18

19

20

21

22

23

24

25

26

LIMITING VALUES

HANDLING

DC CHARACTERISTICS

AC CHARACTERISTICS

RESET

8

BLOCK DIAGRAM FUNCTIONS

APPLICATION INFORMATION

CHIP INFORMATION

8.1

8.2

8.3

8.4

8.5

8.6

Oscillator

I²C-bus interface

Display control logic

Display Data RAM (DDRAM)

Timing generator

PAD INFORMATION

DEVICE PROTECTION DIAGRAM

TRAY INFORMATION

LCD row and column drivers

DEFINITIONS

9

INITIALIZATION

ADDRESSING

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

BARE DIE DISCLAIMER

10

10.1

10.2

Display data RAM structure

RAM access

11

I²C-BUS INTERFACE

11.1

Characteristics of the I²C-bus

Bit transfer

11.1.1

11.1.2

11.1.3

11.1.4

11.2

START and STOP conditions

System configuration

Acknowledge

I²C-bus protocol

1999 Aug 16

2

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

1

FEATURES

• Single-chip LCD controller/driver

• 65 row and 102 column outputs

• Display data RAM 65 × 102 bits

• On-chip:

2

APPLICATIONS

– Configurable 5 (4, 3 and 2) × voltage multiplier

generating V_LCD(external V_LCDalso possible)

• Telecom equipment

• Portable instruments

• Point of sale terminals.

– Generation of intermediate LCD bias voltages

– Oscillator requires no external components

(external clock also possible).

• 400 kbits/s fast I²C-bus interface

• CMOS compatible inputs

• Mux rate: 1 : 65

3

GENERAL DESCRIPTION

The PCF8548 is a low power CMOS LCD controller driver,

designed to drive a graphic display of 65 rows and

102 columns. All necessary functions for the display are

provided in a single chip, including on-chip generation of

LCD supply and bias voltages, resulting in a minimum of

external components and low power consumption.

The PCF8548 interfaces to most microcontrollers via an

I²C-bus interface.

• Logic supply voltage range V_DD1to V_SS

:

– 1.9 to 5.5 V.

• High voltage generator supply voltage range V_DD2to

V_SSand V_DD3to V_SS

:

– 2.4 to 4.5 V with LCD voltage internally generated

(voltage generator enabled).

• Display supply voltage range V_LCDto V_SS

:

3.1

Packages

– 4.5 to 9.0 V

The PCF8548 is available as chip with bumps in tray; tape

carrier package is available on request.

• Low power consumption, suitable for battery operated

systems

• Temperature compensation of V_LCD

• Slim chip layout, suitable for Chip-On-Glass (COG)

applications

• Programmable bottom row pads mirroring and top row

pads mirroring, for compatibility with both Tape Carrier

Package (TCP) and COG applications.

4

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

PCF8548U/2

PCF8548U/9

Tray

Bumped wafer

chip with bumps in tray

quarter wafer

−

1999 Aug 16

3

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

5

BLOCK DIAGRAM

V

DD3

handbook, full pagewidth

C0 to C101

R0 to R64

DD1

DD2

102

65

V

SS1

SS2

ROW DRIVERS

COLUMN DRIVERS

PCF8548

RES

DATA LATCHES

SHIFT REGISTER

OSCILLATOR

BIAS

VOLTAGE

GENERATOR

V

LCDIN

OSC

HIGH

DISPLAY DATA RAM

V

LCDSENSE

VOLTAGE

GENERATOR

4 STAGES

65 × 102 BITS

TIMING

GENERATOR

V

LCDOUT

2

I C-BUS

DISPLAY CONTROL LOGIC

INTERFACE

MGS393

SDAOUT SDAIN SCL

SA0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

Fig.1 Block diagram.

6

PINNING

SYMBOL

PAD

DESCRIPTION

SYMBOL

PAD

DESCRIPTION

RES

1

external reset input (active

LOW)

V_LCDIN

35 to 40

41 to 54

57 to 75

76 to 177

LCD supply voltage

R32 to R19

R0 to R18

C0 to C101

R50 to R33

R51 to R64

T12 to T9

OSC

LCD row driver outputs

LCD column driver outputs

SDAOUT

SDAIN

SCL

2

3 and 4

5 and 6

7

I²C-bus data output

I²C-bus data input

I²C-bus clock input

test 2 output

178 to 195 LCD row driver outputs

198 to 211 LCD row driver outputs

212 to 215 test outputs

T2

SA0

8

least signiﬁcant bit of slave

address

216

217

oscillator

test input

T7 to T5

T4 and T3

T1

9 to 11

12 and 13

14

test inputs

T8

test input/output

V_DD1

218 to 223 supply voltage 1

224 to 226 supply voltage 3

227 to 233 supply voltage 2

test input

V_DD3

V_SS1

15 to 20

21 to 26

28 to 33

34

negative power supply 1

negative power supply 2

voltage multiplier output

voltage multiplier

V_DD2

V_SS2

27, 55, 56, dummy pads

196 and 197

V_LCDOUT

V_LCDSENSE

regulation input (V_LCD

)

1999 Aug 16

4

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

7

PIN FUNCTIONS

7.8

T1 to T12: test pads

7.1

R0 to R64: row driver outputs

T1 and T3 to T7 must be connected to V_SS1. T8 must be

connected to V_DD1. T2 and T9 to T12 must be left

open-circuit; not accessible to user.

These pads output the row signals.

7.2

C0 to C101: column driver outputs

7.9

SDAIN and SDAOUT: I²C-bus data lines

These pads output the column signals.

Serial data and acknowledge lines for the I²C-bus.

By connecting SDAIN to SDAOUT, the SDA line becomes

fully I²C-bus compatible. Having the acknowledge output

(SDAOUT) separated from the serial data line is

advantageous in Chip-On-Glass (COG) applications.

In COG applications where the track resistance from the

SDAOUT pad to the system SDA line can be significant, a

potential divider is generated by the bus pull-up resistor

and the Indium Tin Oxide (ITO) track resistance. It is

possible that during the acknowledge cycle the PCF8548

will not be able to create a valid logic 0 level. By splitting

the SDA input from the output the device could be used in

a mode that ignores the acknowledge bit. In COG

applications where the acknowledge cycle is required, it is

necessary to minimize the track resistance from the

SDACK pad to the system SDA line to guarantee a valid

LOW level.

7.3

V_SS1and V_SS2: negative power supply rails

V_SS2is related to V_DD2and V_DD3and V_SS1is related to

V_DD1

.

7.4

V_DD1to V_DD3: positive power supply rails

V_DD2and V_DD3are the supply voltages for the internal

voltage generator. Both have to be at the same voltage

and must be connected together outside of the chip. If the

internal voltage generator is not used, they should both be

connected to power or to the V_DD1pad.

V_DD1is used as the power supply for the rest of the chip.

This voltage can be a different voltage than V_DD2and

V_DD3

.

7.5

V_LCDIN: LCD power supply

7.10 SCL: I²C-bus clock signal

Internally generated positive power supply for the liquid

crystal display. An external LCD supply voltage can be

supplied using the V_LCDINpad. In this case, V_LCDOUThas

to be connected to ground, and the internal voltage

generator has to be programmed to zero. If the PCF8548

is in power-down mode, the external LCD supply voltage

must be switched off.

I²C-bus serial clock signal input.

7.11 SA0: slave address

Two different slave addresses can be selected using the

SA0 pad. This allows two PCF8548 LCD drivers to be

connected to the same I²C-bus.

7.6

V_LCDOUT: LCD power supply

7.12 OSC: oscillator

Positive power supply for the liquid crystal display. If the

internal voltage generator is used, the two supply rails

When the on-chip oscillator is used this input must be

connected to V_DD1. An external clock signal, if used, is

connected to this input.

V_LCDINand V_LCDOUTmust be connected together and an

external capacitor must be connected (see Fig.19).

7.13 RES: reset

7.7

V_LCDSENSE: voltage multiplier regulation input

(V_LCD

This signal is used to reset the device. The signal is active

LOW.

)

V_LCDSENSEis the input voltage for the internal voltage

multiplier regulation.

If the internal voltage generator is used then V_LCDSENSE

must be connected to V_LCDOUT. If an external supply

voltage is used then V_LCDSENSEmust be connected to

ground.

1999 Aug 16

5

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

8

BLOCK DIAGRAM FUNCTIONS

Oscillator

8.5

Timing generator

8.1

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the I²C-bus.

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC input must be connected to V_DD1. An external

clock signal (if used), is connected to this input.

8.6

LCD row and column drivers

The PCF8548 contains 65 row and 102 column drivers,

which connect the appropriate LCD bias voltages to the

display in accordance with the data to be displayed.

Figure 2 shows typical waveforms. Unused outputs should

be left unconnected.

8.2

I²C-bus interface

The I²C-bus interface receives and executes the

commands sent via the I²C-bus. It also receives RAM data

and sends it to the RAM.

9

INITIALIZATION

8.3

Display control logic

Immediately following Power-on, all internal registers and

the RAM content are undefined. A reset pulse must first be

applied.

The display control logic generates the control signals to

read from the RAM via the 102 bits parallel port. It also

generates the control signals for the row and column

drivers.

Reset is accomplished by applying an external RES pulse

(active LOW). When reset occurs within the specified time

all internal registers are initialized, however the RAM is still

undefined. The state after reset is described in

Section 12.1.

8.4

Display Data RAM (DDRAM)

The PCF8548 contains a 65 × 102 bit static RAM which

stores the display data. The RAM is divided into 8 banks of

102 bytes and 1 bank of 102 bits [(8 × 8 + 1) × 102 bits].

During RAM access, data is transferred to the RAM via the

I²C-bus interface. There is a direct correspondence

between the X address and column output number.

The RES input must be ≤0.3 V_DDwhen V_DDreaches

V_DD(min)(or higher) within a maximum time t_VHRLafter V_DD

goes HIGH (see Fig.17).

1999 Aug 16

6

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

frame n

frame n + 1

V

(t)

LCD

2

3

state1

state2

ROW 0

R0 (t)

V

4

5

SS

V

LCD

2

3

ROW 1

R1 (t)

V

4

5

SS

V

LCD

2

3

COL 0

C0 (t)

V

4

5

SS

V

LCD

2

3

COL 1

C1 (t)

V

4

5

SS

V

− V

LCD

SS

− V

3

SS

V

− V

V

0 V

V

− V

LCD

0 V

3

2

4

5

V

(t)

state1

− V

SS

5

V

− V

4

LCD

− V

V

SS

LCD

V

− V

LCD

SS

2

− V

3

SS

V

− V

V

0 V

V

− V

LCD

0 V

3

4

5

V

(t)

state2

− V

SS

5

V

− V

4

LCD

− V

V

SS

LCD

0 1 2 3 4 5 6 7 8...

... 64 0 1 2 3 4 5 6 7 8...

... 64

MGS671

V_state1(t) = C1(t) − R0(t).

V_state2(t) = C1(t) − R1(t).

Fig.2 Typical LCD driver waveforms.

7

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

DDRAM

bank 0

top of LCD

bank 1

bank 2

bank 3

bank 7

bank 8

LCD

MGS395

Fig.3 DDRAM to display mapping.

8

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

10 ADDRESSING

The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs 3, 6, 7, 8 and 9. The DDRAM has a

matrix of 65 × 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to

X101 (1100101b) and Y0 to Y8 (1000b). Addresses outside of these ranges are not allowed. In vertical addressing mode

(V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 8), Y wraps around to 0 and

X increments to address the next column. In the horizontal addressing mode (V = 0) the X address increments after each

byte (see Fig.4). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After

the very last address (X = 101 and Y = 8) the address pointers wrap around to address X = 0 and Y = 0.

10.1 Display data RAM structure

handbook, full pagewidth

0

1

2

0

102

204

306

408

510

612

714

816

103

205

307

409

511

613

715

817

104

206

308

410

512

614

716

818

Y address

917

101

8

0

X address

MGS396

Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

1999 Aug 16

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Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

0

1

2

3

4

5

6

7

8

9

0

10

Y address

917

101

8

0

X address

MGS397

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

The DO bit defines the bit order (MSB on top or MSB on bottom) for writing to the RAM (see Figs 6 and 7).

handbook, full pagewMidtShB

LSB

MSB

MGS398

LSB

Fig.6 RAM byte organization, if DO = 0.

1999 Aug 16

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Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidLtShB

MSB

LSB

MGS399

MSB

Fig.7 RAM byte organization, if DO = 1.

The MX bit allows a horizontal mirroring; when MX = 1, the X address space is mirrored. The address X = 0 is then

located at the right side (column 101) of the display (see Fig.9). When MX = 0 the mirroring is disabled and the address

X = 0 is located at the left side (column 0) of the display (see Fig.8).

handbook, full pagewidth

0

8

0

X address

Y address

101

MGS400

Fig.8 RAM format addressing (MX = 0).

1999 Aug 16

11

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

0

8

101

X address

Y address

0

MBL044

Fig.9 RAM format addressing (MX = 1).

10.2 RAM access

If the D/C bit is logic 1 the RAM can be written to. The data is written to the RAM during the acknowledge cycle.

1999 Aug 16

12

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

11 I²C-BUS INTERFACE

• Slave: the device addressed by a master

• Multi-Master: more than one master can attempt to

control the bus at the same time without corrupting the

message

11.1 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

Serial Data line (SDA) and a Serial Clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

11.1.1 BIT TRANSFER

11.1.4 ACKNOWLEDGE

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse because changes in the

data line at this time will be interpreted as a control signal.

Bit transfer is illustrated in Fig.10.

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH signal put on the bus by the

transmitter during which time the master generates an

extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte. A master receiver must also

generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration). A master receiver must

signal an end-of-data to the transmitter by not generating

an acknowledge on the last byte that has been clocked out

of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a STOP

condition. Acknowledgement on the I²C-bus is illustrated

in Fig.13.

11.1.2 START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P). The START

and STOP conditions are illustrated in Fig.11.

11.1.3 SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.12.

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.10 Bit transfer.

13

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

SDA

SCL

S

P

STOP condition

START condition

MBC622

Fig.11 Definition of START and STOP conditions.

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

MGA807

Fig.12 System configuration.

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

8

SCL FROM

MASTER

1

2

9

S

clock pulse for

acknowledgement

START

condition

MBC602

Fig.13 Acknowledgement on the I²C-bus.

14

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

11.2 I²C-bus protocol

The control and data bytes are also acknowledged by all

addressed slaves on the bus.

The PCF8548 supports command, data write and status

read access.

After the last control byte, depending on the D/C bit setting,

either a series of display data bytes or command data

bytes may follow. If the D/C bit is set to logic 1, these

display bytes are stored in the display RAM at the address

specified by the data pointer. The data pointer is

automatically updated and the data is directed to the

intended PCF8548 device. If the D/C bit of the last control

byte is set to logic 0, these command bytes will be

decoded and the setting of the device will be changed

according to the received commands. The

Before any data is transmitted on the I²C-bus, the device

which should respond is addressed first. Two 7-bit slave

addresses (0111100 and 0111101) are reserved for the

PCF8548. The least significant bit of the slave address is

set by connecting the input SA0 to either logic 0 (V_SS1) or

logic 1 (V_DD1).

The I²C-bus protocol is illustrated in Fig.14.

The sequence is initiated with a START condition (S) from

the I²C-bus master which is followed by the slave address.

All slaves with the corresponding address acknowledge in

parallel, all the others will ignore the I²C-bus transfer. After

acknowledgement, one or more command words follow

which define the status of the addressed slaves.

acknowledgement after each byte is made only by the

addressed slave. At the end of the transmission the

I²C-bus master issues a STOP condition (P).

If the R/W bit is set to logic 1 the chip will output data

immediately after the slave address if the D/C bit, which

was sent during the last write access, is set to logic 0. If no

acknowledge is generated by the master after a byte, the

driver stops transferring data to the master.

A command word consists of a control byte, which defines

Co and D/C, plus a data byte (see Fig.14 and Table 1).

The last control byte is tagged with a cleared most

significant bit (i.e. the continuation bit Co). After a control

byte with a cleared Co bit, only data bytes will follow. The

state of the D/C bit defines whether the data byte is

interpreted as a command or as RAM data.

Write mode

handbook, full pagewidth

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

S

A

0

control byte

S

0

1

0

A

1

A

data byte

A

0

A

data byte

A P

DC

slave address

2n ≥ 0 bytes

command word

1 byte

n ≥ 0 bytes

MSB . . . . . . . . . . . LSB

Co

S

A

0

R/

W

0

1 1 1 1 0

Read mode

PCF8548

slave address

acknowledgement

from PCF8548

acknowledgement

from master

S

A

0

status bytes

S

0

1

0

1

A

A P

A

0 0

Co

DC

0

control byte

MGS401

slave address

Fig.14 I²C-bus protocol.

15

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

12 INSTRUCTIONS

The instruction format is divided into two modes:

1. If D/C is set LOW, commands can be sent to the chip.

2. If D/C is set HIGH, the DDRAM will be accessed.

Every instruction can be sent in any order to the PCF8548.

Table 1 Instruction set

COMMAND BYTE

INSTRUCTION D/C R/W

H = 0 or 1

DESCRIPTION

B7

B6

B5

B4

B3

B2

B1

B0

NOP

0

1

0

1

no operation

Reserved

Function set

do not use

MX MY

PD

V

H

Power-down control; entry

mode; extended instruction

set control (H)

Read status byte

Write data

0

1

0

PD TRS BRS

D

E

MX

D₂

MY DO read status byte

D₇

D₆

D₅

D₄

D₃

D₁

D₀writes data to RAM

H = 0

Reserved

Set V_LCDrange

0

1

0

X

do not use

PRS V_LCDprogramming range

select

Display control

0

1

0

D

0

E

sets display conﬁguration

Set HV-gen

stages

S1

S0 # of HV-gen voltage

multiplication

Set Yaddress of

RAM

0

1

0

Y₃

X₃

Y₂

X₂

Y₁

X₁

Y₀sets Yaddress of RAM:

0 ≤ Y ≤ 8

Set X address of

RAM

X₆

X₅

X₄

X₀sets X address of RAM:

0 ≤ X ≤ 101

H = 1

Reserved

0

1

X

do not use

Temperature

control

TC₁TC₀set temperature coefﬁcient

(TCx)

Display

conﬁguration

0

1

DO TRS BRS top/bottom row mode set data

order

Bias system

Reserved

Set V_OP

0

1

0

1

0

1

0

BS₂BS₁BS₀set bias system (BSx)

X

do not use (reserved for test)

V_OP6V_OP5V_OP4V_OP3V_OP2V_OP1V_OP0write V_OPto register

1999 Aug 16

16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

Table 2 Explanations of symbols in Table 1

BIT

0

1

RESET STATE

PD

V

chip is active

chip is in Power-down mode

vertical addressing

1

0

horizontal addressing

H

use basic instruction set

normal X addressing

use extended instruction set

X address is mirrored

MX

MY

TRS

BRS

DO

PRS

display is not vertically mirrored

top rows are not mirrored

bottom rows are not mirrored

MSB is on top

display is vertically mirrored

top rows are mirrored

bottom rows are mirrored

LSB is on top

V

_LCDprogramming range LOW

V_LCDprogramming range HIGH

D and E

TC[1:0]

S[1:0]

00

10

01

11

00

01

10

11

00

01

10

11

display blank

D = 0

E = 0

normal mode

all display segments on

inverse video mode

V_LCDtemperature coefﬁcient 0

V_LCDtemperature coefﬁcient 1

V_LCDtemperature coefﬁcient 2

TC[1:0] = 00

S[1:0] = 00

V_LCDtemperature coefﬁcient 3

2 × voltage multiplier

3 × voltage multiplier

4 × voltage multiplier

5 × voltage multiplier

bias system

BS[2:0]

V_op[6:0]

BS[2:0] = 000

V_LCDprogramming

V_op[6:0] = 0000000

12.1 External reset (RES)

After power-on a reset pulse must be applied immediately to the chip, as it is in an undefined state. A reset of the chip

can be achieved using the external reset pad. After the reset the LCD driver is set to the following states:

• Power-down mode (PD = 1)

• All LCD outputs at V_SS(display off)

• Horizontal addressing (V = 0)

• Normal instruction set (H = 0)

• Normal display (MX = MY = TRS = BRS = 0)

• Display blank (E = D = 0)

• Address counter X[6:0] = 0 and Y[3:0] = 0

• Temperature coefficient (TC[1:0] = 0)

• Bias system (BS[2:0] = 0)

• V_LCDis equal to 0, the HV generator is switched off (V_op[6:0] = 0 and PRS = 0)

• After power-on (RAM data is undefined), the reset signal does not change the content of the RAM.

1999 Aug 16

17

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

12.2 Function set

12.2.5 MY

12.2.1 POWER-DOWN (PD)

When MY = 1, the display is mirrored vertically.

• All LCD outputs at V_SS(display off)

• Bias generator and V_LCDgenerator off

• Oscillator off (external clock possible)

• V_LCDcan be disconnected

A change of this bit has an immediate effect on the display.

12.3 Display control

12.3.1 D AND E

The bits D and E select the display mode (see Table 2).

• RAM contents not cleared (RAM data can be written)

• V_LCDoutput is discharged to V_SS

.

12.4 Display conﬁguration

12.2.2

V

12.4.1 TRS

When V = 0, the horizontal addressing is selected.

The data is written to the RAM as shown in Fig.4. When

V = 1, the vertical addressing is selected. The data is

written to the RAM as shown in Fig.5.

Bit TRS enables the top row pad blocks to be mirrored.

This is used to enable flexibility in the wiring of the row

lines from the PCF8548 to the LCD cell (e.g. COG or TCP

wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64

are organized as illustrated in Fig.22. When TRS = 1 rows

19 to 32 and rows 51 to 64 are mirrored and organized as

illustrated in Fig.23.

12.2.3

H

When H = 0 the commands ‘display control’, ‘set HV-gen

stages’, ‘set Y address’ and ‘set X address’ can be

performed. When H = 1 the other commands can be

executed. The commands ‘write data’ and ‘function set’

can be executed in both cases.

12.4.2 BRS

Bit BRS enables the bottom row pad blocks to be mirrored.

This is used to enable flexibility in the wiring of the row

lines from the PCF8548 to the LCD cell (e.g. COG or TCP

wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are

organized as illustrated in Fig.22. When BRS = 1 rows

0 to 18 and rows 33 to 50 are mirrored and organized as

illustrated in Fig.23.

12.2.4 MX

When MX = 0, the display RAM is written from left to right

(X = 0 is on the left side of the display, X = 100 is on the

right side of the display). When MX = 1 the display RAM is

written from right to left (X = 0 is on the right side of the

display, X = 100 is on the left side of the display).

12.5 Set Y address of RAM

Y[3 : 0] defines the Y address vector address of the RAM.

Thus, if a horizontally mirroring of the display is desired the

RAM must first be rewritten.

Table 3 X and Y address ranges

Y₃

Y₂

Y₁

Y₀

CONTENT

ALLOWED X RANGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

bank 0 (display RAM)

bank 1 (display RAM)

bank 2 (display RAM)

bank 3 (display RAM)

bank 4 (display RAM)

bank 5 (display RAM)

bank 6 (display RAM)

bank 7 (display RAM)

bank 8 (display RAM); note 1

0 to 101

Note

1. In bank 8 only the MSB is accessed.

1999 Aug 16

18

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

12.6 Set X address of RAM

There are 4 different temperature coefficients available in

the PCF8548 (see Fig.15). The coefficients are selected

by the two bits TC[1:0]. Table 6 shows the typical values of

the different temperature coefficients. The coefficients are

The X address points to the columns. The range of X is

0 to 101 (65H).

proportional to the programmed V_LCD

.

12.7 Set HV generator stages

12.7.1 S[1:0]

12.9 Bias system

The PCF8548 incorporates a software configurable

voltage multiplier. After reset the voltage multiplier is set to

2 × V_DD2. Other voltage multiplier factors are set via the

command ‘set HV-gen stages’ (see Tables 1 and 2).

The Bias voltage levels are set in the ratio

1

of R − R − nR − R − R giving a

bias system.

------------

n + 4

The resulting bias levels are shown in Table 5.

Different multiplex rates require different factors n (see

Table 4); this is programmed by BS[2 : 0]. For Mux 1 : 65

the optimum bias value n is given by:

12.8 Temperature control

Due to the temperature dependency of the liquid crystals

viscosity, the LCD controlling voltage V_LCDmust be

increased with lower temperature to maintain optimum

contrast.

n = m – 3 = 65 – 3 = 5.06 = 5 resulting in ¹⁄₉bias.

MGS402

handbook, halfpage

V

LCD

T

cut

Fig.15 Temperature coefficients.

1999 Aug 16

19

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

Table 4 Programming the required bias system

BS[2]

BS[1]

BS[0]

n

RECOMMENDED MUX RATE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

6

5

4

3

2

1

0

1 : 100

1 : 81

1 : 64

1 : 49

1 : 36

1 : 24

1 : 16

1 : 9

Table 5 LCD bias voltage

The parameters are explained in Fig.16 and Table 6.

The maximum voltage that can be generated is dependent

on the V_DD2voltage and the display load current.

Two overlapping V_LCDranges are selectable via the

command ‘HV-gen control’. For the LOW (PRS = 0) range

a = a₁and for the HIGH (PRS = 1) range a = a₂with steps

equal to b in both ranges. It should be noted that the

charge pump is turned off if V_OP[6;0] and bit PRS are all set

to zero. For Mux 1 : 65 the optimum operation voltage of

the liquid can be calculated as follows:

BIAS VOLTAGES

SYMBOL

BIAS VOLTAGES

FOR ¹⁄₉BIAS

V1

V2

V3

V4

V5

V6

V_LCD

(n + 3)/(n + 4)

(n + 2)/(n + 4)

2/(n + 4)

V_LCD

⁸⁄₉× V_LCD

⁷⁄₉× V_LCD

²⁄₉× V_LCD

¹⁄₉× V_LCD

V_SS

1/(n + 4)

V_SS

1 + 65

V_LCD

=

× V = 6.85 × V_th

th

---------------------------------------

1

12.10 Set V_OPvalue

2 × 1 –

----------

65

The voltage at reference temperature can be calculated

as: [V_LCD(T = T_cut)]

where V_this the threshold voltage of the liquid crystal

material used.

V_LCD

= (a + V_OP× b)

(1)

(Tcut)

The operating voltage V_LCDcan be set by software.

The generated voltage is dependent on the temperature,

programmed Temperature Coefficient (TC) and the

programmed voltage at reference temperature (T_cut).

V_LCD= (a + V_OP× b) × [1 + (T – T_cut) × TC]

(2)

Table 6 Typical values for parameters for the HV-generator programming

SYMBOL BITS VALUE

2.94 (PRS = 0)

UNIT

a₁

a₂

b

V

6.75 (PRS = 1)

V

0.03

27

V

T_cut

°C

1999 Aug 16

20

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

V

LCD

b

a

2

a +b

1

a

1

0H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH

(

)

(

)

LOW PRS = 0

HIGH PRS = 1

MGS658

V_OP[6:0] (programmed); 00H to 7FH, programme range LOW and HIGH.

Fig.16 V_OPprogramming of PCF8548.

As the programming range for the internally generated V_LCDallows values above the maximum allowed V_LCD(9.0 V) the

customer must ensure while setting the V_OPregister and selecting the temperature coefficient, under all conditions and

including all tolerances V_LCDremains below 9.0 V.

1999 Aug 16

21

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

13 LIMITING VALUES

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134); parameters are valid

over operating temperature range unless otherwise specified; all voltages referenced to V_SS= 0 V. Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of

the device at these or at any other conditions above those given in the characteristics sections of the speciﬁcation is not

implied. Exposure to limiting values for extended periods may affect device reliability.

SYMBOL

PARAMETER

MIN.

−0.5

MAX.

+6.5

UNIT

V_DD1

supply voltage

V

_DD2,V_DD3supply voltage for internal voltage generator

−0.5

−50

−0.5

−10

−

+4.5

+9.0

+50

V

V_LCD

I_SS

supply voltage for the LCD

supply current

V

mA

V

V_i(n)

I_I

all input voltages

V_DD+ 0.5

+10

DC input current

mA

I_O

DC output current

+10

P_pack

P/out

power dissipation per package

power dissipation per output

300

mW

−

30

14 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

15 DC CHARACTERISTICS

V_DD1= 1.9 to 5.5 V; V_DD2and V_DD3= 2.4 to 4.5 V; V_SS1and V_SS2= 0 V; V_LCD= 4.5 to 9.0 V; T_amb= −40 to +85 °C;

unless otherwise speciﬁed.

SYMBOL

PARAMETER

supply voltage

CONDITIONS

MIN.

1.9

TYP.

MAX.

5.5

UNIT

V_DD1

−

V

T

_amb= −25 to +85 °C

1.8

2.4

5.5

4.5

V_DD2,V_DD3supply voltage for

LCD voltage internally

generated (voltage generator

enabled)

internal voltage

generator

V_LCDIN

V_LCDOUT

I_DD1

LCD input supply

voltage

LCD voltage externally

supplied (voltage generator

disabled)

4.5

−

9.0

−

V

LCD output supply

voltage

LCD voltage internally

generated (voltage generator

enabled); note 1

−

supply current

V_DD1= 2.8 V; V_LCD= 7.6 V;

f_sclk= 0; T_amb= 25 °C;

notes 2 and 3

20

µA

I_DD2,I_DD3

supply current for

internal voltage

generator

with external V_LCD

−

0.5

−

µA

with internal V_LCDgeneration;

V_DD1= 2.8 V; V_LCD= 7.6 V;

f_sclk= 0; T_amb= 25 °C; no

display load; 4 × charge pump;

notes 2 and 3

180

1999 Aug 16

22

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

350

UNIT

µA

I_DD(tot)

total supply current

with internal V_LCDgeneration;

V_DD1= 2.8 V; V_LCD= 7.6 V;

−

200

f

_sclk= 0; T_amb= 25 °C; no

display load; 4 × charge pump;

notes 2 and 3

(Power-down mode) with

internal or external V_LCD

generation; note 4

−

1.5

30

10

µA

I_LCDIN

supply current from

external V_LCD

V_DD1= 2.8 V; V_LCD= 7.6 V;

−

f

_sclk= 0; T_amb= 25 °C; no

display load; notes 2, 3 and 5

Logic

V_IL

V_IH

I_L

LOW-level input voltage

HIGH-level input voltage

leakage current

V_SS1

0.7V_DD1

−1

−

0.3V_DD1

V_DD1

+1

V

V_i= V_DD1or V_SS1

µA

Column and row outputs

R_row

row output resistance

V_DD1to V_DD3= 5.0 V;

−

12

20

kΩ

R0 to R64

V_LCD= 7.6 V; I_L= 10 µA;

outputs tested one at a time

R_col

column output

resistance C0 to C101

V_LCD= 7.6 V

−

12

0

20

kΩ

V_bias(col)

V_bias(row)

column bias tolerance

C0 to C101

−100

+100

mV

row bias tolerance

R0 to R64

0

LCD supply voltage generator

V_LCD

V_LCDtolerance

internally generated

V_DD1= 2.8 V; V_LCD= 7.6 V;

f_sclk= 0; T_amb= 25 °C;

no display load;

−300

0

+300

mV

notes 2, 3 6 and 7

TC

temperature coefﬁcient 00

−

−0.0 × 10⁻³

−0.76 × 10⁻³

−1.05 × 10⁻³

−2.10 × 10⁻³

−

1/°C

01

10

11

Notes

1. The maximum possible V_LCDvoltage that can be generated is dependent on voltage, temperature and (display) load.

2. Internal clock.

3. When f_sclk= 0 there is no I²C-bus clock.

4. Power-down mode. During power-down all static currents are switched off.

5. If external V_LCD, the display load current is not transmitted to I_DD

.

6. Tolerance depends on the temperature; (typically zero at T_amb= 27 °C), maximum tolerance values are measured

at the temperature range limit.

7. For TC0 to TC3.

1999 Aug 16

23

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

16 AC CHARACTERISTICS

V_DD1= 1.9 to 5.5 V; V_DD2and V_DD3= 2.4 to 4.5 V; V_SS1and V_SS2= 0 V; V_LCD= 4.5 to 9 V; T_amb= −40 to +85 °C;

unless otherwise speciﬁed.

SYMBOL

PARAMETER

oscillator frequency

CONDITIONS

V_DD1= 2.8 V;

MIN.

TYP.

38

MAX.

70

UNIT

f_OSC

20

kHz

T_amb= −20 to +70 °C

f_clk(ext)

f_frame

external clock frequency

frame frequency

20

38

73

100

kHz

Hz

f_OSCor f_clk(ext)= 38 kHz;

note 1

−

t_VHRL

V_DD1to RES LOW

see Fig.17 and note 2

see Fig.17 and note 3

0

−

1

µs

t_W(RES)

RES LOW pulse width

100

−

ns

I²C-bus timing characteristics; see note 4

f_SCLK

t_SCLL

t_SCLH

t_SU;DAT

t_HD;DAT

t_r

SCL clock frequency

SCL clock LOW period

SCL clock HIGH period

data set-up time

0

−

400

−

kHz

µs

ns

µs

ns

pF

1.3

0.6

100

0

−

data hold time

0.9

300

1000

400

SCL and SDA rise time

SCL and SDA fall time

SDA fall time for read out

note 5

20 + 0.1C_b

−

t_f

note 5

t_f(SDA)(ro)

C_b

V_DD1= <3.6 V

capacitive load represented by each

bus line

t_SU;STA

set-up time for a repeated START

condition

0.6

−

µs

t_HD;STA

t_SU;STO

t_SW

START condition hold time

set-up time for STOP condition

tolerable spike width on bus

0.6

−

µs

ns

µs

−

note 6

50

−

t_BUF

bus free time between a STOP and

START condition

1.3

Notes

f_clk(ext)

1. f_frame

=

------------------

520

2. RES may be LOW before V_DD1goes HIGH.

3. If t_W(RES)is longer than 3 ns (typical) a reset may be generated.

4. All timing values are valid within the operating supply voltage and ambient temperature ranges and are referenced

to V_ILand V_IHwith an input voltage swing of V_SSto V_DD

.

5. The rise and fall times specified here refer to the driver device (i.e. not PCF8548) and are part of the general fast

I²C-bus specification. When PCF8548 asserts an acknowledge on SDA, the minimum fall time is 10 ns.

C_b= capacitive load per bus line.

6. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <t_SW(max)

.

1999 Aug 16

24

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

17 RESET

handbook, full pagewidth

V

DD

t

W(RES)

RES

t

W(RES)

V

DD

t

VHRL

RES

t

W(RES)

MGS404

W(RES)

Fig.17 Reset timing.

1999 Aug 16

25

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

18 APPLICATION INFORMATION

Table 7 Programming example for PCF8548

BITS

STEP

DISPLAY

OPERATION

B7

B6

B5

B4

B3

B2

B1

B0

1

2

3

I²C-bus start

0

1

0

1

0

1

0

1

0

slave address for write

control byte with cleared Co

bit and D/C set to logic 0

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

function set; PD = 0; V = 0;

select extended instruction

set (H = 1 mode)

set bias system 2; this is the

recommended bias system

for a multiplex rate 1 : 65

set V_OP; V_OPis set to a

+106 × b [V]; it should be

noted that the required

voltage is dependent on the

liquid

7

0

1

0

1

0

1

0

function set; PD = 0; V = 0;

select normal instruction set

(H = 0 mode)

8

9

display control; set normal

mode (D = 1; E = 0)

I²C-bus start

restart; to write into the

display RAM the D/C must

be set to logic 1; therefore a

control byte is needed

10

11

0

1

0

1

0

1

0

slave address for write

control byte with cleared Co

bit and D/C set to logic 1

12

1

0

data write; Yand X are

initialized to 0 by default, so

they are not set here

MGS405

13

1

0

1

0

data write

MGS406

1999 Aug 16

26

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

BITS

STEP

DISPLAY

OPERATION

B7

B6

B5

B4

B3

B2

B1

B0

14

15

16

17

18

1

0

data write

MGS407

MGS408

MGS409

MGS410

MGS411

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

data write

19

20

21

I²C-bus start

restart

0

1

0

1

0

1

0

1

0

slave address for write

control byte with set Co bit

and D/C set to logic 0

22

0

1

0

1

display control; set inverse

video mode (D = 1; E = 1)

MGS412

23

24

1

0

control byte with set Co bit

and D/C set to logic 0

set X address of RAM; set

address to ‘0000000’

MGS413

1999 Aug 16

27

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

BITS

STEP

DISPLAY

OPERATION

B7

B6

B5

B4

B3

B2

B1

B0

25

26

1

0

control byte with set Co bit

and D/C set to logic 1

0

data write

MGS414

27

28

0

1

0

control byte with cleared Co

bit and D/C set to logic 0

set X address of RAM; set

address to ‘0000000’

MGS415

29

30

31

I²C-bus start

restart

0

1

0

1

0

1

0

slave address for write

control byte with set Co bit

and D/C set to logic 1

32

1

0

1

0

write data

MGS416

33

1

0

control byte with set Co bit

and D/C set to logic 0

V

handbook, halfpage

DD1

SCL

V

DD1

MICRO-

CONTROLLER

PCF8548

SDAIN

SDA

SDAOUT

MGS417

Fig.18 Connecting the I²C-bus interface.

28

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

DISPLAY 102 × 65

32

102

33

PCF8548

≥3

C

VLCD

C

VDD

I/O

V

SS

MGS418

DD

The number of I/Os depends on the application.

Fig.19 Internal charge pump is used and a single supply voltage.

handbook, full pagewidth

DISPLAY 102 × 65

32

102

33

PCF8548

≥3

C

VDD1

V

DD1

C

VLCD

I/O

C

VDD2

V

SS

MGS419

DD2

The number of I/Os depends on the application.

Fig.20 Internal charge pump is used and two separate supply voltages.

29

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

DISPLAY 102 × 65

32

102

33

PCF8548

≥3

C

VDD

I/O

V

LCD

MGS420

DD

SS

The number of I/Os depends on the application.

Fig.21 External high voltage generation is used.

The pinning of the PCF8548 is optimized for single plane wiring e.g. for chip-on-glass display modules, or for TCP.

Display size: 65 × 102 pixels. The required minimum value for the external capacitors in an application with the PCF8548

are: C_VDD, C_VDD1, C_VDD2and C_VLCD= 1.0 µF (min.). Higher capacitor values are recommended for ripple reduction.

To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application, it is strongly recommended to

implement on the glass (ITO) a series input resistance in the reset line (The recommended minimum value is 8 kΩ).

19 CHIP INFORMATION

The PCF8548 is manufactured in n-well CMOS technology. The substrate is at V_SSpotential.

20 PAD INFORMATION

PAD

VALUE

UNIT

Minimum bump pitch

Pad size, alumin

70

µm

62 × 100

Bumps

50 (±6) × 90 (±6) × 17.5 (±5)

Wafer thickness without bumps

U/2 = 381; U/9 = 525

1999 Aug 16

30

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

Table 8 Bonding pad location

All x and y coordinates are referenced to the centre of the

chip (dimension in µm; see Fig.22).

SYMBOL

PAD

x

y

SYMBOL

PAD

x

y

RES

SDAOUT

SDAIN

SCL

1

+1160

+840

+899.4

R32

R31

R30

R29

R28

R27

R26

R25

R24

R23

R22

R21

R20

R19

dummy pad

R0

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

−4235

−4305

−4375

−4445

−4515

−4585

−4655

−4725

−4795

−4865

−4935

−5005

−5075

−5145

−5355

−5320

−5040

−4970

−4900

−4830

−4760

−4690

−4620

−4550

−4480

−4410

−4340

−4270

−4200

−4130

−4060

−3990

−3920

−3850

−3780

−3570

−3500

−3430

−3360

−3290

+899.4

−899.4

2

3

+600

4

+520

5

+200

SCL

6

+120

T2

7

−200

SA0

8

−410

T7

9

−620

T6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

−830

T5

−1040

−1250

−1460

−1670

−1750

−1830

−1910

−1990

−2070

−2150

−2310

−2390

−2470

−2550

−2630

−2710

−2790

−2950

−3030

−3110

−3190

−3270

−3350

−3430

−3510

−3590

−3670

−3750

−3830

−3910

T4

T3

T1

V_SS1

R1

V_SS1

R2

V_SS1

R3

V_SS2

R4

V_SS2

R5

V_SS2

R6

V_SS2

R7

V_SS2

R8

V_SS2

R9

dummy pad

V_LCDOUT

V_LCDSENSE

V_LCDIN

R10

R11

R12

R13

R14

R15

R16

R17

R18

C0

C1

C2

C3

C4

1999 Aug 16

31

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

SYMBOL

PAD

x

y

SYMBOL

PAD

x

y

C5

81

82

−3220

−3150

−3080

−3010

−2940

−2870

−2800

−2730

−2660

−2590

−2520

−2450

−2380

−2310

−2240

−2170

−2100

−2030

−1960

−1890

−1750

−1680

−1610

−1540

−1470

−1400

−1330

−1260

−1190

−1120

−1050

−980

−899.4

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

−210

−140

−899.4

C6

C7

83

−70

C8

84

+0

C9

85

+140

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

86

+210

87

+280

88

+350

89

+420

90

+490

91

+560

92

+630

93

+700

94

+770

95

+840

96

+910

97

+980

98

+1050

+1120

+1190

+1260

+1330

+1400

+1470

+1540

+1610

+1680

+1750

+1820

+1890

+2030

+2100

+2170

+2240

+2310

+2380

+2450

+2520

+2590

+2660

+2730

+2800

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

−910

−840

−770

−700

−630

−560

−490

−420

−350

−280

1999 Aug 16

32

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

SYMBOL

PAD

x

y

SYMBOL

PAD

x

y

C89

C90

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

+2870

+2940

+3010

+3080

+3150

+3220

+3290

+3360

+3430

+3500

+3570

+3640

+3710

+3850

+3920

+3990

+4060

+4130

+4200

+4270

+4340

+4410

+4480

+4550

+4620

+4690

+4760

+4830

+4900

+4970

+5040

+5320

+5355

+5145

+5075

+5005

+4935

+4865

+4795

+4725

+4655

+4585

−899.4

+899.4

R60

R61

R62

R63

R64

T12

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

+4515

+4445

+4375

+4305

+4235

+3880

+3720

+3560

+3400

+3160

+2680

+2600

+2520

+2440

+2360

+2280

+2200

+2120

+2040

+1960

+1880

+1800

+1720

+1640

+1560

+1480

+1400

+899.4

C91

C92

C93

C94

C95

T11

C96

T10

C97

T9

C98

OSC

T8

C99

C100

C101

R50

V_DD1

V_DD3

V_DD2

R49

R48

R47

R46

R45

R44

R43

R42

R41

R40

R39

R38

R37

R36

Table 9 Alignment marks

R35

x

y

MARKS

R34

R33

+5214

−5214

+4099

−4099

−899.4

+899.4

mark 1

mark 2

mark 3

mark 4

dummy pad

R51

R52

R53

The alignment marks are circular with a diameter of

100 µm.

R54

R55

R56

R57

R58

R59

1999 Aug 16

33

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

handbook, full pagewidth

R50

R64

R49

.

R63

.

R34

R33

R52

R51

TRS = 1

BRS = 1

R19

R0

R20

R1

.

R31

R32

R17

R18

C0

C1

.

MX = 1

.

C100

C101

MGS657

Fig.23 Pad layout for BRS, TRS and MX.

35

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

21 DEVICE PROTECTION DIAGRAM

handbook, full pagewidth

V

DD1

V

SS1

DD2

T2

V

SS1

V

SS1

V

DD1

SS2

T3, T4

V

DD3

V

SS1

V

SS1

SS2

V

LCDIN

T9

T10

T11

T12

V

SS1

V

LCDIN

LCDOUT

LCDSENSE

V

SS1

V

SS1

COL 0-101/ROW 0-64

V

DD1

LCDIN

SA0

OSC

1 per block

RES

T1

T5 to T7

V

SS1

V

SS1

MGS422

T8

V

SS1

Fig.24 Device protection diagram.

36

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

22 TRAY INFORMATION

x

handbook, full pagewidth

A

C

y

D

B

F

E

MGS423

The dimensions are given in Table 10.

Fig.25 Tray details.

Table 10 Dimensions

DIM.

DESCRIPTION

VALUE

A

B

C

D

E

F

x

pocket pitch, x direction

pocket pitch, y direction

pocket width, x direction

pocket width, y direction

tray width, x direction

13.77 mm

4.45 mm

11.09 mm

2.3 mm

50.8 mm

3

handbook, halfpage

P C 8 5 4 8 - 1

number of pockets in

x direction

y

number of pockets in

y direction

10

MGS424

The orientation of the IC in a pocket is indicated by the position of

the IC type name on the die surface with respect to the chamfer on

the upper left corner of the tray. Refer to the bonding pad location

diagram for the orientating and position of the type name on the die

surface.

Fig.26 Tray alignment.

1999 Aug 16

37

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

23 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

24 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

25 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

26 BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of

ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately

indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern

processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no

control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors

assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of

the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

1999 Aug 16

38

Philips Semiconductors

Product speciﬁcation

65 × 102 pixels matrix LCD driver

PCF8548

NOTES

1999 Aug 16

39

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Tel. +39 039 203 6838, Fax +39 039 203 6800

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA67

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

465006/02/pp40

Date of release: 1999 Aug 16

Document order number: 9397 750 05023


型号：	PCF8548U/9
厂家：	NXP
描述：	65 x 102 pixels matrix LCD driver 65 X 102像素矩阵LCD驱动器驱动器 CD
文件：	总40页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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