PCF8553DTT/AJ_技术文档

PCF8553

40 × 4 LCD segment driver

Rev. 3 — 27 March 2015

Product data sheet

1. General description

PCF8553 is an ultra low-power LCD segment driver with 4 backplane- and 40

segment-driver outputs, with either an I²C- or an SPI-bus interface. It comprises an

internal oscillator, bias generation, instruction decoding, and display controller.

For a selection of NXP LCD segment drivers, see Table 24 on page 45.

2. Features and benefits

 Single chip LCD controller and driver

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with buffers

 40 segment drives:

 Up to 20 7-segment numeric characters

 Up to 10 14-segment alphanumeric characters

 Any graphics of up to 160 segments/elements

 Auto-incrementing display data and instruction loading

 Versatile blinking modes

 Independent supplies of V_LCDand V_DD

 Power supply ranges:

 1.8 V to 5.5 V for V_LCD

 1.8 V to 5.5 V for V_DD

 Ultra low-power consumption

 400 kHz I²C-bus interface

 5 MHz SPI-bus interface

 Internally generated or externally supplied clock signal

3. Applications

 Metering equipment

 Small appliances

 Consumer healthcare devices

 Battery operated devices

 Measuring equipment

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF8553DTT

TSSOP56

plastic thin shrink small outline package; SOT364-1

56 leads; body width 6.1 mm

4.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

IC

revision

PCF8553DTT/A

PCF8553DTT/AJ

935304762118 tape and reel, 13 inch

1

5. Marking

Table 3.

Marking codes

Type number

PCF8553DTT/A

Marking code

PCF8553D

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

6. Block diagram

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Fig 1. Block diagram of PCF8553

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

7. Pinning information

7.1 Pinning

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Fig 2. Pin configuration of PCF8553DTT (TSSOP56)

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

7.2 Pin description

Table 4.

Pin description of PCF8553DTT (TSSOP56)

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

Backplane and segment outputs

SEG34 to SEG39 1 to 6 output

Type

Description

LCD segments

LCD backplanes

SEG0 to SEG33

COM0 to COM3

Supply pins

VLCD

23 to 56

7 to 10 output

11

12

14

supply

LCD supply voltage

supply voltage

VDD

VSS

ground supply

Clock and control pins

RST

PORE^[1]

15

21

input

reset input, active LOW

Power-On Reset (POR) enable

• connect to V_DDfor enabling POR

• connect to V_SS(or leave open) for disabling POR

CLK

18

13

input/output internal oscillator output, external oscillator input

• must be left open if unused

Bus-related pins

IFS^[1]

I²C-bus

SPI-bus

input

interface selector input

• connect to V_SS(or leave open)

• connect to V_DD

serial data input/output

unused

SDIO

A0^[1]

A1^[1]

16

17

22

input/output unused

input

hardware device address selection;

• connect to V_SS(or leave open) for

logic 0

• connect to V_DDfor logic 1

SCL

19

20

input

serial clock input

SDA/CE

input/output serial data output

chip enable input, active LOW

[1] A series resistance between V_DDand the pin must not exceed 1 k to ensure proper functionality, see Section 16.3.

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

8. Functional description

8.1 Registers of the PCF8553

The registers of the PCF8553 are arranged in bytes with 8 bit, addressed by an address

pointer. Table 5 depicts the layout.

Table 5.

Registers of the PCF8553

Bits labeled as 0 must always be written with logic 0.

Register name Address Bits

Reference

AP[4:0]

Command registers

Software_reset 00h

7

6

5

4

3

2

1

0

SR[7:0]

Table 9

Table 6

Table 7

Table 8

Device_ctrl

01h

02h

03h

0

FF[1:0]

OSC

B

COE

DE

Display_ctrl_1

BOOST MUX[1:0]

Display_ctrl_2

0

BL[1:0]

SEG2

INV

Display data registers^[1]

COM0

04h

05h

06h

07h

08h

09h

:

SEG7

SEG6

SEG5

SEG4

SEG3

SEG1

SEG0

SEG8

Table 10

SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9

SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16

SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24

SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32

COM1

COM2

COM3

SEG7

:

SEG6

:

SEG5

:

SEG4

:

SEG3

:

SEG2

:

SEG1

:

SEG0

:

0Dh

0Eh

:

SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32

SEG7

:

SEG6

:

SEG5

:

SEG4

:

SEG3

:

SEG2

:

SEG1

:

SEG0

:

12h

13h

:

SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32

SEG7

:

SEG6

:

SEG5

:

SEG4

:

SEG3

:

SEG2

:

SEG1

:

SEG0

:

17h

SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32

[1] See Table 10.

For writing to the registers, send the address byte first, then write the data to the register

(see Section 11.1.4 and Section 11.2.1). The address byte works as an address pointer.

For the succeeding registers, the address pointer is automatically incremented by 1 (see

Figure 3) and all following data are written into these register addresses. After register

17h, the auto-incrementing will stop and data are ignored.

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

6 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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8.2 Command registers of the PCF8553

8.2.1 Command: Device_ctrl

The Device_ctrl command sets the device into a defined state. It should be executed

before enabling the display (see bit DE in Table 7).

Table 6.

Bit

Device_ctrl - device control command register (address 01h) bit description

Symbol

-

Value

Description

7 to 4

3 to 2

0000

default value

FF[1:0]

frame frequency selection

f_fr= 32 Hz

00

01^[1]

f_fr= 64 Hz

10

f_fr= 96 Hz

11

f_fr= 128 Hz

1

0

OSC

COE

internal oscillator control

enabled

0^[1]

1

disabled

clock output enable

clock signal not available on pin CLK;

pin CLK is in 3-state

clock signal available on pin CLK

0^[1]

1

[1] Default value.

8.2.1.1 Internal oscillator and clock output

Bit OSC enables or disables the internal oscillator. When the internal oscillator is used, bit

COE allows making the clock signal available on pin CLK. If this is not intended, pin CLK

should be left open. The design ensures that the duty cycle of the clock output is 50 : 50

(% HIGH-level time : % LOW-level time).

In applications where an external clock has to be applied to the PCF8553, bit OSC must

be set logic 1 and COE logic 0. In this case pin CLK becomes an input.

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

In power-down mode (see Section 8.3.1)

• if pin CLK is configured as an output, there is no signal on CLK

• if pin CLK is configured as an input, the signal on CLK can be removed.

Remark: A clock signal must always be supplied to the device if the display is enabled

(see bit DE in Table 7 on page 8). Removing the clock may freeze the LCD in a DC state,

which is not suitable for the liquid crystal.

8.2.2 Command: Display_ctrl_1

The Display_ctrl_1 command allows configuring the basic display set-up.

Table 7.

Bit

Display_ctrl_1 - display control command 1 register (address 02h) bit description

Symbol

-

Value

Description

7 to 5

4

000

default value

BOOST

large display mode support

standard power drive scheme

0^[1]

1

enhanced power drive scheme for higher display

loads

3 to 2

MUX[1:0]

multiplex drive mode selection

00^[1]

01

1:4 multiplex drive mode; COM0 to COM3

(n_MUX= 4)

1:3 multiplex drive mode; COM0 to COM2

(n_MUX= 3)

10

1:2 multiplex drive mode; COM0 and COM1

(n_MUX= 2)

11

static drive mode; COM0 (n_MUX= 1)

1

0

B^[2]

DE

bias mode selection

¹⁄₃bias (a_bias= 2)

¹⁄₂bias (a_bias= 1)

display enable^[3]

0^[1]

1

0^[1]

1

display disabled; device is in power-down mode

display enabled; device is in power-on mode

[1] Default value.

[2] Not applicable for static drive mode.

[3] See Section 8.3.1.

8.2.2.1 Enhanced power drive mode

By setting the BOOST bit to logic 1, the driving capability of the display signals is

increased to cope with large displays with a higher effective capacitance. Setting this bit

increases the current consumption on V_LCD

.

8.2.2.2 Multiplex drive mode

MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals,

which are active. For further details, see Section 9.2 on page 16.

PCF8553

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

8.2.3 Command: Display_ctrl_2

Table 8.

Display_ctrl_2 - display control command 2 register (address 03h) bit description

Bit

Symbol

-

Value

Description

7 to 3

2 to 1

00000

default value

BL[1:0]

blink control

00^[1]

01

blinking off

blinking on, f_blink= 0.5 Hz

blinking on, f_blink= 1 Hz

blinking on, f_blink= 2 Hz

inversion mode selection

line inversion (driving scheme A)

frame inversion (driving scheme B)

10

11

0

INV

0^[1]

1

[1] Default value.

8.2.3.1 Blinking

The whole display blinks at frequencies selected by the blink control bits BL[1:0], see

Table 8. The blink frequencies are derived from the clock frequency. During the blank-out

phase of the blinking period, the display is turned off.

If an external clock with frequency f_clk(ext)is used, the blinking frequency is determined by

Equation 1. For notation, see Section 9.2.

2  n_MUX f_fr f_blink

----------------------------------------------------

f_{blinkeff}

=

(1)

f_clkext

8.2.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)

The waveforms used to drive LCD inherently produce a DC voltage across the display

cell. The PCF8553 compensates for the DC voltage by inverting the waveforms on

alternate frames or alternate lines. The choice of compensation method is determined

with the INV bit.

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Product data sheet

Rev. 3 — 27 March 2015

9 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

8.3 Starting and resetting the PCF8553

If the internal Power-On Reset (POR) is enabled by connecting pin PORE to V_DD, the chip

resets automatically when V_DDrises above the minimum supply voltage. No further action

is required.

If the internal POR is disabled by connecting pin PORE to V_SS, the chip must be reset by

driving the RST pin to logic 0 for at least 10 s, see Figure 4.

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Fig 4. Reset pulse timing

Alternatively a software reset can be applied (see Section 8.3.4).

Following a reset, the register 00h has to be rewritten with 0h by the next command byte

or the address pointer AP[4:0] has to be set to the required address after a new START

procedure.

8.3.1 Power-down mode

After a reset, the PCF8553 remains in power-down mode. In power-down mode the

oscillator is switched off and there is no output on pin CLK. The register settings remain

unchanged and the bus remains active. To enable the PCF8553, bit DE (command

Display_ctrl_1, see Table 7 on page 8) must be set to logic 1.

8.3.2 Power-On Reset (POR)

If pin PORE is connected to V_DD, the PCF8553 comprises an internal POR, which puts the

device into the following starting conditions:

• All backplane and segment outputs are set to V_SS

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• The address pointer is cleared (set to logic 0)

• The display and the internal oscillator are disabled

• The display registers are set to logic 0

Remark: The internal POR can be disabled by connecting pin PORE to V_SS. In this case,

the internal registers are not defined and require a hardware reset according to

Section 8.3.3 or a software reset, see Section 8.3.4.

PCF8553

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

8.3.3 Hardware reset: RST pin

At power-on the PCF8553 can be reset to the following starting conditions by pulling pin

RST low:

• All backplane and segment outputs are set to V_SS

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• The bus interface is initialized

• The address pointer is cleared (set to logic 0)

• The display and the internal oscillator are disabled

• The display registers are set to logic 0

Remark: The hardware reset overrides the POR see Section 8.3.2.

8.3.4 Command: Software_reset

The internal registers including the display registers and the address pointer (set to

logic 0) of the device are reset by the Software_reset command.

Table 9.

Bit

Software_reset - software reset command register (address 00h) bit description

Symbol

Value

Description

software reset

no reset

7 to 0

SR[7:0]

00000000^[1]

00101100

software reset

[1] Default value.

8.4 Display data register mapping

The example in Table 10 and Figure 5 illustrates the segment and backplane mapping of

the display in relation to the display RAM.

For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to

COM3 and the segments are driven by signals SEG0 to SEG39. Contents of addresses

04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost

element and moving forward to the right with increasing bit position. If a bit is logic 0, the

element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB

left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve

COM2 signals, and addresses 13h to 17h serve COM3 signals.

For displays with fewer segments/elements the unused bits are ignored.

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

Table 10. Register to segment and backplane mapping

Backplanes^[1]Segments

SEG0 to SEG7

SEG8 to SEG15

LSB MSB

SEG16 to SEG23

LSB MSB

SEG24 to SEG31

LSB MSB

SEG32 to SEG39

LSB MSB

LSB

MSB

1:4 multiplex drive mode

COM0

COM1

COM2

COM3

content of 04h

content of 09h

content of 05h

content of 0Ah

content of 0Fh

content of 14h

content of 06h

content of 0Bh

content of 10h

content of 15h

content of 07h

content of 0Ch

content of 11h

content of 16h

content of 08h

content of 0Dh

content of 12h

content of 17h

content of 0Eh

content of 13h

1:3 multiplex drive mode

COM0

COM1

COM2

content of 04h

content of 05h

content of 0Ah

content of 0Fh

content of 06h

content of 0Bh

content of 10h

content of 07h

content of 0Ch

content of 11h

content of 08h

content of 0Dh

content of 12h

content of 09h

content of 0Eh

1:2 multiplex drive mode

COM0

COM1

content of 04h

content of 09h

content of 05h

content of 0Ah

content of 06h

content of 0Bh

content of 07h

content of 0Ch

content of 08h

content of 0Dh

static drive mode

COM0

content of 04h

content of 05h

content of 06h

content of 07h

content of 08h

[1] See also Section 9.3.1 on page 24.

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Product data sheet

Rev. 3 — 27 March 2015

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9. Possible display configurations

The possible display configurations of the PCF8553 depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 11. All

of these configurations can be implemented in the typical systems shown in Figure 7 or

Figure 8.

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Fig 6. Example of displays suitable for PCF8553

Table 11. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix:

segments/

elements

14-segment^[2]

4

3

2

1

160

120

80

20

15

10

5

10

7

160 dots (4  40)

120 (3  40)

5

80 dots (2  40)

40 dots (1  40)

40

2

[1] 7 segment display has 8 segments/elements including the decimal point.

[2] 14 segment display has 16 segments/elements including decimal point and accent dot.

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Product data sheet

Rev. 3 — 27 March 2015

14 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least

100 nF is recommended for the supplies.

Fig 7. Typical system configuration using I²C-bus, internal power-on reset enabled

The host microcontroller manages the 2-line I²C-bus communication channel with the

PCF8553. The internal oscillator is used and the internal POR is enabled in the example.

The appropriate biasing voltages for the multiplexed LCD waveforms are generated

internally. The only other connections required to complete the system are the reset, the

power supplies (V_DD, V_SS, and V_LCD) and the LCD panel chosen for the application.

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The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least

100 nF is recommended for the supplies.

Fig 8. Typical system configuration using SPI-bus, internal power-on reset disabled

The host microcontroller manages the 3-line SPI-bus communication channel with the

PCF8553. The internal oscillator is enabled. The appropriate biasing voltages for the

multiplexed LCD waveforms are generated internally. The only other connections required

to complete the system are reset, the power supplies (V_DD, V_SS, and V_LCD) and the LCD

panel chosen for the application.

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Product data sheet

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15 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between V_LCDand V_SS. These intermediate levels are tapped off

at positions of ¹⁄₃and ²⁄₃, or ¹⁄₂, depending on the bias mode chosen. To keep current

consumption to a minimum, on-chip low-power buffers provide these levels to the display.

9.2 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

Display_ctrl_1 command (see Table 7). The biasing configurations that apply to the

preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 12.

Table 12. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

Bias is calculated with Equation 2

1

---------------------

(2)

1 + a_bias

The values for a_biasare:

a_bias= 1 for ¹⁄₂bias

a_bias= 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 3:

a_b²_ias+ 2a_bias+ n_MUX

n_MUX 1 + a_bias²

V_onRMS

=

-----------------------------------------------------

(3)

V

LCD

where the values for n are

_MUX= 1 for static drive mode

n

n_MUX= 2 for 1:2 multiplex drive mode

n_MUX= 3 for 1:3 multiplex drive mode

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Product data sheet

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16 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

n_MUX= 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 4:

a_b²_ias–2a_bias+ n_MUX

n_MUX 1 + a_bias²

V_offRMS

=

--------------------------------------------------

(4)

V

LCD

Discrimination is a term which is defined as the ratio of the on and off RMS voltages

(V_on(RMS)to V_off(RMS)) across a segment. It can be thought of as a measurement of

contrast. Discrimination is determined from Equation 5:

a²_bias+ 2a_bias+ n

a_bias²– 2a_bias+ n_MUX

V_onRMS

V_offRMS

--------------------------------------------^M-----^U---^X--

(5)

----------------------

D =

=

Using Equation 5, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

9.2.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 9. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(6)

(7)

V

_on(RMS)(see Equation 3) and V_off(RMS)(see Equation 5) are properties of the display

driver and are affected by the selection of a_bias, n_MUX, and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

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PCF8553

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Product data sheet

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18 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.2.2 LCD drive mode waveforms

9.2.2.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (COMn) and segment (SEGn) drive waveforms for this mode are shown in

Figure 10.

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V_state1(t) = V_SEGn(t)  V_COM0(t).

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V

.

V_state2(t) = V_{(SEGn + 1)}(t)  V_COM0(t).

V_off(RMS)= 0 V.

Fig 10. Static drive mode waveforms

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.2.2.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF8553 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 11 and

Figure 12.

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V_on(RMS)= 0.791V_LCD

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V_off(RMS)= 0.354V_LCD

.

Fig 11. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCF8553

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Product data sheet

Rev. 3 — 27 March 2015

20 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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V_state1(t) = V_SEGn(t)  V_COM0(t).

V_on(RMS)= 0.745V_LCD

.

V_state2(t) = V_SEGn(t)  V_COM1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 12. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCF8553

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Product data sheet

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21 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.2.2.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 13.

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V_on(RMS)= 0.638V_LCD

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_off(RMS)= 0.333V_LCD

.

V

.

Fig 13. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCF8553

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Product data sheet

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22 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.2.2.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 14.

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V_state1(t) = V_SEGn(t)  V_COM0(t).

_on(RMS)= 0.577V_LCD

V_state2(t) = V_SEGn(t)  V_COM1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 14. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

PCF8553

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Product data sheet

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23 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

9.3 Backplane and segment outputs

9.3.1 Backplane outputs

The LCD drive section includes four backplane outputs COM0 to COM3, which must be

directly connected to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode, COM3 carries the same signal as COM1, therefore these

two outputs can be tied together to give enhanced drive capabilities

• In 1:2 multiplex drive mode, COM0 and COM2, respectively, COM1 and COM3 all

carry the same signals and may also be paired to increase the drive capabilities

• In static drive mode, the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements

9.3.2 Segment outputs

The LCD drive section includes 40 segment outputs SEG0 to SEG39, which must be

directly connected to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display registers.

When less than 39 segment outputs are required, the unused segment outputs must be

left open-circuit.

PCF8553

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Product data sheet

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24 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

10. Power Sequencing

10.1 Power-on

To avoid unwanted artifacts on the display, V_LCDmust never be asserted before V_DD, it is

permitted to assert V_DDand V_LCDat the same time.

10.2 Power-off

Before turning the power to the device off, the display must be disabled by setting bit DE

to logic 0. To avoid unwanted artifacts on the display, V_LCDmust never be connected,

while V_DDis switched off. It is permitted to switch off V_DDand V_LCDsimultaneously.

10.3 Power sequences

Figure 15 depicts the recommended power-up and power-off sequence.

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Fig 15. Recommended power-up and power-off sequence

PCF8553

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Product data sheet

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25 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

11. Bus interfaces

11.1 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs. The two

lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy. Both data and clock lines remain HIGH when the bus is not

busy. The PCF8553 acts as a slave receiver when being written to and as a slave

transmitter when being read from.

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11.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the data line at this time

are interpreted as STOP or START conditions.

PCF8553

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Product data sheet

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26 of 55

PCF8553

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40 × 4 LCD segment driver

11.1.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 17).

11.1.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitted, it must

generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

Remark: The PCF8553 omits the not-acknowledge. After the last byte read, the end of

transmission is indicated by a STOP or START condition from the master.

A detailed description of the I²C-bus specification is given in Ref. 12 “UM10204”.

11.1.4 I²C interface protocol

The PCF8553 uses the I²C interface for data transfer. Interpretation of the data is

determined by the interface protocol.

11.1.4.1 Write protocol

After the I²C slave address is transmitted, the PCF8553 requires that the register address

pointer is defined. It can take the value 00h to 17h. Values outside of that range will result

in the transfer being ignored, however the slave will still respond with acknowledge

pulses.

After the register address has been transmitted, write data is transmitted. The minimum

number of data write bytes is 0 and the maximum number is unlimited. After each write,

the address pointer increments by one. After address 17h, the address pointer stops

incrementing at 18h.

• I²C START condition

• I²C slave address + write

• start register pointer

• write data

• :

• write data

• I²C STOP condition; an I²C RE-START condition is also possible.

PCF8553

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Product data sheet

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PCF8553

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40 × 4 LCD segment driver

11.1.4.2 Read protocol

When reading the PCF8553, reading starts at the current position of the address pointer.

The address pointer for read data should first be defined by a write sequence.

• I²C START condition

• I²C slave address + write

• start address pointer

• I²C STOP condition; an I²C RE-START condition is also possible.

After setting the address pointer, a read can be executed. After the I²C slave address is

transmitted, the PCF8553 will immediately output read data. After each read, the address

pointer increments by one. After address 17h, the address pointer stops incrementing at

18h.

• I²C START condition

• I²C slave address + read

• read data (master sends acknowledge bit)

• :

11.1.4.3 I²C-bus slave address

Device selection depends on the I²C-bus slave address. Four different I²C-bus slave

addresses can be used to address the PCF8553 (see Table 13).

Table 13. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

0

1

0

A1

A0

R/W

The least significant bit of the slave address byte is bit R/W (see Table 14).

Table 14. R/W-bit description

R/W

0

Description

write data

read data

1

Bit 1 and bit 2 of the slave address are defined by connecting the input pins A0 and A1 to

either V_SS(logic 0) or V_DD(logic 1). Therefore, four instances of PCF8553 can be

distinguished on the same I²C-bus.

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11.2 SPI-bus interface

Data transfer to the device is made via a 3-line SPI-bus (see Table 15). There is no

dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin CE

is pulled down.

Table 15. Serial interface

Symbol Function

Description

CE

chip enable input^[1]; active LOW when HIGH, the interface is reset

SCL

SDIO

serial clock input

input may be higher than V_DD

serial data input/output

input data are sampled on the rising edge of SCL,

output data are valid after the falling edge of SCL

[1] The chip enable must not be wired permanently LOW.

11.2.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a byte

with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the register address comprising of the address pointer and the R/W bit.

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Fig 18. Data transfer overview

Table 16. Address byte definition

Bit

Symbol

Value

Description

7

R/W

data read or write selection

write data

0

1

read data

6 to 5

-

00

default value

4 to 0 AP[4:0]

pointer to register start address

valid range; other addresses are ignored

00h to 17h

After the register address byte, the register contents follows with the address pointer

being auto-incremented after every eighth bit sent (see Section 8.1 on page 6).

11.2.1.1 Write protocol

After the CE is set LOW, the PCF8553 requires that R/W and the register address pointer

is defined. It can take the value 00h to 17h. Values outside of that range will result in the

transfer being ignored.

After the register address has been transmitted, write data is transmitted. The minimum

number of data write bytes is 0 and the maximum number is unlimited. After each write,

the address pointer increments by one. After address 17h, the address pointer stops

incrementing at 18h.

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• CE set LOW

• R/W = 0 and register address

• write data

• :

• write data

• CE set HIGH

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Data transfers are terminated by de-asserting CE (set CE to logic 1).

Fig 19. SPI-bus write example: writing two data bytes to registers 00h and 01h

11.2.1.2 Read protocol

When reading the PCF8553, reading starts at the defined position of the address pointer.

After setting the address pointer, the read can be executed. After each read, the address

pointer increments by one. After address 17h, the address pointer stops incrementing at

18h.

• CE set LOW

• R/W = 1 and register address

• read data

• :

• CE set HIGH

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Data transfers are terminated by de-asserting CE (set CE to logic 1).

Fig 20. SPI-bus read example: reading two data bytes from registers 04h and 05h

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PCF8553

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40 × 4 LCD segment driver

11.3 EMC detection

The PCF8553 is ruggedized against EMC susceptibility; however it is not possible to

cover all cases. To detect if a severe EMC event has occurred, it is possible to check the

responsiveness of the device by reading its registers.

12. Internal circuitry

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Fig 21. Device protection diagram

13. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

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40 × 4 LCD segment driver

14. Limiting values

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_LCD

V_I

Parameter

Conditions

Min

0.5

10

50

-

Max

+6.5

+10

+50

100

Unit

V

supply voltage

LCD supply voltage

input voltage

V

V_O

output voltage

V

I_I

input current

mA

mW

I_O

output current

I_DD

supply current

I_DD(LCD)

I_SS

LCD supply current

ground supply current

total power dissipation

output power

P_tot

P_o

-

[1]

V_ESD

electrostatic discharge

voltage

HBM

on pins SCL and SDA/CE

on all other pins

CDM

-

2000

5000

1500

200

V

-

V

[2]

[3]

[4]

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

55

40

+150

+85

operating device

[1] Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.

[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

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40 × 4 LCD segment driver

15. Characteristics

Table 18. Electrical characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 5.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

-

5.5

V

V_LCD

I_DD

LCD supply voltage

supply current

f_fr= 64 Hz; no bus activity

V_DD= 3.3 V; T_amb= 25 C

V_DD= 5.5 V; T_amb= 85 C

f_fr= 64 Hz; no bus activity

-

0.6

1.2

-

A

2.7

[1]

I_DD(LCD)

LCD supply current

V_LCD= 5.5 V;

T_amb= 85 C;

BOOST = 0;

no display load

-

3.2

4.5

A

V_LCD= 3.3 V;

T_amb= 25 C

BOOST = 0;

no display load

-

2.5

5.0

-

A

BOOST = 0;

display enabled;

display load C_L= 1.6 nF

BOOST = 1;

-

6.0

-

A

display enabled;

display load C_L= 1.6 nF

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

V_SS

-

0.3V_DD

V_DD

V

[2]

0.7V_DD

output sink current;

V_OL= 0.4 V; V_DD= 5 V

on pin CLK

on pin SDIO

on pin SDA

2

3

2

-

mA

I_OH

HIGH-level output current output source current;

on pins SDIO, CLK;

V_OH= 4.6 V; V_DD= 5 V

I_L

leakage current

any input pin except for RST

after ESD event

-

0

-

nA

k

500

-

+500

-

R_{pu(RST_n)}pull-up resistance on pin

RST_N

-

100

LCD outputs (pins SEG0 to SEG39 and COM0 to COM3)

V_o

output voltage variation

output resistance

V_LCD= 5 V

100

-

+100

3

mV

[3]

R_o

-

1.5

k

[1] For typical values, also see Figure 22 to Figure 24.

[2] I²C pins SCL and SDA have no diode to V_DDand may be driven up to 5.5 V.

[3] Outputs measured one at a time.

PCF8553

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Product data sheet

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33 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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V_DD= 5.5 V, V_LCD= 5.5 V; power-down mode.

(1) I_DD

(2) I_DD(LCD)

.

Fig 22. Typical I_DDand I_DD(LCD)in power-down mode as function of temperature

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T_amb= 25 C; V_LCD= 3.3 V; V_DD= 3.3 V; f_fr= 64 Hz, BOOST = 0.

(1) Static, all segments/elements off.

(2) Static, all segments/elements on.

(3) MUX 1:2, bias level ¹⁄₂, all segments/elements off.

(4) MUX 1:2, bias level ¹⁄₂, all segments/elements on.

(5) MUX 1:3, bias level ¹⁄₃, all segments/elements off.

(6) MUX 1:3, bias level ¹⁄₃, all segments/elements on.

(7) MUX 1:4, bias level ¹⁄₃, all segments/elements off.

(8) MUX 1:4, bias level ¹⁄₃, all segments/elements on.

Fig 23. Typical I_DD(LCD)as function of display load

PCF8553

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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T_amb= 25 C; V_LCD= 3.3 V; V_DD= 3.3 V; f_fr= 64 Hz, BOOST = 0, C_L= 1.6 nF.

(1) Static, all segments/elements off.

(2) Static, all segments/elements on.

(3) MUX 1:2, bias level ¹⁄₂, all segments/elements off.

(4) MUX 1:2, bias level ¹⁄₂, all segments/elements on.

(5) MUX 1:3, bias level ¹⁄₃, all segments/elements off.

(6) MUX 1:3, bias level ¹⁄₃, all segments/elements on.

(7) MUX 1:4, bias level ¹⁄₃, all segments/elements off.

(8) MUX 1:4, bias level ¹⁄₃, all segments/elements on.

Fig 24. Typical I_DD(LCD)as function of f_fr

Table 19. Frequency characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 5.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

-

Typ

32

64

96

128

1024

-

Max

Unit

Hz

s

f_fr

frame frequency

FF[1:0] = 00

-

FF[1:0] = 01

42

-

86

FF[1:0] = 10

-

FF[1:0] = 11

-

[1]

f_clk(int)

f_clk(ext)

t_clk(H)

t_clk(L)

internal clock frequency

external clock frequency

HIGH-level clock time

LOW-level clock time

reset pulse width

f_fr= 64 Hz, n_MUX= 4

-

4096

external clock

on pin RST

60

10

-

s

t_w(rst)

-

s

[1]

f

_clkint= 2  f_fr n_MUXor f_clkext= 2  f_fr n_MUXrespectively (see Table 6 and Table 7).

PCF8553

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Product data sheet

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35 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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(1) n_MUX= 1.

(2) _MUX= 2.

n

(3) n_MUX= 3.

(4) n_MUX= 4.

Fig 25. Relation of frame frequency (f_fr), clock frequency (f_clk) and multiplex-rate (n_MUX

)

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

Table 20. I²C-bus characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified; all timing values are valid within the

[1]

operating supply voltage and T_ambrange and are referenced to V_ILand V_IHwith an input voltage swing of V_SSto V_DD

.

Symbol

Pin SCL

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

SCL clock frequency

-

400

-

kHz

t_LOW

LOW period of the SCL

clock

1.3

s

t_HIGH

HIGH period of the SCL

clock

0.6

-

s

Pin SDA

t_SU;DAT

data set-up time

data hold time

100

0

-

ns

t_HD;DAT

Pins SCL and SDA

t_BUF

bus free time between a

1.3

-

s

STOP and START

condition

t_SU;STO

t_HD;STA

t_SU;STA

t_r

set-up time for STOP

condition

0.6

-

s

pF

ns

hold time (repeated)

START condition

0.6

-

set-up time for a repeated

START condition

0.6

-

rise time of both SDA and f_SCL= 400 kHz

SCL signals

-

0.3

400

50

t_f

fall time of both SDA and

SCL signals

C_b

capacitive load for each

bus line

t_w(spike)

spike pulse width

on the I²C-bus

[1] The I²C-bus interface of PCF8553 is 5 V tolerant.

PCF8553

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Product data sheet

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37 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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Fig 26. I²C-bus timing waveforms

Table 21. SPI-bus characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified; all timing values are valid within the

operating supply voltage and T_ambrange and are referenced to V_ILand V_IHwith an input voltage swing of V_SSto V_DD

.

Symbol

Pin SCL

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

SCL clock frequency

-

5

-

MHz

ns

t_LOW

LOW period of the SCL

clock

150

t_HIGH

HIGH period of the SCL

clock

80

-

ns

t_r

rise time

fall time

-

100

ns

t_f

Pin CE

t_{su(CE_N)}

t_{h(CE_N)}

t_{rec(CE_N)}

Pin SDIO

t_su

CE_N set-up time

CE_N hold time

30

10

70

-

ns

CE_N recovery time

set-up time

write data

C_L= 50 pF

no load

5

50

-

ns

t_h

hold time

-

t_d(R)SDIO

t_dis(SDIO)

SDIO read delay time

SDIO disable time

150

50

-

t_t(SDI-SDO)transition time from SDI to write to read mode

SDO

0

PCF8553

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Product data sheet

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PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

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Fig 27. SPI-bus timing waveforms

16. Application information

16.1 Power-on with a slowly starting power supply

The built-in POR block acts on the rising edge of the V_DDsupply voltage. It is designed to

react to fast slopes. If the system supply starts slowly, it is recommended to initiate a

software reset immediately after power-on.

16.2 I²C acknowledge after power-on

If the bus does not show an acknowledge at the first access, the command should be sent

a second time.

16.3 Resistors on I/O pins

The pins A0, A1, PORE, and IFS comprise internal, latching pull-down devices, which

keep these inputs at a low potential when left open. If an input is supposed to be at logic 0

potential, this pin can be either connected to V_SSor left open.

In case a pin is supposed to be at logic 1 potential, it must be connected to V_DDto avoid

any cross-current during power-up. A series resistance between V_DDand the associated

pin must not exceed 1 k to ensure proper functionality.

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17. Package outline

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Fig 28. Package outline SOT364-1 (TSSOP56) of PCF8553DTT

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18. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

19. Packing information

19.1 Tape and reel information

For tape and reel packing information, see Ref. 11 “SOT364-1_118” on page 48.

20. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

20.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

20.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

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• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

20.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

20.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 22 and 23

Table 22. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 23. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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21. Footprint information

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PCF8553

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23. Abbreviations

Table 25. Abbreviations

Acronym

CDM

DC

Description

Charged-Device Model

Direct Current

EMC

ESD

HBM

I²C

ElectroMagnetic Compatibility

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit bus

Integrated Circuit

IC

LCD

LSB

MSB

MSL

MUX

PCB

POR

RC

Liquid Crystal Display

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Multiplexer

Printed-Circuit Board

Power-On Reset

Resistance-Capacitance

Root Mean Square

Serial CLock line

RMS

SCL

SDA

SMD

SPI

Serial DAta line

Surface-Mount Device

Serial Peripheral Interface

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24. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — ESD and EMC sensitivity of IC

[3] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] SOT364-1_118 — TSSOP56; Reel pack; SMD, 13", packing information

[12] UM10204 — I²C-bus specification and user manual

[13] UM10569 — Store and transport requirements

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25. Revision history

Table 26. Revision history

Document ID

PCF8553 v.3

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20150327

Product data sheet

-

PCF8553 v.2

• Fixed typo

• Added Figure 4

PCF8553 v.2

PCF8553 v.1

20150216

Product data sheet

-

PCF8553 v.1

-

20141205

Objective data sheet

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26. Legal information

26.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

26.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

26.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

26.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

27. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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28. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description of PCF8553DTT (TSSOP56) . .5

Table 5. Registers of the PCF8553 . . . . . . . . . . . . . . . . .6

Table 6. Device_ctrl - device control command register

(address 01h) bit description . . . . . . . . . . . . . . .7

Table 7. Display_ctrl_1 - display control command 1

register (address 02h) bit description . . . . . . . .8

Table 8. Display_ctrl_2 - display control command 2

register (address 03h) bit description . . . . . . . .9

Table 9. Software_reset - software reset command

register (address 00h) bit description . . . . . . .11

Table 10. Register to segment and backplane mapping .12

Table 11. Selection of possible display configurations . . .14

Table 12. Biasing characteristics . . . . . . . . . . . . . . . . . . .16

Table 13. I²C slave address byte . . . . . . . . . . . . . . . . . . .28

Table 14. R/W-bit description . . . . . . . . . . . . . . . . . . . . . .28

Table 15. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 16. Address byte definition . . . . . . . . . . . . . . . . . . .29

Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 18. Electrical characteristics . . . . . . . . . . . . . . . . .33

Table 19. Frequency characteristics . . . . . . . . . . . . . . . .35

Table 20. I²C-bus characteristics . . . . . . . . . . . . . . . . . . .37

Table 21. SPI-bus characteristics . . . . . . . . . . . . . . . . . .38

Table 22. SnPb eutectic process (from J-STD-020D) . . .42

Table 23. Lead-free process (from J-STD-020D) . . . . . .42

Table 24. Selection of LCD segment drivers . . . . . . . . . .45

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .49

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29. Figures

Fig 1. Block diagram of PCF8553 . . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration of PCF8553DTT (TSSOP56) . . .4

Fig 3. Address counter incrementing. . . . . . . . . . . . . . . .7

Fig 4. Reset pulse timing . . . . . . . . . . . . . . . . . . . . . . . .10

Fig 5. Display RAM organization bitmap for MUX 1:4 . .13

Fig 6. Example of displays suitable for PCF8553 . . . . .14

Fig 7. Typical system configuration using I²C-bus,

internal power-on reset enabled . . . . . . . . . . . . .15

Fig 8. Typical system configuration using SPI-bus,

internal power-on reset disabled . . . . . . . . . . . . .15

Fig 9. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .18

Fig 10. Static drive mode waveforms. . . . . . . . . . . . . . . .19

Fig 11. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 13. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 14. Waveforms for the 1:4 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 15. Recommended power-up and power-off

sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 16. I²C read and write protocol . . . . . . . . . . . . . . . . .26

Fig 17. I²C read and write signaling. . . . . . . . . . . . . . . . .26

Fig 18. Data transfer overview. . . . . . . . . . . . . . . . . . . . .29

Fig 19. SPI-bus write example: writing two data bytes

to registers 00h and 01h . . . . . . . . . . . . . . . . . . .30

Fig 20. SPI-bus read example: reading two data bytes

from registers 04h and 05h . . . . . . . . . . . . . . . . .30

Fig 21. Device protection diagram. . . . . . . . . . . . . . . . . .31

Fig 22. Typical I_DDand I_DD(LCD)in power-down mode

as function of temperature. . . . . . . . . . . . . . . . . .34

Fig 23. Typical I_DD(LCD)as function of display load . . . . .34

Fig 24. Typical I_DD(LCD)as function of f_fr. . . . . . . . . . . . . .35

Fig 25. Relation of frame frequency (f_fr), clock

frequency (f_clk) and multiplex-rate (n_MUX) . . . . . .36

Fig 26. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .38

Fig 27. SPI-bus timing waveforms . . . . . . . . . . . . . . . . .39

Fig 28. Package outline SOT364-1 (TSSOP56)

of PCF8553DTT. . . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 29. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 30. Footprint information for reflow soldering

of SOT364-1 (TSSOP56) of PCF8553DTT . . . . .44

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 27 March 2015

53 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

30. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

10.3

Power sequences . . . . . . . . . . . . . . . . . . . . . 25

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

11

11.1

11.1.1

11.1.2

11.1.3

11.1.4

Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 26

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . 26

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

START and STOP conditions. . . . . . . . . . . . . 27

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27

I²C interface protocol . . . . . . . . . . . . . . . . . . . 27

3

4

4.1

5

6

11.1.4.1 Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . 27

11.1.4.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . 28

11.1.4.3 I²C-bus slave address . . . . . . . . . . . . . . . . . . 28

11.2

11.2.1

11.2.1.1 Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . 29

11.2.1.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . 30

11.3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 29

Data transmission . . . . . . . . . . . . . . . . . . . . . 29

8

8.1

8.2

Functional description . . . . . . . . . . . . . . . . . . . 6

Registers of the PCF8553 . . . . . . . . . . . . . . . . 6

Command registers of the PCF8553 . . . . . . . . 7

Command: Device_ctrl . . . . . . . . . . . . . . . . . . . 7

Internal oscillator and clock output . . . . . . . . . . 7

Command: Display_ctrl_1. . . . . . . . . . . . . . . . . 8

Enhanced power drive mode . . . . . . . . . . . . . . 8

Multiplex drive mode. . . . . . . . . . . . . . . . . . . . . 8

Command: Display_ctrl_2. . . . . . . . . . . . . . . . . 9

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Line inversion

EMC detection . . . . . . . . . . . . . . . . . . . . . . . . 31

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 31

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2.1

8.2.1.1

8.2.2

8.2.2.1

8.2.2.2

8.2.3

8.2.3.1

8.2.3.2

12

13

14

15

16

Application information . . . . . . . . . . . . . . . . . 39

Power-on with a slowly starting power supply 39

I²C acknowledge after power-on . . . . . . . . . . 39

Resistors on I/O pins . . . . . . . . . . . . . . . . . . . 39

16.1

16.2

16.3

(driving scheme A)

and frame inversion

17

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Handling information . . . . . . . . . . . . . . . . . . . 41

Packing information . . . . . . . . . . . . . . . . . . . . 41

Tape and reel information . . . . . . . . . . . . . . . 41

(driving scheme B) . . . . . . . . . . . . . . . . . . . . . . 9

Starting and resetting the PCF8553 . . . . . . . . 10

Power-down mode . . . . . . . . . . . . . . . . . . . . . 10

Power-On Reset

(POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hardware reset: RST pin . . . . . . . . . . . . . . . . 11

Command: Software_reset. . . . . . . . . . . . . . . 11

Display data register mapping . . . . . . . . . . . . 11

8.3

8.3.1

8.3.2

18

19

19.1

20

Soldering of SMD packages. . . . . . . . . . . . . . 41

Introduction to soldering. . . . . . . . . . . . . . . . . 41

Wave and reflow soldering. . . . . . . . . . . . . . . 41

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 42

8.3.3

8.3.4

8.4

20.1

20.2

20.3

20.4

9

9.1

9.2

9.2.1

9.2.2

9.2.2.1

9.2.2.2

9.2.2.3

9.2.2.4

9.3

Possible display configurations. . . . . . . . . . . 14

LCD bias generator . . . . . . . . . . . . . . . . . . . . 16

LCD voltage selector . . . . . . . . . . . . . . . . . . . 16

Electro-optical performance . . . . . . . . . . . . . . 17

LCD drive mode waveforms . . . . . . . . . . . . . . 19

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 19

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 20

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 22

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 23

Backplane and segment outputs . . . . . . . . . . 24

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 24

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 24

21

Footprint information . . . . . . . . . . . . . . . . . . . 44

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

LCD segment driver selection . . . . . . . . . . . . 45

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

22

22.1

23

24

25

26

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

26.1

26.2

26.3

26.4

9.3.1

9.3.2

10

10.1

10.2

Power Sequencing. . . . . . . . . . . . . . . . . . . . . . 25

Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

27

Contact information . . . . . . . . . . . . . . . . . . . . 51

continued >>

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 27 March 2015

54 of 55

PCF8553

NXP Semiconductors

40 × 4 LCD segment driver

28

29

30

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 March 2015

Document identifier: PCF8553


型号：	PCF8553DTT/AJ
厂家：	NXP
描述：	PCF8553 - 40 × 4 LCD segment driver TSSOP 56-Pin PC 驱动 CD 接口集成电路
文件：	总55页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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