PCF8558U [NXP]
Universal LCD driver for small graphic panels; 对于小图形板通用LCD驱动
| 型号： | PCF8558U |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for small graphic panels |
| 文件： | 总24页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8558
Universal LCD driver for small
graphic panels
1998 Apr 07
Objective specification
Supersedes data of 1997 Feb 27
File under Integrated Circuits, IC12
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
FEATURES
• Single-chip LCD controller/driver
• 40 row and 101 column outputs
• Display data RAM
40 × 101 bits = 505 bytes = 4040 bits
• On-chip:
GENERAL DESCRIPTION
– Generation of intermediate LCD bias voltages
The PCF8558 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 40 rows and
101 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD bias voltages, resulting in a minimum of external
components and lower power consumption.
– Oscillator requires no external components
(external clock also possible)
• 400 kHz fast I2C-bus interface
• CMOS compatible
• MUX rate 1 : 40
The PCF8558 interfaces to most microcontrollers via a
I2C-bus interface.
• Logic supply voltage range VDD − VSS = 2.5 to 6 V
• Display supply voltage range VDD − VLCD = 3.5 to 9 V
• Low power consumption, suitable for battery operated
systems.
APPLICATIONS
• Telecom equipment
• Portable instruments
• Point of sale terminals
• Alarm systems.
ORDERING INFORMATION
TYPE
PACKAGE(1)
NUMBER
NAME
DESCRIPTION
VERSION
PCF8558U/10
PCF8558U/12
−
−
chip on FFC
−
−
chip with bumps on FFC
Note
1. For further details see Chapter “Bonding pad locations”.
1998 Apr 07
2
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
BLOCK DIAGRAM
C1 to C101
R1 to R40
COLUMN DRIVERS
DATA LATCHES
ROW DRIVERS
BIAS
VOLTAGE
GENERATOR
SHIFT REGISTER
OSCILLATOR
V
LCD
CURSOR AND
DATA CONTROL
OSC
V
DD
TIMING
GENERATOR
V
SS
T1
DISPLAY DATA RAM
505 BYTES
T3
DISPLAY
ADDRESS
COUNTER
ADDRESS
COUNTER
T2
POWER-ON
RESET
DATA
REGISTER
PCF8558
I/O BUFFER
MGG558
SDA SCL
SA0
Fig.1 Block diagram.
3
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
PINNING
SYMBOL
SCL
PAD
DESCRIPTION
1
I2C-bus serial clock input
R20 to R1
C101 to C1
R21 to R40
T2
2 to 21
LCD row driver data outputs
22 to 122 LCD column driver data outputs
123 to 142 LCD row driver data outputs
143
144
145
146
147
148
test pad output, must be left unconnected (not user accessible)
I2C-bus serial data input/output
SDA
VSS
ground
T1
test pad input, must be connected to VSS (not user accessible)
VLCD
negative supply voltage input
SA0
the LSB bit of the I2C-bus slave address input is set by connecting this pin to either
0 (VSS) or 1 (VDD
)
T3
149
150
test pad input, must be connected to VDD (not user accessible)
OSC
when the on-chip oscillator is used this pin must be connected to VDD; an external clock
signal, if used, is input at this pin
VDD
151
positive supply voltage
1998 Apr 07
4
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
Display Data RAM (DDRAM). Both registers can be written
to but not read from by the system controller.
FUNCTIONAL DESCRIPTION
LCD bias voltage generator
Address Counter (AC)
The intermediate bias voltages for the LCD display are
generated and buffered on-chip. This removes the need
for an external resistor bias chain and significantly reduces
the system power consumption.
The address counter assigns addresses to the DDRAM for
writing and is set by Y2 to Y0 in the command and
X6 to X0 in the address. After a write operation the
address counter is automatically incremented by 1 in
accordance with the V flag.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
Display Data RAM (DDRAM)
the OSC pin must be connected to VDD
.
The PCF8558 contains a 40 × 101-bit static RAM which
stores the display data. The RAM is divided into 5 banks of
101 bytes (5 × 8 × 101 bits). During RAM access, data is
transferred to the RAM via the I2C-bus. There is a direct
correspondence between the X address and the column
output number.
External clock
If an external clock is to be used it is input at the OSC pin.
The resulting display frame frequency is given by
fOSC
fframe
=
.
------------
3072
Timing generator
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD will
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
be frozen in a state where a DC voltage is applied to it.
Power-on reset
Display control
The on-chip power-on reset block initializes the chip after
power-on or power failure. This is a synchronous reset and
requires 2 oscillator cycles to execute. These oscillator
cycles must be provided from the external clock source if
the internal oscillator is not used. If this is not done, the
device may not respond to command sequences
transmitted via the I2C-bus interface.
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command word.
LCD row and column drivers
The PCF8558 contains 40 row and 101 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 3 illustrates typical waveforms. Unused
outputs should be left unconnected.
Power-down
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no internal
power-on reset, no bias level generation and all LCD
outputs are internally connected to VDD) when
PD = logic 1.
The bias voltage levels, V2 to V5, are chosen to give
optimum display contrast for a multiplex rate of 1 : 40.
During power-down the information in the RAMs and the
internal chip states are preserved. Instruction execution
during power-down is possible if an externally clock signal
is applied to pad OSC.
Table 1 Voltage bias levels
LEVEL
VOLTAGE
V2
V3
V4
V5
0.8635 × (VDD − VLCD
0.7270 × (VDD − VLCD
0.2730 × (VDD − VLCD
0.1365 × (VDD − VLCD
)
)
)
)
Registers
The PCF8558 has one 8-bit register, time shared as a
Command Register (CR) and a Data Register (DR).
The command register stores the command code such as
display on or display off and address information for the
1998 Apr 07
5
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
RAM
bank 0
top of LCD
bank 1
bank 2
bank 3
LCD
bank 4
MGG559
Fig.2 DDRAM to display mapping.
6
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
V
V
(t)
(t)
frame n
frame n + 1
state 1
state 2
V
DD
V
2
V
ROW 1
R1 (t)
3
V
V
V
4
5
LCD
V
V
V
V
V
V
DD
2
ROW 2
R2 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
COL 1
C1 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
3
COL 2
C2 (t)
4
5
LCD
V
OP
0.7269V
OP
0.2731V
0 V
OP
V
(t)
state 1
0.2731V
OP
OP
0.7269V
V
OP
V
OP
0.7269V
OP
OP
0.2731V
0 V
V
(t)
state 2
0.2731V
OP
OP
0.7269V
V
OP
MGG560
1 2 3 4 5 6 7 8 9
... 40 1 2 3 4 5 6 7 8 9
... 40
Vstate1(t) = C2(t) − R1(t); Vstate2(t) = C2(t) − R2(t)
.
Fig.3 Typical LCD driver waveforms (MUX rate 1 : 40).
7
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
ADDRESSING
The data is downloaded into the matrix of the PCF8558 as indicated in Figs 4 and 5.
The display RAM has a matrix of 40 by 101 bits (5 by 101 bytes). The columns are addressed by the address pointer.
After writing one byte the pointer is set to the next byte. Control of address increment, horizontal or vertical, is by bit V in
the command byte.
LSB
display line 0 to 7
000
display line 8 to 15
display line 16 to 23
display line 24 to 31
display line 32 to 39
001
010 Y address
011
100
MSB
X
address 2
address 1
address 0
address 98
address 99
address 100
MGG561
Fig.4 RAM format, addressing.
DATA STRUCTURE
0 5
0
1
2
. . .
1 6
2 7
3 8
4 9
101 102 103 . . .
202 203 204 . . .
303 304 305 . . .
404 405 406 . . .
MGG562
a. Order of writing data bytes into RAM (V = 1).
b. Order of writing data bytes into RAM (V = 0).
Fig.5 Order of writing data bytes into RAM.
1998 Apr 07
8
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
I2C-BUS PROTOCOL
automatically incremented, enabling a stream of data to be
transferred to the DDRAM.
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8558. The least-significant bit of
the slave address is set by connecting input SA0 to
either 0 (VSS) or 1 (VDD). Therefore, two PCF8558 can be
used on the same I2C-bus allowing displays of up to
80 × 101 or 40 × 202 dots to be driven.
The instruction format is composed of I2C-bus slave
address followed by one command byte, one X address
pointer, followed by any number of data bytes.
Command execution/storing of data takes place during the
acknowledge cycle.
The I2C-bus protocol is shown in Fig.6.
Definitions
All communications are initiated with a START condition
(S) from the I2C-bus master, which is followed by the
desired slave address and write bit. All devices with this
slave address acknowledge in parallel. All other devices
ignore the bus transfer.
• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
In write mode (indicated by setting the read/write bit LOW)
one or more commands follow the slave address
acknowledgement. The commands are also
• Slave: the device addressed by a master
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C. After
the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
addressed device. After the last data byte has been
acknowledged, the I2C-bus master issues a STOP
condition (P).
• Multi-master: more than one master can attempt to
control the bus at the same time. The I2C-bus can
accommodate this without data los/contention.
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
For PCF8558, no read mode is provided.
Display bytes are written into the RAM at the address
specified by the data pointer and subaddress counter.
Both the data pointer and subaddress counter are
R/W
S
A
O
A
C
K
A
C
K
A
C
K
A
C
K
S
0
1
1
1
1
0
P
COMMAND
X ADDRESS
DISPLAY DATA
slave address
N ≥ 0 bytes
MGG563
Fig.6 I2C-bus protocol.
1998 Apr 07
9
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
COMMANDS
Set X address
The X address points to the columns. The range of X is
0 to 100 (64H).
Display Control
BIT
PD
LOGIC 0
normal
horizontal addressing vertical addressing
LOGIC 1
Reset function
power-down
V
After power-on the chip has the following state:
• Power-down mode (PD = 1)
Table 2 Display status
• RAM undefined
BITS
• RAM X and Y address undefined
• Display control bits (except PD) undefined
• I2C-bus interface reset.
DISPLAY STATUS
E
D
Blank
0
1
1
0
0
1
0
1
Normal
Note
All segments on
Inverse video
If the chip is used with an external clock source, after
power-on, the chip requires at least 2 clock pulses to
ensure that an internal synchronous reset is carried out.
After the internal reset, the chip goes into power-down
mode (PD = 1). If the clock pulses are not supplied, and
the reset is not cleared, the chip cannot respond to
commands in the I2C bus.
PD: POWER-DOWN
• All LCD outputs at VDD (display off)
• Bias generator off
• Power-on reset on, oscillator off (external clock still
possible)
In applications where the internal oscillator is used
(pin OSC = VDD), the oscillator starts after power-on.
As soon as the synchronous reset is cleared, the chip goes
into power-down mode, and the oscillator is stopped.
• VLCD can be disconnected
• I2C-bus, RAM, commands, etc. still function in
power-down mode.
Set Address
Table 3 Y0, Y1 and Y2 define the Y address vector
address of the display RAM
Y2
Y1
Y0
LINE
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
2
3
4
Table 4 Instructions: control byte, address
INSTRUCTION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
Display control
X address
0
0
E
D
PD
V
Y2
Y1
Y0 Y address vector, display control
set column address
X address
1998 Apr 07
10
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
CHARACTERISTICS OF THE I2C-BUS
Acknowledge
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
System configuration
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
h
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.7 Bit transfer.
1998 Apr 07
11
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBC622
Fig.8 Definition of START and STOP condition.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.9 System configuration.
12
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
1
2
9
MASTER
S
clock pulse for
acknowledgement
START
condition
MBC602
The general characteristics and detailed specification of the I2C-bus are available on request (order number 9398 393 40011).
Fig.10 Acknowledgment on the I2C-bus.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+8.0
VDD
UNIT
supply voltage
V
V
V
V
V
V
VLCD
Vi1
Vi2
Vo1
Vo2
II
LCD supply voltage
V
V
V
V
V
DD − 11
input voltage T1, T3, SA0 and OSC
input voltage SDA and SCL
output voltage T2 and SDA
output voltage R1 to R40 and C1 to C101
DC input current
SS − 0.5 VDD + 0.5
SS − 0.5 8.0
SS − 0.5 VDD + 0.5
LCD − 0.5 VDD + 0.5
−10
−10
−50
−
+10
+10
+50
400
100
+150
mA
mA
mA
mW
mW
°C
IO
DC output current
IDD, ISS, ILCD
VDD, VSS or VLCD current
power dissipation per package
power dissipation per output
storage temperature
Ptot
Po
−
Tstg
−65
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices.
1998 Apr 07
13
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified, note 1.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD
supply voltage
2.5
−
−
5
6.0
V
VLCD
IDD(PD)
IDD1
LCD supply voltage
V
−
−
−
−
DD − 9
VDD − 3.5 V
supply current in power-down mode
supply current external clock
supply current internal clock
LCD input current
10
µA
µA
µA
µA
V
120
130
50
180
200
100
1.8
IDD2
ILCD
VPOR
power-on reset level
note 2
0.6
1.3
Logic
VIL1
LOW level input voltage (all inputs
except OSC)
VSS
−
−
−
0.3VDD
VDD
V
V
VIH1
HIGH level input voltage (all inputs
except OSC)
0.7VDD
VSS
VIL2
VIH2
IL1
LOW level input voltage (pin OSC)
HIGH level input voltage (pin OSC)
VDD − 1.5 V
VDD − 0.1 −
VDD
+1
5
V
leakage current at T1, T3 OSC and SA0 VI = VDD or VSS
−1
−
−
−
mA
pF
CI1
input capacitance at T1, T3 OSC and
SA0
note 3
LCD outputs
VDC
DC component of LCD drivers R1 to R40
−
±20
−
mV
and C1 to C101
RROW
RCOL
output resistance R1 to R40
output resistance C1 to C101
note 4
note 4
−
−
1.5
3
6
kΩ
kΩ
10
I2C-bus; SDA and SCL
VIL3
VIH3
IL2
LOW level input voltage
note 5
VSS
0.7VDD
−1
−
−
−
−
−
0.3VDD
V
HIGH level input voltage
leakage current
note 5
6
V
VI = VDD or VSS
note 3
+1
7
mA
pF
mA
CI2
IOL
input capacitance
−
LOW level output current at SDA
VOL = 0.4 V;
VDD = 5 V
3.0
−
Notes
1. Outputs are open-circuit; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD < VPOR
3. Periodically sampled, not 100% tested.
.
4. Resistance of output terminals (R1 to R40 and C1 to C101) with IL = 20 µA; VOP = VDD − VLCD = 9 V; outputs
measured one at a time.
5. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow. This current must
not exceed ±0.5 mA.
1998 Apr 07
14
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;
SS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
62.5
MAX.
94
UNIT
Hz
fFR)
LCD frame frequency
(internal oscillator)
37
fOSC(ext)
tPLCD
external clock frequency
driver delays
90
150
225
100
kHz
VDD − VLCD = 9 V;
−
−
µs
with test loads
I2C-bus (see Fig.12)
fSCL
SCL clock frequency
−
−
−
−
−
400
−
kHz
µs
tCLKL
tCLKH
tBUF
SCL LOW time
SCL HIGH time
bus free time
1.3
0.6
1.3
−
µs
between successive STOP
and START conditions
−
µs
tr
SCL and SDA rise time
SCL and SDA fall time
note 1
note 1
−
−
−
−
−
−
−
−
−
−
300
300
−
ns
ns
µs
µs
ns
ns
µs
ns
pF
tf
20 + 0.1Cb
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tSW
START condition set-up time repeated start codes only
START condition hold time
0.6
0.6
100
0
−
data set-up time
−
data hold time
−
STOP condition set-up time
tolerable spike width on bus note 2
capacitive load per bus line
0.6
−
−
50
400
Cb
−
Notes
1. The rise and fall times specified here refer to the driver device (i.e. not PCF8558) and are part of the general fast
I2C-bus specification. However, when PCF8558 asserts an acknowledge on SDA, the fall time is given by parameter
tf. Cb = capacitive load per bus line.
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max)
.
1 nF
1.5 kΩ
R1 to R40,
C1 to C101
SDA
V
DD
MGG564
Fig.11 AC test loads.
15
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
n
SDA
t
t
t
LOW
f
BUF
SCL
SDA
t
t
t
SU;DAT
t
HD;STA
r
t
HIGH
HD;DAT
t
SU;STA
MGA728
t
SU;STO
Fig.12 I2C-bus timing waveforms.
1998 Apr 07
16
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
APPLICATION INFORMATION
The pinning of the PCF8558 is optimized for single plane wiring e.g. for Chip-on-glass display modules.
V
V
V
DD
DD DD
SA0
OSC
R1 to R40
40
40 × 101 dots
full graphic display
V
V
V
V
DD
DD
100
nF
PCF8558
C1 to C101
101
V
LCD
LCD
SS
100 nF
V
SS
SCL SDA
V
SS
SA0
OSC
R1 to R40
40
40 × 101 dots
full graphic display
V
V
V
V
DD
DD
100
nF
PCF8558
C1 to C101
101
V
LCD
SS
LCD
100 nF
V
SS
SCL SDA
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
MGG565
Fig.13 Application using I2C-bus interface.
1998 Apr 07
17
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
handbook, halfpage
9 mm
handbook, halfpage
DISPLAY 40 × 101
4 mm
PCF8558
Y
20
101
20
X
pitch
PCF8558
8
MGG567
supply, I/O
MGG566
Fig.14 Application, display size 40 × 101 pixels.
Fig.15 Bonding pads.
CHIP INFORMATION
The PCF8558 is manufactured in p-well CMOS
technology. VDD − VLCD is positive. The chip substrate is
connected to VDD
.
Bonding pads
Pad pitch
100
80 × 120
59 × 99 × 15
381
µm
µm
µm
µm
Pad size, aluminium
Bump dimensions
Wafer thickness
1998 Apr 07
18
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
BONDING PAD LOCATIONS
R33
C18
R40
dummy 1
~8.95
mm
y
0
0
dummy 6
x
PCF8558
T2
SDA
T1
V
V
SS
LCD
SA0
T3
V
OSC
DD
C95
~3.99 mm
MGG568
Fig.16 Bonding pad locations.
19
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
Table 5 Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to the centre
of the chip, see Fig.16.
SYMBOL
SCL
PAD
x
y
SYMBOL
C81
PAD
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
x
y
1
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−3903.6
−3803.6
−3703.6
−3603.6
−3503.6
−3403.6
−3303.6
−3203.6
−3103.6
−3003.6
−2903.6
−2803.6
−2703.6
−2603.6
1280.0
1005.8
905.8
−2503.6
−2403.6
−2303.6
−2203.6
−2103.6
−2003.6
−1814.6
−1714.6
−1614.6
−1514.6
−1414.6
−1314.6
−1214.6
−1114.6
−1014.6
−914.6
−814.6
−714.6
−614.6
−514.6
−414.6
−314.6
−214.6
−114.6
−14.6
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
2
C80
C79
C78
C77
C76
C75
C74
C73
C72
C71
C70
C69
C68
C67
C66
C65
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
3
4
805.8
5
705.8
6
605.8
7
505.8
8
405.8
9
305.8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
205.8
105.8
5.8
−94.3
R8
−194.3
−383.3
−483.3
−583.3
−683.3
−783.3
−883.3
−983.3
−1083.3
−1183.3
−1283.3
−1383.3
−1483.3
−1583.3
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
R7
R6
R5
R4
R3
R2
R1
C101
C100
C99
C98
C97
C96
C95
C94
C93
C92
C91
C90
C89
C88
C87
C86
C85
C84
C83
C82
85.4
274.4
374.4
474.4
574.4
674.4
774.4
874.4
974.4
1074.4
1174.4
1274.4
1374.4
1474.4
1574.4
1674.4
1998 Apr 07
20
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
SYMBOL
C40
PAD
83
x
y
SYMBOL
R25
PAD
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
x
y
1774.4
1874.4
1974.4
2074.4
2174.4
2363.4
2463.4
2563.4
2663.4
2763.4
2863.4
2963.4
3063.4
3163.4
3263.4
3363.4
3463.4
3563.4
3663.4
3763.4
3863.4
3963.4
4063.4
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1583
−1483
−1383
−1283
−1183
−1083
−983
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4017.1
3917.1
3817.1
3717.1
3617.1
3517.1
3417.1
3317.1
−2695.6
−3044.1
−3190.6
−3362.1
−3463.6
−3635.1
−3735.1
−3839.1
−3939.6
883
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
84
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
T2
983
85
1083
86
1183
87
1283
88
1383
89
1483
90
1583
91
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SDA
VSS
T1
VLCD
SA0
T3
OSC
VDD
Dummy pads
dummy 1
dummy 2
dummy 3
dummy 4
dummy 5
dummy 6
dummy 7
dummy 8
dummy 9
dummy 10
−
−
−
−
−
−
−
−
−
−
−257.1
−155.6
−54.1
1790.4
1790.4
1790.4
1790.4
1790.4
1790.4
1823.4
1843.5
−1843.5
−1843.5
47.4
−883
148.9
−783
250.4
C8
−683
−4223.6
4303.5
−4303.6
4323.6
C7
−583
C6
−483
C5
−383
C4
−283
Alignment marks
C3
−183
Sign C
Sign C
Sign F
−
−
−
−4082.6
4147.4
−1782.5
1807.5
1417.5
C2
5.8
C1
105.8
−4262.6
R21
R22
R23
R24
483
583
683
783
1998 Apr 07
21
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Apr 07
22
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
NOTES
1998 Apr 07
23
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
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International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/02/pp24
Date of release: 1998 Apr 07
Document order number: 9397 750 03284
相关型号：
PCF8562TT
IC LIQUID CRYSTAL DISPLAY DRIVER, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, Display Driver
NXP
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