PCF8562TT/S400/2,1 [NXP]
PCF8562 - Universal LCD driver for low multiplex rates TSSOP 48-Pin;
| 型号： | PCF8562TT/S400/2,1 |
| 厂家： | 
NXP |
| 描述： | PCF8562 - Universal LCD driver for low multiplex rates TSSOP 48-Pin PC 驱动 CD 光电二极管 接口集成电路 |
| 文件： | 总41页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF8562
Universal LCD driver for low multiplex rates
Rev. 7 — 21 July 2015
Product data sheet
1. General description
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562
is compatible with most microcontrollers and communicates via the two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features and benefits
AEC-Q100 compliant (PCF8562TT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with voltage-follower buffers
32 segment drives:
Up to sixteen 7-segment numeric characters
Up to eight 14-segment alphanumeric characters
Any graphics of up to 128 elements
32 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
No external components required
Manufactured in silicon gate CMOS process
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF8562TT/2[1]
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
PCF8562TT/S400/2[2] TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
[1] Not to be used for new designs. Replacement part is PCF85162T/1 for industrial applications.
[2] Not to be used for new designs. Replacement part is PCA85162T/Q900/1 for automotive applications.
4. Marking
Table 2.
Marking codes
Type number
Marking code
PCF8562TT
PCF8562TT/2
PCF8562TT/S400/2
PCF8562TT/S400
PCF8562
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© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 21 July 2015
2 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3
S0 to S31
26 to 48,
1 to 9
22 23 24 25
21
V
LCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROLLER
LCD BIAS
GENERATOR
20
V
SS
PCF8562
13
12
DISPLAY
RAM
CLK
BLINKER
TIMEBASE
CLOCK SELECT
AND TIMING
SYNC
15
COMMAND
DECODER
DATA POINTER AND
AUTO INCREMENT
WRITE DATA
CONTROL
POWER-ON
RESET
OSC
OSCILLATOR
14
11
10
V
DD
SCL
SDA
2
SUBADDRESS
COUNTER
INPUT
FILTERS
I C-BUS
CONTROLLER
16 17 18
19
SA0
A0 A1 A2
001aac262
Fig 1. Block diagram of PCF8562
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
3 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S23
S24
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
3
S25
4
S26
5
S27
6
S28
7
S29
8
S30
9
S31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDA
SCL
SYNC
CLK
PCF8562TT
V
DD
OSC
A0
S8
S7
A1
S6
A2
S5
SA0
S4
V
SS
S3
V
LCD
S2
BP0
S1
BP2
BP1
S0
BP3
001aac263
Top view. For mechanical details, see Figure 22.
Fig 2. Pinning diagram for TSSOP48 (PCF8562TT)
6.2 Pin description
Table 3.
Pin description
Symbol
SDA
Pin
10
Type
Description
input/output
input
I2C-bus serial data line
I2C-bus serial clock
cascade synchronization
clock line
SCL
11
SYNC
CLK
12
input/output
input/output
supply
13
VDD
14
supply voltage
OSC
A0 to A2
SA0
15
input
internal oscillator enable
subaddress inputs
I2C-bus address input
ground supply voltage
16 to 18
19
input
input
VSS
20
supply
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
4 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 3.
Pin description …continued
Symbol
VLCD
Pin
Type
Description
21
supply
output
output
LCD supply voltage
LCD backplane outputs
LCD segment outputs
BP0 to BP3
22 to 25
S0 to S22,
S23 to S31
26 to 48,
1 to 9
7. Functional description
The PCF8562 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
32 segments.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 3. Example of displays suitable for PCF8562
The possible display configurations of the PCF8562 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure 4.
Table 4.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
Dot matrix/
Elements
7-segment
14-segment
4
3
2
1
128
96
16
12
8
8
6
4
2
128 dots (4 32)
96 dots (3 32)
64 dots (2 32)
32 dots (1 32)
64
32
4
PCF8562
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© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 21 July 2015
5 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
DD
t
r
R ≤
2C
b
V
V
DD
LCD
14
21
32 segment drives
4 backplanes
SDA
SCL
OSC
HOST
MICRO-
10
11
15
LCD PANEL
PROCESSOR/
MICRO-
CONTROLLER
PCF8562
(up to 128
elements)
16 17 18 19 20
A0 A1 A2 SA0
001aac264
V
SS
V
SS
The resistance of the power lines must be kept to a minimum.
Fig 4. Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF8562. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8562 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is: 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• Display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. The center impedance is
bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode
configuration is selected. The LCD voltage can be temperature compensated externally,
using the supply to pin VLCD
.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
V
LCD and the resulting discrimination ratios (D) are given in Table 5.
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 5.
Biasing characteristics
Number of:
LCD drive
mode
LCD bias
configuration
VoffRMS VonRMS
------------------------ ----------------------- D = ------------------------
VLCD VLCD VoffRMS
VonRMS
Backplanes Levels
static
1
2
2
3
4
2
3
4
4
4
static
0
1
1
⁄
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth(off)
.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------ , where the values for a are
1 + a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
a2 + 2a + n
n 1 + a2
VonRMS
=
-----------------------------
(1)
V
LCD
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
a2 – 2a + n
n 1 + a2
VoffRMS
=
-----------------------------
(2)
(3)
V
LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
a2 + 2a + n
VonRMS
----------------------
D =
=
---------------------------
a2 – 2a + n
VoffRMS
PCF8562
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© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 21 July 2015
7 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21
1⁄2 bias is ---------- = 1.528 .
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): VLCD
• 1:4 multiplex (1⁄2 bias): VLCD
=
=
6 VoffRMS = 2.449VoffRMS
4 3
---------------------
= 2.309VoffRMS
3
These compare with VLCD = 3VoffRMS when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
V
V
onRMS Vthon
offRMS Vthoff
(4)
(5)
V
on(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
100 %
90 %
10 %
V
[V]
RMS
V
th(off)
V
th(on)
OFF
SEGMENT
GREY
SEGMENT
ON
SEGMENT
013aaa494
Fig 5. Electro-optical characteristic: relative transmission curve of the liquid
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 6.
T
fr
LCD segments
V
LCD
BP0
Sn
V
SS
state 1
(on)
state 2
(off)
V
LCD
V
SS
V
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = VLCD
V
.
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 6. Static drive mode waveforms
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
10 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8562 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and
Figure 8.
T
fr
V
LCD
LCD segments
V
V
/2
BP0
BP1
Sn
LCD
SS
state 1
V
LCD
state 2
V
V
/2
LCD
SS
V
LCD
V
V
SS
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
V
LCD
/2
LCD
0 V
−V
state 1
/2
LCD
−V
LCD
V
V
LCD
/2
LCD
0 V
state 2
−V
/2
LCD
LCD
−V
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.791VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD
V
.
.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
Sn
V
V
/3
LCD
SS
state 1
V
LCD
state 2
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 1
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCF8562
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Product data sheet
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 9.
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
BP2
Sn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+2
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V /3
LCD
V
/3
LCD
state 1
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V /3
LCD
V
/3
LCD
state 2
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD
Vstate2(t) = VSn(t) VBP1(t).
off(RMS) = 0.333VLCD
.
V
.
Fig 9. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 10.
T
fr
V
2V
LCD segments
LCD
LCD
/3
BP0
BP1
BP2
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
/3
LCD
BP3
Sn
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+1
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+2
Sn+3
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
/3
LCD
V
LCD
state 1
state 2
0 V
LCD
-V
/3
/3
-2V
LCD
LCD
-V
V
LCD
2V
LCD
/3
/3
V
LCD
0 V
-V
/3
LCD
-2V
LCD
/3
LCD
-V
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.577VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin VSS
.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD
.
The LCD frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
fclk
-------
.
the internal or an external clock: ffr
=
24
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
• In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these
two adjacent outputs can be tied together to give enhanced drive capabilities.
• In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the
same signals and may also be paired to increase the drive capabilities.
• In the static drive mode the same signal is carried by all four backplane outputs and
they can be connected in parallel for very high drive requirements.
PCF8562
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Product data sheet
Rev. 7 — 21 July 2015
15 of 41
PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 32 4-bit RAM which stores LCD data. There is a one-to-one
correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the
segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,
second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
columns
display RAM addresses/segment outputs (S)
0
1
2
3
4
27 28 29 30 31
rows
0
1
2
3
display RAM rows/
backplane outputs
(BP)
001aac265
The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bit map
When display data is transmitted to the PCF8562, the display bytes received are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and depending on the current multiplex drive mode the bits are stored singularly, in
pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Figure 12; the RAM filling organization
depicted applies equally to other LCD types.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
S
S
S
S
S
a
n+2
n+3
n+4
n+5
n+6
b
BP0
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
S
f
n+1
rows
static
display RAM
rows/backplane
outputs (BP)
MSB
LSB
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
S
S
n
x
x
x
e
n+7
c
b
a
f
g
e
d
DP
c
x
d
DP
x
columns
display RAM address/segment outputs (s)
byte1 byte2
BP0
a
S
S
n
1:2
b
n
n + 1 n + 2 n + 3
f
n+1
rows
MSB
LSB
DP
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP
x
multiplex
g
x
x
BP1
a
b
f
g
e c d
e
S
S
n+2
n+3
c
d
DP
x
columns
display RAM address/segment outputs (s)
BP0
BP1
byte1
byte2
byte3
S
S
n+1
n+2
a
1:3
b
n
n + 1 n + 2
S
f
n
rows
MSB
LSB
e
display RAM
rows/backplane
outputs (BP)
0
1
2
3
b
DP
c
a
d
g
x
f
g
multiplex
b
DP
c
a
d
g
f
e
x
x
BP2
e
c
d
DP
x
columns
display RAM address/segment outputs (s)
byte2 byte3 byte4
byte1
byte5
a
S
S
n
1:4
b
BP2
BP3
n
n + 1
BP0
BP1
f
rows
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
c
f
MSB
LSB
d
multiplex
e
g
d
e
c
b
a
c
b
DP
f
e
g
d
DP
DP
n+1
001aaj646
x = data bit unchanged.
Fig 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCF8562
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Universal LCD driver for low multiplex rates
The following applies to Figure 12:
• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.10.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 12.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed to take place only when the content of the subaddress counter
matches with the hardware subaddress applied to A0, A1, and A2. The subaddress
counter value is defined by the device-select command (see Table 13). If the content of
the subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as
well).
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Table 6.
Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1
a0
-
b7
b6
b5
-
b4
b3
b2
-
b1
b0
-
c7
c6
c5
-
c4
c3
c2
-
c1
c0
-
d7
d6
d5
-
:
:
:
:
-
-
-
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 7.
Table 7.
Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1/b7 b4
a0/b6 b3
b1/c7 c4
b0/c6 c3
c1/d7 d4
c0/d6 d3
d1/e7 e4
d0/e6 e3
:
:
:
:
b5
-
b2
-
c5
-
c2
-
d5
-
d2
-
e5
-
e2
-
In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the content of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
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The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the content of
row 2 to be selected for display instead of the content of row 0. In the 1:2 multiplex mode,
the content of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.5 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration.
The bank-select command (see Table 14) can be used to load display data in row 2 in
static drive mode or in rows 2 and 3 in 1:2 mode. The input bank selector functions are
independent of the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF8562 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are fractions of the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 8).
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
Table 8.
Blinking frequencies[1]
Blink mode
Normal operating mode ratio
Nominal blink frequency
off
1
-
blinking off
2 Hz
fclk
---------
768
2
3
1 Hz
fclk
------------
1536
0.5 Hz
fclk
------------
3072
[1] Blink modes 1, 2, and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz, and 2 Hz correspond to an
oscillator frequency (fclk) of 1536 Hz (see Section 12).
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
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7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCF8562 are defined in Table 9.
Table 9.
Definition of PCF8562 commands
Operation code
Command
Bit
Reference
7
6
1
0
1
1
1
5
0
0
1
1
1
4
3
2
1
0
[1]
mode-set
C
C
C
C
C
-
E
B
M[1:0]
Table 11
Table 12
Table 13
Table 14
Table 15
load-data-pointer
device-select
bank-select
blink-select
P[4:0]
0
1
1
0
1
0
A[2:0]
0
I
O
AB
BF[1:0]
[1] Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to
arrive will also represent a command. If this bit is reset, it indicates that the command byte
is the last in the transfer. Further bytes will be regarded as display data (see Table 10).
Table 10. C bit description
Bit
Symbol Value
Description
continue bit
7
C
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command too
Table 11. Mode-set command bit description
Bit
7
Symbol Value
Description
C
-
0, 1
10
-
see Table 10
6, 5
4
fixed value
-
unused
3
E
display status
0
1
disabled (blank)[1]
enabled
2
B
LCD bias configuration[2]
1⁄3 bias
1⁄2 bias
0
1
1 to 0
M[1:0]
LCD drive mode selection
static; BP0
01
10
11
00
1:2 multiplex; BP0, BP1
1:3 multiplex; BP0, BP1, BP2
1:4 multiplex; BP0, BP1, BP2, BP3
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Not applicable for static drive mode.
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Table 12. Load-data-pointer command bit description
Bit
Symbol Value
Description
7
C
0, 1
00
see Table 10
fixed value
6, 5
4 to 0
-
P[4:0]
00000 to
11111
5 bit binary value, 0 to 31; transferred to the data pointer to
define one of 32 display RAM addresses
Table 13. Device-select command bit description
Bit
Symbol Value
Description
see Table 10
fixed value
7
C
0, 1
6 to 3
2 to 0
-
1100
A[2:0]
000 to 111
3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
Table 14. Bank-select command bit description
Bit
Symbol Value
Description
Static
1:2 multiplex[1]
7
C
-
0, 1
see Table 10
fixed value
6 to 2
1
11110
I
input bank selection; storage of arriving display data
0
1
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
O
output bank selection; retrieval of LCD display data
0
1
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
Table 15. Blink-select command bit description
Bit
7
Symbol Value
Description
C
-
0, 1
see Table 10
6 to 3
2
1110
fixed value
AB
blink mode selection
0
1
normal blinking[1]
alternate RAM bank blinking[2]
1 to 0
BF[1:0]
blink frequency selection
00
01
10
11
off
1
2
3
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
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Universal LCD driver for low multiplex rates
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling order.
PCF8562
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8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 13. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 14. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see Figure 15).
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Universal LCD driver for low multiplex rates
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 15. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 16.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 16. Acknowledgement of the I2C-bus
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Universal LCD driver for low multiplex rates
8.5 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.
The least significant bit of the slave address that a PCF8562 will respond to is defined by
the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to
a read access.
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8562
slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8562s whose SA0 inputs are set to the alternative level.
R/W
acknowledge
acknowledge
COMMAND
slave address
S
A
0
0
1
1
1
0
0
0
A
C
A
DISPLAY DATA
A
P
S
1 byte
n ≥ 1 byte(s)
n ≥ 0 byte(s)
update data pointers
001aac266
Fig 17. I2C-bus protocol
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8562.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 18). The command bytes are also acknowledged by all addressed
PCF8562s on the bus.
MSB
LSB
C
REST OF OPCODE
msa833
Fig 18. Format of command byte
PCF8562
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Universal LCD driver for low multiplex rates
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically
updated.
An acknowledgement, after each byte, is asserted only by the PCF8562s that are
addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus
access.
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Universal LCD driver for low multiplex rates
9. Internal circuitry
V
V
DD
DD
SA0
CLK
V
V
V
SS
SS
DD
SCL
V
V
SS
DD
V
SS
OSC
V
V
SS
SDA
DD
SYNC
V
V
V
SS
SS
DD
A0, A1, T1
V
V
SS
LCD
BP0, BP1,
BP2, BP3
V
V
SS
V
LCD
LCD
S0 to S31
V
SS
V
SS
001aac269
Fig 19. Device protection circuits
PCF8562
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Universal LCD driver for low multiplex rates
10. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
0.5
0.5
0.5
Max
+6.5
+7.5
+6.5
Unit
V
VDD
VLCD
VI
supply voltage
LCD supply voltage
input voltage
V
on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
V
VO
output voltage
on each of the pins S0 to
S31, BP0 to BP3
0.5
+7.5
V
II
input current
output current
supply current
10
10
50
50
50
-
+10
mA
mA
mA
mA
mA
mW
mW
V
IO
IDD
+10
+50
IDD(LCD) LCD supply current
+50
ISS
ground supply current
total power dissipation
output power
+50
Ptot
Po
400
-
100
[1]
[2]
[3]
[4]
[5]
Vesd
electrostatic discharge
voltage
HBM
MM
-
5000
200
1500
300
-
V
CDM
-
V
Ilu
latch-up current
-
mA
C
Tstg
Tamb
storage temperature
ambient temperature
65
40
+150
+85
operating device
C
[1] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.
[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[3] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[4] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be
stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
PCF8562
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PCF8562
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Universal LCD driver for low multiplex rates
11. Static characteristics
Table 17. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
2.5
-
-
5.5
6.5
7
V
[1]
[2]
[2]
VLCD
LCD supply voltage
supply current
-
V
IDD
fclk(ext) = 1536 Hz
fclk(ext) = 1536 Hz
3.5
23
A
A
IDD(LCD)
Logic[3]
VP(POR)
VIL
LCD supply current
-
32
power-on reset supply voltage
LOW-level input voltage
1.0
1.3
-
1.6
V
V
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS
0.3VDD
[4][5]
VIH
HIGH-level input voltage
LOW-level output current
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
0.7VDD
-
VDD
V
IOL
output sink current;
VOL = 0.4 V; VDD = 5 V
on pins CLK and SYNC
on pin SDA
1
3
1
-
-
-
-
-
-
mA
mA
mA
IOH(CLK)
IL
HIGH-level output current on pin CLK output source current;
VOH = 4.6 V; VDD = 5 V
leakage current
VI = VDD or VSS
;
1
-
+1
A
on pins CLK, SCL, SDA,
A0 to A2 and SA0
IL(OSC)
leakage current on pin OSC
input capacitance
VI = VDD
1
-
-
+1
7
A
[6]
[7]
CI
-
pF
LCD outputs
VO
output voltage variation
on pins BP0 to BP3 and
S0 to S31
100
-
+100
mV
RO
output resistance
VLCD = 5 V
on pins BP0 to BP3
on pins S0 to S31
-
-
1.5
6.0
-
-
k
k
[1] VLCD > 3 V for 1⁄3 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3] The I2C-bus interface of PCF8562 is 5 V tolerant.
[4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 16 (see Figure 19
as well).
[5] Propagation delay of driver between clock (CLK) and LCD driving signals.
[6] Periodically sampled, not 100 % tested.
[7] Outputs measured one at a time.
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Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 18. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
fclk(int)
fclk(ext)
tclk(H)
tclk(L)
[1]
internal clock frequency
external clock frequency
HIGH-level clock time
LOW-level clock time
1440
960
60
1850
2640
Hz
Hz
s
s
-
-
-
2640
-
-
60
Synchronization
tPD(SYNC_N) SYNC propagation delay
-
30
-
-
ns
s
s
tSYNC_NL
tPD(drv)
I2C-bus[3]
Pin SCL
fSCL
SYNC LOW time
1
-
-
[2]
driver propagation delay
VLCD = 5 V
-
30
SCL clock frequency
-
-
-
-
400
kHz
s
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
-
-
tHIGH
s
Pin SDA
tSU;DAT
tHD;DAT
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
Pins SCL and SDA
tBUF
bus free time between a STOP and
1.3
-
-
s
START condition
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP condition
hold time (repeated) START condition
0.6
0.6
0.6
-
-
-
-
-
-
s
s
s
set-up time for a repeated START
condition
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
fSCL < 125 kHz
-
-
-
-
-
-
-
-
-
-
0.3
1.0
0.3
400
50
s
s
s
pF
ns
tf
fall time of both SDA and SCL signals
capacitive load for each bus line
Cb
tw(spike)
spike pulse width
on the I2C-bus
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD
.
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PCF8562
NXP Semiconductors
Universal LCD driver for low multiplex rates
1/f
clk
t
t
clk(L)
clk(H)
0.7V
0.3V
DD
DD
CLK
0.7V
0.3V
DD
DD
SYNC
t
t
PD(SYNC_N)
PD(SYNC_N)
t
SYNC_NL
0.5 V
(V
BP0 to BP3,
and S0 to S31
= 5 V)
DD
0.5 V
t
PD(drv)
013aaa493
Fig 20. Driver timing waveforms
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 21. I2C-bus timing waveforms
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Universal LCD driver for low multiplex rates
13. Application information
13.1 Multiple chip operation
For large display configurations or for more segments (> 128 elements) to drive please
refer to the PCF8576D device.
The contact resistance between the SYNC input/output on each cascaded device must be
controlled. If the resistance is too high, the device will not be able to synchronize properly;
this is particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 19.
Table 19. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
2200
1200
700
3 to 5
6 to 10
10 to 16
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
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Universal LCD driver for low multiplex rates
15. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
(1)
(2)
Unit
max
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
0.4
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig 22. Package outline SOT362-1 (TSSOP48)
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Universal LCD driver for low multiplex rates
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
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Universal LCD driver for low multiplex rates
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 21. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
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Universal LCD driver for low multiplex rates
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 22. Abbreviations
Acronym
CMOS
CDM
HBM
ITO
Description
Complementary Metal Oxide Semiconductor
Charged-Device Model
Human Body Model
Indium Tin Oxide
LCD
Liquid Crystal Display
Least Significant Bit
Machine Model
LSB
MM
MSB
MSL
PCB
RAM
RMS
SCL
Most Significant Bit
Moisture Sensitivity Level
Printed Circuit Board
Random Access Memory
Root Mean Square
Serial Clock Line
SDA
SMD
Serial Data line
Surface Mount Device
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Universal LCD driver for low multiplex rates
19. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10853 — ESD and EMC sensitivity of IC
[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9] JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] NX3-00092 — NXP store and transport requirements
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
[13] UM10204 — I2C-bus specification and user manual
20. Revision history
Table 23. Revision history
Document ID
PCF8562 v.7
Modifications:
PCF8562 v.6
Modifications:
Release date
20150721
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF8562 v.6
• Table 17: Replaced values (LCD) supply
20110616 Product data sheet
-
PCF8562 v.5
• Added design-in and replacement part information
• Added Section 7.10.3
PCF8562 v.5
PCF8562 v.4
PCF8562 v.3
PCF8562 v.2
PCF8562 v.1
20100519
20090318
20081202
20070122
20050801
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
-
PCF8562 v.4
PCF8562 v.3
PCF8562 v.2
PCF8562 v,1
-
PCF8562
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PCF8562
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Universal LCD driver for low multiplex rates
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
21.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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PCF8562
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Universal LCD driver for low multiplex rates
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Universal LCD driver for low multiplex rates
23. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
13
13.1
14
14.1
15
Application information . . . . . . . . . . . . . . . . . 33
Multiple chip operation. . . . . . . . . . . . . . . . . . 33
Test information . . . . . . . . . . . . . . . . . . . . . . . 33
Quality information. . . . . . . . . . . . . . . . . . . . . 33
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34
Handling information . . . . . . . . . . . . . . . . . . . 35
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
16
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
17
Soldering of SMD packages. . . . . . . . . . . . . . 35
Introduction to soldering. . . . . . . . . . . . . . . . . 35
Wave and reflow soldering. . . . . . . . . . . . . . . 35
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 36
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 36
17.1
17.2
17.3
17.4
7
7.1
7.2
7.3
7.3.1
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
7.6
Functional description . . . . . . . . . . . . . . . . . . . 5
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6
Electro-optical performance . . . . . . . . . . . . . . . 8
LCD drive mode waveforms . . . . . . . . . . . . . . 10
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 10
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 11
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 14
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Display register. . . . . . . . . . . . . . . . . . . . . . . . 15
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subaddress counter . . . . . . . . . . . . . . . . . . . . 18
RAM writing in 1:3 multiplex drive mode. . . . . 18
Output bank selector . . . . . . . . . . . . . . . . . . . 19
Input bank selector . . . . . . . . . . . . . . . . . . . . . 20
Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command decoder. . . . . . . . . . . . . . . . . . . . . 21
Display controller . . . . . . . . . . . . . . . . . . . . . . 23
18
19
20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . 38
21
Legal information . . . . . . . . . . . . . . . . . . . . . . 39
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
21.1
21.2
21.3
21.4
22
23
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.7
7.8
7.9
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
7.11
7.12
7.13
8
Characteristics of the I2C-bus . . . . . . . . . . . . 24
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
START and STOP conditions . . . . . . . . . . . . . 24
System configuration . . . . . . . . . . . . . . . . . . . 24
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 26
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29
Static characteristics. . . . . . . . . . . . . . . . . . . . 30
Dynamic characteristics . . . . . . . . . . . . . . . . . 31
10
11
12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 July 2015
Document identifier: PCF8562
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