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PCF8563BS-4 [NXP]

Real-time clock/calendar; 实时时钟/日历
PCF8563BS-4
型号： PCF8563BS-4
厂家： NXP    NXP
描述：

Real-time clock/calendar
实时时钟/日历

时钟
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中文：  中文翻译
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PCF8563  
Real-time clock/calendar  
Rev. 9 — 16 June 2011  
Product data sheet  
1. General description  
The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power  
consumption. A programmable clock output, interrupt output, and voltage-low detector are  
also provided. All addresses and data are transferred serially via a two-line bidirectional  
I2C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented  
automatically after each written or read data byte.  
2. Features and benefits  
Provides year, month, day, weekday, hours, minutes, and seconds based on a  
32.768 kHz quartz crystal  
Century flag  
Clock operating voltage: 1.0 V to 5.5 V at room temperature  
Low backup current; typical 0.25 A at VDD = 3.0 V and Tamb = 25 C  
400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V)  
Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and  
1 Hz)  
Alarm and timer functions  
Integrated oscillator capacitor  
Internal Power-On Reset (POR)  
I2C-bus slave address: read A3h and write A2h  
Open-drain interrupt pin  
3. Applications  
Mobile telephones  
Portable instruments  
Electronic metering  
Battery powered products  
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
PCF8563BS/4  
HVSON10 plastic thermal enhanced very thin small outline  
package; no leads; 10 terminals;  
SOT650-1  
body 3 3 0.85 mm  
PCF8563P/F4  
PCF8563T/5  
DIP8  
SO8  
plastic dual in-line package; 8 leads (300 mil)  
SOT97-1  
SOT96-1  
plastic small outline package; 8 leads;  
body width 3.9 mm  
PCF8563T/F4[1] SO8  
plastic small outline package; 8 leads;  
body width 3.9 mm  
SOT96-1  
SOT505-1  
SOT505-1  
PCF8563TS/4[2] TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm  
PCF8563TS/5  
TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm  
[1] Not to be used for new designs. Replacement part is PCF8563T/5.  
[2] Not to be used for new designs. Replacement part is PCF8563TS/5.  
5. Marking  
Table 2.  
Marking codes  
Type number  
PCF8563BS/4  
PCF8563P/F4  
PCF8563T/5  
PCF8563T/F4  
PCF8563TS/4  
PCF8563TS/5  
Marking code  
8563S  
PCF8563P  
8563T  
8563T  
8563  
8563  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
2 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
6. Block diagram  
OSCI  
OSCILLATOR  
32.768 kHz  
DIVIDER  
CLOCK OUT  
CLKOUT  
OSCO  
CONTROL  
MONITOR  
00  
01  
0D  
CONTROL_STATUS_1  
CONTROL_STATUS_2  
CLKOUT_CONTROL  
(1)  
POWER ON  
RESET  
TIME  
VL_SECONDS  
MINUTES  
02  
03  
04  
05  
06  
07  
08  
HOURS  
V
DD  
DAYS  
V
SS  
WEEKDAYS  
CENTURY_MONTHS  
YEARS  
WATCH  
DOG  
ALARM FUNCTION  
MINUTE_ALARM  
HOUR_ALARM  
09  
0A  
0B  
0C  
2
DAY_ALARM  
SDA  
SCL  
I C-BUS  
INTERFACE  
WEEKDAY_ALARM  
INT  
INTERRUPT  
TIMER FUNCTION  
TIMER_CONTROL  
TIMER  
0E  
0F  
PCF8563  
001aah658  
(1) COSCO; values see Table 30.  
Fig 1. Block diagram of PCF8563  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
3 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
7. Pinning information  
7.1 Pinning  
terminal 1  
index area  
1
2
3
4
5
10  
9
OSCI  
OSCO  
n.c.  
n.c.  
V
DD  
8
PCF8563BS  
CLKOUT  
SCL  
1
2
3
4
8
7
6
5
OSCI  
OSCO  
INT  
V
DD  
7
INT  
CLKOUT  
SCL  
PCF8563P  
6
V
SS  
SDA  
V
SS  
SDA  
001aaf981  
Transparent top view  
For mechanical details, see Figure 30.  
001aaf977  
Top view. For mechanical details, see  
Figure 31.  
Fig 2. Pin configuration for HVSON10  
(PCF8563BS)  
Fig 3. Pin configuration for DIP8  
(PCF8563P)  
1
2
3
4
8
7
6
5
OSCI  
OSCO  
INT  
V
DD  
1
2
3
4
8
7
6
5
OSCI  
OSCO  
INT  
V
DD  
CLKOUT  
SCL  
CLKOUT  
SCL  
PCF8563T  
PCF8563TS  
V
SDA  
SS  
V
SS  
SDA  
001aaf975  
001aaf976  
Top view. For mechanical details, see  
Figure 32.  
Top view. For mechanical details, see  
Figure 33.  
Fig 4. Pin configuration for SO8  
(PCF8563T)  
Fig 5. Pin configuration for TSSOP8  
(PCF8563TS)  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
4 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
7.2 Pin description  
Table 3.  
Symbol  
Pin description  
Pin  
Description  
DIP8, SO8, TSSOP8 HVSON10  
OSCI  
OSCO  
INT  
1
2
3
4
5
6
7
8
-
1
oscillator input  
2
oscillator output  
4
5[1]  
interrupt output (open-drain; active LOW)  
ground  
VSS  
SDA  
SCL  
6
serial data input and output  
serial clock input  
7
CLKOUT  
VDD  
8
clock output, open-drain  
supply voltage  
9
n.c.  
3, 10  
not connected; do not connect and do not  
use as feed through  
[1] The die paddle (exposed pad) is wired to VSS but should not be electrically connected.  
8. Functional description  
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address,  
an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which  
provides the source clock for the Real-Time Clock (RTC) and calender, a programmable  
clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I2C-bus interface.  
All 16 registers are designed as addressable 8-bit parallel registers although not all bits  
are implemented. The first two registers (memory address 00h and 01h) are used as  
control and/or status registers. The memory addresses 02h through 08h are used as  
counters for the clock function (seconds up to years counters). Address locations 09h  
through 0Ch contain alarm registers which define the conditions for an alarm.  
Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the Timer_control  
and Timer registers, respectively.  
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm,  
Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD)  
format.  
When one of the RTC registers is written or read, the contents of all time counters are  
frozen. Therefore, faulty writing or reading of the clock and calendar during a carry  
condition is prevented.  
8.1 CLKOUT output  
A programmable square wave is available at the CLKOUT pin. Operation is controlled by  
the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),  
1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller  
clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain  
output and enabled at power-on. If disabled it becomes high-impedance.  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
5 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
8.2 Register organization  
Table 4.  
Formatted registers overview  
Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they  
could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.  
Address Register name  
Bit  
7
6
5
4
3
2
1
0
Control and status registers  
00h  
01h  
Control_status_1 TEST1  
N
N
STOP  
N
N
TESTC  
AF  
N
N
N
Control_status_2  
N
TI_TP  
TF  
AIE  
TIE  
Time and date registers  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
VL_seconds  
Minutes  
VL  
x
SECONDS (0 to 59)  
MINUTES (0 to 59)  
Hours  
x
x
x
x
x
HOURS (0 to 23)  
DAYS (1 to 31)  
Days  
x
Weekdays  
Century_months  
Years  
x
x
x
x
x
WEEKDAYS (0 to 6)  
C
MONTHS (1 to 12)  
YEARS (0 to 99)  
Alarm registers  
09h  
0Ah  
0Bh  
0Ch  
Minute_alarm  
AE_M  
AE_H  
AE_D  
AE_W  
MINUTE_ALARM (0 to 59)  
Hour_alarm  
x
x
x
HOUR_ALARM (0 to 23)  
DAY_ALARM (1 to 31)  
Day_alarm  
Weekday_alarm  
x
x
x
x
x
x
x
x
x
WEEKDAY_ALARM (0 to 6)  
CLKOUT control register  
0Dh  
CLKOUT_control FE  
x
x
x
x
FD[1:0]  
TD[1:0]  
Timer registers  
0Eh  
0Fh  
Timer_control  
Timer  
TE  
TIMER[7:0]  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
6 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
8.3 Control registers  
8.3.1 Register Control_status_1  
Table 5.  
Control_status_1 - control and status register 1 (address 00h) bit description  
Bit  
Symbol  
Value  
Description  
Reference  
7
TEST1  
0[1]  
normal mode  
Section 8.9  
must be set to logic 0 during normal operations  
EXT_CLK test mode  
unused  
1
6
5
N
0[2]  
0[1]  
1
STOP  
RTC source clock runs  
Section 8.10  
all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC  
clock is stopped (CLKOUT at 32.768 kHz is still available)  
4
3
N
0[2]  
0
unused  
TESTC  
Power-On Reset (POR) override facility is disabled; set to logic 0 for  
normal operation  
Section 8.11.1  
1[1]  
000[2]  
Power-On Reset (POR) override may be enabled  
unused  
2 to 0  
N
[1] Default value.  
[2] Bits labeled as N should always be written with logic 0.  
8.3.2 Register Control_status_2  
Table 6.  
Bit  
Control_status_2 - control and status register 2 (address 01h) bit description  
Symbol  
N
Value  
000[1]  
0[2]  
Description  
Reference  
7 to 5  
4
unused  
TI_TP  
INT is active when TF is active (subject to the status of TIE)  
INT pulses active according to Table 7 (subject to the status of TIE);  
Section 8.3.2.1  
and  
Section 8.8  
1
Remark: note that if AF and AIE are active then INT will be  
permanently active  
3
2
AF  
TF  
0[2]  
read: alarm flag inactive  
write: alarm flag is cleared  
read: alarm flag active  
Section 8.3.2.1  
1
0[2]  
write: alarm flag remains unchanged  
read: timer flag inactive  
write: timer flag is cleared  
read: timer flag active  
1
write: timer flag remains unchanged  
alarm interrupt disabled  
alarm interrupt enabled  
1
0
AIE  
TIE  
0[2]  
1
0[2]  
timer interrupt disabled  
1
timer interrupt enabled  
[1] Bits labeled as N should always be written with logic 0.  
[2] Default value.  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
7 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
8.3.2.1 Interrupt output  
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a  
timer countdown, TF is set to logic 1. These bits maintain their value until overwritten  
using the interface. If both timer and alarm interrupts are required in the application, the  
source of the interrupt can be determined by reading these bits. To prevent one flag being  
overwritten while clearing another, a logic AND is performed during a write access.  
TI_TP  
TE  
e.g. AIE  
to interface:  
read TF  
TF: TIMER  
SET  
TIE  
0
1
COUNTDOWN COUNTER  
0
1
PULSE  
GENERATOR 2  
CLEAR  
TRIGGER  
CLEAR  
INT  
from interface:  
clear TF  
AIE  
to interface:  
read AF  
AF: ALARM  
FLAG  
set alarm  
flag AF  
SET  
CLEAR  
from interface:  
clear AF  
013aaa087  
When bits TIE and AIE are disabled, pin INT will remain high-impedance.  
Fig 6. Interrupt scheme  
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when  
TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions  
when both AIE and TIE are set.  
Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses  
an internal clock and is dependent on the selected source clock for the countdown timer  
and on the countdown value n. As a consequence, the width of the interrupt pulse varies  
(see Table 7).  
Table 7.  
INT operation (bit TI_TP = 1)[1]  
Source clock (Hz)  
INT period (s)  
n = 1[2]  
n > 1[2]  
1
1
4096  
64  
⁄
⁄
8192  
4096  
1
1
⁄
⁄
128  
64  
1
1
1
⁄
⁄
64  
64  
1
1
1
⁄
⁄
⁄
60  
64  
64  
[1] TF and INT become active simultaneously.  
[2] n = loaded countdown value. Timer stops when n = 0.  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
8 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
8.4 Time and date registers  
The majority of the registers are coded in the BCD format to simplify application use.  
8.4.1 Register VL_seconds  
Table 8.  
VL_seconds - seconds and clock integrity status register (address 02h) bit  
description  
Bit  
Symbol  
VL  
Value  
Place value Description  
7
0
-
clock integrity is guaranteed  
1[1]  
-
integrity of the clock information is not guaranteed  
actual seconds coded in BCD format, see Table 9  
6 to 4 SECONDS 0 to 5  
ten’s place  
unit place  
3 to 0  
0 to 9  
[1] Start-up value.  
Table 9.  
Seconds coded in BCD format  
Seconds value  
(decimal)  
Digit (unit place)  
Upper-digit (ten’s place)  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
00  
01  
02  
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
1
:
0
1
0
:
09  
10  
:
0
0
:
0
0
:
0
1
:
1
0
:
0
0
:
0
0
:
1
0
:
58  
59  
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.4.1.1 Voltage-low detector and clock monitor  
The PCF8563 has an on-chip voltage-low detector (see Figure 7). When VDD drops below  
low, bit VL in the VL_seconds register is set to indicate that the integrity of the clock  
V
information is no longer guaranteed. The VL flag can only be cleared by using the  
interface.  
mgr887  
V
DD  
normal power  
operation  
period of battery  
operation  
V
low  
t
VL set  
Fig 7. Voltage-low detection  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
9 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
The VL flag is intended to detect the situation when VDD is decreasing slowly, for example  
under battery operation. Should the oscillator stop or VDD reach Vlow before power is  
re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.  
8.4.2 Register Minutes  
Table 10. Minutes - minutes register (address 03h) bit description  
Bit  
Symbol  
Value  
Place value Description  
7
-
-
-
unused  
6 to 4 MINUTES 0 to 5  
ten’s place  
unit place  
actual minutes coded in BCD format  
3 to 0  
0 to 9  
8.4.3 Register Hours  
Table 11. Hours - hours register (address 04h) bit description  
Bit  
Symbol  
Value  
-
Place value Description  
7 to 6 -  
-
unused  
5 to 4 HOURS  
3 to 0  
0 to 2  
0 to 9  
ten’s place  
unit place  
actual hours coded in BCD format  
8.4.4 Register Days  
Table 12. Days - days register (address 05h) bit description  
Bit  
Symbol  
Value  
-
Place value Description  
7 to 6 -  
-
unused  
5 to 4 DAYS[1]  
0 to 3  
0 to 9  
ten’s place  
unit place  
actual day coded in BCD format  
3 to 0  
[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a  
value which is exactly divisible by 4, including the year 00.  
8.4.5 Register Weekdays  
Table 13. Weekdays - weekdays register (address 06h) bit description  
Bit  
Symbol  
Value  
-
Description  
7 to 3 -  
unused  
2 to 0 WEEKDAYS  
0 to 6  
actual weekday values, see Table 14  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
10 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
Table 14. Weekday assignments  
Day[1]  
Bit  
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday  
0
Monday  
Tuesday  
Wednesday  
Thursday  
Friday  
0
0
0
1
1
Saturday  
1
[1] Definition may be re-assigned by the user.  
8.4.6 Register Century_months  
Table 15. Century_months - century flag and months register (address 07h) bit description  
Bit  
Symbol  
Value  
Place value Description  
7
C[1]  
0[2]  
-
indicates the century is x  
1
-
indicates the century is x + 1  
unused  
6 to 5 -  
-
-
4
MONTHS 0 to 1  
0 to 9  
ten’s place  
unit place  
actual month coded in BCD format, see Table 16  
3 to 0  
[1] This bit may be re-assigned by the user.  
[2] This bit is toggled when the register Years overflows from 99 to 00.  
Table 16. Month assignments in BCD format  
Month  
Upper-digit  
(ten’s place)  
Digit (unit place)  
Bit 4  
0
Bit 3  
0
Bit 2  
Bit 1  
0
Bit 0  
1
January  
February  
March  
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
April  
0
0
0
0
May  
0
0
0
1
June  
0
0
1
0
July  
0
0
1
1
August  
September  
October  
November  
December  
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
11 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
8.4.7 Register Years  
Table 17. Years - years register (08h) bit description  
Bit  
Symbol  
Value  
0 to 9  
0 to 9  
Place value Description  
ten’s place actual year coded in BCD format[1]  
7 to 4 YEARS  
3 to 0  
unit place  
[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is  
toggled.  
8.5 Setting and reading the time  
Figure 8 shows the data flow and data dependencies starting from the 1 Hz clock tick.  
1 Hz tick  
SECONDS  
MINUTES  
HOURS  
LEAP YEAR  
CALCULATION  
DAYS  
MONTHS  
YEARS  
C
WEEKDAY  
013aaa092  
Fig 8. Data flow for the time function  
During read/write operations, the time counting circuits (memory locations 02h through  
08h) are blocked.  
This prevents  
• Faulty reading of the clock and calendar during a carry condition  
• Incrementing the time registers, during the read cycle  
After this read/write access is completed, the time circuit is released again and any  
pending request to increment the time counters that occurred during the read access is  
serviced. A maximum of 1 request can be stored; therefore, all accesses must be  
completed within 1 second (see Figure 9).  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
12 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
t < 1 s  
SLAVE ADDRESS  
DATA  
DATA  
STOP  
START  
013aaa215  
Fig 9. Access time for read/write operations  
As a consequence of this method, it is very important to make a read or write access in  
one go, that is, setting or reading seconds through to years should be made in one single  
access. Failing to comply with this method could result in the time becoming corrupted.  
As an example, if the time (seconds through to hours) is set in one access and then in a  
second access the date is set, it is possible that the time may increment between the two  
accesses. A similar problem exists when reading. A roll over may occur between reads  
thus giving the minutes from one moment and the hours from the next.  
Recommended method for reading the time:  
1. Send a START condition and the slave address for write (A2h).  
2. Set the address pointer to 2 (VL_seconds) by sending 02h.  
3. Send a RESTART condition or STOP followed by START.  
4. Send the slave address for read (A3h).  
5. Read VL_seconds.  
6. Read Minutes.  
7. Read Hours.  
8. Read Days.  
9. Read Weekdays.  
10. Read Century_months.  
11. Read Years.  
12. Send a STOP condition.  
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8.6 Alarm registers  
8.6.1 Register Minute_alarm  
Table 18. Minute_alarm - minute alarm register (address 09h) bit description  
Bit  
Symbol  
Value  
Place value Description  
7
AE_M  
0
1[1]  
-
-
minute alarm is enabled  
minute alarm is disabled  
6 to 4 MINUTE_ALARM  
3 to 0  
0 to 5  
0 to 9  
ten’s place minute alarm information coded in BCD  
format  
unit place  
[1] Default value.  
8.6.2 Register Hour_alarm  
Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description  
Bit  
Symbol  
Value  
Place value Description  
7
AE_H  
0
1[1]  
-
-
-
hour alarm is enabled  
hour alarm is disabled  
unused  
6
-
-
5 to 4 HOUR_ALARM  
3 to 0  
0 to 2  
0 to 9  
ten’s place hour alarm information coded in BCD  
format  
unit place  
[1] Default value.  
8.6.3 Register Day_alarm  
Table 20. Day_alarm - day alarm register (address 0Bh) bit description  
Bit  
Symbol  
Value  
Place value Description  
7
AE_D  
0
1[1]  
-
-
-
day alarm is enabled  
day alarm is disabled  
unused  
6
-
-
5 to 4 DAY_ALARM  
3 to 0  
0 to 3  
0 to 9  
ten’s place day alarm information coded in BCD  
format  
unit place  
[1] Default value.  
8.6.4 Register Weekday_alarm  
Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description  
Bit  
Symbol  
Value  
Description  
7
AE_W  
0
1[1]  
weekday alarm is enabled  
weekday alarm is disabled  
unused  
6 to 3 -  
-
2 to 0 WEEKDAY_ALARM 0 to 6  
[1] Default value.  
weekday alarm information  
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8.6.5 Alarm flag  
By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the  
corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.  
The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the  
interface.  
The registers at addresses 09h through 0Ch contain alarm information. When one or  
more of these registers is loaded with minute, hour, day or weekday, and its  
corresponding AE_x is logic 0, then that information is compared with the current minute,  
hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in  
register Control_2) is set to logic 1.  
The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is  
enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the  
interface. Once AF has been cleared, it will only be set again when the time increments to  
match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1  
are ignored.  
check now signal  
example  
AE_M  
AE_M = 1  
MINUTE ALARM  
=
1
MINUTE TIME  
0
AE_H  
HOUR ALARM  
=
HOUR TIME  
(1)  
set alarm flag AF  
AE_D  
DAY ALARM  
=
DAY TIME  
AE_W  
WEEKDAY ALARM  
=
013aaa088  
WEEKDAY TIME  
(1) Only when all enabled alarm settings are matching.  
It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5.  
Fig 10. Alarm function block diagram  
8.7 Register CLKOUT_control and clock output  
Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for  
use as a system clock, microcontroller clock, input to a charge pump, or for calibration of  
the oscillator.  
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Table 22. CLKOUT_control - CLKOUT control register (address 0Dh) bit description  
Bit  
Symbol  
Value  
Description  
7
FE  
0
the CLKOUT output is inhibited and CLKOUT output is  
set to logic 0  
1[1]  
-
the CLKOUT output is activated  
6 to 2 -  
unused  
1 to 0 FD[1:0]  
frequency output at pin CLKOUT  
00[1]  
01  
32.768 kHz  
1.024 kHz  
32 Hz  
10  
11  
1 Hz  
[1] Default value.  
8.8 Timer function  
The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at  
address 0Eh. The Timer_control register determines one of 4 source clock frequencies for  
the timer (4096 Hz, 64 Hz, 1 Hz, or 1⁄60 Hz), and enables or disables the timer. The timer  
counts down from a software-loaded 8-bit binary value. At the end of every countdown,  
the timer sets the timer flag TF. The TF may only be cleared by using the interface. The  
asserted TF can be used to generate an interrupt on pin INT. The interrupt may be  
generated as a pulsed signal every countdown period or as a permanently active signal  
which follows the state of TF. Bit TI_TP is used to control this mode selection. When  
reading the timer, the current countdown value is returned.  
8.8.1 Register Timer_control  
Table 23. Timer_control - timer control register (address 0Eh) bit description  
Bit  
Symbol  
Value  
Description  
7
TE  
0[1]  
timer is disabled  
timer is enabled  
unused  
1
6 to 2 -  
-
1 to 0 TD[1:0]  
timer source clock frequency select[2]  
00  
4.096 kHz  
01  
64 Hz  
10  
1 Hz  
1
11[2]  
⁄60 Hz  
[1] Default value.  
[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to  
1
⁄60 Hz for power saving.  
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8.8.2 Register Timer  
Table 24. Timer - timer value register (address 0Fh) bit description  
Bit  
Symbol  
Value  
Description  
countdown period in seconds:  
7 to 0  
TIMER[7:0]  
00h to FFh  
n
--------------------------------------------------------------  
CountdownPeriod =  
SourceClockFrequency  
where n is the countdown value  
Table 25. Timer register bits value range  
Bit  
7
6
5
4
3
2
1
0
128  
64  
32  
16  
8
4
2
1
The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the  
Timer_control register bit TE. The source clock for the timer is also selected by the  
Timer_control register. Other timer properties such as interrupt generation are controlled  
via the register Control_status_2.  
For accurate read back of the count down value, it is recommended to read the register  
twice and check for consistent results, since it is not possible to freeze the countdown  
timer counter during read back.  
8.9 EXT_CLK test mode  
A test mode is available which allows for on-board testing. In such a mode it is possible to  
set up test conditions and control the operation of the RTC.  
The test mode is entered by setting bit TEST1 in register Control_status_1. Then  
pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the  
signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then  
generate an increment of one second.  
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a  
maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is  
divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into  
a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP  
must be cleared before the prescaler can operate again).  
From a STOP condition, the first 1 second increment will take place after 32 positive  
edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second  
increment.  
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.  
When entering the test mode, no assumption as to the state of the prescaler can be made.  
8.9.1 Operation example:  
1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).  
2. Set STOP (Control_status_1, bit STOP = 1).  
3. Clear STOP (Control_status_1, bit STOP = 0).  
4. Set time registers to desired value.  
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5. Apply 32 clock pulses to CLKOUT.  
6. Read time registers to see the first change.  
7. Apply 64 clock pulses to CLKOUT.  
8. Read time registers to see the second change.  
Repeat steps 7 and 8 for additional increments.  
8.10 STOP bit function  
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP  
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and  
thus no 1 Hz ticks will be generated (see Figure 11). The time circuits can then be set and  
will not increment until the STOP bit is released (see Figure 12 and Table 26).  
OSCILLATOR STOP  
reset  
DETECTOR  
F
F
F
F
F
14  
0
1
2
13  
OSCILLATOR  
1 Hz tick  
STOP  
RESET  
RESET  
RESET  
1 Hz  
32 Hz  
CLKOUT source  
1024 Hz  
32768 Hz  
013aaa089  
Fig 11. STOP bit functional diagram  
The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop  
the generation of 1.024 kHz, 32 Hz, and 1 Hz.  
The lower two stages of the prescaler (F0 and F1) are not reset; and because the I2C-bus  
is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be  
between zero and one 8.192 kHz cycle (see Figure 12).  
8192 Hz  
stop released  
0 μs to 122 μs  
001aaf912  
Fig 12. STOP bit release timing  
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Table 26. First increment of time circuits after STOP bit release  
[1]  
Bit  
Prescaler bits  
F0F1-F2 to F14  
1 Hz tick  
Time  
Comment  
STOP  
hh:mm:ss  
Clock is running normally  
0
01-0 0001 1101 0100  
12:45:12  
prescaler counting normally  
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally  
1
XX-0 0000 0000 0000  
12:45:12  
prescaler is reset; time circuits are frozen  
New time is set by user  
1
XX-0 0000 0000 0000  
08:00:00  
prescaler is reset; time circuits are frozen  
STOP bit is released by user  
0
XX-0 0000 0000 0000  
XX-1 0000 0000 0000  
XX-0 1000 0000 0000  
XX-1 1000 0000 0000  
:
08:00:00  
08:00:00  
08:00:00  
08:00:00  
:
prescaler is now running  
-
-
-
:
11-1 1111 1111 1110  
00-0 0000 0000 0001  
10-0 0000 0000 0001  
:
08:00:00  
08:00:01  
08:00:01  
:
-
0 to 1 transition of F14 increments the time circuits  
-
:
11-1 1111 1111 1111  
00-0 0000 0000 0000  
10-0 0000 0000 0000  
:
08:00:01  
08:00:01  
08:00:01  
:
-
-
-
:
11-1 1111 1111 1110  
00-0 0000 0000 0001  
08:00:01  
08:00:02  
-
0 to 1 transition of F14 increments the time circuits  
013aaa076  
[1] F0 is clocked at 32.768 kHz.  
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP  
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset  
(see Table 26) and the unknown state of the 32 kHz clock.  
8.11 Reset  
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is  
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and  
all registers are set according to Table 27. I2C-bus communication is not possible during  
reset.  
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Table 27. Register reset value[1]  
Address Register name  
Bit  
7
0
0
1
x
6
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
0
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
Control_status_1  
Control_status_2  
VL_seconds  
Minutes  
Hours  
x
Days  
x
Weekdays  
x
Century_months  
Years  
x
x
Minute_alarm  
Hour_alarm  
Day_alarm  
Weekday_alarm  
CLKOUT_control  
Timer_control  
Timer  
1
1
1
1
1
0
x
[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.  
8.11.1 Power-On Reset (POR) override  
The POR duration is directly related to the crystal oscillator start-up time. Due to the long  
start-up times experienced by these types of circuits, a mechanism has been built in to  
disable the POR and hence speed up on-board test of the device. The setting of this  
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as  
shown in Figure 13. All timings are required minimums.  
Once the override mode has been entered, the device immediately stops, being reset,  
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus  
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be  
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0  
during normal operation has no effect except to prevent entry into the POR override  
mode.  
500 ns  
2000 ns  
SDA  
SCL  
8 ms  
power-on  
mgm664  
override active  
Fig 13. POR override sequence  
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9. Characteristics of the I2C-bus  
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.  
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must  
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only  
when the bus is not busy.  
9.1 Bit transfer  
One data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the HIGH period of the clock pulse as changes in the data line at this time  
will be interpreted as a control signal (see Figure 14).  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
mbc621  
Fig 14. Bit transfer  
9.2 START and STOP conditions  
Both data and clock lines remain HIGH when the bus is not busy.  
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START  
condition - S.  
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP  
condition - P (see Figure 15).  
SDA  
SCL  
SDA  
SCL  
S
P
START condition  
STOP condition  
mbc622  
Fig 15. Definition of START and STOP conditions  
9.3 System configuration  
A device generating a message is a transmitter; a device receiving a message is a  
receiver. The device that controls the message is the master; and the devices which are  
controlled by the master are the slaves (see Figure 16).  
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SDA  
SCL  
MASTER  
TRANSMITTER  
RECEIVER  
SLAVE  
TRANSMITTER  
RECEIVER  
MASTER  
TRANSMITTER  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
mba605  
Fig 16. System configuration  
9.4 Acknowledge  
The number of data bytes transferred between the START and STOP conditions from  
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge  
cycle.  
• A slave receiver, which is addressed, must generate an acknowledge after the  
reception of each byte.  
• Also a master receiver must generate an acknowledge after the reception of each  
byte that has been clocked out of the slave transmitter.  
• The device that acknowledges must pull-down the SDA line during the acknowledge  
clock pulse, so that the SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times must be taken into  
consideration).  
• A master receiver must signal an end of data to the transmitter by not generating an  
acknowledge on the last byte that has been clocked out of the slave. In this event, the  
transmitter must leave the data line HIGH to enable the master to generate a STOP  
condition.  
Acknowledgement on the I2C-bus is illustrated in Figure 17.  
data output  
by transmitter  
not acknowledge  
data output  
by receiver  
acknowledge  
SCL from  
master  
1
2
8
9
S
clock pulse for  
acknowledgement  
START  
condition  
mbc602  
Fig 17. Acknowledgement on the I2C-bus  
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9.5 I2C-bus protocol  
9.5.1 Addressing  
Before any data is transmitted on the I2C-bus, the device which should respond is  
addressed first. The addressing is always carried out with the first byte transmitted after  
the start procedure.  
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL  
is only an input signal, but the data signal SDA is a bidirectional line.  
Two slave addresses are reserved for the PCF8563:  
Read: A3h (10100011)  
Write: A2h (10100010)  
The PCF8563 slave address is illustrated in Figure 18.  
1
0
1
0
0
0
1
R/W  
group 2  
group 1  
mce189  
Fig 18. Slave address  
9.5.2 Clock and calendar READ or WRITE cycles  
The I2C-bus configuration for the different PCF8563 READ and WRITE cycles is shown in  
Figure 19, Figure 20 and Figure 21. The register address is a 4-bit value that defines  
which register is to be accessed next. The upper four bits of the register address are not  
used.  
acknowledgement  
from slave  
acknowledgement  
from slave  
acknowledgement  
from slave  
S
SLAVE ADDRESS  
0
A
REGISTER ADDRESS  
A
DATA  
A
P
R/W  
n bytes  
auto increment  
memory register address  
013aaa346  
Fig 19. Master transmits to slave receiver (WRITE mode)  
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acknowledgement  
from slave  
acknowledgement  
from slave  
acknowledgement  
from slave  
acknowledgement  
from slave  
SLAVE ADDRESS  
DATA  
S
0
A
REGISTER ADDRESS  
A
S
1
A
A
SLAVE ADDRESS  
n bytes  
R/W  
R/W  
auto increment  
memory register address  
(1)  
no acknowledgement  
from master  
1
P
DATA  
last byte  
auto increment  
memory register address  
013aaa041  
(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.  
Fig 20. Master reads after setting register address (write register address; READ data)  
acknowledgement  
from slave  
acknowledgement  
from master  
no acknowledgement  
from master  
1
A
A
DATA  
1
P
S
SLAVE ADDRESS  
DATA  
R/W  
n bytes  
last byte  
auto increment  
register address  
auto increment  
register address  
013aaa347  
Fig 21. Master reads slave immediately after first byte (READ mode)  
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9.6 Interface watchdog timer  
t < 1 s  
data  
START  
SLAVE ADDRESS DATA DATA  
STOP  
WD timer  
WD timer tracking  
time  
counters  
running  
time counters frozen  
running  
013aaa420  
a. Correct data transfer: read or write  
1 s < t < 2 s  
data transfer fail  
data  
START  
SLAVE ADDRESS  
running  
DATA DATA  
WD timer  
WD timer tracking  
time counters frozen  
WD trips  
time  
counters  
running  
013aaa421  
b. Incorrect data transfer; read or write  
Fig 22. Interface watchdog timer  
During read/write operations, the time counting circuits are frozen. To prevent a situation  
where the accessing device becomes locked and does not clear the interface, the  
PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s  
from the time a valid slave address is transmitted, then the PCF8563 will automatically  
clear the interface and allow the time counting circuits to continue counting. The watchdog  
will trigger between 1 s and 2 s after receiving a valid slave address. Each time the  
watchdog period is exceeded, 1 s will be lost from the time counters.  
The watchdog is implemented to prevent the excessive loss of time due to interface  
access failure e.g. if main power is removed from a battery backed-up system during an  
interface access.  
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10. Internal circuitry  
V
OSCI  
DD  
CLKOUT  
SCL  
OSCO  
INT  
V
SDA  
SS  
PCF8563  
013aaa348  
Fig 23. Device diode protection diagram  
PCF8563  
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Product data sheet  
Rev. 9 — 16 June 2011  
26 of 45  
PCF8563  
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11. Limiting values  
Table 28. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
0.5  
50  
0.5  
Max  
+6.5  
+50  
Unit  
V
VDD  
IDD  
VI  
supply voltage  
supply current  
input voltage  
mA  
V
on pins SCL, SDA,  
and OSCI  
+6.5  
VO  
II  
output voltage  
on pins CLKOUT and INT  
at any input  
0.5  
10  
10  
-
+6.5  
+10  
+10  
300  
V
input current  
mA  
mA  
mW  
IO  
output current  
at any output  
Ptot  
VESD  
total power dissipation  
electrostatic discharge voltage  
HBM  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
HVSON10 (PCF8563BS/4)  
DIP8 (PCF8563P/F4)  
SO8 (PCF8563T/F4)  
TSSOP8 (PCF8563TS/4)  
SO8 (PCF8563T/5)  
TSSOP8 (PCF8563TS/5)  
CDM  
-
3500  
V
-
2000  
V
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
[3]  
[4]  
HVSON10 (PCF8563BS/4)  
DIP8 (PCF8563P/F4)  
SO8 (PCF8563T/F4)  
SO8 (PCF8563T/5)  
TSSOP8 (PCF8563TS/4)  
TSSOP8 (PCF8563TS/5)  
-
2000  
500  
V
-
V
-
1000  
1500  
1500  
1750  
200  
V
-
V
-
V
-
V
Ilu  
latch-up current  
-
mA  
C  
C  
Tstg  
Tamb  
storage temperature  
ambient temperature  
65  
40  
+150  
+85  
operating device  
[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.  
[2] Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”.  
[3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (Tamb(max)).  
[4] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be stored at a temperature of  
+8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.  
PCF8563  
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Product data sheet  
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12. Static characteristics  
Table 29. Static characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise  
specified.  
Symbol  
Supplies  
VDD  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
[1]  
[1]  
supply voltage  
interface inactive;  
fSCL = 0 Hz;  
1.0  
-
5.5  
V
Tamb = 25 C  
interface active;  
fSCL = 400 kHz  
1.8  
-
-
5.5  
5.5  
V
V
clock data integrity;  
Vlow  
Tamb = 25 C  
IDD  
supply current  
interface active  
fSCL = 400 kHz  
fSCL = 100 kHz  
-
-
-
-
800  
200  
A  
A  
[2]  
[2]  
[2]  
[2]  
interface inactive (fSCL = 0 Hz); CLKOUT  
disabled; Tamb = 25 C  
VDD = 5.0 V  
VDD = 3.0 V  
VDD = 2.0 V  
-
-
-
275  
250  
225  
550  
500  
450  
nA  
nA  
nA  
interface inactive (fSCL = 0 Hz); CLKOUT  
disabled; Tamb = 40 C to +85 C  
VDD = 5.0 V  
VDD = 3.0 V  
VDD = 2.0 V  
-
-
-
500  
400  
400  
750  
650  
600  
nA  
nA  
nA  
interface inactive (fSCL = 0 Hz); CLKOUT  
enabled at 32 kHz; Tamb = 25 C  
VDD = 5.0 V  
VDD = 3.0 V  
VDD = 2.0 V  
-
-
-
825  
550  
425  
1600  
1000  
800  
nA  
nA  
nA  
interface inactive (fSCL = 0 Hz); CLKOUT  
enabled at 32 kHz; Tamb = 40 C to +85 C  
VDD = 5.0 V  
VDD = 3.0 V  
VDD = 2.0 V  
-
-
-
950  
650  
500  
1700  
1100  
900  
nA  
nA  
nA  
Inputs  
VIL  
LOW-level input  
voltage  
VSS  
-
0.3VDD  
VDD  
+1  
V
VIH  
ILI  
HIGH-level  
input voltage  
0.7VDD  
-
V
input leakage  
current  
VI = VDD or VSS  
1  
0
-
A  
pF  
[3]  
Ci  
input  
-
7
capacitance  
PCF8563  
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Table 29. Static characteristics …continued  
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise  
specified.  
Symbol  
Outputs  
IOL  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
LOW-level  
output sink current;  
output current  
VOL = 0.4 V; VDD = 5 V  
on pin SDA  
3
-
-
mA  
mA  
mA  
A  
on pin INT  
1
-
-
on pin CLKOUT  
1
-
-
ILO  
output leakage VO = VDD or VSS  
current  
1  
0
+1  
Voltage detector  
Vlow low voltage  
Tamb = 25 C; sets bit VL; see Figure 7  
-
0.9  
1.0  
V
[1] For reliable oscillator start-up at power-up: VDD(min)power-up = VDD(min) + 0.3 V.  
[2] Timer source clock = 1  
⁄60 Hz, level of pins SCL and SDA is VDD or VSS.  
[3] Tested on sample basis.  
mgr888  
mgr889  
1
1
I
I
DD  
DD  
(μA)  
(μA)  
0.8  
0.8  
0.6  
0.4  
0.2  
0
0.6  
0.4  
0.2  
0
0
2
4
6
0
2
4
6
V
(V)  
V
DD  
(V)  
DD  
Tamb = 25 C; Timer = 1 minute.  
Tamb = 25 C; Timer = 1 minute.  
Fig 24. Supply current IDD as a function of supply  
voltage VDD; CLKOUT disabled  
Fig 25. Supply current IDD as a function of supply  
voltage VDD; CLKOUT = 32 kHz  
PCF8563  
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Product data sheet  
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29 of 45  
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Real-time clock/calendar  
mgr891  
mgr890  
1
I
DD  
4
(μA)  
frequency  
0.8  
deviation  
(ppm)  
2
0.6  
0.4  
0.2  
0
0
−2  
−4  
0
2
4
6
−40  
0
40  
80  
120  
V
DD  
(V)  
T (°C)  
VDD = 3 V; Timer = 1 minute.  
Tamb = 25 C; normalized to VDD = 3 V.  
Fig 26. Supply current IDD as a function of  
temperature T; CLKOUT = 32 kHz  
Fig 27. Frequency deviation as a function of supply  
voltage VDD  
PCF8563  
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Product data sheet  
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13. Dynamic characteristics  
Table 30. Dynamic characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise  
specified.  
Symbol  
Oscillator  
COSCO  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
capacitance on pin OSCO  
15  
-
25  
35  
-
pF  
fosc/fosc  
relative oscillator frequency variation  
VDD = 200 mV;  
Tamb = 25 C  
0.2  
ppm  
Quartz crystal parameters (f = 32.768 kHz)  
Rs  
series resistance  
load capacitance  
trimmer capacitance  
-
-
-
-
100  
12.5  
25  
k  
pF  
pF  
[1]  
CL  
parallel  
7
5
Ctrim  
external;  
on pin OSCI  
CLKOUT output  
[2]  
[5]  
CLKOUT  
duty cycle on pin CLKOUT  
-
50  
-
%
I2C-bus timing characteristics (see Figure 28)[3][4]  
fSCL  
SCL clock frequency  
-
-
-
-
-
-
400  
kHz  
s  
tHD;STA  
tSU;STA  
tLOW  
tHIGH  
tr  
hold time (repeated) START condition  
set-up time for a repeated START condition  
LOW period of the SCL clock  
0.6  
0.6  
1.3  
0.6  
-
-
-
-
s  
s  
HIGH period of the SCL clock  
s  
rise time of both SDA and SCL signals  
standard-mode  
fast-mode  
-
-
-
-
-
-
-
-
-
1
s  
s  
s  
pF  
ns  
ns  
s  
ns  
-
0.3  
0.3  
400  
-
tf  
fall time of both SDA and SCL signals  
capacitive load for each bus line  
data set-up time  
-
Cb  
-
tSU;DAT  
tHD;DAT  
tSU;STO  
tw(spike)  
100  
0
data hold time  
-
set-up time for STOP condition  
spike pulse width  
0.6  
-
-
on bus  
50  
Ctrim COSCO  
-----------------------------------------  
.
[1] CL is a calculation of Ctrim and COSCO in series: CL  
=
Ctrim + COSCO  
[2] Unspecified for fCLKOUT = 32.768 kHz.  
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage  
swing of VSS to VDD  
.
[4] A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.  
[5] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.  
PCF8563  
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Product data sheet  
Rev. 9 — 16 June 2011  
31 of 45  
PCF8563  
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Real-time clock/calendar  
SDA  
t
t
t
f
BUF  
LOW  
SCL  
SDA  
t
HD;STA  
t
t
t
SU;DAT  
r
HD;DAT  
t
HIGH  
t
SU;STA  
t
SU;STO  
mga728  
Fig 28. I2C-bus timing waveforms  
14. Application information  
V
DD  
SDA  
SCL  
MASTER  
TRANSMITTER/  
RECEIVER  
1 F  
100 nF  
V
DD  
SCL  
SDA  
CLOCK CALENDAR  
OSCI  
PCF8563  
V
R
DD  
OSCO  
V
SS  
R
R: pull-up resistor  
t
r
R =  
C
b
SDA SCL  
mgm665  
2
(I C-bus)  
Fig 29. Application diagram  
PCF8563  
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Product data sheet  
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32 of 45  
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14.1 Quartz frequency adjustment  
14.1.1 Method 1: fixed OSCI capacitor  
By evaluating the average capacitance necessary for the application layout, a fixed  
capacitor can be used. The frequency is best measured via the 32.768 kHz signal  
available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz  
crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average  
5 ppm). Average deviations of 5 minutes per year can be easily achieved.  
14.1.2 Method 2: OSCI trimmer  
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a  
trimmer is possible.  
14.1.3 Method 3: OSCO output  
Direct measurement of OSCO out (accounting for test probe capacitance).  
PCF8563  
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Product data sheet  
Rev. 9 — 16 June 2011  
33 of 45  
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Real-time clock/calendar  
15. Package outline  
HVSON10: plastic thermal enhanced very thin small outline package; no leads;  
10 terminals; body 3 x 3 x 0.85 mm  
SOT650-1  
0
1
2 mm  
scale  
X
B
A
D
A
A
1
E
c
detail X  
terminal 1  
index area  
C
e
1
terminal 1  
index area  
y
y
v
M
e
C
C
A
B
b
C
1
1
5
w
M
L
E
h
6
10  
D
h
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
(1)  
(1)  
UNIT  
A
b
E
e
e
y
c
D
D
E
L
v
w
y
1
1
h
1
h
0.05 0.30  
0.00 0.18  
3.1  
2.9  
2.55  
2.15  
3.1  
2.9  
1.75  
1.45  
0.55  
0.30  
mm  
0.05  
0.1  
1
0.2  
0.5  
2
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-01-22  
02-02-08  
SOT650-1  
- - -  
MO-229  
- - -  
Fig 30. Package outline SOT650-1 (HVSON10) of PCF8563BS  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
34 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
DIP8: plastic dual in-line package; 8 leads (300 mil)  
SOT97-1  
D
M
E
A
2
A
A
1
L
c
w M  
Z
b
1
e
(e )  
1
M
H
b
b
2
8
5
pin 1 index  
E
1
4
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
Z
A
A
A
2
(1)  
(1)  
1
w
UNIT  
mm  
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.  
min.  
max.  
max.  
1.73  
1.14  
0.53  
0.38  
1.07  
0.89  
0.36  
0.23  
9.8  
9.2  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.1  
7.62  
0.3  
0.254  
0.01  
1.15  
0.068 0.021 0.042 0.014  
0.045 0.015 0.035 0.009  
0.39  
0.36  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.02  
0.13  
0.045  
Note  
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-13  
SOT97-1  
050G01  
MO-001  
SC-504-8  
Fig 31. Package outline SOT97-1 (DIP8) of PCF8563P  
PCF8563  
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Product data sheet  
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35 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 32. Package outline SOT96-1 (SO8) of PCF8563T  
PCF8563  
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Product data sheet  
Rev. 9 — 16 June 2011  
36 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm  
SOT505-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )  
2
A
3
A
1
pin 1 index  
θ
L
p
L
1
4
detail X  
e
w M  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
max.  
0.15  
0.05  
0.95  
0.80  
0.45  
0.25  
0.28  
0.15  
3.1  
2.9  
3.1  
2.9  
5.1  
4.7  
0.7  
0.4  
0.70  
0.35  
6°  
0°  
mm  
1.1  
0.65  
0.25  
0.94  
0.1  
0.1  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-04-09  
03-02-18  
SOT505-1  
Fig 33. Package outline SOT505-1 (TSSOP8) of PCF8563TS  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
37 of 45  
PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
16. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that  
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent  
standards.  
17. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
17.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
17.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
• Through-hole components  
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
• Board specifications, including the board finish, solder masks and vias  
• Package footprints, including solder thieves and orientation  
• The moisture sensitivity level of the packages  
• Package placement  
• Inspection and repair  
• Lead-free soldering versus SnPb soldering  
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17.3 Wave soldering  
Key characteristics in wave soldering are:  
• Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
• Solder bath specifications, including temperature and impurities  
17.4 Reflow soldering  
Key characteristics in reflow soldering are:  
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 34) than a SnPb process, thus  
reducing the process window  
• Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 31 and 32  
Table 31. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 32. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 34.  
PCF8563  
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Product data sheet  
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39 of 45  
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maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 34. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
18. Abbreviations  
Table 33. Abbreviations  
Acronym  
BCD  
CDM  
CMOS  
ESD  
HBM  
I2C  
Description  
Binary Coded Decimal  
Charged-Device Model  
Complementary Metal Oxide Semiconductor  
ElectroStatic Discharge  
Human Body Model  
Inter-Integrated Circuit  
Integrated Circuit  
IC  
LSB  
Least Significant Bit  
Most Significant Bit  
MSB  
MSL  
PCB  
POR  
RTC  
SCL  
Moisture Sensitivity Level  
Printed-Circuit Board  
Power-On Reset  
Real-Time Clock  
Serial CLock line  
SDA  
SMD  
Serial DAta line  
Surface Mount Device  
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19. References  
[1] AN10365 — Surface mount reflow soldering description  
[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous  
semiconductor devices  
[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena  
[4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for  
Nonhermetic Solid State Surface Mount Devices  
[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body  
Model (HBM)  
[6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for  
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components  
[7] JESD78 — IC Latch-Up Test  
[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive  
(ESDS) Devices  
[9] NX3-00092 — NXP store and transport requirements  
[10] SNV-FA-01-02 — Marking Formats Integrated Circuits  
[11] UM10204 — I2C-bus specification and user manual  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
41 of 45  
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20. Revision history  
Table 34. Revision history  
Document ID  
PCF8563 v.9  
Modifications:  
PCF8563 v.8  
PCF8563 v.7  
PCF8563_6  
PCF8563_5  
Release date  
20110616  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
PCF8563 v.8  
• Added design-in and replacement part information  
20101118  
20100723  
20080221  
20070717  
20040312  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
Product data  
-
-
-
-
-
PCF8563 v.7  
PCF8563_6  
PCF8563_5  
PCF8563-04  
PCF8563-03  
PCF8563-04  
(9397 750 12999)  
PCF8563-03  
(9397 750 11158)  
20030414  
19990416  
19980325  
Product data  
-
-
-
PCF8563-02  
PCF8563-02  
(9397 750 04855)  
Product data  
PCF8563_N_1  
-
PCF8563_N_1  
Objective specification  
(9397 750 03282)  
PCF8563  
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Product data sheet  
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42 of 45  
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21. Legal information  
21.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
21.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
21.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
43 of 45  
PCF8563  
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Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
non-automotive qualified products in automotive equipment or applications.  
21.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
I2C-bus — logo is a trademark of NXP B.V.  
22. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PCF8563  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 9 — 16 June 2011  
44 of 45  
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23. Contents  
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1  
9.5  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23  
Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Clock and calendar READ or WRITE cycles . 23  
Interface watchdog timer . . . . . . . . . . . . . . . . 25  
9.5.1  
9.5.2  
9.6  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
10  
11  
12  
13  
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27  
Static characteristics . . . . . . . . . . . . . . . . . . . 28  
Dynamic characteristics. . . . . . . . . . . . . . . . . 31  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
14  
14.1  
14.1.1  
14.1.2  
14.1.3  
Application information . . . . . . . . . . . . . . . . . 32  
Quartz frequency adjustment. . . . . . . . . . . . . 33  
Method 1: fixed OSCI capacitor. . . . . . . . . . . 33  
Method 2: OSCI trimmer . . . . . . . . . . . . . . . . 33  
Method 3: OSCO output . . . . . . . . . . . . . . . . 33  
8
8.1  
8.2  
8.3  
Functional description . . . . . . . . . . . . . . . . . . . 5  
CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5  
Register organization . . . . . . . . . . . . . . . . . . . . 6  
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7  
Register Control_status_1 . . . . . . . . . . . . . . . . 7  
Register Control_status_2 . . . . . . . . . . . . . . . . 7  
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Time and date registers . . . . . . . . . . . . . . . . . . 9  
Register VL_seconds . . . . . . . . . . . . . . . . . . . . 9  
Voltage-low detector and clock monitor . . . . . . 9  
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10  
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10  
Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10  
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 10  
Register Century_months. . . . . . . . . . . . . . . . 11  
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12  
Setting and reading the time. . . . . . . . . . . . . . 12  
Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 14  
Register Minute_alarm . . . . . . . . . . . . . . . . . . 14  
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14  
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14  
Register Weekday_alarm . . . . . . . . . . . . . . . . 14  
Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Register CLKOUT_control and clock output. . 15  
Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16  
Register Timer_control . . . . . . . . . . . . . . . . . . 16  
Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17  
EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17  
Operation example: . . . . . . . . . . . . . . . . . . . . 17  
STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18  
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Power-On Reset (POR) override . . . . . . . . . . 20  
15  
16  
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34  
Handling information . . . . . . . . . . . . . . . . . . . 38  
8.3.1  
8.3.2  
8.3.2.1  
8.4  
8.4.1  
8.4.1.1  
8.4.2  
8.4.3  
8.4.4  
8.4.5  
8.4.6  
8.4.7  
8.5  
17  
Soldering of SMD packages. . . . . . . . . . . . . . 38  
Introduction to soldering. . . . . . . . . . . . . . . . . 38  
Wave and reflow soldering. . . . . . . . . . . . . . . 38  
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 39  
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 39  
17.1  
17.2  
17.3  
17.4  
18  
19  
20  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 42  
21  
Legal information . . . . . . . . . . . . . . . . . . . . . . 43  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
21.1  
21.2  
21.3  
21.4  
8.6  
8.6.1  
8.6.2  
8.6.3  
8.6.4  
8.6.5  
8.7  
22  
23  
Contact information . . . . . . . . . . . . . . . . . . . . 44  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
8.8  
8.8.1  
8.8.2  
8.9  
8.9.1  
8.10  
8.11  
8.11.1  
9
Characteristics of the I2C-bus . . . . . . . . . . . . 21  
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
START and STOP conditions . . . . . . . . . . . . . 21  
System configuration . . . . . . . . . . . . . . . . . . . 21  
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22  
9.1  
9.2  
9.3  
9.4  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 16 June 2011  
Document identifier: PCF8563  

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