PCF8576D_11_技术文档

PCF8576D

Universal LCD driver for low multiplex rates

Rev. 10 — 14 February 2011

Product data sheet

1. General description

The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD) with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily

cascaded for larger LCD applications. The PCF8576D is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing and by display memory switching (static and duplex drive

modes).

2. Features and benefits

AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications

Single chip LCD controller and driver

Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing

Selectable display bias configuration: static, ¹⁄₂or ¹⁄₃

Internal LCD bias generation with voltage-follower buffers

40 segment drives:

Up to 20 7-segment numeric characters

Up to 10 14-segment alphanumeric characters

Any graphics of up to 160 elements

40 × 4-bit RAM for display data storage

Auto-incremented display data loading across device subaddress boundaries

Display memory bank switching in static and duplex drive modes

Versatile blinking modes

Independent supplies possible for LCD and logic voltages

Wide power supply range: from 1.8 V to 5.5 V

Wide logic LCD supply range:

From 2.5 V for low-threshold LCDs

Up to 6.5 V for high-threshold twisted nematic LCDs

Low power consumption

400 kHz I²C-bus interface

May be cascaded for large LCD applications (up to 2560 elements possible)

No external components required

Compatible with chip-on-glass and chip-on-board technology

Manufactured in silicon gate CMOS process

PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF8576DT/2

TSSOP56

plastic thin shrink small outline package, SOT364-1

56 leads; body width 6.1 mm

PCF8576DT/S400/2 TSSOP56

plastic thin shrink small outline package, SOT364-1

56 leads; body width 6.1 mm

PCF8576DU/DA/2

wire bond die 59 bonding pads^[1]

PCF8576DU/DA

PCF8576DU/2DA/2 bare die

59 bumps^[2]

PCF8576DU/2DA

[1] Chips in tray.

[2] Chips with bumps in tray.

4. Marking

Table 2.

Marking codes

Type number

Marking code

PCF8576DT

PCF8576DT/2

PCF8576DT/S400/2

PCF8576DU/DA/2

PCF8576DU/2DA/2

PCF8576DT/S400

PC8576D-2

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

5. Block diagram

BP0 BP2 BP1 BP3

S0 to S39

40

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT

OUTPUTS

LCD

VOLTAGE

SELECTOR

DISPLAY

REGISTER

DISPLAY

CONTROLLER

OUTPUT BANK SELECT

AND BLINK CONTROL

LCD BIAS

GENERATOR

V

SS

CLK

DISPLAY RAM

40 × 4-BIT

CLOCK SELECT

AND TIMING

BLINKER

TIMEBASE

PCF8576D

SYNC

POWER-ON

RESET

COMMAND

DECODER

WRITE DATA

CONTROL

DATA POINTER AND

AUTO INCREMENT

OSC

OSCILLATOR

V

DD

SCL

SDA

2

INPUT

FILTERS

I C-BUS

SUBADDRESS

COUNTER

CONTROLLER

SA0

A0

A1

A2

001aai900

Fig 1. Block diagram of PCF8576D

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

BP2

BP1

BP3

S0

BP0

2

V

LCD

SS

3

4

SA0

A2

5

S1

6

S2

A1

7

S3

A0

8

S4

OSC

9

S5

V

DD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

S6

CLK

SYNC

SCL

SDA

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

PCF8576DT

001aaf646

Top view. For mechanical details, see Figure 24.

Fig 2. Pinning diagram for PCF8576DT/x (TSSOP56)

PCF8576D

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Universal LCD driver for low multiplex rates

S3

S2

S1

S0

21

20

19

18

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

BP3

BP1

BP2

BP0

17

16

15

14

PCF8576DU

V

13

LCD

V

12

11

SS

SA0

A2

A1

10

9

001aag424

Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 25

and Figure 26.

Fig 3. Pinning diagram for PCF8576DU/x (bare die)

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

6.2 Pin description

Table 3.

Symbol

Pin description

Description

PCF8576DT/x

PCF8576DU/x

SDA

SCL

44

1, 58, 59

I²C-bus serial data input and output

I²C-bus serial clock input

external clock input or output

supply voltage

45

2, 3

CLK

47

5

V_DD

48

6

SYNC

OSC

A0 to A2

SA0

46

4

cascade synchronization input or output

internal oscillator enable input

subaddress inputs

49

7

50 to 52

53

8 to 10

11

I²C-bus address input; bit 0

V_SS

54

12^[1]

13

ground supply voltage

V_LCD

55

LCD supply voltage

BP0, BP2,

BP1, BP3

56, 1, 2, 3

14 to 17

LCD backplane outputs

S0 to S39

n.c.

4 to 43

-

18 to 57

-

LCD segment outputs

not connected

[1] The substrate (rear side of the die) is connected to V_SSand should be electrically isolated.

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8576D is a versatile peripheral device designed to interface any

microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any

static or multiplexed LCD containing up to four backplanes and up to 40 segments.

The possible display configurations of the PCF8576D depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 4. All

of these configurations can be implemented in the typical system shown in Figure 4.

Table 4.

Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

Dot matrix/

Elements

7-segment

14-segment

4

3

2

1

160

120

80

20

15

10

5

10

7

160 (4 × 40)

120 (3 × 40)

80 (2 × 40)

40 (1 × 40)

5

40

2

V

DD

t

r

R ≤

2C

B

V

DD

LCD

SDA

SCL

OSC

HOST

MICRO-

PROCESSOR/

MICRO-

40 segment drives

4 backplanes

LCD PANEL

PCF8576D

(up to 160

elements)

CONTROLLER

A0 A1 A2 SA0

V

SS

V

SS

mdb079

The resistance of the power lines must be kept to a minimum.

For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line

must be routed separately between the chip and the connector.

Fig 4. Typical system configuration

The host microprocessor or microcontroller maintains the 2-line I²C-bus communication

channel with the PCF8576D. The internal oscillator is enabled by connecting

pin OSC to pin V_SS. The appropriate biasing voltages for the multiplexed LCD waveforms

are generated internally. The only other connections required to complete the system are

to the power supplies (V_DD, V_SSand V_LCD) and the LCD panel chosen for the application.

7.1 Power-on reset

At power-on the PCF8576D resets to the following starting conditions:

• All backplane outputs are set to V_LCD

• All segment outputs are set to V_LCD

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

• Input and output bank selectors are reset

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• Display is disabled

Data transfers on the I²C-bus must be avoided for 1 ms following power-on to allow the

reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between V_LCDand V_SS. The middle resistor can be

bypassed to provide a ¹⁄₂bias voltage level for the 1:2 multiplex configuration. The LCD

voltage can be temperature compensated externally using the supply to pin V_LCD

.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command (see Table 9) from the command decoder. The biasing configurations

that apply to the preferred modes of operation, together with the biasing characteristics as

functions of V_LCDand the resulting discrimination ratios (D), are given in Table 5.

Table 5.

Discrimination ratios

Number of:

LCD drive

mode

LCD bias

configuration

V_off(RMS)V_on(RMS)

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_off(RMS)

V_on(RMS)

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1

∞

1

1:2 multiplex

1:3 multiplex

1:4 multiplex

⁄

2

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1

a²+ 2a + n

n × (1 + a)²

V_on(RMS)

=

-----------------------------

(1)

V

LCD

PCF8576D

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PCF8576D

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Universal LCD driver for low multiplex rates

where the values for n are

n = 1 for static mode

n = 2 for 1:2 multiplex

n = 3 for 1:3 multiplex

n = 4 for 1:4 multiplex

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n × (1 + a)²

V_off(RMS)

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

(a + 1)²+ (n – 1)

V_on(RMS)

----------------------

D =

=

-------------------------------------------

(a – 1)²+ (n – 1)

V_off(RMS)

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

=

6 × V_off(RMS)= 2.449V_off(RMS)

(4 × 3)

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

= 2.309V_off(RMS)

---------------------

3

These compare with V_LCD= 3V_off(RMS)when ¹⁄₃bias is used.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage.

7.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependant on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_low) and the other at 90 % relative transmission (at V_high), see Figure 5.

For a good contrast performance, the following rules should be followed:

V

_on(RMS)≥ V_high

_off(RMS)≤ V_low

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

V_lowand V_highare properties of the LCD liquid and can be provided by the module

manufacturer.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

100 %

90 %

10 %

V

RMS

[V]

V

low

V

high

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

001aam358

Fig 5. Electro-optical characteristic: relative transmission curve of the liquid

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment drive (S_n) waveforms for this mode are shown in Figure 6.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

state 1

0 V

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl745

(1) V_state1(t) = V_Sn(t) − V_BP0(t).

(2) V_on(RMS)= V_LCD

.

(3) V_state2(t) = V_Sn+1(t) − V_BP0(t).

(4) V_off(RMS)= 0 V.

Fig 6. Static drive mode waveforms

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This

mode allows fractional LCD bias voltages of ¹⁄₂bias or ¹⁄₃bias as shown in Figure 7 and

Figure 8.

T

fr

V

LCD

LCD segments

V

/ 2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/ 2

0 V

−V

state 1

/ 2

LCD

−V

LCD

V

LCD

/ 2

LCD

0 V

state 2

−V

/ 2

LCD

−V

(b) Resultant waveforms

at LCD segment.

mgl746

(1) V_state1(t) = V_Sn(t) − V_BP0(t).

(2) V_on(RMS)= 0.791V_LCD

(3) V_state2(t) = V_Sn+1(t) − V_BP1(t).

(4) V_off(RMS)= 0.354V_LCD

.

Fig 7. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

Sn

V

LCD

SS

state 1

V

LCD

state 2

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl747

(1) V_state1(t) = V_Sn(t) − V_BP0(t).

(2) V_on(RMS)= 0.745V_LCD

(3) V_state2(t) = V_Sn+1(t) − V_BP1(t).

(4) V_off(RMS)= 0.333V_LCD

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies

(see Figure 9).

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

BP2

Sn

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl748

(1) V_state1(t) = V_Sn(t) − V_BP0(t).

(2) V_on(RMS)= 0.638V_LCD

(3) V_state2(t) = V_Sn+1(t) − V_BP1(t).

(4) V_off(RMS)= 0.333V_LCD

.

Fig 9. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCF8576D

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Product data sheet

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PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see

Figure 10).

T

fr

V

LCD segments

LCD

2V

/ 3

LCD

/ 3

BP0

BP1

BP2

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

BP3

Sn

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

Sn+3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl749

(1) V_state1(t) = V_Sn(t) − V_BP0(t).

(2) V_on(RMS)= 0.577V_LCD

(3) V_state2(t) = V_Sn+1(t) − V_BP1(t).

(4) V_off(RMS)= 0.333V_LCD

.

Fig 10. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

PCF8576D

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Product data sheet

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PCF8576D

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Universal LCD driver for low multiplex rates

7.5 Oscillator

7.5.1 Internal clock

The internal logic of the PCF8576D and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin V_SS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCF8576Ds in the system that are connected in cascade.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD

.

The LCD frame signal frequency is determined by the clock frequency (f_clk).

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF8576D timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF8576D in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

f_clk

-------

.

clock: f_fr

=

24

7.7 Display register

The display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs and each column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display latch. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

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In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals

and may also be paired to increase the drive capabilities.

In the static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map Figure 11 shows the rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which

correspond with the segment outputs S0 to S39. In multiplexed LCD applications the

segment data of the first, second, third and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

35 36 37 38 39

0

1

2

3

display RAM bits

(rows)/

backplane outputs

(BP)

mbe525

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 11. Display RAM bit map

When display data is transmitted to the PCF8576D, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triplets or

quadruplets. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 12; the RAM filling organization depicted

applies equally to other LCD types.

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The following applies to Figure 12:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer.

This allows the loading of an individual display data byte, or a series of display data bytes,

into any location of the display RAM. The sequence commences with the initialization of

the data pointer by the load-data-pointer command (see Section 7.17).

Following this command, an arriving data byte is stored at the display RAM address

indicated by the data pointer. The filling order is shown in Figure 12.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

After each byte is stored, the contents of the data pointer is automatically incremented by

a value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

defined by the device-select command (see Section 7.17). If the contents of the

subaddress counter and the hardware subaddress do not match then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overflows.

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The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character (such as during the 14^th

display data byte transmitted in 1:3 multiplex mode).

The hardware subaddress must not be changed while the device is being accessed on the

I²C-bus interface.

7.13 Output bank selector

The output bank selector selects one of the four bits per display RAM address for transfer

to the display latch. The actual bit chosen depends on the selected LCD drive mode in

operation and on the instant in the multiplex sequence.

• In 1:4 mode, all RAM addresses of bit 0 are selected, these are followed by the

contents of bit 1, bit 2 and then bit 3.

• In 1:3 mode, bits 0, 1 and 2 are selected sequentially

• In 1:2 mode, bits 0 and 1 are selected

• In static mode, bit 0 is selected

The PCF8576D includes a RAM bank switching feature in the static and 1:2 drive modes.

In the static drive mode, the bank-select command (see Section 7.17) may request the

contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the

contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision

for preparing display information in an alternative bank and to be able to switch to it once

it is assembled.

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration.

The bank-select command (see Section 7.17) can be used to load display data in bit 2 in

static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are

independent of the output bank selector.

7.15 Blinker

The PCF8576D has a very versatile display blinking capability. The whole display can

blink at a frequency selected by the blink-select command (see Section 7.17). Each blink

frequency is a fraction of the clock frequency; the ratio between the clock frequency and

blink frequency depends on the blink mode selected (see Table 6).

An additional feature allows an arbitrary selection of LCD segments to blink in the static

and 1:2 drive modes. This is implemented without any communication overheads by the

output bank selector which alternates the displayed data between the data in the display

RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can

also be implemented by the blink-select command (see Section 7.17).

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In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of

LCD segments can blink selectively by changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency by

sequentially resetting and setting the display enable bit E at the required rate using the

mode-set command (see Section 7.17).

Table 6.

Blinking frequencies^[1]

Blink mode

Normal operating mode ratio

Nominal blink frequency

off

1

-

blinking off

2 Hz

f_clk

---------

768

2

3

1 Hz

f_clk

------------

1536

0.5 Hz

f_clk

------------

3072

[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator

frequency (f_clk) of 1536 Hz (see Section 11).

7.16 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 13).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 13. Bit transfer

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7.16.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 14).

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 14. Definition of START and STOP conditions

7.16.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves (see Figure 15).

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 15. System configuration

7.16.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

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• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is shown in Figure 16.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 16. Acknowledgement of the I²C-bus

7.16.5 I²C-bus controller

The PCF8576D acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCF8576D are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally

tied to V_SSwhich defines the hardware subaddress 0. In multiple device

applications A0, A1 and A2 are tied to V_SSor V_DDin accordance with a binary coding

scheme such that no two devices with a common I²C-bus slave address have the same

hardware subaddress.

7.16.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.16.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D.

The least significant bit of the slave address that a PCF8576D will respond to is defined by

the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to

a read access. Having two reserved slave addresses allows the following on the same

I²C-bus:

• Up to 16 PCF8576Ds for very large LCD applications

• The use of two types of LCD multiplex drive.

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The I²C-bus protocol is shown in Figure 17. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of two possible PCF8576D

slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the

slave address respond by asserting an acknowledge in parallel. This I²C-bus transfer is

ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.

acknowledge

acknowledge by

by A0, A1 and A2

all addressed

selected

PCF8576D only

PCF8576Ds

R/W

0

slave address

S

A

0

1

0

A

C

COMMAND

A

DISPLAY DATA

A

P

S

1 byte

n ≥ 1 byte(s)

n ≥ 0 byte(s)

update data pointers

and if necessary,

subaddress counter

mdb078

Fig 17. I²C-bus protocol

After an acknowledgement, one or more command bytes follow, that define the status of

each addressed PCF8576D.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C, (see Figure 18). The command bytes are also acknowledged by all addressed

PCF8576D on the bus.

MSB

LSB

C

REST OF OPCODE

msa833

Fig 18. Format of command byte

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCF8576D device.

An acknowledgement after each byte is asserted only by the PCF8576Ds that are

addressed via address lines A0, A1 and A2. After the last display byte, the I²C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I²C-bus

access.

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7.17 Command decoder

The command decoder identifies command bytes that arrive on the I²C-bus.

The commands available to the PCF8576D are defined in Table 7.

Table 7.

Definition of PCF8576D commands

Operation Code

Command

Bit

Reference

7

6

1

0

1

5

4

3

2

1

0

[1]

mode-set

C

0

E

P3

0

B

M1

P1

A1

I

M0

P0

A0

O

Table 9

load-data-pointer

device-select

bank-select

blink-select

P5

1

P4

0

P2

A2

0

Table 10

Table 11

Table 12

1

0

A

BF1 BF0 Table 13

[1] Not used.

All available commands carry a continuation bit C in their most significant bit position as

shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to

arrive will also represent a command. If this bit is reset, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data (see Table 8).

Table 8.

C bit description

Bit

Symbol Value

Description

continue bit

7

C

0

last control byte in the transfer; next byte will be regarded

as display data

1

control bytes continue; next byte will be a command too

Table 9.

Mode-set command bits description

Bit

7

Symbol Value

Description

C

-

0, 1

10

-

see Table 8

6, 5

4

fixed value

-

unused

3

E

display status

0

1

disabled (blank)^[1]

enabled

2

B

LCD bias configuration^[2]

¹⁄₃bias

¹⁄₂bias

0

1

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

01

10

11

00

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Not applicable for static drive mode.

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Table 10. Load-data-pointer command bits description

Bit

7

Symbol Value

Description

C

0, 1

0

see Table 8

fixed value

6

-

5 to 0

P[5:0]

000000 to

100111

6 bit binary value, 0 to 39; transferred to the data pointer to

define one of forty display RAM addresses

Table 11. Device-select command bits description

Bit

Symbol Value

Description

see Table 8

fixed value

7

C

0, 1

6 to 3

2 to 0

-

1100

A[2:0]

000 to 111

3 bit binary value, 0 to 7; transferred to the subaddress

counter to define one of eight hardware subaddresses

Table 12. Bank-select command bits description

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7

C

-

0, 1

see Table 8

fixed value

6 to 2

1

11110

I

input bank selection; storage of arriving display data

0

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

0

O

output bank selection; retrieval of LCD display data

0

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

Table 13. Blink-select command bits description

Bit

7

Symbol Value

Description

C

-

0, 1

see Table 8

6 to 3

2

1110

fixed value

A

blink mode selection

0

1

normal blinking^[1]

alternate RAM bank blinking^[2]

1 to 0

BF[1:0]

blink frequency selection

00

01

10

11

off

1

2

3

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

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7.18 Display controller

The display controller executes the commands identified by the command decoder. It

contains the device’s status registers and coordinates their effects. The display controller

is also responsible for loading display data into the display RAM in the correct filling order.

8. Internal circuitry

V

DD

V

DD

SA0

CLK

V

SS

DD

SCL

V

SS

DD

V

SS

OSC

V

SS

DD

SDA

SYNC

V

SS

DD

A0, A1 A2

V

SS

LCD

BP0, BP1,

BP2, BP3

V

SS

V

LCD

S0 to S39

V

SS

mdb076

Fig 19. Device protection circuits

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9. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 14. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

−0.5

Max

6.5

Unit

V

V_DD

V_LCD

V_I

supply voltage

LCD supply voltage

input voltage

+7.5

+6.5

V

on each of the pins CLK,

SDA, SCL, SYNC, SA0,

OSC, A0 to A2

V

V_O

output voltage

on each of the pins S0 to

S39, BP0 to BP3

−0.5

+7.5

V

I_I

input current

output current

supply current

−10

−50

-

+10

mA

mW

V

I_O

I_DD

+10

+50

I_DD(LCD)LCD supply current

+50

I_SS

ground supply current

total power dissipation

output power

+50

P_tot

P_o

400

-

100

[1]

[2]

[3]

[4]

[5]

V_ESD

electrostatic discharge

voltage

HBM

MM

-

±5000

±200

±1000

100

-

V

CDM

-

V

I_lu

latch-up current

-

mA

°C

T_stg

T_amb

storage temperature

ambient temperature

−65

−40

+150

+85

°C

[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”.

[3] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.

[4] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (T_amb(max)).

[5] According to the NXP store and transport requirements (see Ref. 12 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long-term storage products,

divergent conditions are described in that document.

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10. Static characteristics

Table 15. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= −40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

2.5

-

5.5

6.5

20

-

V

[1]

[2]

V_LCD

I_DD

LCD supply voltage

supply current

-

V

f_clk(ext)= 1536 Hz

6

μA

V_DD= 3.0 V;

-

2.7

T_amb= 25 °C

[2]

I_DD(LCD)

LCD supply current

f_clk(ext)= 1536 Hz

-

18

30

-

μA

V_DD(LCD)= 3.0 V;

17.5

T_amb= 25 °C

Logic

V_P(POR)

V_IL

power-on reset supply voltage

LOW-level input voltage

1.0

1.3

-

1.6

V

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

V_SS

0.3V_DD

[3][4]

V_IH

HIGH-level input voltage

LOW-level output current

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

0.7V_DD

-

V_DD

V

I_OL

output sink current;

V_OL= 0.4 V; V_DD= 5 V

on pins CLK and SYNC

on pin SDA

1

3

1

-

mA

I_OH(CLK)

I_L

HIGH-level output current on pin CLK output source current;

V_OH= 4.6 V; V_DD= 5 V

leakage current

V_I= V_DDor V_SS

;

−1

-

+1

μA

on pins CLK, SCL, SDA,

A0 to A2 and SA0

I_L(OSC)

leakage current on pin OSC

input capacitance

V_I= V_DD

−1

-

+1

7

μA

[5]

[6]

C_I

-

pF

LCD outputs

ΔV_O

output voltage variation

on pins BP0 to BP3 and

S0 to S39

−100

-

+100

mV

R_O

output resistance

V_LCD= 5 V

on pins BP0 to BP3

on pins S0 to S39

-

1.5

6.0

-

kΩ

[1] V_LCD> 3 V for ¹⁄₃bias.

[2] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[3] When tested, I²C pins SCL and SDA have no diode to V_DDand may be driven to the V_Ilimiting values given in Table 14 (see Figure 19

too).

[4] Propagation delay of driver between clock (CLK) and LCD driving signals.

[5] Periodically sampled, not 100 % tested.

[6] Outputs measured one at a time.

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11. Dynamic characteristics

Table 16. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= −40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

f_clk(int)

f_clk(ext)

t_clk(H)

t_clk(L)

[1]

internal clock frequency

external clock frequency

HIGH-level clock time

LOW-level clock time

1440

960

60

1850

2640

Hz

μs

-

2640

-

60

Synchronization

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

μs

t_{SYNC_NL}

t_PD(drv)

I²C-bus^[3]

Pin SCL

f_SCL

SYNC LOW time

1

-

[2]

driver propagation delay

V_LCD= 5 V

-

30

SCL clock frequency

-

400

kHz

μs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

μs

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP and

1.3

-

μs

START condition

t_SU;STO

t_HD;STA

t_SU;STA

set-up time for STOP condition

hold time (repeated) START condition

0.6

-

μs

set-up time for a repeated START

condition

t_r

rise time of both SDA and SCL signals f_SCL= 400 kHz

f_SCL< 125 kHz

-

0.3

1.0

0.3

400

50

μs

pF

ns

t_f

fall time of both SDA and SCL signals

capacitive load for each bus line

C_b

t_w(spike)

spike pulse width

on the I²C-bus

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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Universal LCD driver for low multiplex rates

1 / f

CLK

t

clk(L)

clk(H)

0.7 V

0.3 V

DD

CLK

DD

0.7 V

0.3 V

DD

SYNC

DD

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

BP0 to BP3,

and S0 to S39

(V

DD

= 5 V)

0.5 V

t

001aai163

PD(drv)

Fig 20. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

r

t

SU;DAT

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 21. I²C-bus timing waveforms

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Universal LCD driver for low multiplex rates

12. Application information

12.1 Cascaded operation

In large display configurations, up to 16 PCF8576Ds can be differentiated on the same

I²C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the

programmable I²C-bus slave address (SA0).

Table 17. Addressing cascaded PCF8576D

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

PCF8576Ds connected in cascade are synchronized to allow the backplane signals from

only one device in the cascade to be shared. This arrangement is cost-effective in large

LCD applications since the backplane outputs of only one device need to be

through-plated to the backplane electrodes of the display. The other cascaded

PCF8576Ds contribute additional segment outputs but their backplane outputs are left

open-circuit (see Figure 22).

All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.

This synchronization is guaranteed after the power-on reset. The only time that SYNC is

likely to be needed is if synchronization is lost accidentally, for example, by noise in

adverse electrical environments, or if the LCD multiplex drive mode is changed in an

application using several cascaded PCF8576Ds, as the drive mode cannot be changed

on all of the cascaded devices simultaneously. SYNC can be either an input or an output

signal; a SYNC output is implemented as an open-drain driver with an internal pull-up

resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and

monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored

by the first PCF8576D to assert SYNC. The timing relationship between the backplane

waveforms and the SYNC signal for each LCD drive mode is shown in Figure 23.

PCF8576D

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PCF8576D

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Universal LCD driver for low multiplex rates

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 18.

Table 18. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6 kΩ

3 to 5

6 to 10

10 to 16

2.2 kΩ

1.2 kΩ

700 Ω

The PCF8576D can be cascaded with the PCF8562, the PCF8533 or the PCF8534A.

This allows optimal drive selection for a given number of pixels to display. Figure 20 and

Figure 21 show the timing of the synchronization signals.

V

LCD

DD

6

13

SDA

SCL

1, 58, 59

40 segment drives

2, 3

4

LCD PANEL

SYNC

CLK

PCF8576DU

(up to 2560

elements)

5

7

OSC

BP0 to BP3

8

9

10 11 12

(open-circuit)

A0 A1 A2 SA0 V

SS

V

LCD

DD

t

r

R ≤

V

2C

B

DD

LCD

6

13

SDA

HOST

MICRO-

PROCESSOR/

MICRO-

1, 58, 59

40 segment drives

SCL

SYNC

CLK

2, 3

4

PCF8576DU

4 backplanes

BP0 to BP3

CONTROLLER

5

7

OSC

mdb077

8

9

10 11 12

A0 A1 A2 SA0 V

SS

V

SS

Fig 22. Cascaded PCF8576D configuration

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Universal LCD driver for low multiplex rates

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 23. Synchronization of the cascade for the various PCF8576D drive modes

13. Test information

The following quality information corresponds with the following product type:

PCF8576DT/S400/2

13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

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Universal LCD driver for low multiplex rates

14. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 24. Package outline SOT364-1 (TSSOP56)

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Universal LCD driver for low multiplex rates

15. Bare die outline

Wire bond die; 59 bonding pads

PCF8576DU/DA

D

A

(1)

35

22

21

e

36

x

E

0

y

X

9

51

C2 52

59 1

8

C1

P

4

P

3

P

2

1

detail X

0

0.5

1 mm

scale

Notes

1. Marking code: PC8576D-2

pcf8576du_da_do

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

08-12-10

10-12-20

PCF8576DU/DA

Fig 25. Bare die outline PCF8576DU/DA/2 (for dimensions see Table 19)

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PCF8576D

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Universal LCD driver for low multiplex rates

Bare die; 59 bumps

PCF8576DU/2DA

D

(1)

35

22

Y

21

e

36

x

E

0

y

51

9

C2 52

59 1

8

C1

X

L

A

2

A

b

detail X

A

1

detail Y

0

0.5

1 mm

scale

Notes

1. Marking code: PC8576D-2

pcf8576du_2da_do

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

08-12-10

10-12-20

PCF8576DU/2DA

Fig 26. Bare die outline PCF8576DU/2DA/2 (for dimensions see Table 20)

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Universal LCD driver for low multiplex rates

Table 19. Dimensions of PCF8576DU/DA/2

Original dimensions are in mm.

[2]

[3]

[2]

[3]

Unit (mm)

max

A

D

-

E

-

e^[1]

P₁

P₂

P₃

P₄

-

nom

0.38

-

2.2

-

2.0

-

0.09

-

0.08

-

0.066

-

0.056

-

min

0.072

[1] Dimension not drawn to scale.

[2] Pad size.

[3] Passivation opening.

Table 20. Dimensions of PCF8576DU/2DA/2

Original dimensions are in mm.

Unit (mm)

max

A

A₁

A₂

b

D

-

E

-

e^[1]

L

-

nom

0.40

-

0.015

-

0.381

-

0.052

-

2.2

-

2.0

-

0.077

-

min

0.072

[1] Dimension not drawn to scale.

Table 21. Bonding pad location for PCF8576DU/x

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26).

Symbol

SDA

SCL

SYNC

CLK

V_DD

OSC

A0

Pad

1

X (μm)

Y (μm)

−876.6

−630.9

−513.9

−396.9

−221.4

10.71

Description

−34.38

I²C-bus serial data input/output

I²C-bus serial clock input

2

109.53

3

181.53

4

365.58

cascade synchronization input/output

external clock input/output

supply voltage

5

469.08

6

577.08

7

740.88

internal oscillator enable input

subaddress inputs

8

835.83

A1

9

1005.48

A2

10

11

12

13

14

15

16

17

18

19

20

21

SA0

V_SS

V_LCD

BP0

BP2

BP1

BP3

S0

I²C-bus address input; bit 0

ground supply voltage

LCD supply voltage

156.51

232.74

308.97

385.2

LCD backplane outputs

493.2

LCD segment outputs

S1

565.2

S2

637.2

S3

709.2

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Table 21. Bonding pad location for PCF8576DU/x …continued

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26).

Symbol

S4

Pad

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

X (μm)

Y (μm)

876.6

Description

347.22

LCD segment outputs

S5

263.97

876.6

S6

180.72

876.6

S7

97.47

876.6

S8

14.22

876.6

S9

−69.03

876.6

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

−152.28

−235.53

−318.78

−402.03

−485.28

−568.53

−651.78

−735.03

−1005.5

−735.03

−663.03

−591.03

−519.03

−447.03

876.6

625.59

541.62

458.19

374.76

291.33

207.9

124.47

41.04

−42.39

−125.8

−209.3

−292.7

−376.1

−459.5

−543

−625.6

−876.6

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Table 21. Bonding pad location for PCF8576DU/x …continued

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26).

Symbol

S39

Pad

57

X (μm)

Y (μm)

−876.6

Description

−375.03

−196.38

−106.38

LCD segment outputs

I²C-bus serial data input/output

SDA

58

SDA

59

Table 22. Alignment marks

All x/y coordinates represent the position of the center of each alignment mark with respect to the

center (x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26).

Symbol

C1

X (μm)

930.42

−829.98

Y (μm)

−870.3

C2

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

17. Packing information

17.1 Tray information

x

G

A

C

H

y

1,1

1,2

2,1

x,1

D

B

F

x,y

1,y

E

mce404

Fig 27. Tray details

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Universal LCD driver for low multiplex rates

Table 23. Tray dimensions (see Figure 27)

Symbol

Description

Value

5.59

6.35

3.16

50.8

5.83

6.35

8

Unit

mm

-

A

B

C

D

E

F

G

H

x

pocket pitch in x direction

pocket pitch in y direction

pocket width in x direction

pocket width in y direction

tray width in x direction

tray width in y direction

cut corner to pocket 1.1 center

number of pockets, x direction

number of pockets, y direction

y

7

-

PC8576D

mdb080

Fig 28. Tray alignment

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Universal LCD driver for low multiplex rates

17.2 Carrier tape information

4

A0

K0

pin 1 index

W

B0

P1

direction of feed

001aaj314

Fig 29. Tape details

Table 24. Carrier tape dimensions

Symbol

A0

Description

Value

8.6

Unit

pocket width in x direction

pocket width in y direction

pocket height

mm

B0

14.5

1.8

K0

P1

sprocket hole pitch

tape width in y direction

12

W

24

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

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Universal LCD driver for low multiplex rates

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 25 and 26

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Universal LCD driver for low multiplex rates

Table 25. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 26. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 30.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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Universal LCD driver for low multiplex rates

19. Abbreviations

Table 27. Abbreviations

Acronym

CDM

CMOS

HBM

ITO

Description

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Human Body Model

Indium Tin Oxide

LCD

Liquid Crystal Display

Least Significant Bit

Machine Model

LSB

MM

MSB

MSL

PCB

RAM

RMS

SCL

Most Significant Bit

Moisture Sensitivity Level

Printed Circuit Board

Random Access Memory

Root Mean Square

Serial CLock line

SDA

SMD

Serial DAta line

Surface Mount Device

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Universal LCD driver for low multiplex rates

20. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10365 — Surface mount reflow soldering description

[3] AN10706 — Handling bare die

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[10] JESD78 — IC Latch-Up Test

[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[12] NX3-00092 — NXP store and transport requirements

[13] UM10204 — I²C-bus specification and user manual

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PCF8576D

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Universal LCD driver for low multiplex rates

21. Revision history

Table 28. Revision history

Document ID

PCF8576D v.10

Modifications:

Release date

20110214

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8576D_9

• Adjusted die size

• Removed product type PCF8576DH/2

• Adjusted values of I_DDand I_DD(LCD)in Table 15

• Deleted power-on remark in Section 7.5.1

PCF8576D_9

PCF8576D_8

PCF8576D_7

PCF8576D_6

PCF8576D_5

PCF8576D_4

PCF8576D_3

PCF8576D_2

PCF8576D_1

20090825

20090319

20081218

20081202

20041222

20041008

20040617

20030623

20030401

Product data sheet

Product specification

Objective specification

-

PCF8576D_8

PCF8576D_7

PCF8576D_6

PCF8576D_5

PCF8576D_4

PCF8576D_3

PCF8576D_2

PCF8576D_1

-

PCF8576D

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Universal LCD driver for low multiplex rates

22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

22.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

PCF8576D

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 14 February 2011

48 of 50

PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCF8576D

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 14 February 2011

49 of 50

PCF8576D

NXP Semiconductors

Universal LCD driver for low multiplex rates

24. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

12.1

13

13.1

14

Cascaded operation. . . . . . . . . . . . . . . . . . . . 32

Test information . . . . . . . . . . . . . . . . . . . . . . . 34

Quality information. . . . . . . . . . . . . . . . . . . . . 34

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 36

Handling information . . . . . . . . . . . . . . . . . . . 40

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15

16

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

17

17.1

17.2

Packing information . . . . . . . . . . . . . . . . . . . . 40

Tray information . . . . . . . . . . . . . . . . . . . . . . . 40

Carrier tape information . . . . . . . . . . . . . . . . . 42

7

Functional description . . . . . . . . . . . . . . . . . . . 7

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8

Electro-optical performance . . . . . . . . . . . . . . . 9

LCD drive mode waveforms . . . . . . . . . . . . . . 11

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 12

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 14

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 15

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Display register. . . . . . . . . . . . . . . . . . . . . . . . 16

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Subaddress counter . . . . . . . . . . . . . . . . . . . . 19

Output bank selector . . . . . . . . . . . . . . . . . . . 20

Input bank selector . . . . . . . . . . . . . . . . . . . . . 20

Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Characteristics of the I²C-bus. . . . . . . . . . . . . 21

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

START and STOP conditions . . . . . . . . . . . . . 22

System configuration . . . . . . . . . . . . . . . . . . . 22

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 23

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23

Command decoder. . . . . . . . . . . . . . . . . . . . . 25

Display controller . . . . . . . . . . . . . . . . . . . . . . 27

7.1

7.2

7.3

7.3.1

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

18

Soldering of SMD packages. . . . . . . . . . . . . . 42

Introduction to soldering. . . . . . . . . . . . . . . . . 42

Wave and reflow soldering. . . . . . . . . . . . . . . 42

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43

18.1

18.2

18.3

18.4

19

20

21

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision history . . . . . . . . . . . . . . . . . . . . . . . 47

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 48

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 49

22.1

22.2

22.3

22.4

7.7

7.8

7.9

23

24

Contact information . . . . . . . . . . . . . . . . . . . . 49

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.16.1

7.16.2

7.16.3

7.16.4

7.16.5

7.16.6

7.16.7

7.17

7.18

8

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28

Static characteristics. . . . . . . . . . . . . . . . . . . . 29

Dynamic characteristics . . . . . . . . . . . . . . . . . 30

Application information. . . . . . . . . . . . . . . . . . 32

9

10

11

12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 February 2011

Document identifier: PCF8576D


型号：	PCF8576D_11
厂家：	NXP
描述：	Universal LCD driver for low multiplex rates 低复用率的通用LCD驱动器驱动器 CD
文件：	总50页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF8576D_11 [NXP]

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