PCIMX6D5CZK08CC_技术文档

Document Number: IMX6DQCPOPEC

Rev. 2, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MCIMX6Q5ExxxxD

MCIMX6Q7CxxxxD

MCIMX6Q5ExxxxE

MCIMX6Q7CxxxxE

MCIMX6D5ExxxxD

MCIMX6D7CxxxxD

MCIMX6D5ExxxxE

MCIMX6D7CxxxxE

i.MX 6Dual/6Quad

Applications Processors

Consumer - PoP

Package Information

Plastic Package

12 x 12 mm, 0.4 mm pitch

Ordering Information

See Table 1

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 17

3.2 Recommended Connections for Unused Analog

Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Power Supplies Requirements and Restrictions . . 31

4.3 Integrated LDO Voltage Regulator Parameters . . 32

4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34

4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35

4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41

4.8 Output Buffer Impedance Parameters. . . . . . . . . . 45

4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48

4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 60

4.11 General-Purpose Media Interface (GPMI) Timing. 60

4.12 External Peripheral Interface Parameters . . . . . . . 69

Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 130

5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 130

5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 131

Package Information and Contact Assignments. . . . . . 133

6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 133

6.2 21 x 21 mm Package Information . . . . . . . . . . . . 133

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

1 Introduction

The i.MX 6Dual/6Quad processors are part of a growing

family of multimedia-focused products that offer high

performance processing and are optimized for lowest

power consumption.

2

3

The i.MX 6Dual/6Quad processors feature advanced

4

®

implementation of the quad Arm Cortex -A9 core,

which operates at speeds up to 800 MHz. They include

2D and 3D graphics processors, 1080p video processing,

and integrated power management. Each processor

provides a 2 × 32-bit LPDDR2-800 memory interface

and a number of other interfaces for connecting

®

peripherals, such as WLAN, Bluetooth , GPS, hard

drive, displays, and camera sensors.

The i.MX 6Dual/6Quad processors are specifically

useful for applications such as the following:

5

6

7

•

High-end mobile Internet devices (MID)

High-end PDAs

High-end portable media players (PMP) with HD

video capability

NXP Reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Introduction

•

Gaming consoles

Portable navigation devices (PND)

The i.MX 6Dual/6Quad processors offers numerous advanced features, such as:

•

Applications processors—The processors enhance the capabilities of high-tier portable

applications by fulfilling the ever increasing MIPS needs of operating systems and games. The

Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing

the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio

decode.

Multilevel memory system—The multilevel memory system of each processor is based on the L1

instruction and data caches, L2 cache, and internal and external memory. The processors support

many types of external memory devices, including LPDDR2, NOR Flash, PSRAM, cellular RAM,

NAND Flash (MLC and SLC), OneNAND™, and managed NAND, including eMMC up to rev

4.4/4.41.

Smart speed technology—The processors have power management throughout the device that

enables the rich suite of multimedia features and peripherals to consume minimum power in both

active and various low power modes. Smart speed technology enables the designer to deliver a

feature-rich product, requiring levels of power far lower than industry expectations.

•

Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices

by scaling the voltage and frequency to optimize performance.

Multimedia powerhouse—The multimedia performance of each processor is enhanced by a

®

multilevel cache system, Neon MPE (Media Processor Engine) co-processor, a multi-standard

hardware video codec, 2 autonomous and independent image processing units (IPU), and a

programmable smart DMA (SDMA) controller.

•

Powerful graphics acceleration—Each processor provides three independent, integrated graphics

processing units: an OpenGL ES .0 3D graphics accelerator with four shaders (up to MTri/s and

OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.

®

Interface flexibility—Each processor supports connections to a variety of interfaces: LCD

controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS

display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with

PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host

and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces

2

(such as UART, I C, and I S serial audio, SATA-II, and PCIe-II).

•

Advanced security—The processors deliver hardware-enabled security features that enable secure

e-commerce, digital rights management (DRM), information encryption, secure boot, and secure

software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad

security reference manual (IMX6DQ6SDLSRM).

Integrated power management—The processors integrate linear regulators and internally generate

voltage levels for different domains. This significantly simplifies system power management

structure.

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

2

NXP Semiconductors

Introduction

1.1

Ordering Information

Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include

all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your

desired part number is not listed in the table, or you have questions about available parts, see

nxp.com/imx6series or contact your NXP representative.

Table 1. Orderable Part Numbers

Quad/Dual

CPU

Speed Temperature

Part Number

Options

Package

Grade

MCIMX6Q5EZK08AD

i.MX 6Quad

i.MX 6Dual

MLB not

supported

800

MHz

Extended

Commercial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MCIMX6Q5EZK08AE

MCIMX6Q7CZK08AD

MCIMX6Q7CZK08AE

MCIMX6D5EZK08AD

MCIMX6D5EZK08AE

MCIMX6D7CZK08AD

MCIMX6D7CZK08AE

MLB not

supported

800

MHz

Extended

Commercial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

Industrial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

Extended

Commercial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

Extended

Commercial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

Industrial

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

MLB not

supported

800

MHz

12 mm x 12 mm, 0.4 mm pitch,

FCPBGA,

Package on Package (PoP)

Figure 1 describes the part number nomenclature to identify the characteristics of the specific part number

you have (for example, cores, frequency, temperature grade, fuse options, silicon revision). Figure 1

applies to the i.MX 6Dual/6Quad.

The two characteristics that identify which data sheet a specific part applies to are the part number series

field and the temperature grade (junction) field:

•

The i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors data sheet

(IMX6DQAEC) covers parts listed with “A (Automotive temp)”

•

The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet (IMX6DQCEC)

covers parts listed with “D (Commercial temp)” or “E (Extended Commercial temp)”

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

3

Introduction

•

The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet

(IMX6DQCPOPEC) covers parts listed with “D (Commercial temp)” or “E (Extended Commercial

temp)” and that uses the Package-on-Package.

The i.MX 6Dual/6Quad Applications Processors for Industrial Products data sheet (IMX6DQIEC)

covers parts listed with “C (Industrial temp)”

Ensure that you have the right data sheet for your specific part by checking the temperature grade

(junction) field and matching it to the right data sheet. If you have questions, see nxp.com/imx6series or

contact your NXP representative.

MC

IMX6 X @

+

VV

$$ % A

Qualification level

MC

Silicon revision¹

Rev 1.2

A

C

D

E

Prototype Samples

Mass Production

Special

PC

MC

SC

Rev 1.3

Rev 1.6

Fusing

%

A

Part # series

i.MX 6Quad

i.MX 6Dual

X

Q

D

Default Setting

HDCP Enabled

C

Frequency

$$

08

Part differentiator

@

800 MHz²

Package

ZK

VPU

GPU

Y

MLB

N

Industrial

Y

7

5

RoHS

Package type

Extended

Commercial

Y

N

FCPBGA PoP 12x12 0.4mm

ZK

Temperature Tj

+

Extended commercial: -20 to + 105^°C

Industrial: -40 to +105^°C

E

C

1. See the nxp.com\imx6series Web page for latestinformation on the available silicon revision.

2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.

Figure 1. Part Number Nomenclature—i.MX 6Dual PoP and 6Quad PoP

1.2

Features

The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the

following features:

®

•

Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone )

The core configuration is symmetric, where each core includes:

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

4

NXP Semiconductors

Introduction

The Arm Cortex-A9 MPCore complex includes:

•

General Interrupt Controller (GIC) with 128 interrupt support

Global Timer

Snoop Control Unit (SCU)

1 MB unified I/D L2 cache, shared by two/four cores

Two Master AXI (64-bit) bus interfaces output of L2 cache

Frequency of the core (including Neon and L1 cache) as per Table 6.

NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

•

Boot ROM, including HAB (96 KB)

Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)

Secure/non-secure RAM (16 KB)

External memory interfaces:

— 2 × 32-bit, LPDDR2-800 channels supporting DDR interleaving mode

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.

— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.

— 16/32-bit PSRAM, Cellular RAM

Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are

muxed and not available simultaneously):

•

Hard Disk Drives—SATA II, 3.0 Gbps

Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450

Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.

— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual

HD1080 and WXGA at 60 Hz)

— LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two

ports up to 85 MP/sec each

— HDMI 1.4 port

— MIPI/DSI, two lanes at 1 Gbps

Camera sensors:

•

— Parallel Camera port (up to 20 bit and up to 240 MHz peak)

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

5

Introduction

— MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to

800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to

four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.

•

Expansion cards:

— Four MMC/SD/SDIO card ports all supporting:

– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104

mode (104 MB/s max)

– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR

and DDR modes (104 MB/s max)

USB^:

— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY

— Three USB 2.0 (480 Mbps) hosts:

– One HS host with integrated High Speed PHY

– Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY

Expansion PCI Express port (PCIe) v2.0 one lane

•

— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint

operations. Uses x1 PHY configuration.

Miscellaneous IPs and interfaces:

— SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and

2

outputs with I S mode

— ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with

7.1 multi channel outputs

— Five UARTs, up to 5.0 Mbps each:

– Providing RS232 interface

– Supporting 9-bit RS485 multidrop mode

– One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This

is due to the SoC IOMUX limitation, because all UART IPs are identical.

— Five eCSPI (Enhanced CSPI)

— Three I2C, supporting 400 kbps

1

— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/1000 Mbps

— Four Pulse Width Modulators (PWM)

— System JTAG Controller (SJC)

— GPIO with interrupt capabilities

— 8x8 Key Pad Port (KPP)

— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx

— Two Controller Area Network (FlexCAN), 1 Mbps each

— Two Watchdog timers (WDOG)

1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus

throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the

ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

6

NXP Semiconductors

Introduction

— Audio MUX (AUDMUX)

The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:

•

Provide PMU, including LDO supplies, for on-chip resources

Use Temperature Sensor for monitoring the die temperature

Support DVFS techniques for low power modes

Use Software State Retention and Power Gating for Arm and MPE

Support various levels of system power modes

Use flexible clock gating control scheme

The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia

performance. The use of hardware accelerators is a key factor in obtaining high performance at low power

consumption numbers, while having the CPU core relatively free for performing other tasks.

The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:

•

VPU—Video Processing Unit

IPUv3H—Image Processing Unit version 3H (2 IPUs)

GPU3Dv4—3D Graphics Processing Unit (OpenGL ES .0)

GPU2Dv2—2D Graphics Processing Unit (BitBlt)

GPUVG—OpenVG 1.1 Graphics Processing Unit

ASRC—Asynchronous Sample Rate Converter

Security functions are enabled and accelerated by the following hardware:

•

Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)

SJC—SystemJTAGController. ProtectingJTAGfromdebugportattacks by regulating or blocking

the access to the system debug features.

•

CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and

True and Pseudo Random Number Generator (NIST certified)

•

SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock

CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be

configured during boot and by eFUSEs and will determine the security level operation mode as

well as the TZ policy.

•

A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.

1.3

Signal Naming Convention

Throughout this document, the updated signal names are used except where referenced as a ball name

(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal

name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be

used to map the signal names used in older documentation to the new standardized naming conventions.

The signal names of the i.MX6 series of products are standardized to align the signal names within the

family and across the documentation. Benefits of this standardization are as follows:

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

7

Introduction

•

Signal names are unique within the scope of an SoC and within the series of products

Searches will return all occurrences of the named signal

Signal names are consistent between i.MX 6 series products implementing the same modules

The module instance is incorporated into the signal name

This standardization applies only to signal names. The ball names are preserved to prevent the need to

change schematics, BSDL models, IBIS models, and so on.

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

8

NXP Semiconductors

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system.

2.1

Block Diagram

Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system.

MIPI

Raw/ONFI 2.2

LPDDR2

NOR Flash Battery Ctrl 4x Camera 1 / 2 LVDS 1 / 2 LCD HDMI 1.4

Display

Nand-Flash 400MHz (DDR800)

PSRAM

Device

Parallel/MIPI (WUXGA+) Displays

Display

Application Processor

Domain (AP)

CSI2/MIPI LDB

HDMI

DSI/MIPI

External

Memory

Interface

Digital

GPMI

Audio

MMDC

Internal

RAM

(272KB)

Clock and Reset

PLL (8)

Crystals

& Clock sources

Image Processing

EIM

Subsystem

2x IPUv3H

CCM

Boot

ROM

GPC

SRC

(96KB)

SATA II

3.0Gbps

ARM Cortex A9

MPCore Platform

Smart DMA

(SDMA)

XTALOSC

OSC32K

Debug

DAP

4x

A9-Core

L1 I/D Cache

Timer, Wdog

TPIU

CTIs

SJC

SPBA

MMC/SD

eMMC/eSD

2xCAN

Interface

AP Peripherals

1MB L2 cache

SCU, Timer

PTM’s CTI’s

uSDHC (4)

MMC/SD

SDXC

Shared Peripherals

AUDMUX

2

Security

I C(3)

Video

eCSPI (5)

ESAI

SSI (3)

CAAM

(16KB Ram)

Proc. Unit

PWM (4)

OCOTP

IOMUXC

KPP

5xFast-UART

SPDIF Rx/Tx

Modem IC

PCIe Bus

GPS

(VPU + Cache)

SNVS

(SRTC)

ASRC

3D Graphics

Proc. Unit

(GPU3D)

CSU

Fuse Box

2D Graphics

Proc. Unit

(GPU2D)

Keypad

GPIO

CAN(2)

Consumer-POP

Standard

Block Diagram

Timers/Control

WDOG (2)

GPT

OpenVG 1.1

Proc. Unit

(GPUVG)

1-Gbps ENET

HSI/MIPI

Ethernet

10/100/1000

Mbps

EPIT (2)

Audio,

Power

Mngmnt

USB OTG +

3 HS Ports

Temp Monitor

.

OTG PHY1

Host PHY2

2xHSIC

PHY

USB OTG

(dev/host)

JTAG

(IEEE1149.6)

Bluetooth

WLAN

Figure 2. i.MX 6Dual/6QuadConsumer Grade System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (4) indicates four separate PWM peripherals.

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

9

Modules List

3 Modules List

The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these

modules in alphabetical order.

Table 2. i.MX 6Dual/6Quad Modules List

Block

Mnemonic

Block Name

Subsystem

Brief Description

512 x 8 Fuse Electrical Fuse Array Security

Box

Electrical Fuse Array. Enables to setup Boot Modes, Security Levels,

Security Keys, and many other system parameters.

The i.MX 6Dual/6Quad processors consist of 512x8-bit fuse box

accessible through OCOTP_CTRL interface.

APBH-DMA NAND Flash and

BCH ECC DMA

System

Control

DMA controller used for GPMI2 operation.

Controller

Peripherals

Arm

Arm Platform

Arm

The Arm Cortex-A9 platform consists of 4x (four) Cortex-A9 cores version

r2p10 and associated sub-blocks, including Level 2 Cache Controller,

SCU (Snoop Control Unit), GIC (General Interrupt Controller), private

timers, Watchdog, and CoreSight debug modules.

ASRC

Asynchronous

Sample Rate

Converter

Multimedia

Peripherals

The Asynchronous Sample Rate Converter (ASRC) converts the

sampling rate of a signal associated to an input clock into a signal

associated to a different output clock. The ASRC supports concurrent

sample rate conversion of up to 10 channels of about -120dB THD+N. The

sample rate conversion of each channel is associated to a pair of

incoming and outgoing sampling rates. The ASRC supports up to three

sampling rate pairs.

AUDMUX

Digital Audio Mux

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (for example,

SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice

codecs). The AUDMUX has seven ports with identical functionality and

programming models. A desired connectivity is achieved by configuring

two or more AUDMUX ports.

BCH40

CAAM

Binary-BCH ECC

Processor

System

Control

Peripherals

The BCH40 module provides up to 40-bit ECC error correction for NAND

Flash controller (GPMI).

Cryptographic

Accelerator and

Assurance Module

Security

CAAM is a cryptographic accelerator and assurance module. CAAM

implements several encryption and hashing functions, a run-time integrity

checker, and a Pseudo Random Number Generator (PRNG). The pseudo

random number generator is certified by Cryptographic Algorithm

Validation Program (CAVP) of National Institute of Standards and

Technology (NIST). Its DRBG validation number is 94 and its SHS

validation number is 1455.

CAAM also implements a Secure Memory mechanism. In i.MX

6Dual/6Quad processors, the security memory provided is 16 KB.

CCM

GPC

SRC

Clock Control

Module, General

Power Controller,

System Reset

Controller

Clocks,

These modules are responsible for clock and reset distribution in the

Resets, and system, and also for the system power management.

Power Control

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

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NXP Semiconductors

Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

The CSI IP provides MIPI CSI-2 standard camera interface port. The

CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800

Mbps for 4 data lanes.

CSI

MIPI CSI-2 Interface Multimedia

Peripherals

CSU

Central Security Unit Security

The Central Security Unit (CSU) is responsible for setting comprehensive

security policy within the i.MX 6Dual/6Quad platform. The Security

Control Registers (SCR) of the CSU are set during boot time by the HAB

and are locked to prevent further writing.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger

Interfaces

Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from

masters attached to CTIs. The CTI module is internal to the Cortex-A9

Core Platform.

CTM

Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.

The CTM module is internal to the Cortex-A9 Core Platform.

DAP

Debug Access Port System

Control

The DAP provides real-time access for the debugger without halting the

core to:

Peripherals

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains. The DAP

module is internal to the Cortex-A9 Core Platform.

DCIC-0

DCIC-1

Display Content

Integrity Checker

Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX

6Dual/6Quad processor has two such modules, one for each IPU.

DSI

MIPI DSI interface

Multimedia

Peripherals

The MIPI DSI IP provides DSI standard display port interface. The DSI

interface support 80 Mbps to 1 Gbps speed per data lane.

eCSPI1-5

Configurable SPI

Connectivity Full-duplex enhanced Synchronous Serial Interface. It is configurable to

Peripherals

support Master/Slave modes, four chip selects to support multiple

peripherals.

ENET

Ethernet Controller Connectivity The Ethernet Media Access Controller (MAC) is designed to support

Peripherals

10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external

transceiver interface and transceiver function are required to complete the

interface to the media. The i.MX 6Dual/6Quad processors also consist of

hardware assist for IEEE 1588 standard. For details, see the ENET

chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

Note: The theoretical maximum performance of 1 Gbps ENET is limited

to 470 Mbps (total for Tx and Rx) due to internal bus throughput

limitations. The actual measured performance in optimized environment

is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX

6Dual/6Quad errata document (IMX6DQCE).

EPIT-1

EPIT-2

Enhanced Periodic Timer

Interrupt Timer Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts counting after the

EPIT is enabled by software. It is capable of providing precise interrupts

at regular intervals with minimal processor intervention. It has a 12-bit

prescaler for division of input clock frequency to get the required time

setting for the interrupts to occur, and counter value can be programmed

on the fly.

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11

Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

ESAI

Enhanced Serial

Audio Interface

Connectivity The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial

Peripherals

port for serial communication with a variety of serial devices, including

industry-standard codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and receiver sections, each

section with its own clock generator. All serial transfers are synchronized

to a clock. Additional synchronization signals are used to delineate the

word frames. The normal mode of operation is used to transfer data at a

periodic rate, one word per period. The network mode is also intended for

periodic transfers; however, it supports up to 32 words (time slots) per

period. This mode can be used to build time division multiplexed (TDM)

networks. In contrast, the on-demand mode is intended for non-periodic

transfers of data and to transfer data serially at high speed when the data

becomes available.

The ESAI has 12 pins for data and clocking connection to external

devices.

FlexCAN-1 Flexible Controller

FlexCAN-2 Area Network

Connectivity The CAN protocol was primarily, but not only, designed to be used as a

Peripherals

vehicle serial data bus, meeting the specific requirements of this field:

real-time processing, reliable operation in the Electromagnetic

interference (EMI) environment of a vehicle, cost-effectiveness and

required bandwidth. The FlexCAN module is a full implementation of the

CAN protocol specification, Version 2.0 B, which supports both standard

and extended message frames.

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

GPIO-7

General Purpose I/O System

Used for general purpose input/output to external devices. Each GPIO

module supports 32 bits of I/O.

Modules

Control

Peripherals

GPMI

General Purpose

Media Interface

Connectivity The GPMI module supports up to 8x NAND devices. 40-bit ECC error

Peripherals

correction for NAND Flash controller (GPMI2). The GPMI supports

separate DMA channels per NAND device.

GPT

General Purpose

Timer

Peripherals

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with

programmable prescaler and compare and capture register. A timer

counter value can be captured using an external event and can be

configured to trigger a capture event on either the leading or trailing edges

of an input pulse. When the timer is configured to operate in “set and

forget” mode, it is capable of providing precise interrupts at regular

intervals with minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at comparison. This

timer can be configured to run either on an external clock or on an internal

clock.

GPU2Dv2

GPU3Dv4

Graphics Processing Multimedia

Unit-2D, ver. 2 Peripherals

The GPU2Dv2 provides hardware acceleration for 2D graphics

algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.

Graphics Processing Multimedia

Unit-3D, ver. 4 Peripherals

The GPU2Dv4 provides hardware acceleration for 3D graphics algorithms

with sufficient processor power to run desktop quality interactive graphics

applications on displays up to HD1080 resolution. The GPU3D provides

OpenGL ES 2.0, including extensions, OpenGL ES 1.1, and OpenVG 1.1

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

GPUVGv2

Vector Graphics

Processing Unit,

ver. 2

Multimedia

Peripherals

OpenVG graphics accelerator provides OpenVG 1.1 support as well as

other accelerations, including Real-time hardware curve tesselation of

lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and

various Vector Drawing functions.

HDMI Tx

HSI

HDMI Tx interface

MIPI HSI interface

I²C Interface

Multimedia

Peripherals

The HDMI module provides HDMI standard interface port to an HDMI 1.4

compliant display.

Connectivity The MIPI HSI provides a standard MIPI interface to the applications

Peripherals processor.

I²C-1

I²C-2

I²C-3

Connectivity I²C provide serial interface for external devices. Data rates of up to 400

Peripherals

kbps are supported.

IOMUXC

IOMUX Control

System

Control

Peripherals

This module enables flexible IO multiplexing. Each IO pad has default and

several alternate functions. The alternate functions are software

configurable.

IPUv3H-1

IPUv3H-2

Image Processing

Unit, ver. 3H

Multimedia

Peripherals

IPUv3H enables connectivity to displays and video sources, relevant

processing and synchronization and control capabilities, allowing

autonomous operation.

The IPUv3H supports concurrent output to two display ports and

concurrent input from two camera ports, through the following interfaces:

• Parallel Interfaces for both display and camera

• Single/dual channel LVDS display interface

• HDMI transmitter

• MIPI/DSI transmitter

• MIPI/CSI-2 receiver

The processing includes:

• Image conversions: resizing, rotation, inversion, and color space

conversion

• A high-quality de-interlacing filter

• Video/graphics combining

• Image enhancement: color adjustment and gamut mapping, gamma

correction, and contrast enhancement

• Support for display backlight reduction

KPP

LDB

Key Pad Port

Connectivity KPP Supports 8 x 8 external key pad matrix. KPP features are:

Peripherals

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LVDS Display Bridge Connectivity LVDS Display Bridge is used to connect the IPU (Image Processing Unit)

Peripherals

to External LVDS Display Interface. LDB supports two channels; each

channel has following signals:

• One clock pair

• Four data pairs

Each signal pair contains LVDS special differential pad (PadP, PadM).

MMDC

Multi-Mode DDR

Controller

Connectivity DDR Controller has the following features:

Peripherals

• Supports dual x32 for LPDDR2-800

• Supports up to 4 GByte DDR memory space

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

OCOTP_CTRL OTP Controller

Security

The On-Chip OTP controller (OCOTP_CTRL) provides an interface for

reading, programming, and/or overriding identification and control

information stored in on-chip fuse elements. The module supports

electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also

provides a set of volatile software-accessible signals that can be used for

software control of hardware elements, not requiring non-volatility. The

OCOTP_CTRL provides the primary user-visible mechanism for

interfacing with on-chip fuse elements. Among the uses for the fuses are

unique chip identifiers, mask revision numbers, cryptographic keys, JTAG

secure mode, boot characteristics, and various control signals, requiring

permanent non-volatility.

OCRAM

On-Chip Memory

Controller

Data Path

Clocking

The On-Chip Memory controller (OCRAM) module is designed as an

interface between system’s AXI bus and internal (on-chip) SRAM memory

module.

In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the

256 KB multimedia RAM through a 64-bit AXI bus.

OSC 32 kHz OSC 32 kHz

Generates 32.768 kHz clock from an external crystal.

PCIe

PCI Express 2.0

Connectivity The PCIe IP provides PCI Express Gen 2.0 functionality.

Peripherals

PMU

Power-Management Data Path

Functions

Integrated power management unit. Used to provide power to various

SoC domains.

PWM-1

PWM-2

PWM-3

PWM-4

Pulse Width

Modulation

Connectivity The pulse-width modulator (PWM) has a 16-bit counter and is optimized

Peripherals

to generate sound from stored sample audio images and it can also

generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate

sound.

RAM

Secure/non-secure Secured

Secure/non-secure Internal RAM, interfaced through the CAAM.

16 KB

RAM

Internal

Memory

RAM

256 KB

Internal RAM

Boot ROM

Internal

Memory

Internal RAM, which is accessed through OCRAM memory controllers.

ROM

96 KB

Internal

Memory

Supports secure and regular Boot Modes. Includes read protection on 4K

region for content protection

ROMCP

ROM Controller with Data Path

Patch

ROM Controller with ROM Patch support

SATA

Serial ATA

Connectivity The SATA controller and PHY is a complete mixed-signal IP solution

Peripherals designed to implement SATA II, 3.0 Gbps HDD connectivity.

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block Name Subsystem Brief Description

Smart Direct Memory System

Block

Mnemonic

SDMA

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by off-loading the various cores in dynamic data

routing. It has the following features:

Access

Control

Peripherals

• Powered by a 16-bit Instruction-Set micro-RISC engine

• Multi-channel DMA supporting up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between Arm and SDMA

• Very fast context-switching with 2-level priority based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment,

decrement, and no address changes on source and destination

address)

• DMA ports can handle unit-directional and bi-directional flows (copy

mode)

• Up to 8-word buffer for configurable burst transfers

• Support of byte-swapping and CRC calculations

• Library of Scripts and API is available

SJC

System JTAG

Controller

System

Control

Peripherals

The SJC provides JTAG interface, which complies with JTAG TAP

standards, to internal logic. The i.MX 6Dual/6Quad processors use JTAG

port for production, testing, and system debugging. In addition, the SJC

provides BSR (Boundary Scan Register) standard support, which

complies with IEEE1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform initial laboratory

bring-up, for manufacturing tests and troubleshooting, as well as for

software debugging by authorized entities. The i.MX 6Dual/6Quad SJC

incorporates three security modes for protecting against unauthorized

accesses. Modes are selected through eFUSE configuration.

SNVS

SPDIF

Secure Non-Volatile Security

Storage

Secure Non-Volatile Storage, including Secure Real Time Clock, Security

State Machine, Master Key Control, and Violation/Tamper Detection and

reporting.

Sony Philips Digital Multimedia

Interconnect Format Peripherals

A standard audio file transfer format, developed jointly by the Sony and

Phillips corporations. It supports Transmitter and Receiver functionality.

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity The SSI is a full-duplex synchronous interface, which is used on the

Peripherals

processor to provide connectivity with off-chip audio peripherals. The SSI

supports a wide variety of protocols (SSI normal, SSI network, I2S, and

AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.

The SSI has two pairs of 8x24 FIFOs and hardware support for an

external DMA controller to minimize its impact on system performance.

The second pair of FIFOs provides hardware interleaving of a second

audio stream that reduces CPU overhead in use cases where two time

slots are being used simultaneously.

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block Name Subsystem Brief Description

Block

Mnemonic

TEMPMON Temperature Monitor System

Control

The temperature monitor/sensor IP module for detecting high temperature

conditions. The temperature read out does not reflect case or ambient

temperature. It reflects the temperature in proximity of the sensor location

on the die. Temperature distribution may not be uniformly distributed;

therefore, the read out value may not be the reflection of the temperature

value for the entire die.

Peripherals

TZASC

Trust-Zone Address Security

Space Controller

The TZASC (TZC-380 by Arm) provides security address region control

functions required for intended application. It is used on the path to the

DRAM controller.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface

Connectivity Each of the UARTv2 modules support the following serial data

Peripherals

transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd

or none)

• Programmable baud rates up to 5 MHz

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USBOH3A USB 2.0 High Speed Connectivity USBOH3 contains:

OTG and 3x HS

Hosts

Peripherals

• One high-speed OTG module with integrated HS USB PHY

• One high-speed Host module with integrated HS USB PHY

• Two identical high-speed Host modules connected to HSIC USB ports.

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

uSDHC-1

uSDHC-2

uSDHC-4

SD/MMC and SDXC Connectivity i.MX 6Dual/6Quad specific SoC characteristics:

Enhanced

Peripherals

All four MMC/SD/SDIO controller IPs are identical and are based on the

uSDHC IP. They are:

Multi-Media Card /

Secure Digital Host

Controller

• Conforms to the SD Host Controller Standard Specification version 3.0

• Fully compliant with MMC command/response sets and Physical Layer

as defined in the Multimedia Card System Specification,

v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.

Hardware reset as specified for eMMC cards is supported at ports #3

and #4 only.

• Fully compliant with SD command/response sets and Physical Layer

as defined in the SD Memory Card Specifications, v3.0 including

high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.

• Fully compliant with SDIO command/response sets and

interrupt/read-wait mode as defined in the SDIO Card Specification,

Part E1, v1.10

• Fully compliant with SD Card Specification, Part A2, SD Host

Controller Standard Specification, v2.00

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to

UHS-I SDR104 mode (104 MB/s max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52

MHz in both SDR and DDR modes (104 MB/s max)

However, the SoC-level integration and I/O muxing logic restrict the

functionality to the following:

• Instances #1 and #2 are primarily intended to serve as external slots or

interfaces to on-board SDIO devices. These ports are equipped with

“Card Detection” and “Write Protection” pads and do not support

hardware reset.

• Instances #3 and #4 are primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board SDIO devices.

These ports do not have “Card detection” and “Write Protection” pads

and do support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There are two completely

independent I/O power domains for Ports #1 and #2 in four bit

configuration (SD interface). Port #3 is placed in his own independent

power domain and port #4 shares power domain with some other

interfaces.

VDOA

VPU

VDOA

Multimedia

Peripherals

The Video Data Order Adapter (VDOA) is used to re-order video data from

the “tiled” order used by the VPU to the conventional raster-scan order

needed by the IPU.

Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which covers many

SD-level and HD-level video decoders and SD-level encoders as a

multi-standard video codec engine as well as several important video

processing, such as rotation and mirroring.

See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete

list of VPU’s decoding/encoding capabilities.

WDOG-1

Watchdog

Timer

Peripherals

The Watchdog Timer supports two comparison points during each

counting period. Each of the comparison points is configurable to evoke

an interrupt to the Arm core, and a second point evokes an external event

on the WDOG line.

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Modules List

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

WDOG-2

(TZ)

Watchdog

(TrustZone)

Timer

Peripherals

The TrustZone Watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such a situation is

undesirable as it can compromise the system’s security. Once the TZ

WDOG module is activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer times out. Upon

a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces

switching to the TZ mode. If it is still not served, the TZ WDOG asserts a

security violation signal to the CSU. The TZ WDOG module cannot be

programmed or deactivated by a normal mode Software.

EIM

NOR-Flash /PSRAM Connectivity The EIM NOR-FLASH / PSRAM provides:

interface

Peripherals

• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and

async operating modes), at slow frequency

• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow

frequency

• Multiple chip selects

XTALOSC

Crystal Oscillator

interface

—

The XTALOSC module enables connectivity to external crystal oscillator

device. In a typical application use-case, it is used for 24 MHz oscillator.

3.1

Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

Special signal consideration information is contained in the Hardware Development Guide for i.MX

6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

3.2

Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of

Applications Processors (IMX6DQ6SDLHDG).

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Electrical Characteristics

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad

processors.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick

reference to the individual tables and sections.

Table 3. i.MX 6Dual/6Quad Chip-Level Conditions

For these characteristics, …

Absolute Maximum Ratings

Topic appears …

on page 20

on page 21

on page 22

on page 24

on page 26

on page 27

on page 29

on page 30

on page 31

PoP Package Thermal Resistance

Operating Ranges

External Clock Sources

Maximum Measured Supply Currents

Low Power Mode Supply Currents

USB PHY Current Consumption

SATA Typical Power Consumption

PCIe 2.0 Maximum Power Consumption

HDMI Maximum Power Consumption

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 4 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the Operating Ranges or Parameters tables is not implied.

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Electrical Characteristics

Table 4. Absolute Maximum Ratings

Symbol

Parameter Description

Min

Max

Unit

Core supply input voltage (LDO enabled)

Core supply input voltage (LDO bypass)

Core supply output voltage (LDO enabled)

VDD_ARM_IN

VDD_ARM23_IN

VDD_SOC_IN

-0.3

1.6

V

VDD_ARM_IN

VDD_ARM23_IN

VDD_SOC_IN

-0.3

1.4

V

VDD_ARM_CAP

VDD_SOC_CAP

VDD_PU_CAP

NVCC_PLL_OUT

VDD_HIGH_IN supply voltage

DDR I/O supply voltage

VDD_HIGH_IN

NVCC_DRAM

-0.3

-0.4

3.7

V

1.975 ^{(See note 1)}

GPIO I/O supply voltage

NVCC_CSI

NVCC_EIM

NVCC_ENET

NVCC_GPIO

NVCC_LCD

NVCC_NAND

NVCC_SD

-0.5

3.7

V

NVCC_JTAG

HDMI, PCIe, and SATA PHY high (VPH) supply voltage

HDMI, PCIe, and SATA PHY low (VP) supply voltage

LVDS and MIPI I/O supply voltage (2.5V supply)

HDMI_VPH

PCIE_VPH

SATA_VPH

-0.3

2.85

V

HDMI_VP

PCIE_VP

SATA_VP

-0.3

1.4

V

NVCC_LVDS_2P5

NVCC_MIPI

2.85

PCIe PHY supply voltage

RGMII I/O supply voltage

PCIE_VPTX

NVCC_RGMII

VDD_SNVS_IN

-0.3

-0.5

-0.3

1.4

2.725

3.4

V

SNVS IN supply voltage

(Secure Non-Volatile Storage and Real Time Clock)

USB I/O supply voltage

USB_H1_DN

USB_H1_DP

USB_OTG_DN

USB_OTG_DP

USB_OTG_CHD_B

-0.3

—

3.73

5.35

V

USB VBUS supply voltage

USB_H1_VBUS

USB_OTG_VBUS

V_in/V_outinput/output voltage range (non-DDR pins)

V_in/V_outinput/output voltage range (DDR pins)

ESD immunity (HBM)

V_in/V_out

-0.5

—

OVDD+0.3 ^{(See note 2)}

OVDD+0.4 ^{(See notes1&2)}

V

V_{esd_HBM}

V_{esd_CDM}

T_storage

2000

500

V

ESD immunity (CDM)

—

V

Storage temperature range

-40

150

°C

1

The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the

allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.

2

OVDD is the I/O supply voltage.

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Electrical Characteristics

4.1.2

Thermal Resistance

NOTE

Per JEDEC JESD51-2, the intent of thermal resistance measurements is

solely for a thermal performance comparison of one package to another in a

standardized environment. This methodology is not meant to and will not

predict the performance of a package in an application-specific

environment.

4.1.2.1

4.1.2.2

FCPBGA Package Thermal Resistance

PoP Package Thermal Resistance

Table 5 provides the PoP package thermal resistance data.

Table 5. PoP Package Thermal Resistance Data

Rating

Board Symbol

Value

Unit

Junction to Ambient¹(natural convection)

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

R_θJA

41

26

33

22

13

2

°C/W

Junction to Ambient¹(at 200 ft/min)

R_θJMA

R_θJB

Junction to Board²

Junction to Case³(Top)

—

R_θJCtop

1

Junction-to-Ambient Thermal Resistance was determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

2

3

Junction-to-Board Thermal Resistance was determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package.

Junction-to-Case at the top of the package was determined by using MIL-STD 883 Method 1012.1. The cold plate temperature

is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

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Electrical Characteristics

4.1.3

Operating Ranges

Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors.

Table 6. Operating Ranges

Parameter

Description

Symbol

Min

Typ

Max¹

Unit

Comment²

Run mode: LDO

enabled

VDD_ARM_IN

1.275⁴

—

1.5

V

LDO Output Set Point (VDD_ARM_CAP⁵) of

1.150 V minimum for operation up to 792 MHz.

VDD_ARM23_IN³

1.05⁴

—

1.5

V

LDO Output Set Point (VDD_ARM_CAP) of

0.925 V minimum for operation up to 396 MHz.

VDD_SOC_IN⁶

1.350⁴

264 MHz < VPU ≤ 352 MHz; VDDSOC and

VDDPU LDO outputs (VDD_SOC_CAP and

VDD_PU_CAP) require 1.225 V minimum.

1.275^4,7

—

1.5

V

VPU ≤ 264 MHz; VDDSOC and VDDPU LDO

outputs (VDD_SOC_CAP and VDD_PU_CAP)

require 1.15 V minimum.

Run mode: LDO

bypassed⁸

VDD_ARM_IN

1.150

0.925

1.225

1.15

—

1.3

V

LDO bypassed for operation up to 792 MHz.

LDO bypassed for operation up to 396 MHz.

264 MHz < VPU ≤ 352 MHz.

VDD_ARM23_IN³

VDD_SOC_IN

VPU ≤ 264 MHz.

Standby/DSM Mode

VDD_ARM_IN

0.9

See Table 9, “Stop Mode Current and Power

Consumption,” on page 27.

VDD_ARM23_IN³

VDD_SOC_IN

VDD_HIGH_IN⁹

0.9

2.8

—

1.3

3.3

V

VDD_HIGH internal

Regulator

Must match the range of voltages that the

rechargeable backup battery supports.

Backup battery supply VDD_SNVS_IN⁹

range

2.8

—

3.3

V

Should be supplied from the same supply as

VDD_HIGH_IN, if the system does not require

keeping real time and other data on OFF state.

USB supply voltages USB_OTG_VBUS

USB_H1_VBUS

4.4

—

5.25

1.3

V

—

DDR I/O supply

NVCC_DRAM

NVCC_RGMII

1.14

1.15

1.2

—

LPDDR2

Supply for RGMII I/O

power group¹⁰

2.625

• 1.15 V – 1.30 V in HSIC 1.2 V mode

• 1.43 V – 1.58 V in RGMII 1.5 V mode

• 1.70 V – 1.90 V in RGMII 1.8 V mode

• 2.25 V – 2.625 V in RGMII 2.5 V mode

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Electrical Characteristics

Comment²

Table 6. Operating Ranges (continued)

Parameter

Description

Symbol

Min

Typ

Max¹

Unit

GPIO supplies¹⁰

NVCC_CSI,

NVCC_EIM0,

NVCC_EIM1,

NVCC_EIM2,

NVCC_ENET,

NVCC_GPIO,

NVCC_LCD,

NVCC_NANDF,

NVCC_SD1,

NVCC_SD2,

NVCC_SD3,

NVCC_JTAG

1.65

1.8,

2.8,

3.3

3.6

V

Isolation between the NVCC_EIMx and

NVCC_SDx different supplies allow them to

operate at different voltages within the specified

range.

Example: NVCC_EIM1 can operate at 1.8 V

while NVCC_EIM2 operates at 3.3 V.

NVCC_LVDS_2P5¹¹

NVCC_MIPI

2.25

2.5

2.75

V

—

HDMI supply voltages

PCIe supply voltages

HDMI_VP

HDMI_VPH

PCIE_VP

PCIE_VPH

PCIE_VPTX

SATA_VP

SATA_VPH

T_J

0.99

2.25

1.023

2.325

1.023

0.99

2.25

-20

1.1

2.5

1.1

2.5

1.1

2.5

—

1.3

2.75

1.3

V

—

2.75

1.3

SATA Supply voltages

1.3

2.75

105

Junction temperature

Extended Commercial

°C See i.MX 6Dual/6Quad Product Lifetime Usage

Estimates Application Note, AN4724, for

information on product lifetime (power-on

years) for this processor.

Junction temperature

Industrial

T_J

-40

—

105

°C See i.MX 6Dual/6Quad Product Usage Lifetime

Estimates Application Note, AN4724, for

information on product lifetime (power-on

years) for this processor.

1

Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.

2

3

See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.

For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with

VDD_ARM23_CAP to reduce leakage.

4

5

VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.

VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed

VDD_ARM_CAP by more than 200 mV.

6

7

VDD_SOC_CAP and VDD_PU_CAP must be equal.

In LDO enabled mode, the internal LDO output set points must be configured such that the:

VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.

VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.

The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set

points shown in this table must be maintained.

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Electrical Characteristics

8

In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more

than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages

shown in this table must be maintained.

9

To set VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for i.MX

6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

¹⁰All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or

not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current.

¹¹This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used.

4.1.4

External Clock Sources

Each i.MX 6Dual/6Quad processor has two external input system clocks: a low frequency (RTC_XTALI)

and a high frequency (XTALI).

The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watchdog counters. The clock input can be

connected to either an external oscillator or a crystal using the internal oscillator amplifier. Additionally,

there is an internal ring oscillator, that can be used instead of RTC_XTALI when accuracy is not important.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either an external oscillator or a crystal using the

internal oscillator amplifier.

NOTE

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used instead, careful consideration should be given to

the timing implications on all of the SoC modules dependent on this clock.

Table 7 shows the interface frequency requirements.

Table 7. External Input Clock Frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^2,4

f_ckil

f_xtal

—

32.768³/32.0

24

—

kHz

MHz

1

External oscillator or a crystal with internal oscillator amplifier.

2

The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware

Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

3

4

Recommended nominal frequency 32.768 kHz.

External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 7 are required for use with NXP BSPs to ensure precise time keeping

and USB operation. For RTC_XTALI operation, two clock sources are available:

•

On-chip 40 kHz ring oscillator: This clock source has the following characteristics:

— Approximately 25 μA more Idd than crystal oscillator

— Approximately 50ꢀ tolerance

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NXP Semiconductors

Electrical Characteristics

— No external component required

— Starts up quicker than 32 kHz crystal oscillator

External crystal oscillator with on-chip support circuit

•

— At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit

switches over to the crystal oscillator automatically.

— Higher accuracy than ring oscillator.

— If no external crystal is present, then the ring oscillator is used.

The decision to choose a clock source should be based on real-time clock use and precision timeout.

4.1.5

Maximum Measured Supply Currents

Power consumption is highly dependent on the application. Estimating the maximum supply currents

required for power supply design is difficult because the use case that requires maximum supply current is

not a realistic use case.

To help illustrate the effect of the application on power consumption, data was collected while running

industry standard benchmarks that are designed to be compute and graphic intensive. The results provided

are intended to be used as guidelines for power supply design.

Description of test conditions:

•

The Power Virus data shown in Table 8 represent a use case designed specifically to show the

maximum current consumption possible for the Arm core complex. All cores are running at the

defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls.

Although a valid condition, it would have a very limited, if any, practical use case, and be limited

to an extremely low duty cycle unless the intention was to specifically cause the worst case power

consumption.

•

EEMBC CoreMark: Benchmark designed specifically for the purpose of measuring the

performance of a CPU core. More information available at www.eembc.org/coremark. Note that

this benchmark is designed as a core performance benchmark, not a power benchmark. This use

case is provided as an example of power consumption that would be typical in a

computationally-intensive application rather than the Power Virus.

•

3DMark Mobile 2011: Suite of benchmarks designed for the purpose of measuring graphics and

overall system performance. Note that this benchmark is designed as a graphics performance

benchmark, not a power benchmark. This use case is provided as an example of power

consumption that would be typical in a very graphics-intensive application.

Devices used for the tests were from the high current end of the expected process variation.

The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor

family, supports the power consumption shown in Table 8, however a robust thermal design is required for

the increased system power dissipation.

See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for more

details on typical power consumption under various use case definitions.

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25

Electrical Characteristics

Power Supply

Table 8. Maximum Supply Currents

Conditions

Maximum Current

Power Virus CoreMark

Unit

i.MX 6Quad:

VDD_ARM_IN + VDD_ARM23_IN

• ARM frequency = 792 MHz

• ARM LDOs set to 1.3V

• T_j= 105°C

3270

2090

mA

i.MX 6Dual: VDD_ARM_IN

• ARM frequency = 792 MHz

• ARM LDOs set to 1.3V

• T_j= 105°C

1960

1250

mA

i.MX 6Dual or i.MX 6Quad:

VDD_SOC_IN

• GPU frequency = 600 MHz

• SOC LDO set to 1.3 V

• T_j= 105°C

2370

VDD_HIGH_IN

VDD_SNVS_IN

—

125¹

275²

25³

mA

μA

USB_OTG_VBUS/

mA

USB_H1_VBUS (LDO 3P0)

Primary Interface (IO) Supplies

NVCC_DRAM

NVCC_ENET

NVCC_LCD

NVCC_GPIO

NVCC_CSI

—

(see note⁴)

N=10

N=29

N=24

N=20

N=19

N=14

N=20

N=6

Use maximum IO equation⁵

25.5

NVCC_EIM0

NVCC_EIM1

NVCC_EIM2

NVCC_JTAG

NVCC_RGMII

NVCC_SD1

N=6

NVCC_SD2

N=6

NVCC_SD3

N=11

N=26

—

NVCC_NANDF

NVCC_MIPI

NVCC_LVDS2P5

mA

—

NVCC_LVDS2P5 is connected to

VDD_HIGH_CAP at the board

level. VDD_HIGH_CAP is capable

of handing the current required by

NVCC_LVDS2P5.

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Electrical Characteristics

Table 8. Maximum Supply Currents (continued)

Conditions

Maximum Current

CoreMark

Power Supply

Unit

Power Virus

MISC

DRAM_VREF

—

1

mA

1

2

The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the

VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or

HDMI, PCIe, and SATA VPH supplies).

Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN

current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of

the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that

current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

3

4

This is the maximum current per active USB physical interface.

The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators

are typically available from memory vendors which take into account factors such as signal termination.

See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power

consumption during specific use case scenarios.

5

General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

4.1.6

Low Power Mode Supply Currents

Table 9 shows the current core consumption (not including I/O) of the i.MX 6Dual/6Quad processors in

selected low power modes.

Table 9. Stop Mode Current and Power Consumption

Mode

Test Conditions

Supply

Typical¹

Unit

WAIT

• Arm, SoC, and PU LDOs are set to 1.225 V

• HIGH LDO set to 2.5 V

• Clocks are gated

• DDR is in self refresh

• PLLs are active in bypass (24 MHz)

• Supply voltages remain ON

VDD_ARM_IN (1.4 V)

VDD_SOC_IN (1.4 V)

VDD_HIGH_IN (3.0 V)

Total

6

mA

mW

mA

mW

23

3.7

52

7.5

22

3.7

52

STOP_ON

• Arm LDO set to 0.9 V

• SoC and PU LDOs set to 1.225 V

• HIGH LDO set to 2.5 V

• PLLs disabled

VDD_ARM_IN (1.4 V)

VDD_SOC_IN (1.4 V)

VDD_HIGH_IN (3.0 V)

Total

• DDR is in self refresh

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27

Electrical Characteristics

Table 9. Stop Mode Current and Power Consumption (continued)

Mode

Test Conditions

• Arm LDO set to 0.9 V

• SoC LDO set to 1.225 V

• PU LDO is power gated

• HIGH LDO set to 2.5 V

• PLLs disabled

Supply

Typical¹

Unit

STOP_OFF

VDD_ARM_IN (1.4 V)

VDD_SOC_IN (1.4 V)

VDD_HIGH_IN (3.0 V)

Total

7.5

13.5

3.7

41

mA

mW

mA

mW

• DDR is in self refresh

STANDBY

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5 V

• PLLs are disabled

• Low voltage

• Well Bias ON

VDD_ARM_IN (0.9 V)

VDD_SOC_IN (0.9 V)

VDD_HIGH_IN (3.0 V)

Total

0.1

13

3.7

22

• Crystal oscillator is enabled

Deep Sleep Mode

(DSM)

• Arm and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5 V

• PLLs are disabled

• Low voltage

• Well Bias ON

VDD_ARM_IN (0.9 V)

VDD_SOC_IN (0.9 V)

VDD_HIGH_IN (3.0 V)

Total

0.1

2

mA

mW

0.5

3.4

• Crystal oscillator and bandgap are disabled

SNVS Only

• VDD_SNVS_IN powered

• All other supplies off

• SRTC running

VDD_SNVS_IN (2.8V)

Total

41

μA

115

μW

1

The typical values shown here are for information only and are not guaranteed. These values are average values measured

on a worst-case wafer at 25°C.

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NXP Semiconductors

Electrical Characteristics

4.1.7

USB PHY Current Consumption

Power Down Mode

4.1.7.1

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.

Table 10 shows the USB interface current consumption in power down mode.

Table 10. USB PHY Current Consumption in Power Down Mode

VDD_USB_CAP (3.0 V)

VDD_HIGH_CAP (2.5 V)

NVCC_PLL_OUT (1.1 V)

Current

5.1 μA

1.7 μA

<0.5 μA

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level shifters.

4.1.8

SATA Typical Power Consumption

Table 11 provides SATA PHY currents for certain Tx operating modes.

NOTE

Tx power consumption values are provided for a single transceiver. If

T = single transceiver power and C = Clock module power, the total power

required for N lanes = N x T + C.

Table 11. SATA PHY Current Drain

Mode

Test Conditions

Supply

Typical Current

Unit

P0: Full-power state¹

Single Transceiver

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

11

13

mA

Clock Module

Single Transceiver

Clock Module

6.9

6.2

11

P0: Mobile²

mA

11

6.9

6.2

9.4

2.9

6.9

6.2

P0s: Transmitter idle

Single Transceiver

Clock Module

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Electrical Characteristics

Mode

Table 11. SATA PHY Current Drain (continued)

Test Conditions

Supply

Typical Current

Unit

P1: Transmitter idle, Rx powered

down, LOS disabled

Single Transceiver

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

SATA_VP

SATA_VPH

0.67

0.23

6.9

mA

Clock Module

Single Transceiver

Clock Module

6.2

P2: Powered-down state, only

LOS and POR enabled

0.53

0.11

0.036

0.12

0.13

0.012

0.008

0.004

mA

PDDQ mode³

Single Transceiver

Clock Module

1

Programmed for 1.0 V peak-to-peak Tx level.

2

3

Programmed for 0.9 V peak-to-peak Tx level with no boost or attenuation.

LOW power non-functional.

4.1.9

PCIe 2.0 Maximum Power Consumption

Table 12 provides PCIe PHY currents for certain operating modes.

Table 12. PCIe PHY Current Drain

Mode

Test Conditions

Supply

Max Current

Unit

P0: Normal Operation

5G Operations

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

40

20

21

27

20

30

2.4

18

20

2.4

18

mA

2.5G Operations

5G Operations

2.5G Operations

P0s: Low Recovery Time

Latency, Power Saving State

mA

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Electrical Characteristics

Table 12. PCIe PHY Current Drain (continued)

Mode

Test Conditions

Supply

Max Current

Unit

P1: Longer Recovery Time

Latency, Lower Power State

—

PCIE_VP (1.1 V)

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

PCIE_VP (1.1 V)

12

2.4

mA

12

Power Down

—

1.3

mA

PCIE_VPTX (1.1 V)

PCIE_VPH (2.5 V)

0.18

0.36

4.1.10 HDMI Maximum Power Consumption

Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down

modes.

Table 13. HDMI PHY Current Drain

Mode

Test Conditions

Supply

Max Current

Unit

Active

Bit rate 251.75 Mbps

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

HDMI_VPH

HDMI_VP

14

4.1

14

mA

μA

Bit rate 279.27 Mbps

Bit rate 742.5 Mbps

Bit rate 1.485 Gbps

Bit rate 2.275 Gbps

Bit rate 2.97 Gbps

—

4.2

17

7.5

17

12

16

17

19

22

Power-down

49

1100

μA

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Electrical Characteristics

4.2

Power Supplies Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to ensure the reliable operation of the device. Any deviation from

these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor

4.2.1

Power-Up Sequence

For power-up sequence, the restrictions are as follows:

•

VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected

(shorted) with VDD_HIGH_IN supply.

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

The SRC_POR_B signal controls the processor POR and must be immediately asserted at

power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP

supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no

restrictions.

NOTE

Ensure that there is no back voltage (leakage) from any supply on the board

towards the 3.3 V supply (for example, from the external components that

use both the 1.8 V and 3.3 V supplies).

NOTE

USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply

sequence and can be powered at any time.

4.2.2

Power-Down Sequence

There are no special restrictions for i.MX 6Dual/6Quad SoC.

4.2.3

Power Supplies Usage

•

All I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx) is

OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For

information about I/O power supply of each pin, see the “Power Group” column of Table 85, “12

x 12 mm Functional Contact Assignments”.

•

WhentheSATAinterfaceisnotused, theSATA_VPandSATA_VPHsuppliesshouldbegrounded.

The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N,

SATA_PHY_RX_P, and SATA_PHY_TX_N) can remain unconnected. It is recommended not to

turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive

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NXP Semiconductors

Electrical Characteristics

power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain

powered.

•

When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should

be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N,

PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to

turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive

power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must

remain powered.

4.3

Integrated LDO Voltage Regulator Parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins

named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use

only and should not be used to power any external circuitry. See the i.MX 6Dual/6Quad reference manual

(IMX6DQRM) for details on the power tree scheme recommended operation.

NOTE

The *_CAP signals should not be powered externally. These signals are

intended for internal LDO or LDO bypass operation only.

4.3.1

Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)

There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because

of their construction). The advantages of the regulators are to reduce the input supply variation because of

their input supply ripple rejection and their on die trimming. This translates into more voltage for the die

producing higher operating frequencies. These regulators have three basic modes.

•

Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the

load unaltered. The analog part of the regulator is powered down in this state, removing any loss

other than the IR drop through the power grid and FET.

•

Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.

The analog part of the regulator is powered down here limiting the power consumption.

Analog regulation mode. The regulation FET is controlled such that the output voltage of the

regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV

steps.

Optionally LDO_SOC/VDD_SOC_CAP can be used to power the HDMI, PCIe, and SATA PHY's through

external connections.

For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2

Regulators for Analog Modules

LDO_1P1 / NVCC_PLL_OUT

4.3.2.1

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 6 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

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to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs,

and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the

system to determine when the load capability of the regulator is being exceeded to take the necessary steps.

Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.

Active-pull-down can also be enabled for systems requiring this feature.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2.2

LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 6 for min and max input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V

with the nominal default setting as 2.5 V. The LDO_2P5 supplies the SATA PHY, USB PHY, LVDS PHY,

HDMI PHY, MIPI PHY, E-fuse module and PLLs. A programmable brown-out detector is included in the

regulator that can be used by the system to determine when the load capability of the regulator is being

exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current

requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this

feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for

applications needing to keep the output voltage alive during low-power modes where the main regulator

driver and its associated global bandgap reference module are disabled. The output of the weak-regulator

is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V

input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 Ω.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2.3

LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the

USB_OTG_VBUS and USB_H1_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output

voltage. A programmable brown-out detector is included in the regulator that can be used by the system to

determine when the load capability of the regulator is being exceeded, to take the necessary steps. This

regulator has a built in power-mux that allows the user to select to run the regulator from either VBUS

supply, when both are present. If only one of the VBUS voltages is present, then the regulator

automatically selects this supply. Current limit is also included to help the system meet in-rush current

targets. If no VBUS voltage is present, then the VBUSVALID threshold setting will prevent the regulator

from being enabled.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

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For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.4

PLL Electrical Characteristics

4.4.1

Audio/Video PLL Electrical Parameters

Table 14. Audio/Video PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz ~1.3 GHz

24 MHz

<11250 reference cycles

4.4.2

4.4.3

4.4.4

528 MHz PLL

Table 15. 528 MHz PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

528 MHz PLL output

24 MHz

<11250 reference cycles

Ethernet PLL

Table 16. Ethernet PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

500 MHz

24 MHz

<11250 reference cycles

480 MHz PLL

Table 17. 480 MHz PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

480 MHz PLL output

24 MHz

<383 reference cycles

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4.4.5

Arm PLL

Table 18. Arm PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz~1.3 GHz

24 MHz

<2250 reference cycles

4.5

On-Chip Oscillators

OSC24M

4.5.1

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.5.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements a low power oscillator. It also implements a power mux such that it can be powered

from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when

VDD_HIGH_IN is lost.

In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz

clock will automatically switch to the internal ring oscillator.

CAUTION

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage, and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used instead, careful consideration must be given to the

timing implications on all of the SoC modules dependent on this clock.

The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN

power mux.

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Table 19. OSC32K Main Characteristics

Parameter Min

Typ

Max

Comments

Fosc

—

32.768 kHz

—

This frequency is nominal and determined mainly by the crystal selected. 32.0 K

would work as well.

Current

consumption

—

4 μA

—

The typical value shown is only for the oscillator, driven by an external crystal.

If the internal ring oscillator is used instead of an external crystal, then

approximately 25 μA must be added to this value.

Bias resistor

—

14 MΩ

This the integrated bias resistor that sets the amplifier into a high gain state. Any

leakage through the ESD network, external board leakage, or even a scope probe

that is significant relative to this value will debias the amplifier. The debiasing will

result in low gain, and will impact the circuit's ability to start up and maintain

oscillations.

Target Crystal Properties

Cload

ESR

—

10 pF

—

Usually crystals can be purchased tuned for different Cloads. This Cload value is

typically 1/2 of the capacitances realized on the PCB on either side of the quartz.

A higher Cload will decrease oscillation margin, but increases current oscillating

through the crystal.

50 kΩ

100 kΩ Equivalent series resistance of the crystal. Choosing a crystal with a higher value

will decrease the oscillating margin.

4.6

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2

LVDS I/O

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

ovdd

pmos (Rpu)

Voh min

1

Vol max

or

0

pdat

pad

Predriver

nmos (Rpd)

ovss

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

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4.6.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

Table 20 shows the DC parameters for the clock inputs.

Table 20. XTALI and RTC_XTALI DC Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

XTALI high-level DC input voltage

XTALI low-level DC input voltage

Vih

Vil

—

0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT

V

0

—

0.2

RTC_XTALI high-level DC input

voltage

Vih

0.8

1.1^{(See note 1)}

RTC_XTALI low-level DC input

voltage

Vil

—

0

—

0.2

V

Input capacitance

C_IN

Simulated data

—

5

—

pF

XTALI input leakage current at

startup

I_{XTALI_STARTUP}Power-on startup for

0.15 msecwithadriven

24 MHz clock

—

600

μA

at 1.1 V. ²

DC input current

I_{XTALI_DC}

—

2.5

μA

1

This voltage specification must not be exceeded and, as such, is an absolute maximum specification.

This current draw is present even if an external clock source directly drives XTALI.

2

NOTE

The Vil and Vih specifications only apply when an external clock source is

used. If a crystal is used, Vil and Vih do not apply.

4.6.2

General Purpose I/O (GPIO) DC Parameters

Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the

operating ranges in Table 6, unless otherwise noted.

Table 21. GPIO I/O DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage¹

Voh

Ioh = -0.1 mA (DSE²= 001, 010)

Ioh = -1 mA

OVDD – 0.15

—

V

(DSE = 011, 100, 101, 110, 111)

Low-level output voltage¹

Vol

Iol = 0.1 mA (DSE²= 001, 010)

Iol = 1mA

—

0.15

V

(DSE = 011, 100, 101, 110, 111)

High-Level DC input voltage^{1, 3}

Low-Level DC input voltage^{1, 3}

Input Hysteresis

Vih

Vil

—

0.7 × OVDD

OVDD

0.3 × OVDD

—

V

0

Vhys

OVDD = 1.8 V

OVDD = 3.3 V

0.25

Schmitt trigger VT+^{3, 4}

Schmitt trigger VT–^{3, 4}

VT+

VT–

—

0.5 × OVDD

—

V

—

0.5 × OVDD

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Table 21. GPIO I/O DC Parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input current (no pull-up/down)

Iin

Vin = OVDD or 0

-1

1

μA

Input current (22 kΩ pull-up)

Vin = 0 V

Vin = OVDD

—

212

1

μA

kΩ

Input current (47 kΩ pull-up)

Input current (100 kΩ pull-up)

Input current (100 kΩ pull-down)

Keeper circuit resistance

Iin

Vin = 0 V

Vin = OVDD

—

100

1

Vin = 0 V

Vin= OVDD

48

1

Iin

Vin = 0 V

Vin = OVDD

—

1

48

Rkeep

Vin = 0.3 x OVDD

Vin = 0.7 x OVDD

105

175

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2

3

DSE is the Drive Strength Field setting in the associated IOMUX control register.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

4

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.6.3

DDR I/O DC Parameters

The DDR I/O pads support LPDDR2.

4.6.4

RGMII I/O 2.5V I/O DC Electrical Parameters

The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 22 are

guaranteed per the operating ranges in Table 6, unless otherwise noted.

1

Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage¹

V_OH

Ioh= -0.1 mA (DSE=001,010)

—

V

OVDD-0.15

Ioh= -1.0 mA (DSE=011,100,101,110,111)

Low-level output voltage¹

V_OL

Iol= 0.1 mA (DSE=001,010)

—

0.15

V

Iol= 1.0 mA (DSE=011,100,101,110,111)

0.49xOVDD 0.51xOVDD

Input Reference Voltage

High-Level input voltage ^{2, 3}

Low-Level input voltage ^{2, 3}

V_ref

V_IH

V_IL

—

V

0.7xOVDD

OVDD

0.3xOVDD

—

0

V

Input Hysteresis(OVDD=1.8V) V_{HYS_HighVDD}

Input Hysteresis(OVDD=2.5V) V_{HYS_HighVDD}

OVDD=1.8V

OVDD=2.5V

250

mV

—

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Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters (continued)

1

Schmitt trigger VT+ ^{3, 4}

V_TH+

V_TH-

—

0.5xOVDD

—

mV

Schmitt trigger VT- ^{3, 4}

—

0.5xOVDD mV

Pull-up resistor (22 kΩ PU)

Pull-up resistor (47 kΩ PU)

Pull-up resistor (100 kΩ PU)

Pull-down resistor (100 kΩ PD)

Keeper Circuit Resistance

Input current (no pull-up/down)

R_{PU_22K}

R_{PU_47K}

R_{PU_100K}

R_{PD_100K}

R_keep

V_in=0V

212

1

μA

kΩ

μA

V_in=OVDD

V_in=0V

—

100

1

V_in=OVDD

V_in=0V

—

48

1

V_in=OVDD

V_in=0V

—

48

1

—

105

-2.9

165

2.9

I_in

V_I= 0,VI = OVDD

1

Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode)

SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode).

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6

V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

3

4

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled

(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).

4.6.4.1

LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported LPDDR2

Configurations.”

The parameters in Table 23 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

1

Table 23. LPDDR2 I/O DC Electrical Parameters

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

Low-level output voltage

Input reference voltage

DC input High Voltage

Voh

Vol

Ioh = -0.1 mA

0.9 × OVDD

—

V

Iol = 0.1 mA

0.1 × OVDD

0.51 × OVDD

OVDD

Vref

—

0.49 × OVDD

Vref+0.13V

OVSS

Vih(dc)

Vil(dc)

Vih(diff)

Vil(diff)

Iin

—

V

DC input Low Voltage

—

Vref-0.13V

See Note ²

-0.26

Differential Input Logic High

Differential Input Logic Low

Input current (no pull-up/down)

—

0.26

—

μA

See Note ²

-2.5

Vin = 0 or OVDD

2.5

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1

Table 23. LPDDR2 I/O DC Electrical Parameters (continued)

Parameters

Symbol

Test Conditions

Min

Max

Unit

Pull-up/pull-down impedance mismatch

240 Ω unit calibration resolution

Keeper circuit resistance

MMpupd

Rres

—

-15

—

+15

10

%

Ω

Rkeep

110

175

kΩ

1

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

2

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot (see Table 27).

4.6.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 24 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

Table 24. LVDS I/O DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Unit

Output Differential Voltage

Output High Voltage

Output Low Voltage

Offset Voltage

V_OD

V_OH

V_OL

V_OS

Rload=100 Ω between padP and padN

250

1.25

0.9

450

1.6

mV

I_OH= 0 mA

I_OL= 0 mA

—

1.25

1.375

V

1.125

4.7

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2

LVDS I/O

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and

Figure 5.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

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OVDD

0 V

80%

20%

80%

20%

Output (at pad)

tf

tr

Figure 5. Output Transition Time Waveform

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4.7.1

General Purpose I/O AC Parameters

The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 25 and Table 26,

respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the

IOMUXC control registers.

Table 25. General Purpose I/O AC Parameters 1.8 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=111)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.72/2.79

1.51/1.54

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=101)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.20/3.36

1.96/2.07

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=100)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.64/3.88

2.27/2.53

Output Pad Transition Times, rise/fall

(Low Drive. DSE=011)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

4.32/4.50

3.16/3.17

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Table 26. General Purpose I/O AC Parameters 3.3 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=101)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

1.70/1.79

1.06/1.15

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=011)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.35/2.43

1.74/1.77

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=010)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.13/3.29

2.46/2.60

Output Pad Transition Times, rise/fall

(Low Drive. DSE=001)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

5.14/5.57

4.77/5.15

—

Input Transition Times¹

—

25

ns

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

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4.7.2

DDR I/O AC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported LPDDR2

Configurations.”

Table 27 shows the AC parameters for DDR I/O operating in LPDDR2 mode.

1

Table 27. DDR I/O LPDDR2 Mode AC Parameters

Parameter

AC input logic high

Symbol

Test Condition

Min

Typ

Max

Unit

Vih(ac)

Vil(ac)

—

Vref + 0.22

—

OVDD

Vref – 0.22

—

V

AC input logic low

—

0

0.44

—

AC differential input high voltage²

AC differential input low voltage

Input AC differential cross point voltage³

Over/undershoot peak

Vidh(ac)

Vidl(ac)

Vix(ac)

Vpeak

—

V

—

Relative to Vref

—

0.44

V

-0.12

—

0.12

V

0.35

V

Over/undershoot area (above OVDD

or below OVSS)

Varea

400 MHz

—

0.2

V-ns

Single output slew rate, measured

between Vol(ac) and Voh(ac)

tsr

50 Ω to Vref.

5 pF load.

Drive impedance = 4 0 Ω 30%

1.5

1

—

3.5

2.5

0.1

V/ns

50 Ω to Vref.

5pF load.

Drive impedance = 60 Ω 30%

Skew between pad rise/fall asymmetry +

skew caused by SSN

t_SKD

clk = 400 MHz

ns

—

1

2

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).

3

The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4.7.3

LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 6.

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padp

padn

V

OH

0V

0V (Differential)

V

OL

80%

0V

VDIFF

VDIFF = {padp} - {padn}

20%

t

THL

TLH

Figure 6. Differential LVDS Driver Transition Time Waveform

Table 28 shows the AC parameters for LVDS I/O.

Table 28. I/O AC Parameters of LVDS Pad

Parameter

Differential pulse skew¹

Symbol Test Condition

Min

Typ

Max

Unit

t_SKD

—

0.25

0.5

Rload = 100 Ω,

Cload = 2 pF

Transition Low to High Time²

Transition High to Low Time²

Operating Frequency

t_TLH

ns

t_THL

—

0.5

f

—

600

—

800

150

MHz

mV

Offset voltage imbalance

Vos

1

t_SKD= | t_PHLD– t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

2

Measurement levels are 20–80% from output voltage.

4.8

Output Buffer Impedance Parameters

This section defines the I/O impedance parameters of the i.MX 6Dual/6Quad processors for the following

I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2

LVDS I/O

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 7).

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OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

Vin (do)

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

Rpd =

× Ztl

Vref2

Vovdd – Vref2

Figure 7. Impedance Matching Load for Measurement

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4.8.1

GPIO Output Buffer Impedance

Table 29 shows the GPIO output buffer impedance (OVDD 1.8 V).

Table 29. GPIO Output Buffer Average Impedance (OVDD 1.8 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

260

130

90

60

50

Output Driver

Impedance

Rdrv

Ω

40

33

Table 30 shows the GPIO output buffer impedance (OVDD 3.3 V).

Table 30. GPIO Output Buffer Average Impedance (OVDD 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

150

75

50

37

30

25

20

Output Driver

Impedance

Rdrv

Ω

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4.8.2

DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported LPDDR2

Configurations.”

Table 31 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors.

Table 31. LPDDR2 I/O Output Buffer Impedance

Typical

Parameter

Symbol

Test Conditions

Unit

NVCC_DRAM=1.2 V

DDR_SEL=10

Drive Strength (DSE) =

000

001

010

011

100

101

110

111

Hi-Z

240

120

80

60

48

Output Driver

Impedance

Rdrv

Ω

40

34

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240 W external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.

4.8.3

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.9

System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad

processor.

4.9.1

Reset Timing Parameters

Figure 8 shows the reset timing and Table 32 lists the timing parameters.

SRC_POR_B

(Input)

CC1

Figure 8. Reset Timing Diagram

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Table 32. Reset Timing Parameters

ID

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid

1

—

XTALOSC_RTC_ XTALI cycle

4.9.2

WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 33 lists the timing parameters.

WDOG1_B

(Output)

CC3

Figure 9. WDOG1_B Timing Diagram

Table 33. WDOG1_B Timing Parameters

ID

Parameter

Min

Max

Unit

CC3 Duration of WDOG1_B Assertion

1

—

XTALOSC_RTC_ XTALI cycle

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.

NOTE

WDOG1_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the IOMUX

manual for detailed information.

4.9.3

External Interface Module (EIM)

The following subsections provide information on the EIM. Maximum operating frequency for EIM data

transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or

clock periods are valid for the entire range of allowed frequencies (0–104 MHz).

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4.9.3.1

EIM Interface Pads Allocation

EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.

Table 34 provides EIM interface pads allocation in different modes.

1

Table 34. EIM Internal Module Multiplexing

Multiplexed

Non Multiplexed Address/Data Mode

Address/Data mode

Setup

8 Bit

16 Bit

32 Bit

16 Bit

32 Bit

MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 1, MUM = 1,

DSZ = 100 DSZ = 101 DSZ = 110 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011

EIM_ADDR

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_DATA

[25:16]

EIM_DATA EIM_AD

[07:00] [07:00]

[25:16]

[09:00]

EIM_DATA EIM_DATA

[07:00],

EIM_EB0_B

—

EIM_DATA

[07:00]

—

EIM_AD

[07:00]

—

EIM_DATA

[15:08],

EIM_EB1_B

EIM_DATA

[15:08]

—

EIM_DATA

[15:08]

—

EIM_DATA EIM_AD

EIM_AD

[15:08]

EIM_DATA

[23:16],

EIM_EB2_B

—

EIM_DATA

[23:16]

—

EIM_DATA EIM_DATA

[23:16] [23:16]

—

EIM_DATA

[07:00]

EIM_DATA

[31:24],

—

EIM_DATA

[31:24]

EIM_DATA EIM_DATA

[31:24] [31:24]

—

EIM_DATA

[15:08]

EIM_EB3_B

1

For more information on configuration ports mentioned in this table, see the i.MX 6Dual/6Quad reference manual

(IMX6DQRM).

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4.9.3.2

General EIM Timing-Synchronous Mode

Figure 10, Figure 11, and Table 35 specify the timings related to the EIM module. All EIM output control

signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge

according to corresponding assertion/negation control fields.

WE2

EIM_BCLK

...

WE3

WE1

WE4

WE6

WE5

WE7

WE9

EIM_ADDRxx

EIM_CSx_B

WE8

WE10

WE12

EIM_WE_B

EIM_OE_B

EIM_EBx_B

WE11

WE13

WE15

WE17

WE14

WE16

EIM_LBA_B

Output Data

Figure 10. EIM Output Timing Diagram

EIM_BCLK

WE18

Input Data

WE19

WE20

EIM_WAIT_B

WE21

Figure 11. EIM Input Timing Diagram

4.9.3.3

Examples of EIM Synchronous Accesses

Table 35. EIM Bus Timing Parameters

ID

Parameter

Min¹

Max¹

Unit

WE1

WE2

WE3

EIM_BCLK cycle time²

t × (k+1)

—

ns

EIM_BCLK high level width

EIM_BCLK low level width

0.4 × t × (k+1)

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Table 35. EIM Bus Timing Parameters (continued)

ID

Parameter

Clock rise to address valid

Min¹

Max¹

Unit

WE4

WE5

WE6

WE7

WE8

WE9

-0.5 × t × (k+1) - 1.25

^0.5× t × (k+1) - 1.25

^-0.5× t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

-0.5 × t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

-0.5 × t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

-0.5 × t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

-0.5 × t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

-0.5 × t × (k+1) - 1.25

0.5 × t × (k+1) - 1.25

2.3

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

-0.5 × t × (k+1) + 2.25

0.5 × t × (k+1) + 2.25

—

ns

Clock rise to address invalid

Clock rise to EIM_CSx_B valid

Clock rise to EIM_CSx_B invalid

Clock rise to EIM_WE_B valid

Clock rise to EIM_WE_B invalid

WE10 Clock rise to EIM_OE_B valid

WE11 Clock rise to EIM_OE_B invalid

WE12 Clock rise to EIM_EBx_B valid

WE13 Clock rise to EIM_EBx_B invalid

WE14 Clock rise to EIM_LBA_B valid

WE15 Clock rise to EIM_LBA_B invalid

WE16 Clock rise to output data valid

WE17 Clock rise to output data invalid

WE18 Input data setup time to clock rise

WE19 Input data hold time from clock rise

WE20 EIM_WAIT_B setup time to clock rise

WE21 EIM_WAIT_B hold time from clock rise

k represents register setting BCD value.

2

—

2

—

2

—

1

2

t is clock period (1/Freq). For 104 MHz, t = 9.165 ns.

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Figure 12 to Figure 15 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

EIM_BCLK

EIM_ADDRxx

WE5

WE7

WE4

WE6

Address v1

Last Valid Address

WE6

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE14

WE15

WE10

WE12

WE11

WE13

EIM_EBx_B

WE18

WE19

D(v1)

EIM_DATAxx

Figure 12. Synchronous Memory Read Access, WSC=1

EIM_BCLK

WE4

WE6

WE5

WE7

WE9

EIM_ADDRxx

Last Valid Address

Address V1

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE8

WE14

WE15

WE13

WE17

WE12

WE16

EIM_EBx_B

EIM_DATAxx

D(V1)

Figure 13. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0

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EIM_BCLK

WE16

WE17

WE5

WE4

Last Valid Address

WE6

EIM_ADDRxx/

EIM_ADxx

Write Data

Address V1

WE7

WE9

EIM_CSx_B

EIM_WE_B

WE8

WE14

WE15

EIM_LBA_B

EIM_OE_B

WE10

WE11

EIM_EBx_B

Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access,

WSC=6,ADVA=0, ADVN=1, and ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the

data bus.

EIM_BCLK

WE4

WE5

Address V1

WE19

WE18

EIM_ADDRxx/

EIM_ADxx

Data

Last Valid

Address

WE6

EIM_CSx_B

EIM_WE_B

WE7

WE15

WE10

WE14

WE12

EIM_LBA_B

EIM_OE_B

WE11

WE13

EIM_EBx_B

Figure 15. 16-Bit Muxed A/D Mode, Synchronous Read Access,

WSC=7, RADVN=1, ADH=1, OEA=0

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4.9.3.4

General EIM Timing-Asynchronous Mode

Figure 16 through Figure 20 and Table 36 provide timing parameters relative to the chip select (CS) state

for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing

parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through

Figure 19 as RWSC, OEN & CSN is configured differently. See the i.MX 6Dual/6Quad reference manual

(IMX6DQRM) for the EIM programming model.

end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

WE31

WE32

EIM_ADDRxx/

EIM_ADxx

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

WE39

WE40

WE35

WE37

WE36

WE38

EIM_OE_B

EIM_EBx_B

WE44

MAXCO

EIM_DATA[07:00]

D(V1)

WE43

MAXDI

Figure 16. Asynchronous Memory Read Access (RWSC = 5)

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end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

MAXDI

WE31

EIM_ADDRxx/

EIM_ADxx

D(V1)

Addr. V1

WE44

WE32A

WE40A

WE35A

EIM_WE_B

EIM_LBA_B

WE39

WE37

WE36

WE38

EIM_OE_B

EIM_EBx_B

MAXCO

Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5)

EIM_CSx_B

WE31

Last Valid Address

WE32

WE34

WE40

EIM_ADDRxx

Next Address

Address V1

WE33

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE39

WE45

WE41

WE46

EIM_EBx_B

WE42

EIM_DATAxx

D(V1)

Figure 18. Asynchronous Memory Write Access

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EIM_CSx_B

WE41A

WE31

EIM_ADDRxx/

EIM_DATAxx

D(V1)

Addr. V1

WE32A

WE42

WE33

WE39

WE34

EIM_WE_B

WE40A

EIM_LBA_B

EIM_OE_B

WE45

WE46

EIM_EBx_B

Figure 19. Asynchronous A/D Muxed Write Access

EIM_CSx_B

EIM_ADDRxx

WE31

WE32

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

WE39

WE35

WE37

WE40

WE36

WE38

WE44

D(V1)

EIM_DATAxx[07:00]

EIM_DTACK_B

WE43

WE48

WE47

Figure 20. DTACK Mode Read Access (DAP=0)

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EIM_CSx_B

WE31

WE32

WE34

WE40

EIM_ADDRxx

Next Address

Last Valid Address

Address V1

WE33

EIM_WE_B

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

WE39

WE45

WE41

WE46

WE42

WE48

D(V1)

EIM_DATAxx

EIM_DTACK_B

WE47

Figure 21. DTACK Mode Write Access (DAP=0)

1 2

,

Table 36. EIM Asynchronous Timing Parameters Relative to Chip Select

DeterminationbySynchronous

Ref No.

Parameter

Min

Max

Unit

measured parameters

WE31 EIM_CSx_B valid to Address Valid

WE4-WE6-CSA×t

WE7-WE5-CSN× t

-3.5-CSA×t

-3.5-CSN×t

3.5-CSA×t

3.5-CSN×t

ns

WE32 Address Invalid to EIM_CSx_B

Invalid

WE32A EIM_CSx_B valid to Address

(muxed Invalid

A/D)

t+WE4-WE7+

(ADVN+ADVA+1-CSA)×t

t - 3.5+(ADVN+A t + 3.5+(ADVN+ADVA+ ns

DVA+1-CSA)×t 1-CSA)×t

WE33 EIM_CSx_B Valid to EIM_WE_B

Valid

WE8-WE6+(WEA-WCSA)×t -3.5+(WEA-WCS 3.5+(WEA-WCSA)×t

A)×t

ns

WE34 EIM_WE_B Invalid to EIM_CSx_B WE7-WE9+(WEN-WCSN)×t -3.5+(WEN-WCS 3.5+(WEN-WCSN)×t

Invalid

N)×t

WE35 EIM_CSx_B Valid to EIM_OE_B

Valid

WE10- WE6+(OEA-RCSA)×t -3.5+(OEA-RCS 3.5+(OEA-RCSA)×t

A)×t

WE35A EIM_CSx_B Valid to EIM_OE_B WE10-WE6+(OEA+RADVN+R -3.5+(OEA+RAD 3.5+(OEA+RADVN+RA ns

(muxed Valid

A/D)

ADVA+ADH+1-RCSA)×t

VN+RADVA+ADH DVA+ADH+1-RCSA)×t

+1-RCSA)×t

WE36 EIM_OE_B Invalid to EIM_CSx_B WE7-WE11+(OEN-RCSN)×t -3.5+(OEN-RCS 3.5+(OEN-RCSN)×t

Invalid N)×t

ns

WE37 EIM_CSx_B Valid to EIM_EBx_B WE12-WE6+(RBEA-RCSA)× t -3.5+(RBEA- RC 3.5+(RBEA - RCSA)×t ns

Valid (Read access)

SA)×t

WE38 EIM_EBx_B Invalid to

WE7-WE13+(RBEN-RCSN)×t

-3.5+

(RBEN-RCSN)×t

3.5+(RBEN-RCSN)×t ns

EIM_CSx_B Invalid (Read access)

WE39 EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVA-CSA)×t

-3.5+

(ADVA-CSA)×t

3.5+(ADVA-CSA)×t

ns

Valid

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1 2

,

Table 36. EIM Asynchronous Timing Parameters Relative to Chip Select

(continued)

DeterminationbySynchronous

Ref No.

Parameter

Min

Max

Unit

measured parameters

WE40 EIM_LBA_B Invalid to

EIM_CSx_B Invalid (ADVL is

asserted)

WE7-WE15-CSN×t

-3.5-CSN×t

3.5-CSN×t

ns

WE40A EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVN+ADVA+1- -3.5+(ADVN+AD

3.5+(ADVN+ADVA

ns

(muxed Invalid

A/D)

CSA)×t

VA+1-CSA)×t

+1-CSA)×t

WE41 EIM_CSx_B Valid to Output Data

Valid

WE16-WE6-WCSA×t

-3.5-WCSA×t

3.5-WCSA×t

WE41A EIM_CSx_B Valid to Output Data WE16-WE6+(WADVN+WADVA -3.5+(WADVN+ 3.5+(WADVN+WADVA ns

(muxed Valid

A/D)

+ADH+1-WCSA)×t

WADVA

+ADH+1-WCSA)

×t

+ADH+1-WCSA)×t

WE42 OutputData InvalidtoEIM_CSx_B

Invalid

WE17-WE7-CSN×t

-3.5-CSN×t

3.5-CSN×t

ns

MAXCO Output maximum delay from

internal driving

10

—

10

EIM_ADDRxx/control flip-flops to

chip outputs.

MAXCSO Output maximum delay from

internal chip selects driving

10

5

—

10

5

ns

flip-flops to EIM_CSx_B out.

MAXDI EIM_DATAxx MAXIMUM delay

from chip input data to its internal

flip-flop

WE43 Input Data Valid to EIM_CSx_B

Invalid

MAXCO-MAXCSO+MAXDI MAXCO-MAXCS

O+MAXDI

—

ns

WE44 EIM_CSx_B Invalid to Input Data

Invalid

0

WE45 EIM_CSx_B Valid to EIM_EBx_B WE12-WE6+(WBEA-WCSA)×t -3.5+(WBEA-WC 3.5+(WBEA-WCSA)×t ns

Valid (Write access)

SA)×t

WE46 EIM_EBx_B Invalid to

WE7-WE13+(WBEN-WCSN)×t -3.5+(WBEN-WC 3.5+(WBEN-WCSN)×t ns

SN)×t

EIM_CSx_B Invalid (Write access)

MAXDTI Maximum delay from

EIM_DTACK_B input to its internal

10

—

10

ns

flip-flop + 2 cycles for

synchronization

WE47 EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO-MAXCSO+MAXDTI MAXCO-MAXCS

O+MAXDTI

—

ns

WE48 EIM_CSx_B Invalid to

EIM_DTACK_B invalid

0

1

For more information on configuration parameters mentioned in this table, see the i.MX 6Dual/6Quad reference manual

(IMX6DQRM).

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2

In this table:

• t means clock period from axi_clk frequency.

• CSA means register setting for WCSA when in write operations or RCSA when in read operations.

• CSN means register setting for WCSN when in write operations or RCSN when in read operations.

• ADVN means register setting for WADVN when in write operations or RADVN when in read operations.

• ADVA means register setting for WADVA when in write operations or RADVA when in read operations.

4.10 Multi-Mode DDR Controller (MMDC)

The Multi-mode DDR Controller is a dedicated interface to LPDDR2 SDRAM.

4.10.1 MMDC Compatibility with JEDEC-Compliant SDRAMs

The i.MX 6Dual/6Quad MMDC supports the following memory type:

•

LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009

MMDC operation with the standards stated above is contingent upon the board DDR design adherence to

the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,

6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

4.10.2 MMDC Supported LPDDR2 Configurations

The table below shows the supported LPDDR2 configurations:

Table 37. i.MX 6Dual/6Quad Supported LPDDR2 Configurations

Parameter

LPDDR2

Clock frequency

Bus width

400 MHz

32-bit per channel

Dual

Channel

Chip selects

2 per channel

4.11 General-Purpose Media Interface (GPMI) Timing

The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data

width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source

Synchronous timing mode, and Samsung Toggle timing mode separately described in the following

subsections.

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4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 22 through Figure 25

depict the relative timing between GPMI signals at the module level for different operations under

Asynchronous mode. Table 38 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢀ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 22. Command Latch Cycle Timing Diagram

NF1

.!.$?#,%

NF3

.!.$?#%ꢀ?"

.!.$?7%?"

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 23. Address Latch Cycle Timing Diagram

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

.!.$?!,%

NF8

Data to NF

NF9

.!.$?$!4!XX

Figure 24. Write Data Latch Cycle Timing Diagram

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61

Electrical Characteristics

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?2%?"

NF14

NF13

NF15

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode)

1

Table 38. Asynchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

(AS + DS) × T - 0.12 [see ^2,3

Max

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NF8

NF9

NAND_CLE setup time

NAND_CLE hold time

NAND_CEx_B setup time

NAND_CEx_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

Data setup time

tCLS

tCLH

tCS

]

ns

DH × T - 0.72 [see ²]

(AS + DS + 1) × T [see ^3,2

(DH+1) × T - 1 [see ²]

DS × T [see ²]

]

tCH

tWP

tALS

tALH

tDS

(AS + DS) × T - 0.49 [see ^3,2

(DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

]

Data hold time

tDH

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2) × T [see ^3,2

]

—

DS × T [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

tRC

NF15 NAND_RE_B high hold time

tREH

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1

Table 38. Asynchronous Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF16 Data setup on read

NF17 Data hold on read

tDSR

tDHR

—

(DS × T -0.67)/18.38 [see ^5,6

]

ns

0.82/11.83 [see ^5,6

]

—

1

The GPMI asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

5

6

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075ns (half of maximum p-p jitter).

NF12 is met automatically by the design.

Non-EDO mode.

EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 26), NF16/NF17 are different from the definition in non-EDO mode (Figure 25).

They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The

typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO

mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an

internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter

of the i.MX 6Dual/6Quad reference manual (IMX6DQRM)). The typical value of this control register is

0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay

value should be made larger to compensate the board delay.

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Electrical Characteristics

4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)

Figure 27 shows the write and read timing of Source Synchronous mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 27. Source Synchronous Mode Command and Address Timing Diagram

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NXP Semiconductors

Electrical Characteristics

NF19

NF18

.!.$?#%ꢀ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢁꢂꢀ=

NF28

.!.$?$1;ꢁꢂꢀ=

Output enable

Figure 28. Source Synchronous Mode Data Write Timing Diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢃ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢁꢂꢀ=

/UTPUT ENABLE

Figure 29. Source Synchronous Mode Data Read Timing Diagram

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65

Electrical Characteristics

.!.$?$13

NF30

.!.$?$!4!;ꢁꢂꢀ=

D0

D1

D2

D3

NF30

NF31

Figure 30. NAND_DQS/NAND_DQ Read Valid Window

1

Table 39. Source Synchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

2

NF18 NAND_CEx_B access time

tCE

tCH

CE_DELAY × T - 0.79 [see ]

0.5 × tCK - 0.63 [see ²]

0.5 × tCK - 0.05

ns

—

NF19 NAND_CEx_B hold time

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5 × tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

tDS

PRE_DELAY × T - 0.29 [see ²]

POST_DELAY × T - 0.78 [see ²]

0.5 × tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5 × tCK - 0.37

T - 0.41 [see ²]

0.25 × tCK - 0.35

NF29 Data write hold

tDH

0.25 × tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

tDQSQ

tQHS

—

2.06

1.95

NF31 NAND_DQS/NAND_DQ read hold skew

1

2

The GPMI source synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source

Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200MB/s.

GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,

which can be provided by an internal DPLL. The delay value can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX

6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value of this register is equal

to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot

be ignored, the delay value should be made larger to compensate the board delay.

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4.11.3 Samsung Toggle Mode AC Timing

4.11.3.1 Command and Address Timing

Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC

timing. See Section 4.11.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” for details.

4.11.3.2 Read and Write Timing

DEV?CLK

ꢀ

.!.$?#%X?"

ꢀ

.!.$?#,%

ꢀ

.!.$?!,%

ꢄ

.!.$?7%?"

ꢄ

.!.$?2%?"

.&ꢇꢉ

.&ꢇꢈ

.!.$?$13

ꢀꢅꢆ T#+

.!.$?$!4!;ꢁꢂꢀ=

Figure 31. Samsung Toggle Mode Data Write Timing

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Electrical Characteristics

DEV?CLK

.!.$?#%X?"

.& ꢄꢊ

.!.$?#,%

.!.$?!,%

ꢄ T #+

ꢄ

.&ꢇꢉ

.!.$?7%?"

.!.$?2%?"

ꢄ T #+

.& ꢇꢈ

ꢄ T #+

.!.$?$13

.!.$?$!4!;ꢁꢂꢀ=

Figure 32. Samsung Toggle Mode Data Read Timing

1

Table 40. Samsung Toggle Mode Timing Parameters

Timing

T = GPMI Clock Cycle

Min

ID

Parameter

Symbol

Unit

Max

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

NF3 NAND_CEx_B setup time

NF4 NAND_CEx_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see ^2,3

DH × T - 0.72 [see ²]

(AS + DS) × T - 0.58 [see ^3,2

DH × T - 1 [see ²]

]

—

ns

]

tCH

tWP

tALS

tALH

DS × T [see ²]

(AS + DS) × T - 0.49 [see ^3,2

DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

]

NF8 Command/address NAND_DATAxx setup time tCAS

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

tCAH

tCE

CE_DELAY × T [see ^4,2

]

—

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY × T [see ^5,2

]

NF24 postamble delay

tPOST POST_DELAY × T +0.43 [see ²]

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1

Table 40. Samsung Toggle Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF28 Data write setup

NF29 Data write hold

tDS⁶

tDH⁶

tDQSQ⁷

tQHS⁷

0.25 × tCK - 0.32

—

ns

—

0.25 × tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

—

3.18

3.27

1

The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is met automatically by the design. Read/Write operation is

started with enough time of ALE/CLE assertion to low level.

5

6

7

PRE_DELAY+1) ≥ (AS+DS).

Shown in Figure 28.

Shown in Figure 29.

Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For DDR

Toggle mode, the typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI

will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX

6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value is equal to 0x7 which

means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored,

the delay value should be made larger to compensate the board delay.

4.12 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.12.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.12.2 ECSPI Timing Parameters

This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing

parameters for master and slave modes.

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Electrical Characteristics

4.12.2.1 ECSPI Master Mode Timing

Figure 33 depicts the timing of ECSPI in master mode and Table 41 lists the ECSPI master mode timing

characteristics.

ECSPIx_RDY_B

CS10

ECSPIx_SS_B

CS5

CS6

CS2

CS1

CS3

CS4

ECSPIx_SCLK

ECSPIx_MOSI

CS2

CS7

CS3

CS9

CS8

ECSPIx_MISO

Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be

connected between a single master and a single slave.

Figure 33. ECSPI Master Mode Timing Diagram

Table 41. ECSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1

ECSPIx_SCLK Cycle Time–Read

• Slow group¹

t_clk

—

ns

55

40

15

• Fast group²

ECSPIx_SCLK Cycle Time–Write

CS2

ECSPIx_SCLK High or Low Time–Read

• Slow group¹

t_SW

—

ns

26

20

7

• Fast group²

ECSPIx_SCLK High or Low Time–Write

CS3

CS4

CS5

CS6

CS7

CS8

ECSPIx_SCLK Rise or Fall³

t_RISE/FALL

t_CSLH

—

1

ns

ECSPIx_SSx pulse width

Half ECSPIx_SCLK period

Half ECSPIx_SCLK period - 4

Half ECSPIx_SCLK period - 2

-1

ECSPIx_SSx Lead Time (CS setup time)

ECSPIx_SSx Lag Time (CS hold time)

ECSPIx_MOSI Propagation Delay (C_LOAD= 20 pF)

t_SCS

t_HCS

t_PDmosi

t_Smiso

ECSPIx_MISO Setup Time

• Slow group¹

—

21.5

16

• Fast group²

CS9

ECSPIx_MISO Hold Time

t_Hmiso

t_SDRY

0

5

—

ns

CS10 ECSPIx_RDY to ECSPIx_SSx Time⁴

1

2

ECSPI slow includes:

ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,

ECSPI2/EIM_OE, ECSPI2/ ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2

ECSPI fast includes:

ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0

See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”

3

4

ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

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4.12.2.2 ECSPI Slave Mode Timing

Figure 34 depicts the timing of ECSPI in slave mode and Table 42 lists the ECSPI slave mode timing

characteristics.

ECSPIx_SS_B

CS5

CS6

CS2

CS1

CS4

ECSPIx_SCLK

ECSPIx_MISO

CS2

CS9

CS8

CS7

ECSPIx_MOSI

Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be con-

nected between a single master and a single slave.

Figure 34. ECSPI Slave Mode Timing Diagram

Table 42. ECSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1

ECSPIx_SCLK Cycle Time–Read

• Slow group¹

t_clk

—

ns

55

40

15

• Fast group²

ECSPIx_SCLK Cycle Time–Write

CS2

ECSPIx_SCLK High or Low Time–Read

• Slow group¹

t_SW

—

ns

26

20

7

• Fast group²

ECSPIx_SCLK High or Low Time–Write

CS4

CS5

CS6

CS7

CS8

CS9

ECSPIx_SSx pulse width

t_CSLH

t_SCS

Half ECSPIx_SCLK period

—

ns

ECSPIx_SSx Lead Time (CS setup time)

ECSPIx_SSx Lag Time (CS hold time)

ECSPIx_MOSI Setup Time

5

4

t_HCS

t_Smosi

t_Hmosi

t_PDmiso

ECSPIx_MOSI Hold Time

ECSPIx_MISO Propagation Delay (C_LOAD= 20 pF)

• Slow group¹

• Fast group²

25

17

1

2

ECSPI slow includes:

ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,

ECSPI2/EIM_OE, ECSPI2/DISP0_DAT17, ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2

ECSPI fast includes:

ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0

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Electrical Characteristics

4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 43 shows the interface timing values. The number field in the table refers to timing

signals found in Figure 35 and Figure 36.

Table 43. Enhanced Serial Audio Interface (ESAI) Timing

ID

Parameter^1,2

Symbol Expression²Min

Max Condition³Unit

62 Clock cycle⁴

t_SSICC

4 × T

30.0

—

i ck

ns

c

63 Clock high period:

• For internal clock

• For external clock

ns

—

2 × T − 9.0

6

15

—

c

2 × T

c

64 Clock low period:

• For internal clock

• For external clock

ns

—

2 × T − 9.0

6

15

—

c

2 × T

c

65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high

—

19.0

7.0

x ck

i ck a

ns

66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low

—

19.0

7.0

x ck

i ck a

67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

high⁵

—

19.0

9.0

x ck

i ck a

68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low⁵

69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high

70 ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low

—

19.0

9.0

x ck

i ck a

—

19.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

71 Data in setup time before ESAI_RX_CLK (serial clock in

synchronous mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after ESAI_RX_CLK falling edge

—

3.5

9.0

—

x ck

i ck

73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK

falling edge⁵

—

2.0

19.0

—

x ck

i ck a

74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK

falling edge

—

2.0

19.0

—

x ck

i ck a

75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling

edge

—

2.5

8.5

—

x ck

i ck a

78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high

—

19.0

8.0

x ck

i ck

79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low

—

20.0

10.0

x ck

i ck

80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

high⁵

—

20.0

10.0

x ck

i ck

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Table 43. Enhanced Serial Audio Interface (ESAI) Timing (continued)

Parameter^1,2Symbol Expression²Min Max Condition³Unit

ID

81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low⁵

82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high

83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low

—

22.0

12.0

x ck

i ck

ns

—

19.0

9.0

x ck

i ck

—

20.0

10.0

x ck

i ck

84 ESAI_TX_CLK rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

86 ESAI_TX_CLK rising edge to data out valid

—

19.0

13.0

x ck

i ck

87 ESAI_TX_CLK rising edge to data out high impedance ⁶⁷

—

21.0

16.0

x ck

i ck

89 ESAI_TX_FS input (bl, wr) setup time before

ESAI_TX_CLK falling edge⁵

—

2.0

18.0

—

x ck

i ck

90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK

falling edge

—

2.0

18.0

—

x ck

i ck

91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling

edge

—

4.0

5.0

—

x ck

i ck

95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle

—

2 x T_C

—

15

—

ns

96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK

output

18.0

97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK

output

—

18.0

—

ns

1

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)

2

3

bl = bit length

wl = word length

wr = word length relative

ESAI_TX_CLK(ESAI_TX_CLK pin) = transmit clock

ESAI_RX_CLK(ESAI_RX_CLK pin) = receive clock

ESAI_TX_FS(ESAI_TX_FS pin) = transmit frame sync

ESAI_RX_FS(ESAI_RX_FS pin) = receive frame sync

ESAI_TX_HF_CLK(ESAI_TX_HF_CLK pin) = transmit high frequency clock

ESAI_RX_HF_CLK(ESAI_RX_HF_CLK pin) = receive high frequency clock

4

5

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

6

Periodically sampled and not 100% tested.

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62

63

64

ESAI_TX_CLK

(Input/Output)

78

79

ESAI_TX_FS

(Bit)

Out

82

83

ESAI_TX_FS

(Word)

Out

86

84

86

87

First Bit

Last Bit

Data Out

89

91

ESAI_TX_FS

(Bit) In

91

90

ESAI_TX_FS

(Word) In

Figure 35. ESAI Transmitter Timing

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62

63

64

ESAI_RX_CLK

(Input/Output)

65

66

ESAI_RX_FS

(Bit) Out

69

70

ESAI_RX_FS

(Word) Out

72

71

Data In

Last Bit

First Bit

75

73

ESAI_RX_FS

(Bit) In

74

75

ESAI_RX_FS

(Word) In

Figure 36. ESAI Receiver Timing

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4.12.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)

AC Timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing.

4.12.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 37 depicts the timing of SD/eMMC4.3, and Table 44 lists the SD/eMMC4.3 timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 37. SD/eMMC4.3 Timing

Table 44. SD/eMMC4.3 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1

Clock Frequency (Low Speed)

f_PP

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

2

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

f_PP

3

f_PP

0

f_OD

t_WL

100

7

SD2

SD3

SD4

SD5

Clock High Time

t_WH

t_TLH

t_THL

7

—

ns

Clock Rise Time

—

3

ns

Clock Fall Time

3

ns

eSDHC Output/Card Inputs SD_CMD, SD_DATAx (Reference to SDx_CLK)

eSDHC Output Delay t_OD–6.6

SD6

3.6

ns

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Table 44. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter Symbols Min

eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK)

ID

Max

Unit

SD7

SD8

eSDHC Input Setup Time

eSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

ns

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

3

In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

⁴To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.12.4.2 eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing

Figure 38 depicts the timing of eMMC4.4/4.41. Table 45 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only SDx_DATAx is sampled on both edges of the clock (not applicable to SD_CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 38. eMMC4.4/4.41 Timing

Table 45. eMMC4.4/4.41 Interface Timing Specification

ID

Parameter

Symbols

Card Input Clock¹

f_PP

Min

Max

Unit

SD1

Clock Frequency (EMMC4.4 DDR)

Clock Frequency (SD3.0 DDR)

0

52

50

MHz

uSDHC Output / Card Inputs SD_CMD, SD_DATAx (Reference to SD_CLK)

uSDHC Output Delay t_OD2.8 6.8

uSDHC Input / Card Outputs SD_CMD, SD_DATAx (Reference to SD_CLK)

SD2

ns

SD3

SD4

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

1.7

1.5

—

ns

1

Clock duty cycle will be in the range of 47% to 53%.

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4.12.4.3 SDR50/SDR104 AC Timing

Figure 39 depicts the timing of SDR50/SDR104, and Table 46 lists the SDR50/SDR104 timing

characteristics.

SD1

SD2

SD3

SCK

SD5

SD4

Output from uSDHC to card

SD7

SD6

Input from card to uSDHC

SD8

Figure 39. SDR50/SDR104 Timing

Table 46. SDR50/SDR104 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

4.8

—

ns

0.46 × t_CLK

0.54 × t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD4 uSDHC Output Delay t_OD–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)

uSDHC Output Delay t_OD–1.6 0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

1

ns

SD5

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

2.5

1.5

—

ns

SD6

SD7

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)¹

Card Output Data Window t_ODW0.5 × t_CLK

—

ns

SD8

¹Data window in SDR100 mode is variable.

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4.12.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are

identical to those shown in Table 21, “GPIO I/O DC Parameters,” on page 38.

4.12.5 Ethernet Controller (ENET) AC Electrical Specifications

4.12.5.1 ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.12.5.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1ꢀ. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

Figure 40 shows MII receive signal timings. Table 47 describes the timing parameters (M1–M4) shown in

the figure.

M3

ENET_RX_CLK (input)

M4

ENET_RX_DATA3,2,1,0

(inputs)

ENET_RX_EN

ENET_RX_ER

M1

M2

Figure 40. MII Receive Signal Timing Diagram

Table 47. MII Receive Signal Timing

ID

Characteristic¹

Min

Max

Unit

M1

M2

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

5

—

ns

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

5

—

ns

M3

M4

ENET_RX_CLK pulse width high

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

¹ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

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4.12.5.1.2 MII Transmit Signal Timing

(ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1ꢀ.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET_TX_CLK frequency.

Figure 41 shows MII transmit signal timings. Table 48 describes the timing parameters (M5–M8) shown

in the figure.

M7

ENET_TX_CLK (input)

M5

M8

ENET_TX_DATA3,2,1,0

(outputs)

ENET_TX_EN

ENET_TX_ER

M6

Figure 41. MII Transmit Signal Timing Diagram

Table 48. MII Transmit Signal Timing

ID

Characteristic¹

Min

Max

Unit

M5

M6

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5

—

ns

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—

20

ns

M7

M8

ENET_TX_CLK pulse width high

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

¹ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.12.5.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)

Figure 42 shows MII asynchronous input timings. Table 49 describes the timing parameter (M9) shown in

the figure.

ENET_CRS, ENET_COL

M9

Figure 42. MII Async Inputs Timing Diagram

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Table 49. MII Asynchronous Inputs Signal Timing

ID

M9¹

Characteristic

Min

Max

Unit

ENET_CRS to ENET_COL minimum pulse width

1.5

—

ENET_TX_CLK period

¹ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

4.12.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 43 shows MII asynchronous input timings. Table 50 describes the timing parameters (M10–M15)

shown in the figure.

M14

M15

ENET_MDC (output)

M10

ENET_MDIO (output)

M11

ENET_MDIO (input)

M12

M13

Figure 43. MII Serial Management Channel Timing Diagram

Table 50. MII Serial Management Channel Timing

ID

M10

Characteristic

Min

Max

Unit

ENET_MDC falling edge to ENET_MDIO output invalid

(minimum propagation delay)

0

—

ns

M11

ENET_MDC falling edge to ENET_MDIO output valid

(maximum propagation delay)

—

5

ns

M12

M13

M14

M15

ENET_MDIO (input) to ENET_MDC rising edge setup

ENET_MDIO (input) to ENET_MDC rising edge hold

ENET_MDC pulse width high

18

0

—

ns

40%

60%

ENET_MDC period

ENET_MDC pulse width low

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4.12.5.2 RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz 50 ppm continuous reference

clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include

ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER.

Figure 44 shows RMII mode timings. Table 51 describes the timing parameters (M16–M21) shown in the

figure.

M16

M17

ENET_CLK (input)

M18

ENET0_TXD[1:0] (output)

ENET_TX_EN

M19

ENET_RX_EN (input)

ENET_RXD[1:0]

ENET_RX_ER

M20

M21

Figure 44. RMII Mode Signal Timing Diagram

Table 51. RMII Signal Timing

ID

M16

Characteristic

Min

Max

Unit

ENET_CLK pulse width high

ENET_CLK pulse width low

35%

4

65%

—

ENET_CLK period

M17

M18

M19

M20

ENET_CLK period

ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid

ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN valid

ns

—

13.5

—

ENET_RXD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

4

M21

ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold

2

—

ns

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4.12.5.3 RGMII Signal Switching Specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

1

Table 52. RGMII Signal Switching Specifications

Symbol

Description

Min

Max

Unit

2

T_cyc

Clock cycle duration

7.2

-100

1

8.8

900

2.6

55

ns

ps

ns

%

3

T_skewT

Data to clock output skew at transmitter

Data to clock input skew at receiver

3

T_skewR

Duty_G⁴Duty cycle for Gigabit

Duty_T⁴Duty cycle for 10/100T

45

40

60

%

Tr/Tf

Rise/fall time (20–80%)

—

0.75

ns

1

The timings assume the following configuration:

DDR_SEL = (11)b

DSE (drive-strength) = (111)b

2

3

For 10 Mbps and 100 Mbps, T_cycwill scale to 400 ns 40 ns and 40 ns 4 ns respectively.

For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

delay of greater than 1.2 ns and less than 1.7 ns will be added to the associated clock signal. For 10/100, the max value is

unspecified.

4

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

Figure 45. RGMII Transmit Signal Timing Diagram Original

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Figure 46. RGMII Receive Signal Timing Diagram Original

Figure 47. RGMII Receive Signal Timing Diagram with Internal Delay

4.12.6 Flexible Controller Area Network (FlexCAN) AC Electrical

Specifications

The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing

the CAN protocol according to the CAN 2.0B protocol specification.The processor has two CAN modules

available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See

the IOMUXC chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM) to see which pins

expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.

4.12.7 HDMI Module Timing Parameters

4.12.7.1 Latencies and Timing Information

Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx

PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms.

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Power-up time for the HDMI 3D Tx PHY while operating with the fastest input reference clock supported

(340 MHz) is 133 μs.

4.12.7.2 Electrical Characteristics

The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures

illustrate various definitions and measurement conditions specified in the table below.

Figure 48. Driver Measuring Conditions

Figure 49. Driver Definitions

Figure 50. Source Termination

Table 53. Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Operating conditions for HDMI

avddtmds Termination supply voltage

—

3.15

3.3

3.45

V

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Table 53. Electrical Characteristics (continued)

Symbol

Parameter

Condition

—

Min

45

Typ

Max

Unit

R_T

Termination resistance

50

55

Ω

TMDS drivers DC specifications

V_OFF

Single-ended standby voltage

RT = 50 Ω

avddtmds 10 mV

mV

For measurement conditions and

definitions, see the first two figures

above.

V_SWINGSingle-ended output swing voltage

400

—

600

Compliance point TP1 as defined in

the HDMI specification, version 1.3a,

section 4.2.4.

V_H

Single-ended output high voltage If attached sink supports TMDSCLK <

avddtmds 10 mV

mV

Ω

For definition, see the second

figure above.

or = 165 MHz

If attached sink supports TMDSCLK > avddtmds

—

avddtmds

+ 10 mV

165 MHz – 200 mV

V_L

Single-ended output low voltage

For definition, see the second

figure above.

If attached sink supports TMDSCLK < avddtmds

or = 165 MHz – 600 mV

avddtmds

– 400mV

If attached sink supports TMDSCLK > avddtmds

avddtmds

– 400 mV

165 MHz

– 700 mV

R_TERMDifferential source termination load

(inside HDMI 3D Tx PHY)

—

50

200

Although the HDMI 3D Tx PHY

includes differential source

termination, the user-defined value

is set for each single line (for

illustration, see the third figure

above).

Note: R_TERMcan also be

configured to be open and not

present on TMDS channels.

Hot plug detect specifications

HPD^VHHot plug detect high range

VHPD

—

2.0

0

—

5.3

0.8

—

V

Hot plug detect low range

VL

HPD

Hot plug detect input impedance

10

—

kΩ

µs

Z

HPD

Hot plug detect time delay

100

t

4.12.8 Switching Characteristics

Table 54 describes switching characteristics for the HDMI 3D Tx PHY. Figure 51 to Figure 55 illustrate

various parameters specified in table.

NOTE

All dynamic parameters related to the TMDS line drivers’ performance

imply the use of assembly guidelines.

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P

TMDSCLK

50%

t

CPL

CPH

Figure 51. TMDS Clock Signal Definitions

Figure 52. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1

Figure 53. Intra-Pair Skew Definition

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Figure 54. Inter-Pair Skew Definition

Figure 55. TMDS Output Signals Rise and Fall Time Definition

Table 54. Switching Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TMDS Drivers Specifications

—

Maximum serial data rate

TMDSCLK frequency

TMDSCLK period

—

25

—

3.4

340

40

Gbps

MHz

ns

F

P

On TMDSCLKP/N outputs

TMDSCLK

RL = 50 Ω

See Figure 51.

2.94

t

= t

/ P

TMDSCLK duty cycle

40

50

60

%

CDC

CPH

TMDSCLK

RL = 50 Ω

See Figure 51.

t

TMDSCLK high time

TMDSCLK low time

RL = 50 Ω

4

5

6

UI

CPH

See Figure 51.

t

RL = 50 Ω

See Figure 51.

CPL

—

TMDSCLK jitter¹

RL = 50 Ω

—

0.25

0.15

UI

t

Intra-pair (pulse) skew

RL = 50 Ω

See Figure 53.

SK(p)

t

Inter-pair skew

RL = 50 Ω

—

1

UI

ps

SK(pp)

See Figure 54.

t_R

Differential output signal rise

time

20–80%

RL = 50 Ω

See Figure 55.

75

0.4 UI

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Table 54. Switching Characteristics (continued)

Parameter Conditions Min

Symbol

Typ

Max

Unit

t_F

Differential output signal fall time 20–80%

75

—

0.4 UI

ps

RL = 50 Ω

See Figure 55.

—

Differential signal overshoot

Differential signal undershoot

Referred to 2x V_SWING

—

15

25

%

Data and Control Interface Specifications

2

t_Power-up

HDMI 3D Tx PHY power-up time From power-down to

—

3.35

ms

HSI_TX_READY assertion

Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3.

For information about latencies and associated timings, see Section 4.12.7.1, “Latencies and Timing Information.”

1

2

4.12.9 I²C Module Timing Parameters

2

This section describes the timing parameters of the I C module. Figure 56 depicts the timing of I C

2

module, and Table 55 lists the I C module timing characteristics.

I2Cx_SDA

I2Cx_SCL

IC11

IC9

IC10

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 56. I C Bus Timing

2

Table 55. I C Module Timing Parameters

Standard Mode

Fast Mode

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

I2Cx_SCL cycle time

10

4.0

0¹

—

2.5

0.6

0¹

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

—

3.45²

—

0.9²µs

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

4.0

4.7

250

0.6

1.3

0.6

100³

—

µs

ns

—

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2

Table 55. I C Module Timing Parameters (continued)

Standard Mode

Parameter

Fast Mode

ID

Unit

Min

Max

Min

Max

IC9

Bus free time between a STOP and START condition

4.7

—

1.3

—

µs

4

IC10

IC11

IC12

Rise time of both I2Cx_SDA and I2Cx_SCL signals

Fall time of both I2Cx_SDA and I2Cx_SCL signals

Capacitive load for each bus line (C_b)

1000

300

400

20 + 0.1C_b300 ns

4

20 + 0.1C_b300 ns

—

400 pF

1

A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling

edge of I2Cx_SCL.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.

If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2Cx_SCL line is released.

4

C_b= total capacitance of one bus line in pF.

4.12.10 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor

and/or to a display device. This support covers all aspects of these activities:

•

Connectivity to relevant devices^—cameras, displays, graphics accelerators, and TV encoders.

Related image processing and manipulation: sensor image signal processing, display processing,

image conversions, and other related functions.

•

Synchronization and control capabilities, such as avoidance of tearing artifacts.

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4.12.10.1 IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats. Table 56 defines the mapping of the Sensor Interface

Pins used for various supported interface formats.

Table 56. Camera Input Signal Cross Reference, Format, and Bits Per Cycle

RGB565

8 bits

2 cycles

RGB565²

8 bits

3 cycles

RGB666³RGB888

YCbCr⁴RGB565⁵YCbCr⁶

YCbCr⁷

16 bits

1 cycle

YCbCr⁸

20 bits

1 cycle

Signal

Name¹

8 bits

16 bits

1 cycle

16 bits

1 cycle

3 cycles

3 cycles 2 cycles

IPUx_CSIx_

DATA00

—

0

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

C[8]

C[9]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

IPUx_CSIx_

DATA01

—

0

IPUx_CSIx_

DATA02

—

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

0

IPUx_CSIx_

DATA03

—

IPUx_CSIx_

DATA04

—

B[0]

B[1]

B[2]

B[3]

B[4]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

IPU2_CSIx_

DATA_05

—

IPUx_CSIx_

DATA06

—

IPUx_CSIx_

DATA07

—

IPUx_CSIx_

DATA08

—

IPUx_CSIx_

DATA09

—

IPUx_CSIx_

DATA10

—

IPUx_CSIx_

DATA11

—

0

IPUx_CSIx_

DATA12

B[0], G[3] R[2],G[4],B[2] R/G/B[4]

B[1], G[4] R[3],G[5],B[3] R/G/B[5]

B[2], G[5] R[4],G[0],B[4] R/G/B[0]

B[3], R[0] R[0],G[1],B[0] R/G/B[1]

B[4], R[1] R[1],G[2],B[1] R/G/B[2]

G[0], R[2] R[2],G[3],B[2] R/G/B[3]

G[1], R[3] R[3],G[4],B[3] R/G/B[4]

G[2], R[4] R[4],G[5],B[4] R/G/B[5]

R/G/B[0]

R/G/B[1]

R/G/B[2]

R/G/B[3]

R/G/B[4]

R/G/B[5]

R/G/B[6]

R/G/B[7]

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

Y/C[5]

Y/C[6]

Y/C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

IPUx_CSIx_

DATA13

IPUx_CSIx_

DATA14

IPUx_CSIx_

DATA15

IPUx_CSIx_

DATA16

IPUx_CSIx_

DATA17

IPUx_CSIx_

DATA18

IPUx_CSIx_

DATA19

1

IPU2_CSIx stands for IPU2_CSI1 or IPU2_CSI2.

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2

The MSB bits are duplicated on LSB bits implementing color extension.

3

The two MSB bits are duplicated on LSB bits implementing color extension.

4

YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

5

RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

6

YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.

7

YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

8

YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

4.12.10.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.12.10.2.1 BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The

timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the

data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital

blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding

from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal

use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120

two components per cycle are received over the IPU2_CSIx_DATA_EN bus.

4.12.10.2.2 Gated Clock Mode

The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this

mode. See Figure 57.

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Figure 57. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on IPU2_CSIx_VSYNC (all the timings correspond to straight polarity

of the corresponding signals). Then IPU2_CSIx_HSYNC goes to high and hold for the entire line. Pixel

clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel

clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI

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stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the

next frame, the IPU2_CSIx_VSYNC timing repeats.

4.12.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”)

except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 58). All incoming pixel clocks

are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive

(states low) until valid data is going to be transmitted over the bus.

Start of Frame

nth frame

n+1th frame

IPU2_CSIx_VSYNC

IPU2_CSIx_PIX_CLK

invalid

IPU2_CSIx_DATA_EN[19:0]

1st byte

Figure 58. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 58 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered

IPU2_CSIx_VSYNC; active-high/low IPU2_CSIx_HSYNC; and rising/falling-edge triggered

IPU2_CSIx_PIX_CLK.

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4.12.10.3 Electrical Characteristics

Figure 59 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not

generated by the IPU. Table 57 lists the sensor interface timing characteristics.

IPUx_CSIx_PIX_CLK

(Sensor Output)

1/IP1

IP2

IP3

IPUx_CSIx_DATA_EN,

IPUx_CSIx_VSYNC,

IPUx_CSIx_HSYNC

Figure 59. Sensor Interface Timing Diagram

Table 57. Sensor Interface Timing Characteristics

ID

Parameter

Symbol

Min

Max

Unit

IP1

IP2

IP3

—

Sensor output (pixel) clock frequency

Data and control setup time

Data and control holdup time

Vsync to Hsync

Fpck

Tsu

0.01

2

180

—

MHz

ns

Thd

1

—

ns

Tv-h

Tpulse

Tv-d

1/Fpck

—

ns

—

Vsync and Hsync pulse width

Vsync to first data

—

ns

—

ns

4.12.10.4 IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 58 defines the mapping of the Display

Interface Pins used during various supported video interface formats.

Table 58. Video Signal Cross-Reference

i.MX 6Dual/6Quad

LCD

RGB/TV Signal Allocation (Example)

Comment^1,2

RGB,

Signal

Name

Port Name

(x = 0, 1)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

(General)

IPUx_DISPx_DAT00

IPUx_DISPx_DAT01

IPUx_DISPx_DAT02

IPUx_DISPx_DAT03

IPUx_DISPx_DAT04

DAT[0]

DAT[1]

DAT[2]

DAT[3]

DAT[4]

B[0]

B[1]

B[2]

B[3]

B[4]

B[0]

B[1]

B[2]

B[3]

B[4]

B[0]

B[1]

B[2]

B[3]

B[4]

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

C[0]

C[1]

C[2]

C[3]

C[4]

C[0]

C[1]

C[2]

C[3]

C[4]

—

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Table 58. Video Signal Cross-Reference (continued)

LCD

i.MX 6Dual/6Quad

RGB/TV Signal Allocation (Example)

RGB,

Comment^1,2

Port Name

(x = 0, 1)

Signal

Name

(General)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

IPUx_DISPx_DAT05

IPUx_DISPx_DAT06

IPUx_DISPx_DAT07

IPUx_DISPx_DAT08

IPUx_DISPx_DAT09

IPUx_DISPx_DAT10

IPUx_DISPx_DAT11

IPUx_DISPx_DAT12

IPUx_DISPx_DAT13

IPUx_DISPx_DAT14

IPUx_DISPx_DAT15

IPUx_DISPx_DAT16

IPUx_DISPx_DAT17

IPUx_DISPx_DAT18

IPUx_DISPx_DAT19

IPUx_DISPx_DAT20

IPUx_DISPx_DAT21

IPUx_DISPx_DAT22

IPUx_DISPx_DAT23

IPUx_DIx_DISP_CLK

DAT[5]

DAT[6]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

—

B[5]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

—

B[5]

B[6]

Y/C[5]

Y/C[6]

Y/C[7]

—

C[5]

C[6]

C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

—

C[5]

C[6]

C[7]

C[8]

C[9]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

—

DAT[7]

B[7]

DAT[8]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

PixCLK

DAT[9]

—

DAT[10]

DAT[11]

DAT[12]

DAT[13]

DAT[14]

DAT[15]

DAT[16]

DAT[17]

DAT[18]

DAT[19]

DAT[20]

DAT[21]

DAT[22]

DAT[23]

—

IPUx_DIx_PIN01

IPUx_DIx_PIN02

IPUx_DIx_PIN03

—

May be required for anti-tearing

HSYNC

VSYNC

—

VSYNC out

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Table 58. Video Signal Cross-Reference (continued)

LCD

RGB/TV Signal Allocation (Example)

RGB,

Comment^1,2

Port Name

(x = 0, 1)

Signal

Name

(General)

16-bit 18-bit 24 Bit

8-bit

16-bit 20-bit

RGB RGB RGB YCrCb³YCrCb YCrCb

IPUx_DIx_PIN04

IPUx_DIx_PIN05

IPUx_DIx_PIN06

IPUx_DIx_PIN07

IPUx_DIx_PIN08

IPUx_DIx_D0_CS

IPUx_DIx_D1_CS

—

Additional frame/row synchronous

signals with programmable timing

—

Alternate mode of PWM output for

contrast or brightness control

IPUx_DIx_PIN11

IPUx_DIx_PIN12

IPUx_DIx_PIN13

IPUx_DIx_PIN14

IPUx_DIx_PIN15

IPUx_DIx_PIN16

IPUx_DIx_PIN17

—

Register select signal

Optional RS2

—

DRDY/DV

Data validation/blank, data enable

—

Q

Additional data synchronous

signals with programmable

features/timing

1

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2

Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.

• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.

This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

3

NOTE

Table 58 provides information for both the DISP0 and DISP1 ports.

However, DISP1 port has reduced pinout depending on IOMUXC

configuration and therefore may not support all configurations. See the

IOMUXC table for details.

4.12.10.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls.

4.12.10.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control

has a permanent period and a permanent waveform.

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There are special physical outputs to provide synchronous controls:

•

The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

•

The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counter system can be found in the IPU

chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.12.10.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to

additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

•

The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.

The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any other data-oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data on the bus, a

new internal start (local start point) is generated. The signal generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.12.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.12.10.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

HSYNC—Horizontal synchronization

VSYNC—Vertical synchronization

DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

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4.12.10.6.2 LCD Interface Functional Description

Figure 60 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DI_CLK internal DI clock is used for calculation of other controls.

IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

•

HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPUx_DIx_PIN03 is used as VSYNC.)

•

DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

VSYNC

HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1 LINE n

HSYNC

DRDY

1

2

3

m–1

m

IPP_DISP_CLK

IPP_DATA

Figure 60. Interface Timing Diagram for TFT (Active Matrix) Panels

4.12.10.6.3 TFT Panel Sync Pulse Timing Diagrams

Figure 61 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All the parameters shown in the figure are programmable. All controls are started by

corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of

the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.

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IP13o

IP7

IP5

IP5o

IP8o

IP8

DI clock

IPP_DISP_CLK

VSYNC

HSYNC

DRDY

IPP_DATA

Dn

D0

D1

IP9o

IP10

IP9

IP6

Figure 61. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 62 depicts the vertical timing (timing of one frame). All parameters shown in the figure are

programmable.

End of frame

Start of frame

IP13

VSYNC

HSYNC

DRDY

IP15

IP14

IP12

Figure 62. TFT Panels Timing Diagram—Vertical Sync Pulse

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Table 59 shows timing characteristics of signals presented in Figure 61 and Figure 62.

Table 59. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID

Parameter

Symbol

Value

Description

Unit

IP5

IP6

Display interface clock period Tdicp

Display pixel clock period

(see¹)

Display interface clock IPP_DISP_CLK

ns

Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display,

× Tdicp

DISP_CLK_PER_PIXEL—number of pixel

components in one pixel (1.n).

The DISP_CLK_PER_PIXEL is virtual

parameter to define display pixel clock

period.

TheDISP_CLK_PER_PIXELisreceivedby

DC/DI one access division to n

components.

IP7

Screen width time

Tsw

(SCREEN_WIDTH)

SCREEN_WIDTH—screen width in,

interface clocks. horizontal blanking

included.

ns

× Tdicp

The SCREEN_WIDTH should be built by

suitable DI’s counter².

IP8

IP9

HSYNC width time

Thsw

Thbi1

(HSYNC_WIDTH)

HSYNC_WIDTH—Hsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter.

ns

Horizontal blank interval 1

^BGXP× Tdicp

BGXP—width of a horizontal blanking

before a first active data in a line (in

interface clocks). The BGXP should be built

by suitable DI’s counter.

IP10 Horizontal blank interval 2

IP12 Screen height

Thbi2

Tsh

(SCREEN_WIDTH –

^{BGXP – FW)}× Tdicp

Width a horizontal blanking after a last

active data in a line (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s

counter.

ns

(SCREEN_HEIGHT)

SCREEN_HEIGHT—screen heightin lines ns

with blanking.

The SCREEN_HEIGHT is a distance

between 2 VSYNCs.

× Tsw

The SCREEN_HEIGHT should be built by

suitable DI’s counter.

IP13 VSYNC width

Tvsw

Tvbi1

Tvbi2

VSYNC_WIDTH

VSYNC_WIDTH—Vsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter.

ns

IP14 Vertical blank interval 1

IP15 Vertical blank interval 2

^BGYP× Tsw

BGYP—width of first Vertical

blanking interval in line. The BGYP should

be built by suitable DI’s counter.

(SCREEN_HEIGHT –

^{BGYP – FH)}× Tsw

Width of second vertical blanking interval in ns

line. The FH should be built by suitable DI’s

counter.

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Table 59. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID

Parameter

Symbol

Value

Description

Unit

IP5o Offset of IPP_DISP_CLK

Todicp

DISP_CLK_OFFSET—offset of

IPP_DISP_CLK edges from local start

^{point, in DI_CLK}×2

ns

^DISP_×^CLT^Kd^_ic^Olk^FFSET

(0.5 DI_CLK Resolution).

Defined by DISP_CLK counter.

IP13o Offset of VSYNC

Tovs

Tohs

VSYNC_OFFSET

VSYNC_OFFSET—offset of Vsync edges

from a local start point, when a Vsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution). The

VSYNC_OFFSET should be built by

suitable DI’s counter.

ns

× Tdiclk

IP8o Offset of HSYNC

IP9o Offset of DRDY

HSYNC_OFFSET

HSYNC_OFFSET—offset of Hsync edges

from a local start point, when a Hsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution). The

HSYNC_OFFSET should be built by

suitable DI’s counter.

× Tdiclk

Todrdy

DRDY_OFFSET

DRDY_OFFSET—offset of DRDY edges

from a suitable local start point, when a

corresponding data has been set on the

^{bus, in DI_CLK}×2

× Tdiclk

(0.5 DI_CLK Resolution).

The DRDY_OFFSET should be built by

suitable DI’s counter.

1

Display interface clock period immediate value.









DISP_CLK_PERIOD

----------------------------------------------------

DISP_CLK_PERIOD

DI_CLK_PERIOD

T

×

,

for integer ----------------------------------------------------

diclk

DI_CLK_PERIOD

Tdicp =

DISP_CLK_PERIOD



----------------------------------------------------

+ 0.5 0.5 , for fractional ----------------------------------------------------

DISP_CLK_PERIOD

DI_CLK_PERIOD



T

floor

 diclk



DI_CLK_PERIOD



DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

DISP_CLK_PERIOD

----------------------------------------------------

Tdicp = T

×

DI_CLK_PERIOD

diclk

2

DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the

counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by

corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between

HSYNCs is a SCREEN_WIDTH.

The maximum accuracy of UP/DOWN edge of controls is:

Accuracy = (0.5 × T

) 0.62ns

diclk

The maximum accuracy of UP/DOWN edge of IPP_DISP_DATA is:

Accuracy = T

diclk

0.62ns

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are register-controlled.

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Figure 63 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and

DISP_CLK_UP parameters are register-controlled. Table 60 lists the synchronous display interface timing

characteristics.

IP20o IP20

VSYNC

HSYNC

DRDY

other controls

IPP_DISP_CLK

Tdicd

Tdicu

IP18

IPP_DATA

IP16

IP17

IP19

local start point

Figure 63. Synchronous Display Interface Timing Diagram—Access Level

Table 60. Synchronous Display Interface Timing Characteristics (Access Level)

ID

Parameter

Symbol

Min

Typ¹

Max

Unit

IP16

Display interface clock low Tckl

time

Tdicd-Tdicu-1.24

Tdicd²-Tdicu³

Tdicd-Tdicu+1.24

ns

IP17

Display interface clock

high time

Tckh

Tdicp-Tdicd+Tdicu-1.24 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.2

ns

IP18

IP19

IP20o

Data setup time

Data holdup time

Tdsu

Tdhd

Tocsu

Tdicd-1.24

Tdicu

—

ns

Tdicp-Tdicd-1.24

Tocsu-1.24

Tdicp-Tdicu

Tocsu

Control signals offset

times (defined for each

pin)

Tocsu+1.24

IP20

Control signals setup time Tcsu

to display interface clock

(defined for each pin)

Tdicd-1.24-Tocsu%Tdicp Tdicu

—

ns

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display interface clock down time

2 × DISP_CLK_DOWN

1

2







-----------------------------------------------------------

Tdicd = -- T

 diclk

× ceil

DI_CLK_PERIOD

3

Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

2 × DISP_CLK_UP

1

2







------------------------------------------------

Tdicu = -- T

 diclk

× ceil

DI_CLK_PERIOD

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4.12.11 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”

Table 61. LVDS Display Bridge (LDB) Electrical Specification

Parameter

Symbol

Test Condition

100 Ω Differential load

Min

Max

Units

Differential Voltage Output Voltage

Output Voltage High

V_OD

Voh

250

450

1.6

mV

V

100 Ω differential load

(0 V Diff—Output High Voltage static)

1.25

Output Voltage Low

Offset Static Voltage

Vol

100 Ω differential load

0.9

1.25

V

(0 V Diff—Output Low Voltage static)

V_OS

Two 49.9 Ω resistors in series between N-P

terminal, with output in either Zero or One state, the

voltage measured between the 2 resistors.

1.15

1.375

VOS Differential

V_OSDIFFDifference in V_OSbetween a One and a Zero state

ISA ISB With the output common shorted to GND

-50

-24

247

50

24

mV

mA

mV

Output short-circuited to GND

VT Full Load Test

VTLoad 100 Ω Differential load with a 3.74 kΩ load between

454

GND and I/O supply voltage

4.12.12 MIPI D-PHY Timing Parameters

This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,

D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes) and MIPI DSI Version 1.01, and D-PHY

specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for

MIPI display port x2 lanes).

4.12.12.1 Electrical and Timing Information

Table 62. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min Typ

Max Unit

Input DC Specifications—Apply to DSI_CLK_P/_N and DSI_DATA_P/_N Inputs

V_I

Input signal voltage range

Input leakage current

Transient voltage range is limited from -300

mV to 1600 mV

-50

-10

—

1350 mV

V_LEAK

VGNDSH(min) = VI = VGNDSH(max) +

VOH(absmax)

10

mA

Lane module in LP Receive Mode

V_GNDSH

Ground Shift

—

-50

—

50

mV

V

V_OH(absmax)

Maximum transient output

voltage level

1.45

t_voh(absmax)

Maximum transient time

above VOH(absmax)

—

20

ns

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Symbol

Table 62. Electrical and Timing Information (continued)

Parameters

Test Conditions

Min Typ

Max Unit

HS Line Drivers DC Specifications

|V_OD

|

HS Transmit Differential

output voltage magnitude

80 Ω<= RL< = 125 Ω

140

—

200

—

270

10

mV

Δ|V_OD

|

Change in Differential output

voltage magnitude between

logic states

80 Ω<= RL< = 125 Ω

V_CMTX

Steady-state common-mode

output voltage.

80 Ω<= RL< = 125 Ω

150

—

200

—

250

5

mV

ΔV_CMTX(1,0)

Changes in steady-state

common-mode output voltage

between logic states

V_OHHS

Z_OS

HS output high voltage

80 Ω<= RL< = 125 Ω

—

360

mV

Single-ended output

impedance.

—

40

50

62.5

Ω

ΔZ_OS

Single-ended output

impedance mismatch.

—

10

%

LP Line Drivers DC Specifications

V_OL

Output low-level SE voltage

—

-50

1.1

50

1.3

—

mV

V

V_OH

Z_OLP

Output high-level SE voltage

1.2

—

Single-ended output

impedance.

110

Ω

ΔZ_OLP(01-10)

Single-ended output

impedance mismatch driving

opposite level

—

20

5

%

ΔZ_OLP(0-11)

Single-ended output

impedance mismatch driving

same level

HS Line Receiver DC Specifications

V_IDTH

V_IDTL

V_IHHS

V_ILHS

Differential input high voltage

threshold

—

-70

—

70

—

mV

Differential input low voltage

threshold

Single ended input high

voltage

460

—

Single ended input low

voltage

-40

V_CMRXDC

Z_ID

Input common mode voltage

Differential input impedance

—

70

80

—

330

125

mV

Ω

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Table 62. Electrical and Timing Information (continued)

Symbol

Parameters

Test Conditions

Min Typ

Max Unit

LP Line Receiver DC Specifications

V_IL

V_IH

Input low voltage

—

920

25

—

550

—

mV

Input high voltage

Input hysteresis

V_HYST

—

Contention Line Receiver DC Specifications

V_ILF

Input low fault threshold

—

200

—

450

mV

4.12.12.2 D-PHY Signaling Levels

The signal levels are different for differential HS mode and single-ended LP mode. Figure 64 shows both

the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below

the LP low-level input threshold such that LP receiver always detects low on HS signals.

V_OH,MAX

LP

V_OL

V_OH,MIN

V_IH

LP

V_IH

LP Threshold

Region

V_IL

V_OHHS

Max V_OD

V_CMTX,MAX

LP V_IL

HS Vout

Range

HS Vcm

Range

V_GNDSH,MA

V_CMTX,MIN

V_OLHS

Min V_OD

X

LP V_OL

GND

V_GNDSH,MIN

HS Differential Signaling

LP Single-ended Signaling

Figure 64. D-PHY Signaling Levels

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4.12.12.3 HS Line Driver Characteristics

Ideal Single-Ended High Speed Signals

V_DN

V_CMTX= (V_{DP +}V_DN)/2

V_OD(0)

V_OD(1)

V_DP

Ideal Differential High Speed Signals

V_OD(1)

0V

(Differential)

V_OD(0)

V_OD= V_DP- V_DN

Figure 65. Ideal Single-ended and Resulting Differential HS Signals

4.12.12.4 Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

V_OD/2

Δ

V

_OD(SE HS Signals)

Δ

V_DN

V_{OD (1)}

V_{CM TX}

V_OD(0)

V_DP

V

Δ

_OD/2

Static V_CMTX(SE HS Signals)

Δ

V_DN

V_CMTX

V_DP

V_OD(0)

Dynamic V_CMTX(SE HS Signals)

Δ

V_DN

V_{CM TX}

V_DP

Figure 66. Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

4.12.12.5 D-PHY Switching Characteristics

Table 63. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

HS Line Drivers AC Specifications

—

Maximum serial data rate (forward

direction)

On DATAP/N outputs.

80 Ω <= RL <= 125 Ω

80

—

1000

Mbps

F_DDRCLK

P_DDRCLK

DDR CLK frequency

DDR CLK period

On DATAP/N outputs.

40

2

—

500

25

MHz

ns

80 Ω <= RL< = 125 Ω

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Table 63. Electrical and Timing Information (continued)

Symbol

t_CDC

Parameters

DDR CLK duty cycle

Test Conditions

Min

Typ

Max

Unit

t_CDC= t_CPH/ P_DDRCLK

—

50

1

—

%

UI

t_CPH

DDR CLK high time

—

t_CPL

DDR CLK low time

—

1

—

UI

—

DDR CLK / DATA Jitter

Intra-Pair (Pulse) skew

Data to Clock Skew

—

75

0.075

—

ps pk-pk

UI

t_SKEW[PN]

t_SKEW[TX]

t_r

—

0.350

150

—

0.650

0.3UI

15

UI

Differential output signal rise time

Differential output signal fall time

20% to 80%, RL = 50 Ω

—

ps

t_f

—

ps

ΔV_CMTX(HF)

ΔV_CMTX(LF)

Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω

—

mV_rms

mV_p

Common level variation between 50

MHz and 450 MHz

80 Ω<= RL< = 125 Ω

—

25

LP Line Drivers AC Specifications

t_{rlp, flp}

t

Single ended output rise/fall time

15% to 85%, C_L<70 pF

30% to 85%, C_L<70 pF

15% to 85%, C_L<70 pF

—

0

—

25

35

ns

t_reo

—

δV/δt_SR

C_L

Signal slew rate

120

70

mV/ns

pF

Load capacitance

HS Line Receiver AC Specifications

t_SETUP[RX]

t_HOLD[RX]

Data to Clock Receiver Setup time

Clock to Data Receiver Hold time

—

0.15

—

UI

ΔV_CMRX(HF)

Common mode interference beyond

450 MHz

200

mVpp

ΔV_CMRX(LF)

Common mode interference between

50 MHz and 450 MHz

—

-50

—

50

60

mVpp

pF

C_CM

Common mode termination

LP Line Receiver AC Specifications

e_SPIKE

T_MIN

V_INT

f_INT

Input pulse rejection

—

50

—

300

—

Vps

ns

Minimum pulse response

Pk-to-Pk interference voltage

Interference frequency

—

400

—

mV

MHz

450

Model Parameters used for Driver Load switching performance evaluation

C_PAD

Equivalent Single ended I/O PAD

capacitance.

—

1

2

pF

C_PIN

Equivalent Single ended Package +

PCB capacitance.

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Symbol

Table 63. Electrical and Timing Information (continued)

Parameters

Test Conditions

Min

Typ

Max

Unit

L_S

R_S

R_L

Equivalent wire bond series inductance

Equivalent wire bond series resistance

Load Resistance

—

80

—

1.5

0.15

125

nH

Ω

100

Ω

4.12.12.6 High-Speed Clock Timing

CLKp

CLKn

1 Data Bit Time = 1UI

UI_INST(1)

1 Data Bit Time = 1UI

UI_INST(2)

1 DDR Clock Period = UI_INST(1) + UI_INST(2)

Figure 67. DDR Clock Definition

4.12.12.7 Forward High-Speed Data Transmission Timing

The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in

Figure 68:

2EFERENCE 4IME

4_3%450

4_(/,$

ꢋ

ꢀꢅꢆ5)_).34

4_3+%7

#,+P

#,+N

ꢄ 5)_).34

4_#,+P

Figure 68. Data to Clock Timing Definitions

4.12.12.8 Reverse High-Speed Data Transmission Timing

T_TD

NRZ Data

CLKn

CLKp

Clock to Data

Skew

2UI

Figure 69. Reverse High-Speed Data Transmission Timing at Slave Side

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4.12.12.9 Low-Power Receiver Timing

2*T_LPX

e_SPIKE

V_IH

V_IL

Input

e_SPIKE

T_MIN-RX

Output

Figure 70. Input Glitch Rejection of Low-Power Receivers

4.12.13 HSI Host Controller Timing Parameters

This section describes the timing parameters of the HSI Host Controller which are compliant with

High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01.

4.12.13.1 Synchronous Data Flow

Last bit of

frame

First bit of

frame

Last bit of

frame

First bit of

frame

t_NomBit

DATA

FLAG

N-bits Frame

READY

Receiver has

detected the start

of the Frame

Receiver has captured

and stored a complete

Frame

Figure 71. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)

4.12.13.2 Pipelined Data Flow

First bit of

frame

Last bit of

frame

Last bit of

frame

Last bit of

frame

First bit of

frame

t_NomBit

DATA

FLAG

N-bits Frame

READY

E.

Ready

can

D. Ready shall

maintain zero of if

receiver does not

have free space

F. Ready

shall

maintain

its value

G. Ready

can change

C. Ready can change

A Ready can change

B Ready shall not

change to zero

change

Figure 72. Pipelined Data Flow READY Signal Timing (Frame Transmission Mode)

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Electrical Characteristics

4.12.13.3 Receiver Real-Time Data Flow

Last bit of

frame

First bit of

frame

Last bit of

frame

First bit of

frame

t_NomBit

DATA

FLAG

N-bits Frame

READY

Receiver has

detected the start

of the Frame

Receiver has captured a

complete Frame

Figure 73. Receiver Real-Time Data Flow READY Signal Timing

4.12.13.4 Synchronized Data Flow Transmission with Wake

A

B

C

D

A

TX state

DATA

PHY Frame

FLAG

3. First bit

received

6. Receiver

READY

4. Received

frame stored

2. Receiver in active

start state

can no longer

receive date

5. Transmitter

has no more

data to

transmit

WAKE

1. Transmitter has

data to transmit

A

B

C

A

D

RX state

A: Sleep state(non-operational)

B: Wake-up state

C: Active state (full operational)

D: Disable State(No communication ability)

Figure 74. Synchronized Data Flow Transmission with WAKE

4.12.13.5 Stream Transmission Mode Frame Transfer

Channel

Description

bits

its

Payload Data B

DATA

FLAG

Complete N-bits Frame

READY

Figure 75. Stream Transmission Mode Frame Transfer (Synchronized Data Flow)

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4.12.13.6 Frame Transmission Mode (Synchronized Data Flow)

Frame

Channel

start bit

its

Payload Data B

Description

bits

DATA

FLAG

Complete N-bits Frame

READY

Figure 76. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)

4.12.13.7 Frame Transmission Mode (Pipelined Data Flow)

Frame

Channel

start bit

Data Bits

Payload

Description

bits

DATA

FLAG

Complete N-bits Frame

READY

Figure 77. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)

4.12.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load

Table 64. DATA and FLAG Timing

Parameter

Description

1 Mbit/s 100 Mbit/s

t_{Bit, nom}

Nominal bit time

1000 ns

2 ns

10 ns

2 ns

t_{Rise, min}and t_{Fall, min}Minimum allowed rise and fall time

t_{TxToRxSkew, maxfq}Maximum skew between transmitter and receiver package pins

50 ns

0.5 ns

4 ns

t_{EageSepTx, min}

Minimum allowed separation of signal transitions at transmitter package pins,

including all timing defects, for example, jitter and skew, inside the transmitter.

400 ns

t_{EageSepRx, min}

Minimum separation of signal transitions, measured at the receiver package pins, 350 ns

including all timing defects, for example, jitter and skew, inside the receiver.

3.5 ns

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4.12.13.9 DATA and FLAG Signal Timing

t_EdgeSepTx

80%

50%

DATA

(TX)

t_Rise

Note2

Note1

80%

50%

FLAG

(TX)

20%

t_Bit

t _Fall

t_TxToRxSkew

t_EdgeSepRx

80%

50%

DATA

(RX)

Note1

Note2

50%

FLAG

(RX)

20%

Figure 78. DATA and FLAG Signal Timing

4.12.14 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

4.12.14.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200 Ω. 1ꢀ precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.12.15 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 79 depicts the timing of the PWM, and Table 65 lists the PWM timing parameters.

PWMn_OUT

Figure 79. PWM Timing

Table 65. PWM Output Timing Parameters

ID

Parameter

Min

Max

Unit

—

P1

P2

PWM Module Clock Frequency

PWM output pulse width high

PWM output pulse width low

0

ipg_clk

—

MHz

ns

15

—

ns

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4.12.16 SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.12.16.1 Transmitter and Receiver Characteristics

The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA

specifications.

NOTE

The tables in the following sections indicate any exceptions to the SATA

specification or aspects of the SATA PHY that exceed the standard, as well

as provide information about parameters not defined in the standard.

The following subsections provide values obtained from a combination of simulations and silicon

characterization.

4.12.16.1.1 SATA PHY Transmitter Characteristics

Table 66 provides specifications for SATA PHY transmitter characteristics.

Table 66. SATA PHY Transmitter Characteristics

Parameters

Symbol

Min

Typ

Max

Unit

Transmit common mode voltage

V_CTM

—

0.4

—

0.6

0.5

V

Transmitter pre-emphasis accuracy (measured

change in de-emphasized bit)

–0.5

dB

4.12.16.1.2 SATA PHY Receiver Characteristics

Table 67 provides specifications for SATA PHY receiver characteristics.

Table 67. SATA PHY Receiver Characteristics

Parameters

Symbol

Min

Typ

Max

Unit

Minimum Rx eye height (differential peak-to-peak)

Tolerance

V_{MIN_RX_EYE_HEIGHT}

PPM

175

—

mV

–400

400

ppm

4.12.16.2 SATA_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 191 Ω. 1ꢀ precision resistor

on SATA_REXT pad to ground.

Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an

internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT

pin. The calibration register value is then supplied to all Tx and Rx termination resistors.

During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the

external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.

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4.12.17 SCAN JTAG Controller (SJC) Timing Parameters

Figure 80 depicts the SJC test clock input timing. Figure 81 depicts the SJC boundary scan timing.

Figure 82 depicts the SJC test access port. Figure 83 depicts the JTAG_TRST_B timing. Signal

parameters are listed in Table 68.

SJ1

SJ2

VM

SJ2

VM

JTAG_TCK

(Input)

VIH

VIL

SJ3

Figure 80. Test Clock Input Timing Diagram

JTAG_TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 81. Boundary Scan (JTAG) Timing Diagram

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JTAG_TCK

(Input)

VIH

SJ9

VIL

SJ8

Input Data Valid

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 82. Test Access Port Timing Diagram

JTAG_TCK

(Input)

SJ13

JTAG_TRST_B

(Input)

SJ12

Figure 83. JTAG_TRST_B Timing Diagram

Table 68. JTAG Timing

All Frequencies

ID

Parameter^1,2

Unit

Min

Max

1

SJ0

SJ1

SJ2

SJ3

SJ4

SJ5

SJ6

SJ7

SJ8

JTAG_TCK frequency of operation 1/(3xT_DC

)

0.001

45

22.5

—

22

—

3

MHz

ns

JTAG_TCK cycle time in crystal mode

2

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

ns

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

5

—

40

—

ns

24

—

ns

—

ns

5

ns

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Table 68. JTAG Timing (continued)

Parameter^1,2

All Frequencies

ID

Unit

Min

Max

SJ9

JTAG_TMS, JTAG_TDI data hold time

25

—

44

—

ns

SJ10

SJ11

SJ12

SJ13

JTAG_TCK low to JTAG_TDO data valid

JTAG_TCK low to JTAG_TDO high impedance

JTAG_TRST_B assert time

—

100

40

JTAG_TRST_B set-up time to JTAG_TCK low

1

2

T

= target frequency of SJC

DC

V_M= mid-point voltage

4.12.18 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 69 and Figure 84 and Figure 85 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

Table 69. SPDIF Timing Parameters

Timing Parameter Range

Parameter

Symbol

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

ns

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

ns

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

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srckp

srckpl

V_M

srckph

V_M

SPDIF_SR_CLK

(Output)

Figure 84. SPDIF_SR_CLK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 85. SPDIF_ST_CLK Timing Diagram

4.12.19 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 70.

Table 70. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

AUDMUX port 6

AUDMUX port 7

SSI 1

SSI 2

AUD3

AUD4

AUD5

AUD6

SSI 3

Internal

External – AUD3 I/O

External – EIM or CSPI1 I/O through IOMUXC

External – EIM or SD1 I/O through IOMUXC

External – EIM or DISP2 through IOMUXC

Internal

NOTE

The terms WL and BL used in the timing diagrams and tables refer to Word

Length (WL) and Bit Length (BL).

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4.12.19.1 SSI Transmitter Timing with Internal Clock

Figure 86 depicts the SSI transmitter internal clock timing and Table 71 lists the timing parameters for

the SSI transmitter internal clock.

.

SS1

SS5

SS4

SS3

SS2

AUDx_TXC

(Output)

SS8

SS6

AUDx_TXFS (bl)

(Output)

SS10

SS12

SS14

SS17

AUDx_TXFS (wl)

(Output)

SS15

SS16

SS18

AUDx_TXD

(Output)

SS43

SS42

SS19

AUDx_RXD

(Input)

Note: AUDx_RXD input in synchronous mode only

Figure 86. SSI Transmitter Internal Clock Timing Diagram

Table 71. SSI Transmitter Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock low period

SS4

SS6

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

15.0

6.0

SS8

—

SS10

SS12

SS14

SS15

SS16

SS17

SS18

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

—

AUDx_TXC/AUDx_RXC Internal AUDx_TXFS rise time

AUDx_TXC/AUDx_RXC Internal AUDx_TXFS fall time

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

—

6.0

—

15.0

—

AUDx_TXC high to AUDx_TXD high impedance

—

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Table 71. SSI Transmitter Timing with Internal Clock (continued)

ID

Parameter

Min

Max

Unit

Synchronous Internal Clock Operation

SS42

SS43

AUDx_RXD setup before AUDx_TXC falling

AUDx_RXD hold after AUDx_TXC falling

10.0

0.0

—

ns

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is the same as that of transmit data (for example, during AC97

mode of operation).

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4.12.19.2 SSI Receiver Timing with Internal Clock

Figure 87 depicts the SSI receiver internal clock timing and Table 72 lists the timing parameters for the

receiver timing with the internal clock.

SS1

SS3

SS5

SS4

SS2

AUDx_TXC

(Output)

SS9

SS7

AUDx_TXFS (bl)

(Output)

SS11

SS13

AUDx_TXFS (wl)

(Output)

SS20

SS21

AUDx_RXD

(Input)

SS51

SS50

SS47

SS49

SS48

AUDx_RXC

(Output)

Figure 87. SSI Receiver Internal Clock Timing Diagram

Table 72. SSI Receiver Timing with Internal Clock

ID

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

SS2

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

SS3

6.0

—

SS4

36.0

—

SS5

6.0

15.0

—

SS7

—

SS9

—

SS11

SS13

SS20

SS21

—

10.0

0.0

—

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Table 72. SSI Receiver Timing with Internal Clock (continued)

ID

Parameter

Oversampling Clock Operation

Min

Max

Unit

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

15.04

6.0

—

ns

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

3.0

—

6.0

—

3.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

AUDx_TXC and AUDx_RXC refer to the Transmit and Receive

sections of the SSI.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.12.19.3 SSI Transmitter Timing with External Clock

Figure 88 depicts the SSI transmitter external clock timing and Table 73 lists the timing parameters for

the transmitter timing with the external clock.

SS22

SS25

SS26

SS23

SS24

AUDx_TXC

(Input)

SS27

SS29

AUDx_TXFS (bl)

(Input)

SS33

SS31

AUDx_TXFS (wl)

(Input)

SS39

SS38

SS37

AUDx_TXD

(Output)

SS45

SS44

AUDx_RXD

(Input)

Note: AUDx_RXD Input in Synchronous mode only

SS46

Figure 88. SSI Transmitter External Clock Timing Diagram

Table 73. SSI Transmitter Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

SS39

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

6.0

—

36.0

—

6.0

15.0

—

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

AUDx_TXC high to AUDx_TXD high impedance

–10.0

10.0

–10.0

10.0

—

15.0

—

15.0

—

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Table 73. SSI Transmitter Timing with External Clock (continued)

ID

Parameter

Min

Max

Unit

Synchronous External Clock Operation

SS44

SS45

SS46

AUDx_RXD setup before AUDx_TXC falling

AUDx_RXD hold after AUDx_TXC falling

AUDx_RXD rise/fall time

10.0

2.0

—

ns

6.0

NOTE

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

•

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

AUDx_TXC and AUDx_RXC refer to the Transmit and Receive

sections of the SSI.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

4.12.19.4 SSI Receiver Timing with External Clock

Figure 89 depicts the SSI receiver external clock timing and Table 74 lists the timing parameters for the

receiver timing with the external clock.

SS22

SS24

SS26

SS25

SS23

SS28

AUDx_TXC

(Input)

SS30

AUDx_TXFS (bl)

(Input)

SS32

SS35

SS34

AUDx_TXFS (wl)

(Input)

SS41

SS36

SS40

AUDx_RXD

(Input)

Figure 89. SSI Receiver External Clock Timing Diagram

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Table 74. SSI Receiver Timing with External Clock

ID

Parameter

Min

Max

Unit

External Clock Operation

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

AUDx_TXC/AUDx_RXC clock period

81.4

36

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

6.0

—

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

36

—

6.0

15.0

—

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_TXC/AUDx_RXC External AUDx_TXFS rise time

AUDx_TXC/AUDx_RXC External AUDx_TXFS fall time

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

–10

10

–10

10

—

15.0

—

6.0

—

10

2

—

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

AUDx_TXC and AUDx_RXC refer to the Transmit and Receive

sections of the SSI.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.12.20 UART I/O Configuration and Timing Parameters

4.12.20.1 UART RS-232 I/O Configuration in Different Modes

The i.MX 6Dual/6Quad UART interfaces can serve both as DTE or DCE device. This can be configured

by the DCEDTE control bit (default 0 – DCE mode). Table 75 shows the UART I/O configuration based

on the enabled mode.

Table 75. UART I/O Configuration vs. Mode

DTE Mode

Description

DCE Mode

Description

Port

Direction

UARTx_RTS_B

UARTx_CTS_B

UARTx_DTR_B

UARTx_DSR_B

UARTx_DCD_B

UARTx_RI_B

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Input

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Output

Input

Output

Input

UARTx_TX_DATA

UARTx_RX_DATA

Input

Output

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4.12.20.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.12.20.2.1 UART Transmitter

Figure 90 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit

format. Table 76 lists the UART RS-232 serial mode transmit timing characteristics.

POSSIBLE

PARITY

UA1

Bit 3

BIT

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 90. UART RS-232 Serial Mode Transmit Timing Diagram

Table 76. RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Transmit Bit Time

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA1

t_Tbit

1/F_{baud_rate}¹– T_{ref_clk}

—

1

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

2

4.12.20.2.2 UART Receiver

Figure 91 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 77 lists

serial mode receive timing characteristics.

POSSIBLE

PARITY

UA2

Bit 3

BIT

Start

Bit

UARTx_RX_DATA

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 91. UART RS-232 Serial Mode Receive Timing Diagram

Table 77. RS-232 Serial Mode Receive Timing Parameters

ID

Parameter

Receive Bit Time¹

Symbol

Min

Max

Unit

2

UA2

t_Rbit

1/F_{baud_rate}

–

1/F_{baud_rate}

+

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate})

1

2

The UART receiver can tolerate 1/(16 × F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 × F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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4.12.20.2.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

Figure 92 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 78 lists

the transmit timing characteristics.

UA3

UA4

UA3

UARTx_TX_DATA

(output)

Start

Bit

STOP

BIT

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 92. UART IrDA Mode Transmit Timing Diagram

Table 78. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

2

UA3 Transmit Bit Time in IrDA mode

UA4 Transmit IR Pulse Duration

t_TIRbit

1/F_{baud_rate}¹– T_{ref_clk}

1/F_{baud_rate}+ T_{ref_clk}

—

t_TIRpulse(3/16) × (1/F_{baud_rate}) – T_{ref_clk}

(3/16) × (1/F_{baud_rate}) + T_{ref_clk}

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

UART IrDA Mode Receiver

Figure 93 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 79 lists

the receive timing characteristics.

UA6

UA5

UARTx_RX_DATA

(input)

STOP

BIT

Start

Bit

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 93. UART IrDA Mode Receive Timing Diagram

Table 79. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}

Unit

2

UA5 Receive Bit Time¹in IrDA mode

t_RIRbit

1/F_{baud_rate}

–

+

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate}

)

UA6 Receive IR Pulse Duration

t_RIRpulse

1.41 μs

(5/16) × (1/F_{baud_rate}

)

—

1

2

The UART receiver can tolerate 1/(16 × F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 × F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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4.12.21 USB HSIC Timings

This section describes the electrical information of the USB HSIC port.

NOTE

HSIC is a DDR signal. The following timing specification is for both rising

and falling edges.

4.12.21.1 Transmit Timing

Tstrobe

USB_H_STROBE

Todelay

USB_H_DATA

Figure 94. USB HSIC Transmit Waveform

Table 80. USB HSIC Transmit Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.166

550

4.167

1350

2

ns

ps

—

Todelay data output delay time

Measured at 50% point

Averaged from 30% – 70% points

Tslew

strobe/data rising/falling time

0.7

V/ns

4.12.21.2 Receive Timing

Tstrobe

USB_H_STROBE

USB_H_DATA

Thold

Tsetup

Figure 95. USB HSIC Receive Waveform

1

Table 81. USB HSIC Receive Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.166

300

365

0.7

4.167

—

ns

ps

—

Thold

Tsetup

Tslew

data hold time

Measured at 50% point

data setup time

—

ps

Measured at 50% point

strobe/data rising/falling time

2

V/ns

Averaged from 30% – 70% points

1

The timings in the table are guaranteed when:

—AC I/O voltage is between 0.9x to 1x of the I/O supply

—DDR_SEL configuration bits of the I/O are set to (10)b

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4.12.22 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision

2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB

Revision 2.0 Specification is not applicable to Host port).

•

USB ENGINEERING CHANGE NOTICE

— Title: 5V Short Circuit Withstand Requirement Change

— Applies to: Universal Serial Bus Specification, Revision 2.0

Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

USB ENGINEERING CHANGE NOTICE

•

— Title: Pull-up/Pull-down resistors

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

•

— Title: Suspend Current Limit Changes

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

— Title: USB 2.0 Phase Locked SOFs

— Applies to: Universal Serial Bus Specification, Revision 2.0

On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

— Revision 2.0 plus errata and ecn June 4, 2010

Battery Charging Specification (available from USB-IF)

— Revision 1.2, December 7, 2010

•

— Portable device only

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Boot Mode Configuration

5 Boot Mode Configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot Mode Configuration Pins

Table 82 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see i.MX

6Dual/6Quadthe System Boot chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

Table 82. Fuses and Associated Pins Used for Boot

Direction at Reset

eFuse Name

Boot Mode Selection

BOOT_MODE1

BOOT_MODE0

Input

Boot Mode Selection

Boot Options¹

EIM_DA0

EIM_DA1

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_A16

EIM_A17

EIM_A18

Input

BOOT_CFG1[0]

BOOT_CFG1[1]

BOOT_CFG1[2]

BOOT_CFG1[3]

BOOT_CFG1[4]

BOOT_CFG1[5]

BOOT_CFG1[6]

BOOT_CFG1[7]

BOOT_CFG2[0]

BOOT_CFG2[1]

BOOT_CFG2[2]

BOOT_CFG2[3]

BOOT_CFG2[4]

BOOT_CFG2[5]

BOOT_CFG2[6]

BOOT_CFG2[7]

BOOT_CFG3[0]

BOOT_CFG3[1]

BOOT_CFG3[2]

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Boot Mode Configuration

Table 82. Fuses and Associated Pins Used for Boot (continued)

Direction at Reset

eFuse Name

EIM_A19

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_WAIT

EIM_LBA

EIM_EB0

EIM_EB1

EIM_RW

EIM_EB2

EIM_EB3

Input

BOOT_CFG3[3]

BOOT_CFG3[4]

BOOT_CFG3[5]

BOOT_CFG3[6]

BOOT_CFG3[7]

BOOT_CFG4[0]

BOOT_CFG4[1]

BOOT_CFG4[2]

BOOT_CFG4[3]

BOOT_CFG4[4]

BOOT_CFG4[5]

BOOT_CFG4[6]

BOOT_CFG4[7]

1

Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power

Up. These are special I/O lines that control the boot up configuration during product development. In production,

the boot configuration can be controlled by fuses.

5.2

Boot Devices Interfaces Allocation

Table 83 lists the interfaces that can be used by the boot process in accordance with the specific boot

mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

Table 83. Interfaces Allocation During Boot

Interface

IP Instance

Allocated Pads During Boot

Comment

SPI

ECSPI-1

EIM_D17, EIM_D18, EIM_D16, EIM_EB2, EIM_D19,

EIM_D24, EIM_D25

—

SPI

EIM

ECSPI-2

ECSPI-3

ECSPI-4

ECSPI-5

EIM

CSI0_DAT10, CSI0_DAT9, CSI0_DAT8, CSI0_DAT11,

EIM_LBA, EIM_D24, EIM_D25

—

DISP0_DAT2, DISP0_DAT1, DISP0_DAT0,

DISP0_DAT3,DISP0_DAT4,DISP0_DAT5,DISP0_DAT6

EIM_D22, EIM_D28, EIM_D21, EIM_D20, EIM_A25,

EIM_D24, EIM_D25

SD1_DAT0, SD1_CMD, SD1_CLK, SD1_DAT1,

SD1_DAT2, SD1_DAT3, SD2_DAT3

EIM_DA[15:0], EIM_D[31:16], CSI0_DAT[19:4],

CSI0_DATA_EN, CSI0_VSYNC

Used for NOR, OneNAND boot

Only CS0 is supported

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Boot Mode Configuration

Table 83. Interfaces Allocation During Boot (continued)

Allocated Pads During Boot

Interface

IP Instance

Comment

NAND Flash

GPMI

NANDF_CLE, NANDF_ALE, NANDF_WP_B,

SD4_CMD, SD4_CLK, NANDF_RB0, SD4_DAT0,

NANDF_CS0, NANDF_CS1, NANDF_CS2,

NANDF_CS3, NANDF_D[7:0]

8 bit

Only CS0 is supported

SD/MMC

USDHC-1

USDHC-2

USDHC-3

USDHC-4

SD1_CLK, SD1_CMD,SD1_DAT0, SD1_DAT1,

SD1_DAT2, SD1_DAT3, NANDF_D0, NANDF_D1,

NANDF_D2, NANDF_D3, KEY_COL1

1, 4, or 8 bit

SD2_CLK, SD2_CMD, SD2_DAT0, SD2_DAT1,

SD2_DAT2, SD2_DAT3, NANDF_D4, NANDF_D5,

NANDF_D6, NANDF_D7, KEY_ROW1

1, 4, or 8 bit

SD3_CLK, SD3_CMD, SD3_DAT0, SD3_DAT1,

SD3_DAT2, SD3_DAT3, SD3_DAT4, SD3_DAT5,

SD3_DAT6, SD3_DAT7, GPIO_18

1, 4, or 8 bit

SD4_CLK, SD4_CMD, SD4_DAT0, SD4_DAT1,

SD4_DAT2, SD4_DAT3, SD4_DAT4, SD4_DAT5,

SD4_DAT6, SD4_DAT7, NANDF_CS1

1, 4, or 8 bit

I2C

I2C-1

I2C-2

I2C-3

EIM_D28, EIM_D21

EIM_D16, EIM_EB2

EIM_D18, EIM_D17

—

I2C

SATA

SATA_PHY SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,

SATA_REXT

USB

USB-OTG

PHY

USB_OTG_DP

USB_OTG_DN

USB_OTG_VBUS

—

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Package Information and Contact Assignments

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1

Signal Naming Convention

The signal names of the i.MX6 series of products are standardized to align the signal names within the

family and across the documentation. Benefits of this standardization are as follows:

•

Signal names are unique within the scope of an SoC and within the series of products

Searches will return all occurrences of the named signal

Signal names are consistent between i.MX 6 series products implementing the same modules

The module instance is incorporated into the signal name

This standardization applies only to signal names. The ball names are preserved to prevent the need to

change schematics, BSDL models, IBIS models, and so on.

Throughout this document, the signal names are used except where referenced as a ball name (such as the

Functional Contact Assignments table, Ball Map table, and so on). A master list of signal names is in the

document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be used to map the signal

names used in older documentation to the standardized naming conventions.

6.2

12 x 12 mm Package on Package (PoP) Information

This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid

location) for the 12 x 12 mm, 0.4 mm pitch PoP package.

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Package Information and Contact Assignments

6.2.1

Case PoP, 0.4 mm Pitch, 12 x 12 Ball Matrix

Figure 97 and Figure 97 show the top, bottom, and side views of the 12 x 12 mm PoP package.

Figure 96. 12 x 12 mm PoP Package Top, Bottom, and Side Views (Sheet 1 of 2)

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Package Information and Contact Assignments

Figure 97. 12 x 12 mm PoP Package Top, Bottom, and Side Views (Sheet 2 of 2)

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Package Information and Contact Assignments

6.2.2

12 x 12 mm PoP Ground, Power, Sense, and Reference Contact

Assignments

Table 84 shows the device connection list for ground, power, sense, and reference contact signals

alpha-sorted by name.

Table 84. 12 x 12 mm PoP Ground, Power, Sense, and Reference Contact Assignments

PoP Bottom

Ball Position

PoP Top

Ball Position

Ball Name

Remark

CSI_REXT

DNU

H6

—

A1, A29, AJ1, AJ29

—

DRAM_VREF

DSI_REXT

FA_ANA

GND

AG10

K6

B15, R2, U28, AH16

—

J7

This signal should be tied to GND.

—

A15, A29, B4, C6, D3, F6, F7, H3, A2, A6, A9, A11, A14, A28, B1,

K13, K14, K15, L3, L6, L13, L14, B14, B21, B24, B29, E28, F1,

L15, M3, M6, M13, M14, M15, N3, H28, J1, L29, M2, P1, P2, R28,

N6, N13, N14, N15, P14, R14, V2, V28, AA28, AB2, AE2, AF28,

R19, R20, T14, T19, T20, U10,

AH1, AH5, AH14, AH18, AH29,

U11, U12, U13, U14, U15, U16, AJ2, AJ7, AJ11, AJ16, AJ22, AJ28

U17, U18, V10, V11, V12, V13,

V14, V15, V16, V17, V18, W13,

W14, W17, W18, Y13, Y14, Y17,

Y18, AG5, AG7, AG8, AG11,

AG13, AH11, AH12, AH13, AH14,

AH15, AH16, AH17, AH18, AH19,

AJ1, AJ2, AJ11, AJ12, AJ13,

AJ14, AJ15, AJ16, AJ17, AJ18,

AJ20, AJ29

GPANAIO

C10

—

Analog output for NXP use only. This

output must remain unconnected.

HDMI_DDCCEC

R2

Analog ground reference for the Hot

Plug detect signal.

HDMI_REF

HDMI_VP

HDMI_VPH

NC

P6

M7

N7

A1

T7

—

No connect

NVCC_CSI

NVCC_DRAM

Supply of the camera sensor interface

Supply of the DDR interface

Y23, AA23, AB23, AC8, AC9,

AC10, AC11, AC12, AC13, AC14,

AC15, AC16, AC17, AC18, AC19,

AC20, AC21, AC22, AC23, AD8,

AD9, AD10, AD11, AD12, AD13,

AD14, AD15, AD16, AD17, AD18,

AD19, AD20, AD21

NVCC_EIM0

NVCC_EIM1

NVCC_EIM2

NVCC_ENET

NVCC_GPIO

K23

M23

P23

W23

W7

—

Supply of the EIM interface

Supply of the ENET interface

Supply of the GPIO interface

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Package Information and Contact Assignments

Table 84. 12 x 12 mm PoP Ground, Power, Sense, and Reference Contact Assignments (continued)

PoP Bottom

Ball Position

PoP Top

Ball Position

Ball Name

Remark

NVCC_JTAG

G6

—

Supply of the JTAG tap controller

interface

NVCC_LCD

T23

—

Supply of the LCD interface

NVCC_LVDS2P5

AA7, AG14, AG18, AG20

Supply of the LVDS display interface

and DDR pre-drivers. Even if the

LVDS interface is not used, this supply

must remain powered.

NVCC_MIPI

K7

—

Supply of the MIPI interface

NVCC_NANDF

G18

Supply of the RAW NAND Flash

Memories interface

NVCC_PLL_OUT

NVCC_RGMII

NVCC_SD1

C8

G23

G21

G22

G16

A4

—

Supply of the ENET interface

Supply of the SD card interface

—

NVCC_SD2

—

NVCC_SD3

—

PCIE_REXT

—

PCIE_VP

H7

—

PCIE_VPH

G7

—

PCI PHY supply

PCIE_VPTX

G8

—

PCI PHY supply

POP_VDD1__1

POP_VDD1__2

POP_VDD1__3

POP_VDD1__4

POP_VDD1__5

POP_VDD1__6

POP_VDD1__7

POP_VDD1__8

POP_VDD2__1

POP_VDD2__2

POP_VDD2__3

POP_VDD2__4

POP_VDD2__5

POP_VDD2__6

POP_VDD2__7

POP_VDD2__8

POP_VDDCA

C3

B2, C1

A15

C15

C27

P3

VDD1 supply to the LPDDR2 PoP

memory. The bottom side signals are

connected to the supply source on the

board. The supplies are passed

through the i.MX6 PoP package to the

LPDDR2 memory VDD1 supplies on

the top side.

B28, C28

N2, R1

P29

R27

AG3

AG16

AG26

C4

AH2

AJ15

AH28

A3

C16

D27

P27

T3

A16, B16

C29

P28

VDD2 supply to the LPDDR2 PoP

memory. The bottom side signals are

connected to the supply source on the

board. The supplies are passed

through the i.MX6 PoP package to the

LPDDR2 memory VDD2 supplies on

the top side.

T1, T2

AH3

AH15

AG28

AG4

AG15

AG27

T27, AC27, AE27,

AG19, AG22, AG25

T28, AC28, AE29,

AH22, AJ19, AJ26

VDDCA supply to the LPDDR2 PoP

memory. The bottom side signals are

connected to the supply source on the

board. The supplies are passed

through the i.MX6 PoP package to the

LPDDR2 memory VDDCA supplies on

the top side.

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Package Information and Contact Assignments

Table 84. 12 x 12 mm PoP Ground, Power, Sense, and Reference Contact Assignments (continued)

PoP Bottom

Ball Position

PoP Top

Ball Position

Ball Name

Remark

POP_VDDQ

C5, C7, C9, C13, C18, C22, C25, A22, B4, B7, B9, B13, B18, B25, VDDQ supply to the LPDDR2 PoP

E3, E27, G3, J3, J27, M27, U3, Y3, D2, D29, F29, G2, J2, J28, M28, memory. The bottom side signals are

AC3, AF3, AG6, AG9, AG12

U1, Y1, AC1, AF2, AH9, AH12, connected to the supply source on the

AJ4, AJ6

board. The supplies are passed

through the i.MX6 PoP package to the

LPDDR2 memory VDDQ supplies on

the top side.

POP_ZQP0

POP_ZQP1

AF27

AG29

Bottom side signal should be

connected to an external 240 ohm 1%

resistor to ground.

The bottom side signal is routed

through the package to the top side

signal to connect to the memory.

AG17

AJ17

Bottom side signal should be

connected to an external 240 ohm 1%

resistor to ground.

The bottom side signal is routed

through the package to the top side

signal to connect to the memory.

SATA_REXT

SATA_VP

F15

G15

G14

C11

G11

P7

—

SATA_VPH

USB_H1_VBUS

USB_OTG_VBUS

VDD_CACHE_CAP

Cache supply input. This input should

be connected to (driven by)

VDD_SOC_CAP. The external

capacitor used for VDD_SOC_CAP is

sufficient for this supply.

VDD_FA

J6

—

This signal must be tied to GND.

VDD_SNVS_CAP

G9

Secondary supply for the SNVS

(internal regulator output—requires

capacitor if internal regulator is used)

VDD_SNVS_IN

VDDARM_CAP

G12

—

Primary supply for the SNVS regulator

P15, P16, P17, P18, R15, R16,

R17, R18, T15, T16, T17, T18

Secondary supply for the ARM0 and

ARM1 cores (internal regulator

output—requires capacitor if internal

regulator is used)

VDDARM_IN

K16, K17, K18, L16, L17, L18,

M16, M17, M18, N16, N17, N18

—

Primary supply for the ARM0 and

ARM1 core regulator

VDDARM23_CAP P10, P11, P12, P13, R10, R11,

R12, R13, T10, T11, T12, T13

Secondary supply for the ARM2 and

ARM3 cores (internal regulator

output—requires capacitor if internal

regulator is used)

VDDARM23_IN

K10, K11, K12, L10, L11, L12,

M10, M11, M12, N10, N11, N12

—

Primary supply for the ARM2 and

ARM3 core regulator

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Package Information and Contact Assignments

Table 84. 12 x 12 mm PoP Ground, Power, Sense, and Reference Contact Assignments (continued)

PoP Bottom

Ball Position

PoP Top

Ball Position

Ball Name

Remark

VDDHIGH_CAP

F10, F11

—

Secondary supply for the 2.5 V

domain (internal regulator output—

requires capacitor if internal regulator

is used)

VDDHIGH_IN

VDDPU_CAP

F8, F9

—

Primary supply for the 2.5 V regulator

N19, N20, P19, P20, U19, U20,

V19, V20

Secondary supply for the VPU and

GPU (internal regulator output—

requires capacitor if internal regulator

is used)

VDDSOC_CAP

K19, K20, R6, R7, W10, W11,

W12, W15, W16, Y10, Y11, Y12,

Y15, Y16

—

Secondary supply for the SoC and PU

(internal regulator output—requires

capacitor if internal regulator is used)

VDDSOC_IN

L19, L20, M19, M20, W19, W20,

Y19, Y20

—

Primary supply for the SoC and PU

regulators

VDDUSB_CAP

G10

Secondary supply for the 3 V domain

(internal regulator output—requires

capacitor if internal regulator is used)

ZQPAD

AJ19

—

Connect ZQPAD to an external 240Ω

1% resistor to GND. This is a

reference used during DRAM output

buffer driver calibration.

6.2.3

12 x 12 mm Functional Contact Assignments

Table 85 displays an alpha-sorted list of the signal assignments including power rails. The table also

includes out of reset pad state.

Table 85. 12 x 12 mm Functional Contact Assignments

1

Out of Reset Condition

PoP PoP

Power

Group

Ball

Ball Name

Bottom Top

Default

Mode

Default

Input/

Output

Type

2

Value

Ball

Function

BOOT_MODE0

BOOT_MODE1

CLK1_N

C14

G13

A7

B7

A6

B6

E2

E1

C2

C1

D1

D2

F1

VDD_SNVS_IN

VDD_HIGH_CAP

NVCC_MIPI

GPIO

—

ALT0

—

SRC_BOOT_MODE0

SRC_BOOT_MODE1

CLK1_N

Input

—

PD (100k)

—

PD (100k)

—

CLK1_P

—

CLK2_N

—

CLK2_P

—

CSI_CLK0M

CSI_CLK0P

CSI_D0M

CSI_D0P

CSI_CLK_N

—

NVCC_MIPI

CSI_CLK_P

—

NVCC_MIPI

CSI_DATA0_N

CSI_DATA0_P

CSI_DATA1_N

CSI_DATA1_P

CSI_DATA2_N

CSI_DATA2_P

—

NVCC_MIPI

—

CSI_D1M

CSI_D1P

NVCC_MIPI

—

NVCC_MIPI

—

CSI_D2M

CSI_D2P

NVCC_MIPI

—

F2

NVCC_MIPI

—

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Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

CSI_D3M

CSI_D3P

G2

G1

NVCC_MIPI

NVCC_CSI

NVCC_LCD

CSI_DATA3_N

CSI_DATA3_P

GPIO5_IO22

GPIO5_IO23

GPIO5_IO24

GPIO5_IO25

GPIO5_IO26

GPIO5_IO27

GPIO5_IO28

GPIO5_IO29

GPIO5_IO30

GPIO5_IO31

GPIO6_IO00

GPIO6_IO01

GPIO6_IO02

GPIO6_IO03

GPIO6_IO04

GPIO6_IO05

GPIO5_IO20

GPIO5_IO19

GPIO5_IO18

GPIO5_IO21

GPIO4_IO16

GPIO4_IO18

GPIO4_IO19

GPIO4_IO20

GPIO4_IO17

GPIO4_IO21

GPIO4_IO22

GPIO4_IO23

GPIO4_IO24

GPIO4_IO25

GPIO4_IO26

GPIO4_IO27

GPIO4_IO28

GPIO4_IO29

GPIO4_IO30

GPIO4_IO31

GPIO5_IO05

GPIO5_IO06

—

CSI0_DAT4

CSI0_DAT5

CSI0_DAT6

CSI0_DAT7

CSI0_DAT8

CSI0_DAT9

CSI0_DAT10

CSI0_DAT11

CSI0_DAT12

CSI0_DAT13

CSI0_DAT14

CSI0_DAT15

CSI0_DAT16

CSI0_DAT17

CSI0_DAT18

CSI0_DAT19

CSI0_DATA_EN

CSI0_MCLK

CSI0_PIXCLK

CSI0_VSYNC

DI0_DISP_CLK

DI0_PIN2

U6

GPIO

ALT5

Input

PU (100k)

U7

Y1

Y2

W2

W1

W3

V1

V3

T6

U2

V2

T2

U1

T1

R3

V6

AA2

AD1

AA1

AF29

AD29

W24

U24

AD28

AH29

AD27

AB27

V23

V24

AH27

U23

AE28

AJ26

AG28

AH26

AJ27

AF28

DI0_PIN3

DI0_PIN4

DI0_PIN15

DISP0_DAT0

DISP0_DAT1

DISP0_DAT2

DISP0_DAT3

DISP0_DAT4

DISP0_DAT5

DISP0_DAT6

DISP0_DAT7

DISP0_DAT8

DISP0_DAT9

DISP0_DAT10

DISP0_DAT11

DISP0_DAT12

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Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

DISP0_DAT13

DISP0_DAT14

DISP0_DAT15

DISP0_DAT16

DISP0_DAT17

DISP0_DAT18

DISP0_DAT19

DISP0_DAT20

DISP0_DAT21

DISP0_DAT22

DISP0_DAT23

DRAM_CA0P0

DRAM_CA0P1

DRAM_CA1P0

DRAM_CA1P1

DRAM_CA2P0

DRAM_CA2P1

DRAM_CA3P0

DRAM_CA3P1

DRAM_CA4P0

DRAM_CA4P1

DRAM_CA5P0

DRAM_CA5P1

DRAM_CA6P0

DRAM_CA6P1

DRAM_CA7P0

DRAM_CA7P1

DRAM_CA8P0

DRAM_CA8P1

DRAM_CA9P0

DRAM_CA9P1

DRAM_CKE0P0

DRAM_CKE0P1

DRAM_CKE1P0

DRAM_CKE1P1

AJ25

AJ28

AH25

AB24

AH28

AH24

AA24

AD24

AC24

Y24

AJ24

—

NVCC_LCD

GPIO

DDR

ALT5

ALT0

GPIO5_IO07

GPIO5_IO08

Input

PU (100k)

—

PU (100k)

NVCC_LCD

GPIO5_IO09

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO10

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO11

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO12

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO13

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO14

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO15

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO16

Input

PU (100k)

—

NVCC_LCD

GPIO5_IO17

Input

PU (100k)

—

R29

AJ27

T29

AH27

U29

AH26

V29

AH25

W28

AJ25

AC29

AJ20

AD29

AH20

AD28

AH19

AE28

AJ18

AF29

AH17

NVCC_DRAM

LPDDR2_CA0_P0

LPDDR2_CA0_P1

LPDDR2_CA1_P0

LPDDR2_CA1_P1

LPDDR2_CA2_P0

LPDDR2_CA2_P1

LPDDR2_CA3_P0

LPDDR2_CA3_P1

LPDDR2_CA4_P0

LPDDR2_CA4_P1

LPDDR2_CA5_P0

LPDDR2_CA5_P1

LPDDR2_CA6_P0

LPDDR2_CA6_P1

LPDDR2_CA7_P0

LPDDR2_CA7_P1

LPDDR2_CA8_P0

LPDDR2_CA8_P1

LPDDR2_CA9_P0

LPDDR2_CA9_P1

LPDDR2_CKE0_P0

LPDDR2_CKE0_P1

LPDDR2_CKE1_P0

LPDDR2_CKE1_P1

Output

0

—

Bottom side

signals:

AA29 AA29

AH23 AH23

DRAM_CKE0P0,

DRAM_CKE0P1,

DRAM_CKE1P0&

DRAM_1CKE1P0

must connect to

ground through a

10 kohm resistor.

Y29

AJ23 AJ23

DRAM_CLKP0

DRAM_CLKP0_B

DRAM_CLKP1

AB28

AB29

AJ21

NVCC_DRAM

DDRCLK ALT0

LPDDR2_CK_P0

LPDDR2_CK_P0_B

LPDDR2_CK_P1

Input

—

Hi-Z

—

DDRCLK ALT0

Input

Hi-Z

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

141

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

DRAM_CLKP1_B

DRAM_CS0P0

DRAM_CS1P0

DRAM_CS0P1

DRAM_CS1P1

DRAM_D0P0

DRAM_D1P0

DRAM_D2P0

DRAM_D3P0

DRAM_D4P0

DRAM_D5P0

DRAM_D6P0

DRAM_D7P0

DRAM_D8P0

DRAM_D9P0

DRAM_D10P0

DRAM_D11P0

DRAM_D12P0

DRAM_D13P0

DRAM_D14P0

DRAM_D15P0

DRAM_D16P0

DRAM_D17P0

DRAM_D18P0

DRAM_D19P0

DRAM_D20P0

DRAM_D21P0

DRAM_D22P0

DRAM_D23P0

DRAM_D24P0

DRAM_D25P0

DRAM_D26P0

DRAM_D27P0

DRAM_D28P0

DRAM_D29P0

DRAM_D30P0

DRAM_D31P0

DRAM_D0P1

DRAM_D1P1

DRAM_D2P1

AH21

Y28

W29

AH24

AJ24

U2

NVCC_DRAM

LPDDR2_CK_P1_B

LPDDR2_CS_B0_P0

LPDDR2_CS_B1_P0

LPDDR2_CS_B0_P1

LPDDR2_CS_B1_P1

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DATA32

DRAM_DATA33

DRAM_DATA34

—

0

DDR

ALT0

Output

Input

0

PU (100k)

N1

M1

Y2

V1

W1

W2

L2

AJ3

AH4

AG1

AH6

AE1

AG2

AF1

AJ5

H2

F2

C2

E1

H1

G1

E2

D1

AH11

AJ9

AJ14

AJ12

AH10

AJ10

AJ13

AH13

B3

A7

A4

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

142

NXP Semiconductors

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

DRAM_D3P1

DRAM_D4P1

B5

A5

NVCC_DRAM

DDR

ALT0

DRAM_DATA35

DRAM_DATA36

DRAM_DATA37

DRAM_DATA38

DRAM_DATA39

DRAM_DATA40

DRAM_DATA41

DRAM_DATA42

DRAM_DATA43

DRAM_DATA44

DRAM_DATA45

DRAM_DATA46

DRAM_DATA47

DRAM_DATA48

DRAM_DATA49

DRAM_DATA50

DRAM_DATA51

DRAM_DATA52

DRAM_DATA53

DRAM_DATA54

DRAM_DATA55

DRAM_DATA56

DRAM_DATA57

DRAM_DATA58

DRAM_DATA59

DRAM_DATA60

DRAM_DATA61

DRAM_DATA62

DRAM_DATA63

DRAM_DQM0

Input

Output

Input

—

PU (100k)

0

—

DRAM_D5P1

A8

DRAM_D6P1

B8

DRAM_D7P1

B6

DRAM_D8P1

A18

A13

B19

A12

A19

A17

B12

B17

E29

A24

A27

A26

B27

D28

B26

A25

K28

N29

H29

L28

M29

N28

K29

J29

AB1

AC2

L1

DRAM_D9P1

DRAM_D10P1

DRAM_D11P1

DRAM_D12P1

DRAM_D13P1

DRAM_D14P1

DRAM_D15P1

DRAM_D16P1

DRAM_D17P1

DRAM_D18P1

DRAM_D19P1

DRAM_D20P1

DRAM_D21P1

DRAM_D22P1

DRAM_D23P1

DRAM_D24P1

DRAM_D25P1

DRAM_D26P1

DRAM_D27P1

DRAM_D28P1

DRAM_D29P1

DRAM_D30P1

DRAM_D31P1

DRAM_DM0P0

DRAM_DM1P0

DRAM_DM2P0

DRAM_DM3P0

DRAM_DM0P1

DRAM_DM1P1

DRAM_DM2P1

DRAM_DM3P1

DRAM_DQS0P0

DRAM_DQS0P0_B

DRAM_DQS1P0

DRAM_DQM1

0

DRAM_DQM2

0

AH7

B11

A21

B22

F28

AA1

AA2

AD2

DRAM_DQM3

0

DRAM_DQM4

0

DRAM_DQM5

0

DRAM_DQM6

0

DRAM_DQM7

0

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

DRAM_SDQS0_P

DRAM_SDQS0_N

DRAM_SDQS1_P

Hi-Z

—

Input

Hi-Z

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

143

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

DRAM_DQS1P0_B

DRAM_DQS2P0

DRAM_DQS2P0_B

DRAM_DQS3P0

DRAM_DQS3P0_B

DRAM_DQS0P1

DRAM_DQS0P1_B

DRAM_DQS1P1

DRAM_DQS1P1_B

DRAM_DQS2P1

DRAM_DQS2P1_B

DRAM_DQS3P1

DRAM_DQS3P1_B

DSI_CLK0M

DSI_CLK0P

DSI_D0M

AD1

K2

K1

AH8

AJ8

B10

A10

A20

B20

A23

B23

G28

G29

—

NVCC_DRAM

NVCC_MIPI

NVCC_EIM1

NVCC_EIM0

NVCC_EIM2

NVCC_EIM1

NVCC_EIM0

DDRCLK

DRAM_SDQS1_N

DRAM_SDQS2_P

DRAM_SDQS2_N

DRAM_SDQS3_P

DRAM_SDQS3_N

DRAM_SDQS4_P

DRAM_SDQS4_N

DRAM_SDQS5_P

DRAM_SDQS5_N

DRAM_SDQS6_P

DRAM_SDQS6_N

DRAM_SDQS7_P

DRAM_SDQS7_N

DSI_CLK_N

—

Input

—

Hi-Z

—

Hi-Z

—

Hi-Z

—

Hi-Z

—

Hi-Z

—

Hi-Z

—

0

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

DDRCLK

DDRCLK ALT0

—

Input

—

Input

—

Input

—

Input

—

Input

—

DDRCLK

—

J1

—

J2

DSI_CLK_P

—

H2

DSI_DATA0_N

DSI_DATA0_P

DSI_DATA1_N

DSI_DATA1_P

EIM_ADDR16

EIM_ADDR17

EIM_ADDR18

EIM_ADDR19

EIM_ADDR20

EIM_ADDR21

EIM_ADDR22

EIM_ADDR23

EIM_ADDR24

EIM_ADDR25

EIM_BCLK

—

DSI_D0P

H1

—

DSI_D1M

K2

—

DSI_D1P

K1

—

EIM_A16

T29

N24

M24

R28

R29

P29

P28

N28

N27

H28

AA27

U29

U28

J24

H29

J28

J29

J23

K29

K28

K24

GPIO

ALT0

ALT5

Output

Input

—

EIM_A17

0

—

EIM_A18

0

—

EIM_A19

0

—

EIM_A20

0

—

EIM_A21

0

—

EIM_A22

0

—

EIM_A23

0

—

EIM_A24

0

—

EIM_A25

0

—

EIM_BCLK

0

—

EIM_CS0

EIM_CS0_B

1

—

EIM_CS1

EIM_CS1_B

1

—

EIM_D16

GPIO3_IO16

PU (100k)

—

EIM_D17

GPIO3_IO17

—

EIM_D18

GPIO3_IO18

—

EIM_D19

GPIO3_IO19

—

EIM_D20

GPIO3_IO20

—

EIM_D21

GPIO3_IO21

—

EIM_D22

GPIO3_IO22

—

EIM_D23

GPIO3_IO23

—

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

144

NXP Semiconductors

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

EIM_D24

EIM_D25

L29

L28

NVCC_EIM0

NVCC_EIM2

NVCC_EIM0

NVCC_EIM1

NVCC_EIM2

NVCC_ENET

GPIO

ALT5

ALT0

ALT5

ALT0

ALT5

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

GPIO3_IO29

GPIO3_IO30

GPIO3_IO31

EIM_AD00

EIM_AD01

EIM_AD02

EIM_AD03

EIM_AD04

EIM_AD05

EIM_AD06

EIM_AD07

EIM_AD08

EIM_AD09

EIM_AD10

EIM_AD11

EIM_AD12

EIM_AD13

EIM_AD14

EIM_AD15

EIM_EB0_B

EIM_EB1_B

GPIO2_IO30

GPIO2_IO31

EIM_LBA_B

EIM_OE

Input

Output

Input

Output

Input

PU (100k)

PD (100k)

PU (100k)

1

—

EIM_D26

L27

EIM_D27

M28

M29

L24

EIM_D28

EIM_D29

EIM_D30

N29

EIM_D31

L23

EIM_DA0

V28

EIM_DA1

V27

EIM_DA2

W29

AB29

W27

W28

T24

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

R24

EIM_DA8

AB28

AC29

Y28

EIM_DA9

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_EB0

AE29

Y27

R23

AC28

AA28

N23

EIM_EB1

P24

1

EIM_EB2

H27

PU (100k)

1

EIM_EB3

K27

EIM_LBA

V29

EIM_OE

T28

1

EIM_RW

U27

EIM_RW

1

EIM_WAIT

ENET_CRS_DV

ENET_MDC

ENET_MDIO

ENET_REF_CLK

ENET_RX_ER

ENET_RXD0

ENET_RXD1

ENET_TX_EN

AG29

AG23

AJ21

AJ22

AH21

AD22

AH22

AH20

AG24

EIM_WAIT

GPIO1_IO25

GPIO1_IO31

GPIO1_IO22

GPIO1_IO23

GPIO1_IO24

GPIO1_IO27

GPIO1_IO26

GPIO1_IO28

PU (100k)

3

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

145

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

ENET_TXD0

ENET_TXD1

GPIO_0

AD23

AG21

AE2

AA6

W6

AE1

Y6

NVCC_ENET

NVCC_GPIO

HDMI_VPH

GPIO

—

ALT5

—

GPIO1_IO30

GPIO1_IO29

Input

—

PU (100k)

PD (100k)

PU (100k)

—

GPIO1_IO00

GPIO_1

GPIO1_IO01

GPIO_2

GPIO1_IO02

GPIO_3

GPIO1_IO03

GPIO_4

GPIO1_IO04

GPIO_5

AB3

AC6

AC1

V7

GPIO1_IO05

GPIO_6

GPIO1_IO06

GPIO_7

GPIO1_IO07

GPIO_8

GPIO1_IO08

GPIO_9

AD2

AB2

AC2

AA3

AB1

L1

GPIO1_IO09

GPIO_16

GPIO7_IO11

GPIO_17

GPIO7_IO12

GPIO_18

GPIO7_IO13

GPIO_19

GPIO4_IO05

HDMI_CLKM

HDMI_CLKP

HDMI_D0M

HDMI_D0P

HDMI_D1M

HDMI_D1P

HDMI_D2M

HDMI_D2P

HDMI_HPD

JTAG_MOD

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRSTB

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

HDMI_TX_CLK_N

HDMI_TX_CLK_P

HDMI_TX_DATA0_N

HDMI_TX_DATA0_P

HDMI_TX_DATA1_N

HDMI_TX_DATA1_P

HDMI_TX_DATA2_N

HDMI_TX_DATA2_P

HDMI_TX_HPD

JTAG_MODE

JTAG_TCK

L2

HDMI_VPH

—

M1

HDMI_VPH

—

M2

HDMI_VPH

—

N1

HDMI_VPH

—

N2

HDMI_VPH

—

P1

HDMI_VPH

—

P2

HDMI_VPH

—

R1

HDMI_VPH

—

F3

NVCC_JTAG

NVCC_GPIO

GPIO

ALT0

ALT5

Input

Output

Input

PU (100k)

PU (47k)

Keeper

B1

L7

JTAG_TDI

B2

JTAG_TDO

A2

JTAG_TMS

PU (47k)

PU (100k)

K3

JTAG_TRST_B

GPIO4_IO06

AB6

Y7

GPIO4_IO08

AD7

AD6

AF1

AB7

AD3

AF2

AE3

GPIO4_IO10

GPIO4_IO12

GPIO4_IO14

GPIO4_IO07

GPIO4_IO09

GPIO4_IO11

GPIO4_IO13

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

146

NXP Semiconductors

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

KEY_ROW4

LVDS0_CLK_N

LVDS0_CLK_P

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

LVDS1_CLK_N

LVDS1_CLK_P

LVDS1_TX0_N

LVDS1_TX0_P

LVDS1_TX1_N

LVDS1_TX1_P

LVDS1_TX2_N

LVDS1_TX2_P

LVDS1_TX3_N

LVDS1_TX3_P

NANDF_ALE

NANDF_CLE

NANDF_CS0

NANDF_CS1

NANDF_CS2

NANDF_CS3

NANDF_D0

AC7

AH4

AJ4

AG2

AG1

AH2

AH1

AH3

AJ3

AH5

AJ5

AJ8

AH8

AJ6

AH6

AH7

AJ7

AJ9

AH9

AJ10

AH10

A20

G17

A21

F18

C20

B21

F19

B22

B23

A23

G19

A24

C23

F20

B20

C19

A13

B3

NVCC_GPIO

NVCC_LVDS_2P5

NVCC_NANDF

VDD_SNVS_IN

PCIE_VPH

GPIO

LVDS

GPIO

—

ALT5

—

GPIO4_IO15

LVDS0_CLK_N

LVDS0_CLK_P

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

LVDS1_CLK_N

LVDS1_CLK_P

LVDS1_TX0_N

LVDS1_TX0_P

LVDS1_TX1_N

LVDS1_TX1_P

LVDS1_TX2_N

LVDS1_TX2_P

LVDS1_TX3_N

LVDS1_TX3_P

GPIO6_IO08

GPIO6_IO07

GPIO6_IO11

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO6_IO10

GPIO6_IO09

SRC_ONOFF

PCIE_RX_N

Input

—

PU (100k)

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

—

Input

—

Keeper

—

ALT0

ALT5

—

Input

—

Keeper

PU (100k)

—

NANDF_D1

NANDF_D2

NANDF_D3

NANDF_D4

NANDF_D5

NANDF_D6

NANDF_D7

NANDF_RB0

NANDF_WP_B

ONOFF

PCIE_RXM

—

PCIE_RXP

A3

PCIE_VPH

PCIE_RX_P

—

i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 2, 11/2018

NXP Semiconductors

147

Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

PCIE_TXM

PCIE_TXP

A5

B5

PCIE_VPH

PCIE_TX_N

PCIE_TX_P

—

PMIC_ON_REQ

A12

VDD_SNVS_IN

GPIO

ALT0

SNVS_PMIC_ON_REQ

Output Open Drain with

PU(100k)

PMIC_STBY_REQ

POR_B

C12

F13

G27

F29

H23

G29

F28

H24

C28

E29

G24

F27

G28

C29

B10

A10

A16

B16

A14

B14

C26

D28

A27

B27

F22

A28

E28

D29

B29

F24

B28

F23

C17

F16

A18

B18

A19

VDD_SNVS_IN

NVCC_RGMII

VDD_SNVS_CAP

SATA_VPH

GPIO

DDR

—

ALT0 CCM_PMIC_STBY_REQ

Output

Input

—

0

—

ALT0

ALT5

—

SRC_POR_B

GPIO6_IO25

GPIO6_IO27

GPIO6_IO28

GPIO6_IO29

GPIO6_IO24

GPIO6_IO30

GPIO6_IO20

GPIO6_IO21

GPIO6_IO22

GPIO6_IO23

GPIO6_IO26

GPIO6_IO19

RTC_XTALI

PU (100k)

PD (100k)

PU (100k)

PD (100k)

—

RGMII_RD0

RGMII_RD1

RGMII_RD2

RGMII_RD3

RGMII_RX_CTL

RGMII_RXC

RGMII_TD0

RGMII_TD1

RGMII_TD2

RGMII_TD3

RGMII_TX_CTL

RGMII_TXC

RTC_XTALI

RTC_XTALO

SATA_RXM

SATA_RXP

SATA_TXM

SATA_TXP

SD1_CLK

RTC_XTALO

SATA_PHY_RX_N

SATA_PHY_RX_P

SATA_PHY_TX_N

SATA_PHY_TX_P

GPIO1_IO20

GPIO1_IO18

GPIO1_IO16

GPIO1_IO17

GPIO1_IO19

GPIO1_IO21

GPIO1_IO10

GPIO1_IO11

GPIO1_IO15

GPIO1_IO14

GPIO1_IO13

GPIO1_IO12

GPIO7_IO03

GPIO7_IO02

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

—

SATA_VPH

—

SATA_VPH

—

SATA_VPH

—

NVCC_SD1

GPIO

ALT5

Input

PU (100k)

SD1_CMD

NVCC_SD1

SD1_DAT0

SD1_DAT1

SD1_DAT2

SD1_DAT3

SD2_CLK

NVCC_SD1

NVCC_SD2

SD2_CMD

NVCC_SD2

SD2_DAT0

SD2_DAT1

SD2_DAT2

SD2_DAT3

SD3_CLK

NVCC_SD2

NVCC_SD3

SD3_CMD

NVCC_SD3

SD3_DAT0

SD3_DAT1

SD3_DAT2

NVCC_SD3

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Package Information and Contact Assignments

Table 85. 12 x 12 mm Functional Contact Assignments (continued)

1

Out of Reset Condition

PoP PoP

Bottom Top

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

2

Value

Ball

SD3_DAT3

SD3_DAT4

SD3_DAT5

SD3_DAT6

SD3_DAT7

SD3_RST

F17

F14

B17

B15

A17

B19

A22

C21

B24

A25

G20

A26

F21

C24

B26

B25

B12

B13

B11

A11

NVCC_SD3

GPIO

—

ALT5

ALT0

—

GPIO7_IO07

GPIO7_IO01

GPIO7_IO00

GPIO6_IO18

GPIO6_IO17

GPIO7_IO08

GPIO7_IO10

GPIO7_IO09

GPIO2_IO08

GPIO2_IO09

GPIO2_IO10

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

SNVS_TAMPER

TCU_TEST_MODE

USB_H1_DN

USB_H1_DP

USB_OTG_CHD_B

USB_OTG_DN

USB_OTG_DP

XTALI

Input

—

PU (100k)

PD (100k)

—

NVCC_SD3

SD4_CLK

NVCC_NANDF

VDD_SNVS_IN

VDD_USB_CAP

NVCC_PLL

SD4_CMD

SD4_DAT0

SD4_DAT1

SD4_DAT2

SD4_DAT3

SD4_DAT4

SD4_DAT5

SD4_DAT6

SD4_DAT7

TAMPER

TEST_MODE

USB_H1_DN

USB_H1_DP

—

USB_OTG_CHD_B F12

—

USB_OTG_DN

USB_OTG_DP

XTALI

B9

A9

A8

B8

—

XTALO

NVCC_PLL

XTALO

—

1

2

The state immediately after reset and before ROM firmware or software has executed.

Variance of the pull-up and pull-down strengths are shown in the tables as follows:

• Table 21, “GPIO I/O DC Parameters,” on page 38.

• Table 24, “LVDS I/O DC Parameters,” on page 41.

3

ENET_REF_CLK is used as a clock source for MII and RGMII modes only. RMII mode uses either GPIO_16 or RGMII_TX_CTL

as a clock source. For more information on these clocks, see the device Reference Manual and the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

6.2.4

Signals with Different Reset States

For most of the signals, the state during reset is same as the state after reset, given in Out of Reset Condition

column of Table 85, “12 x 12 mm Functional Contact Assignments”. However, there are few signals for

which the state during reset is different from the state after reset. These signals along with their state during

reset are given in Table 86.

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Package Information and Contact Assignments

Table 86. Signals with Differing Before Reset and After Reset States

Before Reset State

Ball Name

Input/Output

Value

EIM_A16

EIM_A17

EIM_A18

EIM_A19

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_A25

EIM_DA0

EIM_DA1

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_EB0

EIM_EB1

EIM_EB2

EIM_EB3

EIM_LBA

EIM_RW

EIM_WAIT

GPIO_17

Input

Output

PD (100K)

Drive state unknown (x)

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Package Information and Contact Assignments

Table 86. Signals with Differing Before Reset and After Reset States (continued)

Before Reset State

Ball Name

Input/Output

Value

GPIO_19

Output

Drive state unknown (x)

KEY_COL0

6.2.5

12 x 12 mm PoP, 0.4 mm Pitch Ball Maps

Table 87 shows the 12 x 12 mm, 0.4 mm pitch top ball map. Table 88 shows the 12 x 12 mm, 0.4 mm pitch

bottom ball map.

NOTE

On the top of the package, the data and control signals associated with each

byte have been swizzled relative to the ball map of the associated LPDDR2

memory. This does not affect the operation of the i.MX 6Dual/6Quad SoC

with the LPDDR2 memory.

Table 87. PoP 12 x 12 mm, 0.4 mm Pitch Top Ball Map

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Package Information and Contact Assignments

Table 87. PoP 12 x 12 mm, 0.4 mm Pitch Top Ball Map (continued)

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Package Information and Contact Assignments

Table 87. PoP 12 x 12 mm, 0.4 mm Pitch Top Ball Map (continued)

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Package Information and Contact Assignments

Table 87. PoP 12 x 12 mm, 0.4 mm Pitch Top Ball Map (continued)

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Package Information and Contact Assignments

Table 87. PoP 12 x 12 mm, 0.4 mm Pitch Top Ball Map (continued)

Table 88. PoP 12 x 12 mm, 0.4 mm Pitch Bottom Ball Map

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Package Information and Contact Assignments

Table 88. PoP 12 x 12 mm, 0.4 mm Pitch Bottom Ball Map (continued)

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Package Information and Contact Assignments

Table 88. PoP 12 x 12 mm, 0.4 mm Pitch Bottom Ball Map (continued)

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Package Information and Contact Assignments

Table 88. PoP 12 x 12 mm, 0.4 mm Pitch Bottom Ball Map (continued)

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Revision History

7 Revision History

Table 89 provides a revision history for the i.MX 6Dual Pop and i.MX 6Quad Pop data sheet.

Table 89. Data Sheet Document Revision History

Rev.

Number

Date

Substantive Change(s)

Rev. 2 10/2018 Rev. 2 changes include the following:

• Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 38,

– Row: XTALI input leakage current at startup, I_{XTALI_STARTUP}: Changed from “... driven 32KHz RTC

clock @ 1.1V” to “...driven 24 MHz clock at 1.1V.”

• Table 45, “eMMC4.4/4.41 Interface Timing Specification,” on page 77,

– Row: SD2, uSDHC Output Delay: Changed t_ODfrom 2.5 ns minimum to 2.8 ns and 7.1 ns maximum

to 6.8 ns.

1

09/2017 Rev. 1 changes include the following:

• Changed throughout:

– Changed terminology from “floating” to “not connected”.

• Section 1, “Introduction” on page 1: Changed ARM Cortex-A9 operating speed from “up to 1 GHz” to “up

to 800 MHz.”

• Figure 1, "Part Number Nomenclature—i.MX 6Dual PoP and 6Quad PoP," on page 4:

– Removed from Temperature block: Automotive temperature row.

• Table 2, “i.MX 6Dual/6Quad Modules List,” on page 10:

– Added bullet to uSDHC row: “Conforms to the SD Host Controller Standard Specification v3.0”

• Table 4, “Absolute Maximum Ratings,” on page 20: Extensive changes:

– Separated rows Core supply voltage by LDO enable/bypass

— Maximum LDO enabled value change from 1.5 to 1.6 V

— Maximum LDO bypass value added, 1.4 V

– Renamed Internal supply voltages to Core supply output voltage (LDO enabled) and changed

maximum value from 1.3 to 1.4V. Added symbol NVCC_PLL_OUT.

– Reordered VDD_HIGH_IN row and changed maximum value from 3.6 to 3.7V.

– DDR I/O supply voltage row changes:

— Changed Symbols from “Supplies denoted as I/O supply” to: “NVCC_DRAM”

— Added footnote to maximum value regarding “The absolute maximum voltage includes an allowance

for 400 mV …”.

– Change row GPIO I/O supply voltage:

— Changed Symbols from “Supplies denoted as I/O supply” to: multiple values

— Maximum value change from 3.6 to 3.7 V

– Added rows: HDMI, PCIe, and SATA PHY high (VPH) and low (VP) supply voltage and values

– Change row “LVDS I/O supply voltage” to “LVDS and MIPI I/O supply voltage (2.5V supply)”

— Changed Symbols from “Supplies denoted as I/O supply” to: multiple values

— Maximum value change from 2.8 to 2.85 V

– Added row: PCI PHY supply voltage and values

– Added row: RGMII I/O supply voltage and values

– Added row: SNVS IN supply voltage and values

– Added row: USB_OTG_CHD_B and values

– Changed row: “Input voltage on USB_OTG_DP…” to “USB I/O supply voltage”

— Changed Symbols from “USB_DP/USB_DN” to: multiple values

— Maximum value change from 3.63 to 3.73 V

– Separated row: “Input/output voltage range” by non-DDR/DDR pins, and added Vin/Vout to row name

— Maximum value added for Vin/Vout DDR pins: OVDD + 0.4 V and added footnote

– Separated and renamed row: “ESD damage immunity” by HBM/CDM and changed Symbol names

— Maximum value added for Vin/Vout DDR pins: OVDD + 0.4 V and added footnote

(Revision History table continues on next page.)

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Revision History

Table 89. Data Sheet Document Revision History (continued)

Substantive Change(s)

Rev.

Date

Number

1

09/2017 • Section 4.1.2, “Thermal Resistance” on page 21: Added NOTE: “Per JEDEC JESD51-2, the intent of

thermal resistance measurements…”.

(Cont.)

• Table 6, “Operating Ranges,” on page 22:

– Changed row: “Junction Temperature Standard Commercial” to “Junction Temperature Industrial”

– Changed row: Junction Temperature Industrial, maximum value from 95°C to 105°C

• Section 4.1.5, “Maximum Measured Supply Currents” on page 25: Added section.

• Section 4.2.1, “Power-Up Sequence” on page 32:

– Removed content about calculating the proper current limiting resistor for a coin cell.

– Removed inference to internal POR.

• Section 4.5.2, “OSC32K” on page 36: Removed content about calculating the proper current limiting

resistor for a coin cell.

• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters” on page 38: Added “NOTE: The

Vil and Vih specifications only apply when an external clock source is used…”.

• Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 38:

– Added footnote to RTC_XTALI high level DC input voltage row: “This voltage specification must not be

exceeded and …”.

• Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters” on page 39: Added section and table.

• Section 4.10, “Multi-Mode DDR Controller (MMDC)” on page 60: Replaced section with new content.

Was 4.9.4 DDR SDRAM Specific Parameters (LPDDR2)” with timing diagrams and parameter tables for

LPDDR2.

• Section 4.12.4.3, “SDR50/SDR104 AC Timing” on page 78: Adjusted dimension SD5 in Figure 39.

• Table 46, “SDR50/SDR104 Interface Timing Specification,” on page 78: Changes to Min/Max values:

– SD2 min from: 0.3 x tCLK; to: 0.46 x tCLK

– SD2 max from: 0.7 x tCLK to: 0.54 x tCLK

– SD3 min from: 0.3 x tCLK; to: 0.46 x tCLK. Also corrected ID from duplicate SD2 to SD3.

– SD3 max from: 0.7 x tCLK; to: 0.54 x tCLK

– SD5 max from: 1 ns; to: 0.74 ns

• Table 56, “Camera Input Signal Cross Reference, Format, and Bits Per Cycle,” on page 91: Changed

RGB565, 16 bits column heading from 2 cycles to 1 cycle.

• Table 84, “12 x 12 mm PoP Ground, Power, Sense, and Reference Contact Assignments,” on page 136:

– Added description to ZQPAD.

– Added description to GPANAIO row: “…output for NXP use only…”

0

3/2015 • Initial Release

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Information in this document is provided solely to enable system and software implementers to

use NXP products. There are no express or implied copyright licenses granted hereunder to

design or fabricate any integrated circuits based on the information in this document. NXP

reserves the right to make changes without further notice to any products herein.

How to Reach Us:

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for

any particular purpose, nor does NXP assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data

sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. NXP does not convey any license under

its patent rights nor the rights of others. NXP sells products pursuant to standard terms and

conditions of sale, which can be found at the following address:

nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to

unidentified vulnerabilities. Customers are responsible for the design and operation of their

applications and products to reduce the effect of these vulnerabilities on customer’s applications

and products, and NXP accepts no liability for any vulnerability that is discovered. Customers

should implement appropriate design and operating safeguards to minimize the risks associated

with their applications and products.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,

EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE

CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,

MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,

TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C?5, CodeTEST, CodeWarrior,

ColdFire, ColdFire+, C?Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,

mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,

SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,

BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower,

TurboLink, and UMEMS are trademarks of NXP B.V. All other product or service names are the

property of their respective owners. Arm, AMBA, Artisan, Cortex, Jazelle, Keil, SecurCore,

Thumb, TrustZone, and µVision are registered trademarks of Arm Limited (or its subsidiaries) in

the EU and/or elsewhere. Arm7, Arm9, Arm11, big.LITTLE, CoreLink, CoreSight, DesignStart,

Mali, Mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are trademarks of Arm

registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word

marks and the Power and Power.org logos and related marks are trademarks and service marks

licensed by Power.org.

Document Number: IMX6DQCPOPEC

Rev. 2

11/2018


型号：	PCIMX6D5CZK08CC
厂家：	NXP
描述：	i.MX 6Dual/6Quad Applications Processors Consumer - PoP
文件：	总161页 (文件大小：1677K)
中文：	中文翻译
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PCIMX6D5CZK08CC [NXP]

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