PCK2020DL,518 [NXP]
PCK2020DL;
| 型号： | PCK2020DL,518 |
| 厂家： | 
NXP |
| 描述： | PCK2020DL 时钟 PC 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2020
CK00 (100/133MHz) spread spectrum
differential system clock generator
Product specification
2000 Nov 13
Supersedes data of 2000 Jul 25
Philips
Semiconductors
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
FEATURES
PIN CONFIGURATION
• 3.3 V operation
V
Ref
1
2
3
4
5
6
7
8
9
56
V
3.3M
DD
SS
• Four differential CPU clock pairs
• Ten PCI clocks at 3.3 V
Ref0/MultSel0
Ref1/MultSel1
55 3VMref
54 3VMref_b
• Four 66 MHz clocks at 3.3 V
V
3.3Ref
53
V
M
SS
DD
• Two 48 MHz clocks at 3.3 V
XTAL_IN
XTAL_OUT
PCI
52 SPREAD
51 CPUCLK0
50 CPUCLK0
• Two 14.318 MHz reference clocks
• 100 or 133 MHz operation
V
SS
V
49
3.3CPU
PCICLK0
PCICLK1
DD
• Power management control pins
• CPU clock skew less than 200 ps cycle-to-cycle
• CPU clock skew less than 150 ps pin-to-pin
• 1.5 ns to 3.5 ns delay on PCI pins
• Spread Spectrum capability
48 CPUCLK1
47 CPUCLK1
V
V
V
3.3PCI 10
DD
PCICLK2 11
PCICLK3 12
46
V
CPU
SS
45 CPUCLK2
44 CPUCLK2
V
PCI 13
SS
PCICLK4 14
PCICLK5 15
43
V
3.3CPU
DD
42 CPUCLK3
41 CPUCLK3
DESCRIPTION
The PCK2020 is a clock synthesizer/driver for a Pentium III and
other similar processors.
3.3PCI 16
DD
PCICLK6 17
PCICLK7 18
40
V
CPU
SS
39 I_REF
The PCK2020 has four differential pair CPU current source outputs,
two Mref clock outputs running at 1/2 the CPU clock frequency
depending on the state of SEL133/100 pin and four 3V66 clocks
running at 66 MHz. There are ten PCI clock outputs running at
33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V
reference clocks at 14.318 MHz. All clock outputs meet Intel’s drive
strength, rise/fall times, jitter, accuracy, and skew requirements.
V
PCI 19
38
37
36
V
V
3.3Core
DD
SS
PCICLK8 20
PCICLK9 21
Core
3.3
SS
DD
V
3.3PCI 22
35 3V66_0
34 3V66_1
DD
SEL100/133 23
USB 24
V
33
32
V
V
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on-chip and
ensures glitch-free output transitions.
SS
SS
SS
48MHz0/SelA 25
48MHz1/SelB 26
31 3V66_2
30 3V66_3
V
3.3USB 27
DD
PWRDWN 28
29
V
3.3
DD
SW00577
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE (°C)
ORDER CODE
PCK2020 DL
DRAWING NUMBER
56-Pin Plastic SSOP
0 to +70
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
2000 Nov 13
853-2209 25006
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
PIN DESCRIPTION
PIN NUMBER
SYMBOL
Ref
FUNCTION
1
V
SS
During power up, pins functions as a latched inputs that enables MULTSEL0 and
MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be
clocked to latch data in.
Ref0/MultSel0
Ref1/MultSel1
2, 3
4
V
DD
3.3Ref
5
6
XTAL_IN
Crystal input
XTAL_OUT
Crystal output
7, 13, 19
V
SS
PCI
8, 9, 11, 12, 14, 15, 17,
18, 20, 21
PCICLK[0–9]
3.3PCI
3.3 V PCI clock outputs fixed at 33 MHz.
10, 16, 22
V
DD
23
24
SEL100/133
USB
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
V
SS
3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs
that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz.
Part must be clocked to latch data in.
48 MHz/SelA
48 MHz/SelB
25, 26
27
28
V
3.3USB
DD
PWRDWN
3.3
Device enters power down mode when held low. Asserts low.
3.3 V fixed 66 MHz CPU clock outputs.
29, 36
30, 31, 34, 35
32, 33
37
V
DD
3V66[0–3]
V
SS
V
Core
SS
38
V
DD
3.3Core
3.3 V power supply for analog circuits.
This pin controls the reference current for the host pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the correct current.
39
I_REF
V CPU
SS
40, 46
41, 44, 47, 50
42, 45, 48, 51
43, 49
CPUCLK[0–3]
CPUCLK[0–3]
V
3.3CPU
DD
Enables spread spectrum mode when held low on differential host outputs,
MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low.
52
53
54
SPREAD
V
SS
M
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100. (Out of phase with 3VMREF output).
3VMref_b
3VMref
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100.
55
56
V
DD
3.3M
3.3 V power supply
3
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
BLOCK DIAGRAM
PWRDWN
REF [0–1](14.318 MHz)
X
X
XIN
X
X
14.318
MHZ
OSC
XOUT
PWRDWN
PWRDWN
USBPLL
SYSPLL
48 MHz[0–1] 3 V
CPUCLK [0–3]
CPUCLK [0–3]
X
SPREAD
X
X
PWRDWN
PWRDWN
SEL 133/100
SEL0
X
X
X
3V66 [0–3] (66 MHz)
X
DECODE
LOGIC
SEL1
3VMRef
X
X
PWRDWN
PWRDWN
PWRDWN
PCICLK_F (33 MHz)
PWRDWN
X
3VMRef
X
X
PCICLK_F (33 MHz)
SW00727
4
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
FUNCTION TABLES
SEL
100/133
SELA
SELB
HOST
M
REF
3V66
3V33 PCI
48 MHz
REF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 MHz
50 MHz
52.5 MHz
50 MHz
HI-Z
66.7 MHz
33.3 MHz
48 MHz
48 MHz
N/A
14.318 MHz
14.318 MHz
N/A
1
1
1
1
105 MHz
200 MHz
HI-Z
70 MHz
35 MHz
66.7 MHz
HI-Z
33.3 MHz
HI-Z
HI-Z
HI-Z
133 MHz
126.7 MHz
200 MHz
TCLK/2
66.7 MHz
66.7 MHz
33.3 MHz
48 MHz
48 MHz
48 MHz
TCLK/2
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
1
1
1
1
63.3 MHz
66.7 MHz
TCLK/4
63.3 MHz
66.7 MHz
TCLK/4
31.7 MHz
33.3 MHz
TCLK/8
NOTE:
1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion.
SEL
100/133
SELA
SELB
HOST
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Active 100 MHz
Active 100 MHz – ~5% over-clock
200 MHz, 50 MHz M
HI-Z all outputs
REF
Active 133 MHz
Active 133.3 MHz minus ~5 under-clock
200 MHz, 66 MHz M
Test mode
REF
POWER DOWN MODE
PWRDWN
HOST/HOST_BAR
MREF/MREF_B
3V66
LOW
PCI
48 MHz
REF
14.318/66 MHz Seeds
Asserts low
0 = Active
HOST = 2*I
LOW
LOW
LOW
OFF
LOW/(if applicable)
REF
HOST_BAR
NOTE:
1. The differential outputs should have a voltage forced across them when power down is asserted.
SPREAD SPECTRUM FUNCTION TABLE
48 MHz PLL
REF/MULTSEL0
REF/MULTSEL1
SPREAD
FUNCTION
HOST/PCI/3V66/M
/M
REF REF_B
1
0
No spread
No spread
No spread
HOST/PCI/3V66/M
/M
REF REF_B
Down spread –0.5%
5
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
HOST SWING SELECT FUNCTIONS – TABLE 1
BOARD
IMPEDANCE
MULTSEL0
MULTSEL1
I
I
V
OH
@ I
= 2.32 mA
REF
REF
OH
0
0
60 Ω
R
= 475 1%
= –2.32 mA
I
I
I
= 5*I
= 5*I
= 6*I
0.71 V
0.59 V
0.85 V
0.71 V
0.56 V
0.47 V
0.99 V
0.82 V
0.75 V
0.62 V
0.90 V
0.75 V
0.60 V
0.50 V
1.05 V
0.84 V
REF
OH
OH
OH
REF
REF
REF
REF
I
REF
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
50 Ω
60 Ω
50 Ω
60 Ω
50 Ω
60 Ω
50 Ω
30 Ω
25 Ω
30 Ω
25 Ω
30 Ω
25 Ω
30 Ω
25 Ω
R
= 475 1%
REF
= –2.32 mA
I
REF
R
= 475 1%
= –2.32 mA
REF
I
REF
R
= 475 1%
= –2.32 mA
I
= 6
REF
OH
I
REF
R
= 475 1%
= –2.32 mA
I
I
I
I
I
I
I
I
I
I
I
I
= 4*I
= 4*I
= 7*I
= 7*I
= 5*I
= 5*I
= 6*I
= 6*I
= 4*I
= 4*I
= 7*I
= 7*I
REF
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
I
REF
R
= 475 1%
= –2.32 mA
REF
I
REF
R
= 475 1%
= –2.32 mA
REF
I
REF
R
= 475 1%
= –2.32 mA
REF
I
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
R
I
= 221 1%
= –5 mA
REF
REF
NOTE:
1. In Table 1, the outputs are optimized for the configurations in bold.
CONDITIONS
CONFIGURATION
LOAD
MIN.
MAX.
+7% of I
OH
See Table 1
+12% of I
OH
I
I
V
DD
= 3.3 V
All combinations,
see Table 1
Nominal test load for given configuration
–7% of I
OH
See Table 1
OUT
V
= 3.3 V ±5%
All combinations,
see Table 1
Nominal test load for given configuration
–12% of I
See Table 1
OUT
DD
OH
See Table 1
6
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
1, 2
ABSOLUTE MAXIMUM RATINGS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
MAX
+4.6
–50
V
DD3
DC 3.3 V supply
DC input diode current
DC input voltage
–0.5
V
mA
V
I
IK
V < 0
I
V
I
Note 2
I
DC output diode current
DC output voltage
V
O
> V or V < 0
±50
mA
V
OK
DD
O
V
Note 2
–0.5
–65
V
+ 0.5
O
DD
I
DC output source or sink current
Storage temperature range
V
O
= 0 to V
DD
±50
mA
°C
O
T
STG
+150
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3 mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.465
3.465
V
DD3
DC 3.3 V supply voltage
3.135
3.135
V
V
A
VDD
DC 3.3 V analog supply voltage
Capacitive load on:
PCICLK
3V66
48 MHz clock
REF
Must meet PCI 2.1 requirements
1 device load, possible 2 loads
1 device load
10
10
10
10
10
30
30
20
20
30
pF
pF
pF
pF
pF
C
L
1 device load
1 device load
M , M
REF
REF_BAR
f
Reference frequency, oscillator normal value
Operating ambient temperature range in free air
14.31818 14.31818
+70
MHz
REF
T
0
°C
amb
POWER MANAGEMENT
MAXIMUM 3.3 V SUPPLY CONSUMPTION
CONDITION
MAXIMUM DISCRETE CAP LOADS, V
= 3.465 V
DDL
ALL STATIC INPUTS = V
OR V
DD3
SS
Power-down mode (PWRDWN = 0)
Full active 100/133 MHz
60 mA
250 mA
7
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
DC CHARACTERISTICS
LIMITS
= 0°C to +70°C
TEST CONDITIONS
OTHER
T
UNIT
SYMBOL
PARAMETER
amb
V
DD
(V)
MIN
TYP
MAX
V
+
DD3
0.3
V
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
3.135 to 3.465
2.0
V
V
IH
V
V
– 0.3
0.8
IL
SS
3.3 V output HIGH voltage
REF, 3V48M, 3V66, MREF,
MREF_BAR, 48 MHz
V
3.135 to 3.465
3.135 to 3.465
I
I
= –1 mA
= 1 mA
2.0
–
–
V
V
OH3
OH
3.3 V output LOW voltage
REF, 3V48M, 3V66, MREF,
MREF_BAR, 48 MHz
V
I
0.4
–
OL3
OH
3.3 V output HIGH voltage
PCI
V
OHP
3.135 to 3.465
3.135 to 3.465
3.135
= –1 mA
= 1 mA
2.4
–
V
V
OH
3.3 V output LOW voltage
PCI
V
I
0.55
OLP
OH
OH
PCI, 3V66
3VMREF
3VMREF_BAR
output HIGH current
V
= 1.0 V
–33
OUT
Type 5
12–55 Ω
I
mA
3.465
V
= 3.135 V
–33
–23
OUT
3.135
3.465
V
= 1.0 V
–29
–11
OUT
48 MHz, REF
output HIGH current
Type 3
20–60 Ω
I
I
mA
mA
OH
V
= 3.135 V
OUT
0.66 V
0.76 V
HOST/HOST_BAR
OUTPUT CURRENT
3.135 to 3.465
Type X1
OH
–12.7
38
PCI, 3V66
3VMREF
3VMREF_BAR
output LOW current
3.135
3.465
V
V
= 1.95 V
30
29
OUT
Type 5
12–55 Ω
I
mA
mA
OL
V
= 0.4 V
OUT
3.135
3.465
= 1.95 V
= 0.4 V
OUT
48 MHz, REF
output LOW current
Type 3
20–60 Ω
I
OL
V
27
0.05
5
OUT
Rs = 33.2 Ω
Rp = 49.9 Ω
V
HOST/HOST_BAR
V
SS
= 0.0
Type X1
0.0
–5
V
OL
±I
Input leakage current
3.365
3.465
0 < V < V
DD3
µA
µA
I
IN
3-State output OFF-State
current
V
=
OUT
±I
I
O
= 0
10
OZ
V
or GND
DD
Cin
Input pin capacitance
Crystal input capacitance
Output pin capacitance
5
22.5
6
pF
pF
pF
Cxtal
Cout
13.5
NOTE:
1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
8
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
AC CHARACTERISTICS
V
DD3
= 3.3 V –5%; f
= 14.31818 MHz
crystal
HOST CLOCK OUTPUTS (SEE FIGURE 1 FOR WAVEFORMS AND FIGURE 6 FOR TEST SETUP)
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
133 MHz MODE
MIN MAX
100 MHZ MODE
MIN
10.0
9.85
175
175
MAX
10.2
N/A
700
700
200
55
T
PKP
HOST CLK period
Absolute Minimum Host CLK Period
HOST CLK rise time
7.5
7.35
175
175
7.65
N/A
700
700
200
55
ns
ns
ps
ps
ps
%
11, 14, 20
11, 14, 20
11, 15, 20
11, 15, 20
11, 12, 14, 20
11, 14, 20
11, 14, 20
11, 16, 20
11, 14, 20
AbsMinPeriod
T
RISE
T
FALL
HOST CLK fall time
T
HOST CLK cycle-to-cycle jitter
Output duty cycle
JITTER
DUTY CYCLE
45
45
T
SKEW
HOST CLK pin-to-pin skew
Rise and fall time matching
150
35%
150
35%
ps
Rise/Fall Matching
Vcrossover
45% V
60% V
45% V
60% V
OH
V
OH
OH
OH
MREF OUTPUTS
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
133 MHz MODE
100 MHz MODE
MIN
MAX
15.3
N/A
N/A
2.0
MIN
20.0
7.5
MAX
20.4
N/A
N/A
2.0
T
T
MREF period
MREF HIGH time
MREF LOW time
MREF rise time
MREF fall time
15.0
5.25
5.05
0.5
ns
ns
ns
ns
ns
ps
%
2, 9, 20
5, 10, 20
6, 10, 20
8, 20
PKP
PKH
T
7.3
PKL
T
RISE
T
FALL
0.5
0.5
2.0
0.5
2.0
8, 20
T
Cycle-to-cycle jitter
Output Duty Cycle
250
55
250
55
18, 20
18, 20
JITTER
DUTY CYCLE
45
45
3V66 OUTPUTS
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
15.0
5.25
5.05
0.5
MAX
16.0
N/A
N/A
2.0
MIN
15.0
5.25
5.05
0.5
MAX
16.0
N/A
N/A
2.0
T
T
3V66 period
3V66 HIGH time
3V66 LOW time
3V66 rise time
ns
ns
ns
ns
ns
ps
%
2, 4, 9, 20
5, 10, 20
6, 10, 20
8, 20
PKP
PKH
T
PKL
T
RISE
T
FALL
3V66 fall time
0.5
2.0
0.5
2.0
8, 20
T
Cycle-to-cycle jitter
Output Duty Cycle
Pin-to-pin skew
300
55
300
55
18, 20
18, 20
20
JITTER
DUTY CYCLE
45
45
T
SKEW
250
250
ps
9
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
PCI OUTPUTS
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
133 MHz MODE
100 MHz MODE
MIN
MAX
N/A
N/A
N/A
2.0
MIN
30.0
12.0
12.0
0.5
MAX
N/A
N/A
N/A
2.0
T
T
PCI period
PCI HIGH time
PCI LOW time
PCI rise time
30.0
12.0
12.0
0.5
ns
ns
ns
ns
ns
ps
%
2, 3, 9, 20
5, 10, 20
6, 10, 20
8, 20
PKP
PKH
T
PKL
T
RISE
T
FALL
PCI fall time
0.5
2.0
0.5
2.0
8, 20
T
Cycle-to-cycle jitter
Output Duty Cycle
Pin-to-pin skew
500
55
500
55
18, 20
JITTER
DUTY CYCLE
45
45
18, 20
T
SKEW
500
500
ps
18, 20
USB CLOCK OUTPUT, 48 MHz (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
48 MHz
MIN
MAX
MIN
MAX
f
Frequency, Actual
Deviation from 48 MHz
3V48MHZCLK LOW time
3V48MHZCLK rise time
3V48MHZCLK fall time
Cycle-to-cycle jitter
48.008
+167
MHz
ppm
ns
f
D
T
5.05
1.0
N/A
4.0
4.0
350
55
5.05
1.0
N/A
4.0
4.0
350
55
20
HKL
T
T
ns
8, 20
8, 20
18, 20
18, 20
RISE
FALL
1.0
1.0
ns
T
ps
JITTER
DUTY CYCLE
Output Duty Cycle
45
45
%
REF CLOCK OUTPUT, (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
48 MHz
MIN
MAX
MIN
MAX
f
Frequency, Actual
REF CLK LOW time
REF CLK HIGH time
REF CLK rise time
REF CLK fall time
Cycle-to-cycle jitter
Output Duty Cycle
14.318
MHz
ns
20
20
T
31.0
32.0
N/A
N/A
36.67
37.5
N/A
31.0
32.0
N/A
N/A
36.67
37.5
N/A
HKL
HKH
RISE
FALL
T
ns
20
T
T
ns
8, 20
8, 20
18, 20
18, 20
N/A
N/A
ns
T
1000
55
1000
55
ps
JITTER
DUTY CYCLE
45
45
%
ALL OUTPUTS
LIMITS
= 0°C to +70°C
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
133 MHz MODE
MIN MAX
100 MHz MODE
MIN
1.0
MAX
10.0
10.0
3
TpZL, tpZH
TpLZ, tpZH
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from Power-up
1.0
1.0
10.0
10.0
3
ns
ns
20
20
1.0
T
ms
7, 20
STABLE
10
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
GROUP OFFSET LIMITS
GROUP
OFFSET
MEASUREMENT LOADS (LUMPED)
MEASURE POINTS
NOTES
1.5–3.5 ns
3V66 leads
3V66 @ 30 pf
PCI @ 30 pf
3V66 @ 1.5 V
PCI @ 1.5 V
3V66 to PCI
19, 20
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz.
4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host =
100 MHz.
5. T
6. T
is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7.
is measured at 0.4 V for all outputs as shown in Figure 7.
HKH
HKL
7. The time is specified from when V
and operating within specification.
achieves its normal operating level (typical condition V
= 3.3 V) until the frequency output is stable
DDQ
DDQ
8. T
and T are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V (1 mA) JEDEC specification.
HFALL OL OH
HRISE
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Test load is Rs = 33.2 Ω, Rp = 49.9 Ω.
12.Must be guaranteed in a realistic system environment.
13.Configured for V = 0.71 V in a 50 Ω environment.
OH
14.Measured at crossing points.
15.Measured at 20% to 80%.
16.Determined as a fraction of 2* (Trp–Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
17.Voltage measure point (Vm = 1.25 V). V = 2.5 V.
DD
18.Voltage measure point (Vm = 1.5 V). V = 3.3 V.
DD
19.All offsets are to be measured at rising edges.
20.Parameters are guaranteed by design.
11
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
AC WAVEFORMS
V
I
V
V
V
V
= 1.25 V @ V
and 1.5 V @ V
M
X
Y
DDL DD3
= V + 0.3 V
SEL1,
SEL0
OL
V
t
M
= V –0.3 V
OH
and V are the typical output voltage drop that occur with the
OL
OH
GND
output load.
t
PLZ
PZL
V
V
DD
DDQ2
OUTPUT
LOW-to-OFF
OFF-to-LOW
1.25V
CPUCLK
@133MHz
V
M
V
V
SS
V
X
V
OL
t
PHZ
t
PZH
DDQ3
3v66
@66MHz
V
1.5V
OH
V
Y
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
SS
V
M
CPU leads 3V66
V
T
SS
HPOFFSET
Outputs
enabled
Outputs
enabled
Outputs
disabled
SW00569
SW00571
Figure 1. Host clock
Figure 3. State enable and disable times
COMPONENT
MEASUREMENT
POINTS
2.5VOLT MEASURE POINTS
V
DDQ2
V
= 2.0V
OH
V
= 1.7V
IH
1.25V
V
= 0.7V
IL
V
= 0.4V
OL
SYSTEM
MEASUREMENT
POINTS
V
SS
COMPONENT
MEASUREMENT
POINTS
3.3VOLT MEASURE POINTS
V
DDQ3
V
= 2.4V
OH
V
= 2.0V
IH
1.5V
= 0.7V
V
IL
V
= 0.4V
OL
SYSTEM
MEASUREMENT
POINTS
V
SS
SW00570
Figure 2. 3.3 V clock waveforms
12
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
S
1
V
DD
2<V
DD
Open
V
SS
500Ω
500Ω
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
T
L
TEST
/t
S
1
t
Open
PLH PHL
t
/t
2<V
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
or V
, DEPENDS ON THE OUTPUT
DDQ3
DDQ2
SW00572
Figure 4. Load circuitry for switching times
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48 MHz)
SW00573
Figure 5. Power management
13
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
S
1
V
DD
2<V
DD
Open
V
SS
500Ω
500Ω
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
T
L
TEST
/t
S
1
t
Open
PLH PHL
t
/t
2<V
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
or V
, DEPENDS ON THE OUTPUT
DDQ3
DDQ2
SW00574
Figure 6. Host clock measurements
T
HKP
DUTY CYCLE
T
HKH
2.0 V
1.25 V
0.4 V
2.5 V CLOCKING
INTERFACE
T
HKL
T
T
FALL
RISE
T
PKP
DUTY CYCLE
T
PKH
2.4 V
1.5 V
0.4 V
3.3 V CLOCKING
INTERFACE
(TTL)
T
PKL
T
T
FALL
RISE
SW00575
Figure 7. 2.5 V/3.3 V clock waveforms
14
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
15
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 11-00
Document order number:
9397 750 07818
Philips
Semiconductors
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