PCU9669B [NXP]

I2C BUS CONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48;


型号：	PCU9669B
厂家：	NXP
描述：	I2C BUS CONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48 时钟数据传输驱动外围集成电路驱动器
文件：	总69页 (文件大小：1310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCU9669

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus

controller

Rev. 2 — 1 July 2011

Product data sheet

1. General description

The PCU9669 is an advanced single master mode I²C-bus controller. It is a fourth

generation bus controller designed for data intensive I²C-bus data transfers. It has three

independent I²C-bus channels, one of them with data rates up to 1 Mbits/s using the

Fast-mode Plus (Fm+) open-drain topology and two with a much larger transmit only

transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus with push-pull

topology. Each channel has a generous 4352 byte data buffer which makes the PCU9669

the ideal companion to any CPU that needs to transmit and receive large amounts of

serial data with minimal interruptions.

The PCU9669 is a 8-bit parallel-bus to I²C-bus protocol converter. It can be configured to

communicate with up to 64 slaves in one serial sequence with no intervention from the

CPU. The controller also has a sequence loop control feature that allows it to

automatically retransmit a stored sequence.

Its onboard oscillator and PLL allow the controller to generate the clocks for the I²C-bus

and for the interval timer used in sequence looping. This feature greatly reduces CPU

overhead when data refresh is required in fault tolerant applications.

An external trigger input allows data synchronization with external events. The trigger

signal controls the rate at which a stored sequence is re-transmitted over the I²C-bus.

Error reporting is handled at the transaction level, channel level, and controller level.

A simple interrupt tree and interrupt masks allow further customization of interrupt

management.

The controller parallel bus interface runs at 3.3 V and the I²C-bus I/Os logic levels are

referenced to a dedicated V_DD(IO)input pin with a range of 3.0 V to 5.5 V.

2. Features and benefits

 Parallel-bus to I²C-bus protocol converter and interface

 5 Mbit/s unidirectional data transfer on Ultra Fast-mode (UFm) channel (push-pull

driver)

 1 Mbit/s and up to 30 mA SCL/SDA I_OLFast-mode Plus (Fm+) capability

 Internal oscillator trimmed to 1 % accuracy reduces external components

 Individual 4352-byte buffers for the Fm+ and UFm channels for a total of 13056 bytes

of buffer space

 Three levels of reset: individual software channel reset, global software reset, global

hardware RESET pin

 Communicates with up to 64 slaves in one serial sequence

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

 Sequence looping with interval timer

 Supports SCL clock stretching (Fm+ only)

 JTAG port available for boundary scan testing during board manufacturing process

 Trigger input synchronizes serial communication exactly with external events

 Maskable interrupts

 Fast-mode Plus I²C-bus capable and compatible with SMBus

 Operating supply voltage: 3.0 V to 3.6 V (device and host interface)

 I²C-bus I/O supply voltage: 3.0 V to 5.5 V

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 ESD protection exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Packages offered: LQFP48

3. Applications

 Add I²C-bus port to controllers/processors that do not have one

 Add additional I²C-bus ports to controllers/processors that need multiple I²C-bus ports

 Converts 8 bits of parallel data to serial data stream to prevent having to run a large

number of traces across the entire printed-circuit board

 Entertainment systems

 LED matrix control

 Data intensive I²C-bus transfers

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

Description

Version

PCU9669B

PCU9669 LQFP48

plastic low profile quad flat package;

SOT313-2

48 leads; body 7  7  1.4 mm

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

2 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

5. Block diagram

CE WR RD INT RESET

Channel 0

PCU9669

Fm+ I C-bus control

STATUS0_[n]

CONTROL

CHSTATUS

INTMSK

SDA0

SCL0

TRIG

SLATABLE

TRANCONFIG

DATA

TRANSEL

TRANOFS

BYTECOUNT

FRAMECNT

REFRATE

SCLL

SCLH

MODE

TIMEOUT

PRESET

INTERRUPT

CONTROL

BUFFER

CONTROL

4352-BYTE

BUFFER

BUS

INTERFACE

Channel 1

UFm I C-bus control

STATUS1_[n]

CONTROL

CHSTATUS

INTMSK

SLATABLE

TRANCONFIG

DATA

TRANSEL

TRANOFS

BYTECOUNT

FRAMECNT

REFRATE

SCLPER

USDA1

USCL1

CTRLSTATUS

CTRLINTMSK

DEVICE_ID

CTRLPRESET

CTRLRDY

4352-BYTE

BUFFER

CONTROL BLOCK

SDADLY

MODE

PRESET

POWER-ON/

POWER-DOWN

RESET

Channel 2

DC/DC

UFm I C-bus control

REGULATOR

STATUS2_[n]

CONTROL

CHSTATUS

INTMSK

SLATABLE

TRANCONFIG

DATA

USDA2

USCL2

TCK

TRST

TMS

TDI

JTAG

TDO

TRANSEL

TRANOFS

BYTECOUNT

FRAMECNT

REFRATE

SCLPER

OSCILLATOR

PLL

4352-BYTE

BUFFER

DD(IO)

SDADLY

MODE

PRESET

002aaf479

Fig 1. Block diagram

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

3 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

6. Pinning information

6.1 Pinning

RESET

TRIG

31 WR

PCU9669B

SCL0

SDA0

USCL1

USDA1

002aaf480

Fig 2. Pin configuration for LQFP48

6.2 Pin description

Table 2.

Pin description

Symbol Pin

Type

Description

Address inputs: selects the bus controller’s internal registers and

ports for read/write operations. Address is registered when CE is

LOW and whether WR or RD transitions LOW. A0 is the least

significant bit.

I/O

Data bus: bidirectional 3-state data bus used to transfer

commands, data and status between the bus controller and the

host. D0 is the least significant bit. Data is registered on the rising

edge of WR when CE is LOW.

PCU9669

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Product data sheet

Rev. 2 — 1 July 2011

4 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

Table 2.

Pin description …continued

Symbol Pin

Type

Description

TRST

TMS

JTAG test reset input. For normal operation, hold LOW (V_SS).

JTAG test mode select input. For normal operation, hold HIGH

(V_DD).

TCK

TDI

JTAG test clock input. For normal operation, hold HIGH (V_DD).

JTAG test data in input. For normal operation, hold HIGH (V_DD).

TDO

JTAG test data out output. For normal operation, do not connect

(n.c.).

INT

Interrupt request: Active LOW, open-drain, output. This pin

requires a pull-up device.

Channel 2 Ultra Fast-mode I²C-bus serial data output.

USDA2 21

Push-pull drive. No pull-up device is needed.

Channel 2 Ultra Fast-mode I²C-bus serial clock output.

USCL2

Push-pull drive. No pull-up device is needed.

Channel 1 Ultra Fast-mode I²C-bus serial data output.

USDA1 25

Push-pull drive. No pull-up device is needed.

Channel 1 Ultra Fast-mode I²C-bus serial clock output.

USCL1

SDA0

SCL0

Push-pull drive. No pull-up device is needed.

Channel 0 I²C-bus serial data input/output (open-drain).

I/O

This pin requires a pull-up device.

Channel 0 I²C-bus serial clock input/output (open-drain).

This pin requires a pull-up device.

Write strobe: When LOW and CE is also LOW, the content of the

data bus is loaded into the addressed register. Data are latched on

the rising edge of WR. CE may remain LOW or transition with WR.

Read strobe: When LOW and CE is also LOW, causes the

contents of the addressed register to be presented on the data

bus. The read cycle begins on the falling edge of RD. Data lines

are driven when RD and CE are LOW. CE may transition with RD.

Chip Enable: Active LOW input signal. When LOW, data transfers

between the host and the bus controller are enabled on D0 to D7

as controlled by the WR, RD and A0 to A7 inputs. When HIGH,

places the D0 to D7 lines in the 3-state condition.

During the initialization period, CE must transition with RD until

controller is ready.

TRIG

Trigger input: provides the trigger to start a new frame.

RESET 36

Reset: Active LOW input. A LOW level resets the device to the

power-on state. Internally pulled HIGH through weak pull-up

current.

V_DD(IO)

power I/O power supply: 3.0 V to 5.5 V. Power supply reference for

I²C-bus pins. Sets the voltage reference point for V_IL/V_IHand the

output drive rail for the UFm channel.

V_SS(IO)

V_DD

power I/O supply ground. Can be tied to V_SS.

7, 18, 30, power Power supply: 3.0 V to 3.6 V. All V_DDpins should be connected

40, 44, 48 together externally.

V_SS

8, 19, 29, power Supply ground. All V_SSpins should be connected together

35, 39,

43, 47

externally.

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

5 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

7. Functional description

7.1 General

The PCU9669 acts as an interface device between standard high-speed parallel buses

and the serial I²C-bus. On the I²C-bus, it acts as a master. Data transfer between the

I²C-bus and the parallel-bus host is carried out on a buffered basis, using either an

interrupt or polled handshake.

7.2 Internal oscillator and PLL

The PCU9669 contains an internal 12.0 MHz oscillator and 156 MHz PLL which are used

for all internal and I²C-bus timing. The oscillator and PLL require up to t_init(po)to start up

and lock after power-up. The oscillator is not shut down if the serial bus is disabled.

7.3 Buffer description

Remark: In the following section a ‘transaction’ is defined as a contiguous set of

commands and/or data sent/received to/from a single slave. A ‘sequence’ is a set of

transactions stored in the buffer.

The PCU9669 channels have individual 4352-byte data buffers (see Section 7.3.2 “Buffer

sizes”) that allow several transactions to be executed before an interrupt is generated.

This allows the host to request several transactions (up to maximum buffer size on each

channel) in a single sequence and lets the PCU9669 perform it without the intervention of

the host each time a requested transaction is performed. The host can then perform other

tasks while the PCU9669 executes the requested sequences.

By following a simple procedure, the I²C-bus controller can store several I²C-bus

transactions directed to different slaves addresses on any of the channels. The

transaction stored in the buffer can be of any type, thus reads and writes can be interlaced

in a sequence. When multiple slave reads are requested in a sequence, the read data is

stored in-line in the sequence and the buffer number must be specified in the TRANSEL

to provide the read location and the TRANOFS byte offset value. By default, the

TRANOFS is set to 00h. So let us consider the scenario where the host has done the

initialization (mode, masks, and other configuration) and writes data into the buffer of one

of the three channels.

The host starts by programming the buffer configuration registers TRANCONFIG (number

of slaves and bytes per slave) and then the SLATABLE (slave addresses). Then the host

programs the TRANSEL (Transaction Data Buffer Selection) and the TRANOFS (byte

offset selection) to 00h to set the memory pointers to the beginning of the buffer (the

default value is 00h after a power-on or RESET). Next, the host transfers the data into

DATA until the entire sequence is loaded. If the transaction is a read transaction, the host

must write a dummy byte (i.e., FFh) for each expected serial read byte to reserve the

memory space in the buffer for the transaction.

Care should be taken so as to not overflow the buffer with excessive read/write

commands. In the event of an overflow, represented by the BE bit in the CTRLSTATUS

CTRLINTMSK register is logic 0. To recover the channel, a channel reset is required. All

configuration and data needs to be checked by the host and resent to the I²C-bus

controller. (See Section 7.3.2 “Buffer sizes”.)

PCU9669

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Product data sheet

Rev. 2 — 1 July 2011

6 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

After sending all the commands and data it wanted to the I²C-bus controller, the host

could either continue to program data for other channels or write to the CONTROL

on the I²C-bus in the order in which the slave addresses are listed in the SLATABLE,

separated by a RESTART condition. The last transaction in the sequence will end with a

STOP condition.

If during a READ command a NACK on the slave address is received, the buffer space

allocated for the read will remain untouched and will contain the last information written in

that location. A buffer read on the parallel bus should only be done after a valid buffer

state is reached to guarantee data valid (see Section 7.5.1.1 “STATUS0_[n],

STATUS1_[n], STATUS2_[n] — Transaction status registers”).

To program data for another channel, that channel is selected and data programmed as

described above. One or more channels can be busy with serial transmission while

additional parallel-bus data is sent to the buffer of an idle channel.

7.3.1 Buffer management assumptions

• Repeated STARTs will be sent between two consecutive transactions.

• After the last operation on a channel is completed, a STOP will be sent.

• In a READ transaction, after the last data byte has been received from a particular

slave, a NACK is sent to the slave.

7.3.2 Buffer sizes

The PCU9669 channels have individual buffers assigned to them. The contents of the

buffers should only be modified during channel idle states.

The memory allocation is 4352 bytes per channel.

The buffer sizes represent the memory allocated for the data block only. The slave

address table and configuration bytes are contained in other locations and do not need to

be included in the required buffer size calculation.

For example, to calculate the size of the memory needed to write 26 bytes to 10 slaves

and to read 2 bytes from 4 slaves (no command bytes required for the read):

10 slaves  26 bytes/slave = 260 bytes for the write transactions

4 slaves  2 bytes/slave = 8 bytes for the read transactions

A total of 268 bytes of buffer space is required to complete the sequence.

Remark: Note that the bytes required to store the 30 slave addresses are not included in

the calculation since they are stored in the SLATABLE register.

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

7 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

7.4 Error reporting and handling

In case of any transaction error conditions, the device will load the transaction error status

in the STATUSx_[n], generate an interrupt, if unmasked, by pulling down the INT pin and

update the CHSTATUS and CTRLSTATUS registers. The status for the individual SLA

addresses will be stored in the STATUSx_[n] registers.

In the event of a NACK from a slave, there are two possible courses of action. The first is

that an interrupt will be generated and the current transaction and sequence terminated.

The second is that while the WEMSK and/or REMSK is a logic 1, a NACKed byte will be

ignored, and the transmission will continue with the next transaction in the sequence until

the end of the sequence. The controller will skip the slave address and/or data where the

NACK occurred and move on to the next transaction in the sequence. Any error will be

reported in the corresponding STATUSx_[n] register (where ‘n’ is the buffer number of the

slave) or the CHSTATUS or CTRLSTATUS registers.

7.5 Registers

The PCU9669 contains several registers that are used to configure the operation of the

device, status reporting, and to send and receive data. The device also contains global

registers for chip level control and status reporting.

The STATUSx_[n] registers are channel-level direct access registers. The DATA,

SLATABLE, TRANCONFIG, and BYTECOUNT registers are auto-increment registers.

The memory access pointer to the DATA registers can be programmed using the

TRANSEL and TRANOFS registers. See Section 7.5.1.2 “CONTROL — Control register”,

for information on the pointer reset bits BPTRRST and AIPTRRST.

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

8 of 69

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Table 3.

PCU9669 register address map - direct register access

Description

Default

Size

while

(bytes)

CH active

Channel status registers

channel 0 transaction number STATUS0_[n]

(hex)

individual transaction status (direct address)

00h

channel 1 transaction number STATUS1_[n]

(hex)

individual transaction status (direct address)

([7:2] = 0 in UFm)

channel 2 transaction number STATUS2_[n]

(hex)

individual transaction status (direct address)

([7:2] = 0 in UFm)

Channel 0 (Fm+) registers

CONTROL

CHSTATUS

INTMSK

R/W

yes^[1]

channel 0 control

00h

channel 0 status

R/W

yes

channel 0 interrupt mask

SLATABLE

channel 0 slave address table (auto-increment) 00h

TRANCONFIG R/W

yes, for

channel 0 transaction configuration

00h

TRANCOUNT^[2](auto-increment)

DATA

R/W

yes

channel 0 data (auto-increment)

00h

bufsize^[3]

TRANSEL

TRANOFS

BYTECOUNT

channel 0 transaction data buffer select

channel 0 transaction data buffer byte offset

channel 0 transmitted byte count

(auto-increment)

FRAMECNT

REFRATE

SCLL

R/W

yes

channel 0 frame count

channel 0 frame refresh rate

channel 0 clock LOW state

channel 0 clock HIGH state

channel 0 mode

01h

00h

5Eh

3Fh

92h

00h

SCLH

MODE

TIMEOUT

PRESET

channel 0 time-out

channel 0 parallel reset

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PCU9669 register address map - direct register access …continued

Table 3.

Description

Default

Size

while

(bytes)

CH active

Channel 1 (UFm) registers

CONTROL

CHSTATUS

INTMSK

R/W

yes^[1]

channel 1 control ([7] = 1)

00h

channel 1 status ([5:1] = 0 in UFm)

channel 1 interrupt mask ([5:1] = don’t care)

R/W

yes

SLATABLE

channel 1 slave address table (auto-increment) 00h

TRANCONFIG R/W

yes, for

channel 1 transaction configuration

00h

TRANCOUNT^[2](auto-increment)

DATA

R/W

yes

channel 1 data (auto-increment)

00h

bufsize^[3]

TRANSEL

TRANOFS

BYTECOUNT

channel 1 transaction data buffer select

channel 1 transaction data buffer byte offset

channel 1 transmitted byte count

(auto-increment)

FRAMECNT

REFRATE

SCLPER

SDADLY

MODE^[4]

R/W

channel 1 frame count

channel 1 frame refresh rate

channel 1 clock period

channel 1 SDA delay

channel 1 mode

01h

00h

20h

08h

83h

00h

reserved

PRESET

R/W

yes

channel 1 parallel reset

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PCU9669 register address map - direct register access …continued

Table 3.

Description

Default

Size

while

(bytes)

CH active

Channel 2 (UFm) registers

CONTROL

CHSTATUS

INTMSK

R/W

yes^[1]

channel 2 control ([7] = 1)

00h

channel 2 status ([5:1] = 0 in UFm)

channel 2 interrupt mask ([5:1] = don’t care)

R/W

yes

SLATABLE

channel 2 slave address table (auto-increment) 00h

TRANCONFIG R/W

yes, for

channel 2 transaction configuration

00h

TRANCOUNT^[2](auto-increment)

DATA

R/W

yes

channel 2 data (auto-increment)

00h

bufsize^[3]

TRANSEL

TRANOFS

BYTECOUNT

channel 2 transaction data buffer select

channel 2 transaction data buffer byte offset

channel 2 transmitted byte count

(auto-increment)

FRAMECNT

REFRATE

SCLPER

SDADLY

MODE^[4]

R/W

yes

channel 2 frame count

channel 2 frame refresh rate

channel 2 clock period

channel 2 SDA delay

channel 2 mode

01h

00h

20h

08h

83h

00h

reserved

PRESET

R/W

channel 2 parallel reset

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PCU9669 register address map - direct register access …continued

Table 3.

Description

Default

Size

while

(bytes)

CH active

Global registers

CTRLSTATUS

yes

controller status

master interrupt mask

reserved

00h

08h

00h

E9h

00h

FFh

CTRLINTMSK R/W

reserved

DEVICE_ID

device ID

CTRLPRESET R/W

CTRLRDY^[5]

yes

master parallel reset

controller ready register

[1] Except TP and TE. Changing polarity of TP while TE is active will cause a false trigger.

[2] The transaction count (TRANCONFIG[0]) can be written to during the idle period between sequences.

[3] Refer to Section 7.3.2 “Buffer sizes” for channel memory allocation.

[4] Unused bits in the UFm register set will return 0b when read and writes will be ignored.

[5] Controller ready = FFh immediately after POR or after a hardware reset or global reset. It will clear (00h) once the initialization routine is done.

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

7.5.1 Channel registers

7.5.1.1 STATUS0_[n], STATUS1_[n], STATUS2_[n] — Transaction status registers

STATUS0_[n], STATUS1_[n], and STATUS2_[n] are 8-bit  64 read-only registers that

provide status information for a given transaction. Only the 5 lower bits are used; the

top bits will always read 0. When bits [4:2] are set, a channel interrupt is requested (the

INT pin is asserted LOW). A read to STATUSx_[n] register will clear its status. To clear all

the STATUSx_[n] registers, a byte-by-byte read of all STATUSx_[n] registers is required.

The controller will auto-clear the STATUSx_[n] registers at each START of a sequence

when FRAMECNT = 1 and only at the first START when FRAMECNT  1.

Each register byte can be accessed by direct addressing so that the host can choose to

read the status on one or more individual transactions without having to read all

64 status bytes.

Table 4.

STATUSx_[n] - Transaction status code register bit description

Bit Symbol Description

7:5 ST[7:5] always reads 000

RSN^[1]Read slave NACK. When HIGH, a NACK was received after a slave address was

transmitted on the serial bus on a read transaction. An interrupt will be requested.

WSN^[1]Write slave NACK. When HIGH, a NACK was received after a slave address was

transmitted on the serial bus on a write transaction. An interrupt will be requested.

WDN^[1]Write data NACK. When HIGH, a NACK was received for a data byte during a

write transaction on the serial bus. An interrupt will be requested.

Transaction active. When 1, the transaction is currently active on the serial bus.

No interrupt is requested.

Transaction ready. When 1, a transaction is loaded in the buffer and waiting to be

executed. No interrupt is requested.

[1] Does not apply to the UFm channel.

Remark: When STATUSx_[n] = 00h, no interrupt is requested and the transaction is in the

Done/Idle state.

During program execution, the TR and TA bits behave as follows:

Example, we are to transfer 3 transactions in a sequence. All initialization is completed

(loading of SLA, TRANCONFIG, DATA) and device is ready for serial transfer.

Before the STA bit is set, the STATUSx_[n] register will contain:

STATUSx_[0] = 0

STATUSx_[1] = 0

STATUSx_[2] = 0

STATUSx_[3] = 0

PCU9669

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Product data sheet

Rev. 2 — 1 July 2011

13 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

After STA is set:

STATUSx_[0] = 2

STATUSx_[1] = 1

STATUSx_[2] = 1

STATUSx_[3] = 0

Since there is no timing requirement in setting the STA bit after the initialization, the device

will update the first status when the STA bit is set and will always go from 0 to 2 (Idle to

Transaction active).

7.5.1.2 CONTROL — Control register

CONTROL is an 8-bit register. The STO bit is affected by the bus controller hardware: it is

cleared when a STOP condition is present on the I²C-bus.

Table 5.

CONTROL - Control register bit description

Address: Channel 0 = C0h; Channel 1 = D0h; Channel 2 = E0h.

Legend: * reset value

Bit Symbol

Access Value Description

STOSEQ

R/W

Stop sequence bit.

When the STOSEQ bit is set while the channel is active, a STOP condition will be

transmitted immediately following the end of the current sequence being transferred

on the I²C-bus. No further buffered transactions will be carried out and the channel

will return to the idle state. Normal error reporting will occur up until the last bit. When

a STOP condition is detected on the bus, the hardware clears the STOSEQ flag.

When STOSEQ is reset, no action will be taken.

The START flag.

STA

R/W

When the STA bit is set to begin a sequence, the bus controller hardware checks the

status of the I²C-bus and generates a START condition if the bus is free (does not

apply to the UFm channel). If the bus is not idle, then INT will go LOW and the

CHSTATUS register will contain a bus error code (either DAE or CLE will be set).

The STA bit may be set only at a valid idle state. The controller will reset the bit under

the following conditions:

• A sequence is done and FRAMECNT = 1.

• A sequence loop is done and FRAMECNT > 1.

• The STOSEQ bit is set, FRAMECNT = 0, and the current sequence is done.

• The STOSEQ bit is set, FRAMECNT > 1, and the current sequence is done.

• The STO bit is set and the current byte transaction is done. This bit cannot be

set if the CHEN bit is 0.

When the STA bit is reset, no START condition will be generated.

The STOP flag.

STO

R/W

When the STO bit is set while the channel is active, a STOP condition will be

transmitted immediately following the current data or slave address byte being

transferred on the I²C-bus. If a read is in progress, a NACK will be generated before

the STOP. No further buffered transactions will be carried out and the channel will

return to the idle state. Normal error reporting will occur up until the last bit.

When a STOP condition is detected on the bus, the hardware clears the STO flag.

When the STO bit is reset, no action will be taken.

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Table 5.

CONTROL - Control register bit description …continued

Address: Channel 0 = C0h; Channel 1 = D0h; Channel 2 = E0h.

Legend: * reset value

Bit Symbol

Access Value Description

R/W

Trigger polarity bit. Cannot be changed while channel is active.

Trigger will be detected on a falling edge.

Trigger will be detected on a rising edge.

R/W

Trigger Enable (TE) bit controls the trigger input used for frame refresh. TE cannot be

changed while channel is active. When the trigger input is enabled, the trigger will

override the contents of the FRAMECNT register and will start triggering when STA

bit is set. Thereafter, when a trigger tick is detected, the controller will issue a START

command and the stored sequence will be transferred on the serial bus.

When TE = 1, the sequence is controlled by the Trigger input.

When TE = 0, the trigger inputs are ignored.

BPTRRST

Resets auto increment pointers for BYTECOUNT. Reads back as 0.

AIPTRRST W

Resets auto increment pointers for SLATABLE and TRANCONFIG. The DATA

and TRANOFS registers. Reads back as 0.

Remark: To reset the data pointer, write 00h to TRANSEL.

Reserved. User must write 0 to this bit.

Remark: Due to a small latency between setting the STA bit and the ability to detect a

trigger pulse, if the STA bit is set simultaneously to an incoming trigger pulse, the pulse

will be ignored and the controller will wait for the next trigger to send the START.

If the STO or STOSEQ bit are set at anytime while the STA bit is 0, then no action will be

taken and the write to these bits is ignored.

Remark: STO has priority over STOSEQ.

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Table 6.

CONTROL register bits STA, STO, STOSEQ operation/behavior

Channel state

(initialization steps)

Next write action by host

FRAMECNT TE STA STO STOSEQ

Results

Idle (reset, TRANCONFIG,

SLATABLE, DATA, STA = 0)

No action.

START transmitted on serial bus followed by

sequence stored in buffer.

Active (reset, load

TRANCONFIG, SLATABLE,

DATA, STA = 1

No change; cannot write STA while active.

When the STO bit is set, two actions are

possible:

1. If the transaction is a read, a STOP is

sent after the first read byte (NACK sent)

and the byte count is updated.

2. If the transaction is a write, a STOP is

sent after the end of ACK cycle of the

current byte and BYTECNT is updated.

The SD bits will be set.

No action.

REFRATE Loop idle (reset,

load TRANCONFIG,

SLATABLE, DATA STA = 1)^[1]

 1

Channel will go immediately to the inactive

state and SD and FLD bits will be set.^[2]

 1

Channel will go immediately to the inactive

state and SD and FLD bits will be set.^[2]

REFRATE Loop active (reset,  1

No action.

load, TRANCONFIG,

 1

STOP at end of current frame. The SD and

FLD bits will be set.

SLATABLE, DATA, STA = 1)

 1

When the STO bit is set, two actions are

possible:

1. If the transaction is a read, a STOP is

sent after the first read byte (NACK sent)

and the byte count is updated.

2. If the transaction is a write, a STOP is

sent after the end of ACK cycle of the

current byte and BYTECNT is updated.

The SD and FLD bits will be set.

No action.

Trigger Loop Idle (reset, load

TRANCONFIG, SLATABLE,

DATA, STA = 1)

STOP at end of current frame. The SD and

FLD bits will be set.

When the STO bit is set, two actions are

possible:

1. If the transaction is a read, a STOP is

sent after the first read byte (NACK sent)

and the byte count is updated.

2. If the transaction is a write, a STOP is

sent after the end of ACK cycle of the

current byte and the BYTECNT is

updated.

The SD and FLD bits will be set.

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Table 6.

CONTROL register bits STA, STO, STOSEQ operation/behavior …continued

Channel state

(initialization steps)

Next write action by host

FRAMECNT TE STA STO STOSEQ

Results

Trigger Loop active (reset, load

TRANCONFIG, SLATABLE,

DATA, STA = 1)

No action.

Channel will go immediately to the inactive

state and SD and FLD bits will be set.^[2]

Channel will go immediately to the inactive

state and SD and FLD bits will be set.^[2]

[1] Loop Idle is defined as the time elapsed from a STOP to the START of the next sequence while STA = 1.

[2] Channel Active is defined by the CTRLSTATUS[5:3] bits.

7.5.1.3 CHSTATUS — Channel status register

CHSTATUS is an 8-bit read-only register that provides status information for a given

channel. Some of these status bits are error codes that cannot be masked (NMI) by the

INTMSK register and need attention from the host. All these status drive the INT pin

active LOW. To clear the individual channel interrupt request, you must read the

CHSTATUS register. The BE interrupt is cleared by reading the CTRLSTATUS register.

After the CHSTATUS register is cleared, only new errors or status updates will cause the

CHSTATUS bits to be set.

Table 7.

CHSTATUS - Channel and buffer status codes register bit description

Address: Channel 0 = C1h; Channel 1 = D1h; Channel 2 = E1h.

Bit Symbol Description

Sequence Done. The sequence loaded in the buffer was sent and STOP issued

on the serial bus.

FLD

WE^[1]

RE^[1]

Frame Loop Done. The FRAMECNT value has been reached. A STOP has been

issued on the bus.

Write Error detected in transaction. An SLA NACK or data NACK was detected in

a write transaction of the sequence.

Read Error detected in transaction. An SLA NACK was detected in a read

transaction of the sequence.

DAE^[1]

CLE^[1]

SSE^[1]

Bus error, SDA stuck LOW.

Bus error, SCL stuck LOW.

Bus error, illegal START or STOP detected.

Frame Error detected. The time required to send the sequence exceeds refresh

rate programmed to the REFRATE register or the time between trigger ticks.

[1] Does not apply to UFm channel. Always read as logic 0.

The DAE, CLE and SSE bits correspond to bus error states, and the FE bit corresponds to

host programming errors.

DAE - SDA error bit: This bit indicates that the SDA line is stuck LOW when the

PCU9669 is trying to send a START condition.

CLE - SCL error bit: This bit indicates that the SCL line is stuck LOW.

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SSE - illegal START/STOP detected bit: This bit indicates that a bus error has occurred

during a serial transfer. A bus error is caused when a START or STOP condition occurs at

an illegal position in the format frame. Examples of such illegal positions are during the

serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may

also be caused when external interference disturbs the internal PCU9669 signals.

FE - Frame Error bit: This bit indicates that the time required to send the sequence

exceeds the refresh rate programmed in the REFRATE register or the time between

trigger ticks. Solving frame errors include programming longer refresh rates, speeding up

the bus frequency, shortening the amount of bytes sent/received in the sequence, or

increasing the time between trigger ticks. If the frame error is masked by the FEMSK, the

device will continue to transmit transactions until the end of the sequence without

re-starting the sequence even if new triggers are detected. The total number of sequences

transmitted will be the number stored in the FRAMECNT register. Once a complete

sequence is transmitted, a new sequence will initiate when a subsequent trigger appears.

The FE flag will be held HIGH and sequences will still be transmitted unless CHSTATUS is

read. If the frame error is unmasked, the sequence will be aborted at the next logical

stopping point (i.e., for a read transaction a NACK will be sent), a STOP transmitted and

an interrupt will be generated. Since the controller terminates the sequence in a controlled

mechanism, there may be a 2-byte delay if a frame error (FE) is detected during a read

transaction. The FE bit is set after the STOP is detected on the bus.

sequence A

10 ms

sequence A

10 ms

sequence A

10 ms

time

002aaf247

a. Sequence fully executed within the period programmed in REFRATE register

frame error detected, data not sent after FE

sequence B

time

10 ms

002aaf627

This condition causes a frame error and the FE bit to be set.

b. Sequence exceeds period programmed in REFRATE register, FEMSK = 0

frame error detected, FEMSK = 1, data sent after FE

sequence C

10 ms

sequence C

time

10 ms

002aaf628

c. Sequence exceeds period programmed in REFRATE register, FEMSK = 1

Fig 3. Frame Error detection

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Table 8.

Error detection operation/behavior

Channel state

AR (MODE Error detected

Next Action

(CHSTATUS)

DAE CLE SSE

Active or idle

Interrupt set, if a transaction is active it will be

immediately aborted and no further action taken by

controller. Host to re-initialize bus (i.e., force a bus

recovery), reset slaves, or take other appropriate

recovery action. After bus is recovered, host to

re-start transaction.

Active or idle, time-out enabled,

and clock line is LOW

Interrupt set, active transaction will be immediately

aborted and no further action taken by controller.

No bus recovery possible by bus-controller. Host to

recover bus by resetting slaves or system. After

bus is recovered, host to re-start transaction.

Active and at a START or

repeated-START condition

Interrupt not set, active transaction will be

immediately aborted and a bus recovery will be

attempted by the bus-controller. If successful, a

start will be issued automatically and the serial

transfer will continue normally at the location of the

failed transaction. No host action is required.

Interrupt set, an auto-recovery was attempted and

failed. Active transaction will be immediately

aborted and the bus-controller determines bus

recovery actions, for example setting the BR bit or

resetting the slaves.

Interrupt set, active transaction will be immediately

aborted and no bus recovery will be attempted by

the bus-controller. Host may attempt a bus

recovery by setting the BR bit or determine other

bus recovery action.

7.5.1.4 INTMSK — Interrupt mask register

Through the INTMSK register, there is the option to manage which states generate an

interrupt, allowing more control from the host on the transaction. The interrupt mask

applies to all transactions in a given channel. A bit set to 1 indicates that the mask is

active. The INTMSK register default is all interrupts are un-masked (00h).

Table 9.

INTMSK - Interrupt mask register bit description

Address: Channel 0 = C2h; Channel 1 = D2h; Channel 2 = E2h.

Bit

Symbol

Description

SDMSK

Sequence Done Mask. The end of sequence interrupt will not be generated.

FLDMSK Frame loop done mask. A frame loop done interrupt will not be generated. The

controller will enter the idle state.

WEMSK^[1]Write Error Mask. An SLA NACK or data NACK interrupt will not be generated

and the controller will skip the remaining write data in the transaction and

continue with the START of the next transaction in the sequence.

REMSK^[1]Read Error detected in transaction. An SLA NACK interrupt will not be

generated and the controller will skip the read transaction and continue with

the START of the next transaction in the sequence.

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Table 9.

INTMSK - Interrupt mask register bit description …continued

Address: Channel 0 = C2h; Channel 1 = D2h; Channel 2 = E2h.

Bit

3:1

Symbol

Description

reserved

FEMSK

Frame Error Mask. A frame error interrupt will not be generated.

Remark: Use caution and good judgement when using this mask.

Unexpected/erratic behavior may result in the slave devices.

[1] Does not apply to UFm channel.

7.5.1.5 SLATABLE — Slave address table register

SLATABLE is an 8-bit  64 register set that makes up a table that stores the slave address

for each transaction in the sequence. The table is loaded by using an auto-increment

pointer that is not user-accessible. To reset the pointer, the AIPTRRST bit must be set in

the CONTROL register. The slave addresses in the SLATABLE register are stored with a

zero-based (N  1) index. The first slave address occupies the 00h position.

Remark: Slave address entries greater than the transaction count are not part of the

sequence. TRANCONFIG[0] contains the transaction count that will be included in the

sequence.

Table 10. SLATABLE - Slave address table register bit description

Address: Channel 0 = C3h; Channel 1 = D3h; Channel 2 = E3h.

Bit

7:1

Symbol

SLATABLE[7:1] Slave address.

SLATABLE[0] When 1, a read transaction is requested.

When 0, a write transaction is requested.

Description

Table 11. Example of SLATABLE registers

Transaction

Slave address

00h

01h

02h

03h

04h

10h

12h

28h

40h

14h

3Fh

36h

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7.5.1.6 TRANCONFIG — Transaction configuration register

The TRANCONFIG register is an 8-bit  65 register set that makes up a table that

contains the number of transactions that will be executed in a sequence and the number

of data bytes involved in the transaction.

The first byte of the register is the Transaction Count register. The remaining 64 registers

are the Transaction Length registers.

Table 12. TRANCONFIG, byte 0 - Transaction configuration register bit description

Address: Channel 0 = C4h; Channel 1 = D4h; Channel 2 = E4h.

Bit

Symbol

Description

7:0

Number of transactions in the sequence. Maximum is 40h.

Table 13. TRANCONFIG, byte 1 to 40h - Transaction configuration register bit description

Bit

Symbol

Description

7:0

Number of bytes per transaction in the sequence. Maximum is FFh.

Table 14. Example of TRANCONFIG register loaded

Value

10h

0Ah

12h

28h

40h

Description

Transaction count

Transaction length 00h

Transaction length 01h

Transaction length 02h

Transaction length 03h

16 transactions = 16 slave addresses in the SLATABLE

10 byte transaction

18 byte transaction

40 byte transaction

64 byte transaction

Transaction length 3Fh

12h

18 byte transaction

Remark: Even if the Transaction length (TRANCONFIG[1:40h]) and the

SLATABLE([0:3Fh]) are fully initialized, only the specified number of transactions in the

Transaction count (TRANCONFIG[0]) will be part of the sequence.

If the Transaction count is 0, then there will be no activity on the serial bus if the STA bit is

set. In addition, there will be no interrupts generated or status updated. The controller will

simply reset the CONTROL.STA bit without performing any transactions.

If the Transaction length is 0, a read transaction will be skipped and a write transaction will

send the slave address plus write bit (SLA+W) on the serial bus with no data bytes.

7.5.1.7 DATA — I²C-bus Data register

DATA is an 8-bit read/write, auto-increment register. It is the interface port to the channel

buffer. When accessing the buffer, the host writes a byte of serial data to be transmitted or

reads bytes that have just been received at this location. The host can read from the

DATA at any time and can only write to this 8-bit register while the channel is idle.

Remark: Reading the DATA when the serial interface is active may return outdated or

erroneous data.

The host can read or write data up to the amount of memory space allotted to the channel.

The location at which the data is accessed is stored in the TRANSEL and TRANOFS

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To return to the data location pointed by the contents of the TRANSEL and TRANOFS

(auto-increment pointer reset) bit in the control register.

To return to the first DATA register location in the buffer set the TRANSEL to 00h.

Table 15. DATA - Data register bit description

Address: Channel 0 = C5h; Channel 1 = D5h; Channel 2 = E5h.

Bit

Symbol Description

D[7:0] Eight bits to be transmitted or just received. A logic 1 in DATA corresponds to a

HIGH level on the I²C-bus. A logic 0 corresponds to a LOW level on the bus.

7:0

7.5.1.8 TRANSEL — Transaction data buffer select register

The TRANSEL register is used to select the pointer to a specific transaction in the DATA

buffer. This allows the user to update the data of a specific slave without having to re-write

the entire data buffer or to read back the stored serial data from a read transaction. The

value of this register is the slave address position in the SLATABLE register. The

TRANSEL register is zero-based (N  1) register.

For example, if a change to the 22nd slave address data is required, the host would set

the TRANSEL register to 15h. This register can be used in conjunction with the

TRANSOFS register to access a specific byte in the data buffer. The host would then

proceed to write the new data to the DATA register. The auto-increment feature continues

to operate from this new position in the DATA register.

Setting TRANSEL to an uninitialized TRANCONFIG entry may cause a request to

read/write data outside the data buffer. If this occurs, the BE bit in the CTRLSTATUS

When a new transaction is selected by programming the TRANSEL registers, the

TRANSOFS register will automatically be reset to 00h.

Remark: When updating the data buffer, if the number of bytes to be updated or read

exceeds the number of bytes that were specified in the TRANCONFIG register, the

auto-increment will go over the transaction boundary into the next transaction stored in

the buffer.

Remark: To reset the DATA pointer, write 00h to the TRANSEL register.

Table 16. TRANSEL - Transaction data buffer select register bit description

Address: Channel 0 = C6h; Channel 1 = D6h; Channel 2 = E6h.

Bit

Symbol

Description

Reserved.

5:0

TRANSEL[5:0] Slave address position in the SLATABLE. The maximum number is 3Fh.

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7.5.1.9 TRANOFS — Transaction data buffer byte select register

In conjunction with the TRANSEL register, the TRANOFS register is used to select the

pointer to a specific byte in a transaction in the data buffer. This allows the user to read or

re-write a specific data byte of a specific slave without having to read/re-write the entire

data buffer. The TRANOFS register is zero-based (N  1), so the maximum bytes this

For example, if the tenth byte in the 40th slave address data is required, the host would

set the TRANSEL register to 27h and the TRANSOFS register to 09h. The host would

then proceed with a read to the DATA register.

Setting TRANOFS to a byte offset outside of the data buffer will cause the BE bit in the

CTRLSTATUS register will be set to a logic 1. Write data will be ignored and read data will

be invalid.

Remark: The number of bytes to be updated or read should not exceed the number of

bytes that were specified in the TRANCONFIG register. Doing so will cause the

auto-increment to go over the transaction boundary into the next transaction stored in the

buffer.

Table 17. TRANOFS - Transaction data buffer byte select register bit description

Address: Channel 0 = C7h; Channel 1 = D7h; Channel 2 = E7h.

Bit

Symbol

Description

7:0

TRANOFS[7:0]

Byte index for the specified transaction buffer in TRANSEL.

7.5.1.10 BYTECOUNT — Transmitted and received byte count register

The BYTECOUNT register stores the number of bytes that have been sent or received.

The count is continuously updated, therefore the BYTECOUNT is a real time reporting of

transmitted and received bytes. This is a read-only register. The BYTECOUNT includes

only the bytes that have been ACKed in a write transaction and all bytes received in a

read transaction including in transactions where the WEMSK or REMSK are enabled and

part or complete transactions have been skipped (see Figure 9). The BYTECOUNT

Table 18. BYTECOUNT, byte 0 - Transaction configuration register bit description

Address: Channel 0 = C8h; Channel 1 = D8h; Channel 2 = E8h.

Bit

Symbol

Description

7:0

BYTECOUNT[7:0]

Number of bytes sent/received per transaction in the sequence.

Maximum is FFh.

7.5.1.11 FRAMECNT — Frame count register

Table 19. FRAMECNT - Frame count register bit description

Address: Channel 0 = C9h; Channel 1 = D9h; Channel 2 = E9h.

Bit

Symbol

Description

7:0

FRAMECNT[7:0] Bit 7 to bit 0 indicate the number of times buffered commands are to be

re-transmitted. Default is 01h.

This register is a read/write register. The contents of this register holds the programmed

value by the host and is not a real-time count of frames sent on the serial bus.

If the FRAMECNT is 00h, the sequence stored in the buffer will loop continuously. A

STOP will be sent at the end of each sequence.

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If the FRAMECNT is 01h, it is defined as the default state and the sequence stored in the

buffer will be sent once and a STOP will be sent at the end of the sequence.

If the FRAMECNT is greater than 01h, the sequence stored in the buffer will loop

FRAMECNT times and a STOP will be sent at the end of each sequence.

Remark: The FRAMECNT can only be set to loop on the sequence stored in the buffer.

7.5.1.12 REFRATE — Refresh rate register

The REFRATE register defines the time period between each sequence start when

REFRATE looping is enabled (FRAMECNT  1, and TE = 0).

The refresh period defined by REFRATE should always be programmed to be greater

than the time it takes for the sequence to be transferred on the I²C-bus. If the REFRATE

values is too small, the frame error (FE) bit will be set and an interrupt will be requested.

Table 20. REFRATE - Refresh rate register bit description

Address: Channel 0 = CAh; Channel 1 = DAh; Channel 2 = EAh.

Bit

Symbol

Description

7:0

REFRATE[7:0] Bit 7 to bit 0 indicate the sequence refresh period. The resolution is

100 s. The default value is 00h, the timer is disabled, and the sequences

will be sent back-to-back if the FRAMECNT is = 0 or FRAMECNT is > 1.

Remark: If the FRAMECNT is 1, then the refresh rate function will be disabled.

7.5.1.13 SCLL, SCLH and SCLPER, SDADLY — Clock rate registers

Table 21. SCLL - Clock Rate Low register bit description (Standard-mode, Fast-mode,

Fast-mode Plus)

Address: Channel 0 = CBh.

Bit

Symbol

Description

7:0

L[7:0]

Eight bits defining the LOW state of SCL. Default: 94 (5Eh).

Table 22. SCLH - Clock Rate High register bit description (Standard-mode, Fast-mode,

Fast-mode Plus)

Address: Channel 0 = CCh.

Bit

Symbol

Description

7:0

H[7:0]

Eight bits defining the HIGH state of SCL. Default: 63 (3Fh).

The clock rate register for the Standard-mode, Fast-mode, and Fast-mode Plus (Fm+) is

controlled by the SCLL and SCLH registers and the for the Ultra Fast-mode channel by

the SCLPER and SDADLY registers. They define the data rate for the serial bus of the

PCU9669. The actual frequency on the serial bus is determined by t_HIGH(time where SCL

is HIGH), t_LOW(time where SCL is LOW), t_r(rise time), and t_f(fall time) values. Writing

illegal values into the SCLL and SCLH registers or SCLPER registers will cause the part

to operate at the respective maximum channel frequency.

For Standard, Fast, and Fast-mode Plus, t_HIGHand t_LOWare calculated based on the

values that are programmed into SCLH and SCLL registers and the PLL clock frequency.

For UFm mode, the clock is a fixed 50 % duty cycle defined by the SCLPER. In both

cases t_rand t_fare system/application dependent.

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Remark: The MODE register needs to be programmed before programming the SCLL

and SCLH registers in order to know which I²C-bus mode is selected. See Section

7.5.1.14 “MODE — I²C-bus mode register” for more detail.

Fast-mode Plus (Fm+) is the default selected mode at power-up or after reset.

The clock is derived from the internal PLL frequency which is set at 156 MHz (13 OSC

clock). Given a 1 % accuracy on the internal clock, the worst case T_PLLis

---------------------------------------

------------------------------

= 6.347 ns .

12.12 MHz  13

157.56 MHz

Calculating clock settings for Standard, Fast, and Fast-mode Plus:

----------------------------

TOTAL_SCLLH =

 scale factor

(1)

T_PLL freq

The scale factor is set by the MODE register and used in the TOTAL_SCLLH calculation.

The scale factor is 8 for Standard-mode, 4 for Fast-mode, and 1 for Fast-mode Plus.

The SCLL and SCLH can be found by:

SCLL = 0.6  TOTAL_SCLLH

SCLH = 0.4  TOTAL_SCLLH

(2)

(3)

Remark: The contributions for the rise time (t_r) and fall time (t_f) are adjusted internally by

hardware to match the desired frequency. If an invalid number is written to SCLL or SCLH

such that it violates the specification, then the controller will adjust the bus frequency to

the allowable SCLL and SCLH minimums.

Sample resulting SCL frequencies:

Table 23. SCL calculation scale factor

I²C-bus mode

Frequency

100 kHz

Scale factor

Standard

Fast

400 kHz

Fast-mode Plus

1000 kHz

Table 24. Typical SCL frequencies

Data shown under following conditions:

Pull-up resistor R_PU= 500 ; bus capacitance C_b= ~170 pF.

Desired frequency (kHz)

Actual frequency (kHz)

SCLL

SCLH

Standard-mode (Sm)

100

99.3

90.0

80.0

69.5

59.7

50.0

116

129

145

168

194

233

112

132

156

PCU9669

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Table 24. Typical SCL frequencies …continued

Data shown under following conditions:

Pull-up resistor R_PU= 500 ; bus capacitance C_b= ~170 pF.

Desired frequency (kHz)

Actual frequency (kHz)

SCLL

SCLH

Fast-mode (Fm)

400

398.4

348.7

298.2

250.2

198.0

150.1

100.0

350

300

250

200

117

155

233

150

104

156

100

Fast-mode Plus (Fm+)

1000

900

800

700

600

500

400

999.0

900.0

798.3

698.5

599.9

499.5

399.7

100

113

130

152

183

229

105

126

158

Remark: The correct MODE setting should be programmed based on desired frequency

since the bus controller will internally select the appropriate t_rand t_ffor the selected mode.

The minimum I²C-bus frequency is 50 kHz.

Remark: The actual SCL frequency will be affected by the PLL frequency and the bus

load. The controller will adjust the SCL timing by monitoring the rise time on the SCL line

and bring the output frequency as close to the programmed value as possible without

violating the I²C-bus specification for minimum clock HIGH and LOW timing.

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Table 25. SCLPER - Clock Period register bit description (Ultra Fast mode)

Address: Channel 1 = DBh; Channel 2 = EBh.

Bit

Symbol

Description

7:0

L[7:0]

Eight bits defining the clock period (Ultra Fast mode). Default 32 (20h).

Table 26. SDADLY - SDA delay register bit description (Ultra Fast mode)

Address: Channel 1 = DCh; Channel 2 = ECh.

Bit

7:6

5:0

Symbol

H[7:6]

Description

Reserved. Read only read back zero.

Six bits defining the SDA delay (Ultra Fast mode). Default: 8 (08h).

H[5:0]

Calculating clock settings for Ultra Fast mode (UFm):

The clock period is defined as follows (50 % duty cycle):

----------------------------

SCLPER_min

(4)

(5)

T_PLL freq

The data will be delayed with respect to the falling edge of the clock as follows:

SCLPER

----------------------

SDADLY_max

Table 27. Sample clock period and allowable data delay

Frequency

5.0 MHz

4.0 MHz

3.0 MHz

2.0 MHz

1.0 MHz

SCLPER^[1]

SDADLY^[2]

2 to 8

2 to 9

2 to 13

2 to 19

2 to 39

158

[1] The minimum allowable value that can be stored in SCLPER is 32.

[2] The minimum allowable value that can be stored in SDADLY is 2.

The PCU9669 will force a 50 % duty cycle by shifting the contents of the SCLPER register

right by 1.

When the user writes the SCLPER register, the SDADLY will be loaded automatically with

a value ¹⁄₄the value of SCLPER (SCLPER register value right shifted twice). The user can

then overwrite the SDADLY register if desired.

The order in which the registers should be written is first the SCLPER, then the SDADLY

The maximum value for SDADLY is the preferred value to be loaded.

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7.5.1.14 MODE — I²C-bus mode register

MODE is a read/write register. It contains the control bits that select the bus recovery

options, and the correct timing parameters. Timing parameters involved with AC[1:0] are

t_BUF, t_HD;STA, t_SU;STA, t_SU;STO, t_HIGH, t_LOW. The auto recovery and bus recovery bits are

contained in this register. They control the bus recovery sequence as defined in Section

8.5.1 “I²C-bus obstructed by a LOW level on SDA (DAE)”.

Table 28. MODE - I²C-bus mode register bit description

Address: Channel 0 = CDh; Channel 1 = DDh; Channel 2 = EDh.

Bit Symbol Description

CHEN

Channel Enable bit. R/W.

0: Channel is disabled, SCL and SDA high-impedance, USDA and USCL driven

HIGH. All registers are accessible for setup and configuration, however a

sequence cannot be started if the CHEN bit is 0 (STA cannot be set).

1 (default): Channel is enabled.

Reserved.

Bus Recovery. When BR is set to 1, the bus controller will attempt a bus recovery

by sending 9 clock pulses on the bus. Once the bus recovery is complete, the

controller will reset the bit to 0. This bit is not intended to generate random or

asynchronous 9 clock pulses on the bus. This function is performed automatically

when the AR bit is 1.

Auto Recovery.

When AR = 1 (default), the bus controller will automatically attempt to recover the

bus as described in Section 8.5.1 “I²C-bus obstructed by a LOW level on SDA

(DAE)”.

When AR = 0, the bus controller will abort the current transaction and generate an

error code by setting the DAE bit in the CHSTATUS register and pulling the INT

pin LOW.

3:2

Reserved.

Fm+ Channel 0

1:0 AC[1:0] I²C-bus mode selection to ensure proper timing parameters (see Table 29 and

Table 40).

AC[1:0] = 00: Standard-mode AC parameters selected.

AC[1:0] = 01: Fast-mode AC parameters selected.

AC[1:0] = 10 (default): Fast-mode Plus AC parameters selected.

AC[1:0] = 11: Reserved.

UFm Channel 1 and Channel 2

1:0 AC[1:0] I²C-bus mode selection to ensure proper timing parameters (see Table 29 and

Table 40).

AC[1:0] = 00: Reserved.

AC[1:0] = 01: Reserved.

AC[1:0] = 10: Reserved.

AC[1:0] = 11 (default): Ultra Fast-mode AC parameters selected. Read-only

bits.

Remark: CHEN bit value must be changed only when the I²C-bus is idle.

Remark: Any change in the AC[1:0] bits (Fast-mode to Standard-mode, for example) may

cause the HIGH and LOW timings of SCL to be violated. It is then required to program the

SCLL and SCLH registers with values in accordance with the selected mode.

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Remark: The AC[1:0], BR and AR bits are not applicable to the UFm channel, they are

read-only bits. The UFm channel AC parameters are controlled internally.

Table 29. I²C-bus mode selection example

I²C-bus frequency (kHz)^[1]

Scale factor

AC[1:0]

Mode

100

400

1000

Standard

Fast

Fast-mode Plus

reserved

----------------------------------------------------------------------------------------

[1] Using the formula f_SCL

T_PLLSCLL + SCLH  sf + t_r+ t_f

7.5.1.15 TIMEOUT — Time-out register

TIMEOUT is an 8-bit read/write register. It is used to determine the maximum time that

SCL is allowed to be in a LOW logic state before a CLE interrupt is generated.

Remark: The TIMEOUT does not apply to the UFm channel of the controller.

When the I²C-bus interface is operating, TIMEOUT is loaded in the time-out counter at

every LOW SCL transition.

Table 30. TIMEOUT - Time-out register bit description

Address: Channel 0 = CEh.

Bit

Symbol

Description

Time-out enable/disable

TE = 1: Time-out function enabled

TE = 0: Time-out function disabled

6:0

TO[6:0]

Time-out value. The time-out period = (TIMEOUT[6:0] + 1)  200 s.

The time-out value may vary some, and is an approximate value.

The Time-out register can be used in the following cases:

• When the bus controller wants to send a START condition and the SCL line is held

LOW by some other device. Then the bus controller waits a time period equivalent to

the time-out value for the SCL to be released. In case it is not released, the bus

controller concludes that there is a bus error, sets the CLE bit in the CHSTATUS

• The time-out feature starts every time the SCL goes LOW. If SCL stays LOW for a

time period equal to or greater than the time-out value, the bus controller concludes

there is a bus error and behaves in the manner described above. When the I²C-bus

interface is operating, TIMEOUT is loaded in the time-out counter at every SCL

transition. See Section 8.7 “Global reset” for more information.

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7.5.1.16 PRESET — I²C-bus channel parallel software reset register

Table 31. PRESET - I²C-bus channel parallel software reset register bit description

Address: Channel 0 = CFh; Channel 1 = DFh; Channel 2 = EFh.

Bit Symbol

Description

7:0 PRESET[7:0] Read/Write register used during an I²C-bus channel parallel reset command.

PRESET is an 8-bit write-only register. Programming the PRESET register allows the user

to reset each individual PCU9669 channel under software control. The software reset is

achieved by writing two consecutive bytes to this register. The first byte must be A5h while

the second byte must be 5Ah. The writes must be consecutive and the values must match

A5h and 5Ah. If this sequence is not followed as described, the reset is aborted.

The PRESET resets state-machines, registers, and buffer pointers to the default values,

zeroes the TRANCONFIG, SLATABLE, BYTECOUNT, and DATA arrays of the respective

channel and will not reset the entire chip. The parallel bus remains active while a software

reset is active. The user can read the PRESET register to determine when the reset has

completed, PRESET returns all 1s when the reset is active and all 0s when complete.

7.5.2 Global registers

7.5.2.1 CTRLSTATUS — Controller status register

The CTRLSTATUS register reports the status of the controller, including the interrupts

generated by the parallel bus. There are six status bits. When CTRLSTATUS contains

00h, it indicates the idle state and therefore no serial interrupts are requested. The content

of this register is continuously updated during the operation of the controller.

The lower 3 bits represent the channels that have an interrupt request pending. To clear

the individual channel interrupt request, you must read the CHSTATUS register. Bits [5:3]

indicate if a channel is currently active or if it is in the idle state.

Table 32. CTRLSTATUS - Interrupt status register bit description

Address: F0h.

Bit

Symbol

Description

Buffer Error. A buffer error such as overflow has been detected.

CH2ACT

CH1ACT

CH0ACT

CH2INTP

CH1INTP

CH0INTP

Channel 2 is active.

Channel 1 is active.

Channel 0 is active.

Channel 2 interrupt pending.

Channel 1 interrupt pending.

Channel 0 interrupt pending.

Remark: A global reset will reset all channels and configuration settings.

BE - Buffer Error bit: This bit indicates that a buffer error has been detected. For

example, a buffer overflow due to the host programming too many bytes will set this bit. A

software or hardware reset is necessary to recover from a buffer error.

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The buffer error may occur when a data location is being read or written to that has not

previously been configured by the TRANCONFIG register. The buffer error can occur on a

parallel data write or read beyond the buffer capacity, or setting the TRANSEL and

TRANOFS pointers beyond the buffer boundary.

When the DATA register is loaded with data that goes beyond the capacity of the buffer,

the bytes that go over the buffer size will be ignored and a Buffer Error (BE) will be

generated.

Special case: The BE interrupt is cleared by reading the CTRLSTATUS register. All other

interrupts are cleared by reading the respective CHSTATUS register.

FLD

DAE

CLE

SSE

CH0INTP (Fm+)

CH1INTP (UFm)

FLD

CH2INTP (UFm)

002aag093

Fig 4. PCU9669 status reporting logic

See Table 7 for channel status.

7.5.2.2 CTRLINTMSK — Control Interrupt mask register

The CTRLINTMSK masks all interrupts generated by the masked channel. This allows the

host MCU to complete other operations before servicing the interrupt without being

interrupted by the same channel.

Table 33. CTRLINTMSK - Control interrupt mask register bit description

Address: F1h.

Bit

Symbol

Description

BEMSK

Buffer Error Mask. A buffer error interrupt will not be generated.

Remark: Use caution and good judgement when using this mask.

Unexpected/erratic behavior may result in the slave devices.

6:3

reserved

CH2MSK

When this bit is set to 1, all interrupts for the channel will be masked and

the INT pin will not be pulled LOW.

CH1MSK

CH0MSK

When this bit is set to 1, all interrupts for the channel will be masked and

the INT pin will not be pulled LOW.

When this bit is set to 1, all interrupts for the channel will be masked and

the INT pin will not be pulled LOW.

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SDMSK

WEMSK

REMSK

CH0 interrupt

sources and masks

FEMSK

CH0MSK

FLD

FLDMSK

DAE

CLE

SSE

SDMSK

FEMSK

CH1 interrupt

sources and masks

to INT pin

CH1MSK

FLD

FLDMSK

BEMSK

SDMSK

REMSK

CH2 interrupt

sources and masks

FEMSK

CH2MSK

FLD

FLDMSK

002aag094

Fig 5. PCU9669 interrupt logic

See Table 9 for interrupt mask.

7.5.2.3 DEVICE_ID — Device ID

The DEVICE_ID register stores the bus controller part number so it can be identified on

the parallel bus.

Table 34. DEVICE_ID - Device ID register bit description

Address: F6h.

Bit

Symbol

Description

U/A

Selects PCU or PCA device.

1 = PCU96xx

0 = PCA96xx

6:0

BCD

BCD (Binary Coded Decimal) code of the ending 2 digits for ID.

Range is 00h to 79h. The code for the PCU9669 is E9h.

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7.5.2.4 CTRLPRESET — Parallel software reset register

Table 35. CTRLPRESET - Parallel software reset register bit description

Address: F7h.

Bit

Symbol

Description

7:0

CTRLPRESET[7:0] Write-only register used during a device parallel reset command.

CTRLPRESET is an 8-bit write-only register. Programming the CTRLPRESET register

allows the user to reset the PCU9669 under software control. The software reset is

achieved by writing two consecutive bytes to this register. The first byte must be A5h while

the second byte must be 5Ah. The writes must be consecutive and the values must match

A5h and 5Ah. If this sequence is not followed as described, the reset is aborted.

7.5.2.5 CTRLRDY — Controller ready register

Table 36. CTRLRDY - Controller ready register bit description

Address: FFh.

Bit

Symbol

Description

7:0

CTRLRDY[7:0] Read-only register indicates the internal state of the controller. FFh

indicates the controller is initializing, 00h indicates controller is in normal

operating mode.

CTRLRDY (address FFh) is an 8-bit read-only register. It indicates the internal state of the

controller. When the register is FFh, the controller is in the initialization state. The

initialization state will be entered at power-up, after a hardware reset, or after a global

software reset.

The oscillator and the PLL will be initialized only after a Power-On Reset (POR), a

hardware reset, or a global software reset (CTRLPRESET).

When the register is 00h, the controller is in the normal operating mode.

Access while the controller is initializing requires CE pin follow the RD pin transitions to

update the state of the controller that is read back. After controller is ready, the CE pin can

be held LOW while RD and WR pins transition. See Figure 6, Figure 7 and Figure 8.

DATA

FFh

00h

ready

initializing

002aag095

Fig 6. During initialization, CE must transition with RD at each read operation

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ADDR

read address X

read address Y

read address Z

DATA

address X

address Y

address Z

002aag096

Fig 7. During normal operation, CE may remain LOW while RD transitions during

multiple reads

ADDR

write address X

write address Y

write address Z

DATA

data X

data Y

data Z

002aag097

Fig 8. During normal operation, CE may remain LOW while WR transitions during

multiple writes

8. PCU9669 operation

The PCU9669 is designed to efficiently transmit and receive large amounts of data on a

single master bus. There are three major components that compose the architecture of

the I²C-bus controller that interact with each other to provide a high throughput and a high

level of automation when it conducts transactions:

• Slave address table: specifies the address of the slaves on the bus and the direction

(read or write).

• Transaction configuration: specifies the size of the transaction.

• Data buffer: contains the data to be transmitted or received from the slave.

These three components are integrated in the PCU9669 to build a sequence. A sequence

is a set of read or write transactions and the minimum sequence size is one read or write

transaction. Several transactions can be stored in one sequence and be executed without

the intervention of the host controller (CPU) through loop control and using the built-in

refresh rate timers.

The PCU9669 executes transactions in the order they were loaded into the buffer without

interrupting the host. Once the end of a sequence is reached, the Sequence Done (SD) bit

will be asserted in the CHSTATUS register and the controller will request an interrupt, if

SDMSK = 0. At this point, the host can reload the buffer with a new sequence or resend

the one that is currently loaded in the buffer.

When a sequence is in progress, no interrupts are generated unless there is an error

when a transaction is conducted. The host will only receive an interrupt when the

sequence is done. The PCU9669 will dynamically shift between being a Master

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Transmitter or a Master Receiver according to the direction bits specified in the

SLATABLE. The host has the ability to retrieve stored serial data as soon as a read

transaction is done, while the controller carries on the remaining transactions in the

sequence.

8.1 Sequence execution

Sequences can have transactions of two types:

• Write transactions, where the PCU9669 will behave as a Master Transmitter

• Read transactions, where the PCU9669 will behave as a Master Receiver on the

Fm+ channel only, since UFm channels are uni-directional

Data transfers in each direction are shown in Figure 9. This figure contains the following

abbreviations:

S — START condition

SLA — 7-bit slave address

R — Read bit (HIGH level at SDA)

W — Write bit (LOW level at SDA)

A — Acknowledge bit (LOW level at SDA)

A — Not acknowledge bit (HIGH level at SDA)

Data — 8-bit data byte

P — STOP condition

In Figure 9, circles are used to indicate when a bit is set in the CHSTATUS register. A

channel interrupt is not requested when CHSTATUS = 00h and the INT pin is not asserted

when the interrupt is masked (see Section 7.5.2.2).

For a successful sequence execution, all three components mentioned above must exist

in the memory and must be correctly set up. There are not safeguards against

programming incorrect transaction sizes, data buffer lengths, or direction bits. If the

transaction length is set to 00h, then only the slave address with direction bit will be

transmitted.

Once the host has configured the serial port and programmed the TRANCONFIG (number

of slaves and bytes per slave), the SLATABLE (slave addresses), TRANSEL (transaction

data buffer selection) and the TRANOFS (byte offset selection) and loaded the serial data

into the DATA buffer, the sequence is ready to be transmitted.

To send the sequence, the host will set the STA bit in the CONTROL register and the

controller will immediately send a START on the serial bus. Then, the transactions will be

carried out in the order they appear in the SLATABLE, each being separated by a

ReSTART command.

If the interrupts are unmasked, the serial transfer will be conducted without generating

interrupts in between transactions. Once all transactions are successfully completed, the

controller will generate a STOP, the Sequence Done bit (SD) will be set in the CHSTATUS

and an interrupt will be generated.

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When the interrupts are unmasked, a NACK on slave address or data (in a write cycle) will

terminate the serial transfer, generate a STOP, and the INT pin will be asserted. The host

can read the CTRLSTATUS (Controller status register) to determine which channel

generated the interrupt, then it can read the CHSTATUS register of the channel and the

STATUSx_[n] to determine which slave address caused the error.

If the interrupts WEMSK and REMSK are set, then a NACK on slave address or data (in a

write cycle) will not terminate the serial transfer, the error will be stored in the

STATUSx_[n] register and the serial transfer will continue with the next transaction in the

sequence. Once all transactions are completed, the controller will generate a STOP and

the Sequence Done bit (SD) and other error bits (WE or RE) will be set in the CHSTATUS

and an interrupt will be generated.

If the host wants to poll the PCU9669, it can mask all registers including the SD bit and

read the CTRLSTATUS, CHSTATUS, STATUSx_[n], and/or the CONTROL registers to

determine the state of the controller.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

a.) Transactions with WEMSK and REMSK = 0

SLA 0

DATA

SLA 0

DATA

SLA 1

DATAn

SLA n

DATAn

00h

80h

data available

to be read on

parallel bus

01h 01h

08h

04h

10h

F8h

04h

08h

04h

C0h

20h

10h

20h

b.) Transactions with WEMSK and REMSK = 1

SLA 0

DATA

SLA 0

DATA

SLA 1

DATAn

SLA n

DATAn

01h 01h

02h

00h

02h

80h

E0h

C0h

A0h

data available

to be read on

parallel bus

08h

04h

10h

08h

20h

10h

20h

from master to slave

from slave to master

STATUSx_[n] register, no interrupt

CHSTATUS register, interrupt requested; interrupt goes LOW at the STOP

any number of data bytes and their associated Acknowledge bits

last byte is NACK

DATA

002aaf619

Example CHSTATUS codes:

80h: sequence done with no errors

C0h: frame loop and sequence done with no errors

A0h: sequence done with a write error

D0h: frame loop and sequence done with a read error

Fig 9. PCU9669 I²C status codes

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

number of

slave addresses

to be included

in a sequence

TRANCONFIG

DATA

internal memory pointer

0000h

SLATABLE

40h Transaction count

10h Transaction 0, data byte 0

00h Transaction 1, data byte 0

00h Transaction 1, data byte 1

00h Transaction 1, data byte 2

00h Transaction 1, data byte 3

00h Transaction 1, data byte 4

02h Transaction 2, data byte 0

55h Transaction 2, data byte 1

00h 10h

SLAW

SLAR

SLAW

00h 01h Transaction 0 length, 1 byte

01h 05h Transaction 1 length, 5 bytes

02h 10h Transaction 2 length, 16 bytes

03h 08h Transaction 3 length, 8 bytes

01h 11h

02h 40h

03h E0h

3Dh 20h

3Eh 33h

3Fh 20h

SLAW

SLAR

SLAW

3Dh 10h Transaction 61 length, 16 bytes

3Eh 05h Transaction 62 length, 5 bytes

3Fh 08h Transaction 63 length, 8 bytes

sequence read

and write data

memory space

AAh Transaction 2, data byte 15

slave address

plus direction bit

transaction length

corresponding to each

slave address in the

SLATABLE

44h Transaction 63, data byte 0

AAh Transaction 63, data byte 1

55h Transaction 63, data byte 7

The slave address plus transaction count,

direction bit, the transaction length and the

transaction data make up one complete

serial bus transaction or sequence.

unused

memory

space

internal memory pointer

A00h or F00h

The memory pointers are managed

internally by the buffer controller.

002aaf620

Status and configuration registers are not shown.

Shaded areas are comments/indexes that are not user-accessible.

Fig 10. PCU9669 sequence block diagram; sample sequence loaded

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

8.2 Read transactions (Fm+ channel only)

Many I²C-bus slave devices need a command or register offset to setup a read operation.

In this case, a read transaction is actually a multi-part transaction consisting of a write

transaction followed by a read transaction. This is done by setting the transactions in that

order when programming the sequence.

If no write is required prior to a read, then the read transaction can be placed in any

location of the sequence. Once the read transaction is completed (i.e., the TR bit is

cleared to 0) the data is immediately available for the host to retrieve it on the parallel bus.

8.3 Stopping a sequence

If the host needs to stop the execution of a sequence, it should set the STO bit in the

CONTROL register. For write transactions, the host will issue a STOP after the

acknowledge cycle of the current byte being transferred on the serial bus. For read

transactions, if the host sets the STO bit while an address + read bit (SLA+R) is sent, the

controller will complete the read of one byte by sending 9 clocks and a NACK on the ninth

clock before sending the STOP condition. If the host sets the STO bit while a read

transaction is in progress, the current byte will be NACKed before sending a STOP

condition. No interrupts will be generated and all the status registers will be up to date.

The Sequence Done bit (SD) will be set to indicate to the host that the STOP condition

was completed and the bus is idle. The Sequence Done and the Frame Loop Done will be

set if the channel is in Loop mode (FRAMECNT  1) and a STO or STOSEQ bit is set.

If the host issues a STOP (by setting the STO) in the middle of a sequence followed by a

START (by setting the STA), then the controller will re-send the sequence from the

beginning, not from the point where the sequence was last stopped.

8.4 Looping a sequence

A sequence can be set to automatically loop several times using the FRAMECNT and one

of the following:

• The REFRATE register. The REFRATE register contains the value of the refresh rate

which is timing required between the START of two sequences. The refresh rate is

derived from the internal clock of the bus controller. If the REFRATE is programmed to

00h, the sequences will be looped back-to-back.

• Trigger enable (TE) bit. When TE is set, the refresh rate is controlled by the external

trigger input and the contents of the REFRATE registers is ignored. There is no

maximum timing requirement for the trigger interval.

The FRAMECNT register sets the number of times the sequence will be repeated. A

frame is defined as a sequence associated with its respective refresh rate. As described

above, the frame refresh rate is determined by the REFRATE register or an external

trigger source.

During looping, there is no host intervention required and all status and error reporting

remains active. The SD (Sequence Done) bit can be masked to avoid getting interrupted

each time a frame is completed while the other error reporting bits remain unmasked. In

this manner, normal transactions can run without host intervention and errors will be

reported at the STOP of the current byte where the error occurred.

PCU9669

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

Once the FRAMECNT values is reached, the FLD bit in the CHSTATUS register is set and

no further transactions will be executed and the channel will go to the idle state. The FLD

interrupt can be masked with the FLDMSK bit in the CTRLINTMSK register. The host can

poll the CTRLSTATUS register to check if the channel is active (looping) or if it is idle.

For indefinite or long term looping the host can do the following:

1. A sequence can be set to loop indefinitely by setting the FRAMECNT register to 00h.

Each frame will be sent out following the REFRATE settings or the Trigger input if the

TE bit is set. To end the Loop mode, the host sets the STO or STOSEQ bits in the

CONTROL register.

2. A frame will be sent out continuously and back-to-back if FRAMECNT and REFRATE

are set to 00h. To end the Loop mode, the hose sets the STO or STOSEQ bits in the

CONTROL register.

8.4.1 Looping with REFRATE control

When using the REFRATE register (TE bit is 0) the refresh rate timing is controlled

internally. Once the STA bit is set, the START command will be immediately sent on the

serial bus followed by the sequence. Thereafter, the controller will issue a START

command followed by the stored sequence every time the REFRATE value is reached. It

is important to program enough time in the REFRATE to allow a complete sequence to

reach the Sequence Done state. If the refresh rate is not long enough, the Frame Error

(FE) bit will be set and an interrupt will be generated. The FE bit is maskable, however,

masking the FE bit may yield undesired results on the serial interface. If the FE bit is

masked, the Loop mode will continue to operate and the FE flag will remain set. To exit

the Loop mode, the STO or the STOSEQ bit should be set.

8.4.2 Looping with Trigger control

The PCU9669 has one trigger input. The trigger enable (TE) bit in the CONTROL register

is used to control the use of external triggering. Once enabled, the trigger will override the

contents of the REFRATE register, and will start triggering when the STA bit is set.

Therefore, a significant time delay can occur between setting the STA bit and the

detection of a trigger. When a trigger edge is detected, the controller will issue a START

command and the stored sequence will be transferred on the serial bus. The trigger will

control the timing of the frame, therefore, enough time should be allowed by the trigger to

allow the sequence to reach the Sequence Done state.

If a trigger edge is detected while a sequence is actively being transmitted on the bus, the

Frame Error (FE) bit will be set and an interrupt will be generated. The FE bit is maskable,

however, masking the FE bit may yield undesired results on the serial interface. If the FE

bit is masked, the Loop mode will continue to operate and the FE flag will remain set. The

polarity of the trigger edge detect is controlled by the TP bit in the CONTROL register. To

exit the Trigger mode, the STO or the STOSEQ bit should be set.

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Product data sheet

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

8.5 Bus errors (Fm+ channel only)

Bus errors are a rare occurrence in a well designed I²C-bus system. The PCU9669 has a

robust error detection mechanism that detects hang-ups such as if SDA or SCL is pulled

LOW by an external source, or if an illegal START or STOP condition appears on the bus.

8.5.1 I²C-bus obstructed by a LOW level on SDA (DAE)

An I²C-bus hang-up occurs if SDA is pulled LOW by an uncontrolled source (e.g., a slave

device out of bit synchronization). If the SDA line is obstructed by another device on the

bus, the problem can be solved by transmitting additional clock pulses on the SCL line

(see Figure 11). The SDA stuck fault detection is only active during a START or

repeated-START condition.

When the error is detected, if the auto-recovery bit is set (AR = 1), the PCU9669 sends

out nine clock pulses followed by the STOP condition (see Figure 11). If the SDA line is

released by the slave pulling it LOW, a normal START condition is transmitted by the

PCU9669, the TA bit is set in the STATUSx_[n] register and the serial transfer continues. If

the SDA line is not released by the slave pulling it LOW, then the PCU9669 concludes that

there is a bus error, sets the DAE bit in the CHSTATUS register, generates an interrupt

signal, and releases the SCL and SDA lines.

If the auto-recovery bit is reset (AR = 0) during error detection, the PCU9669 loads the

bus error (sets the DAE bit in the CHSTATUS register), generates an interrupt signal, and

releases the SCL and SDA lines. After the host reads the status register, it can force a bus

recovery sequence by setting the bus recovery bit to 1 (BR = 1). The PCU9669 will

transmit additional clock pulses on the SCL line and the host must re-start the

transmission by setting the STA bit.

If a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the

PCU9669 performs the same action as described above. In each case, the TA bit is set

after a successful START condition is transmitted and normal serial transfer continues.

Note that the host is not involved in solving these bus hang-up problems when the

auto-recovery bit is set (AR = 1).

When a host is unable to recover the bus by having the AR bit set or forcing a bus

recovery sequence by setting the bus recovery by setting the BR, then it may be

necessary to reset the slaves or the system.

Remark: If the AR bit is set and an SDA stuck LOW is detected, the transaction will

continue normally after an auto-recovery from the failed location in the sequence. If the

AR bit is zero and a manual bus recovery is performed, the transaction will be re-started

from the beginning of the sequence.

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Product data sheet

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

line released by slave,

bus recovered

line driven

by master

SDA line

line held LOW by slave

SCL line

START

condition

9 clocks driven by master

fault detected

at START

STOP condition

002aaf621

Fig 11. Recovering from a bus obstruction caused by a LOW level on SDA (AR = 1)

8.5.2 I²C-bus obstructed by a LOW level on SCL (CLE)

An I²C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the

SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is

possible, and the PCU9669 cannot resolve this type of problem. When this occurs, the

problem must be resolved by the device that is pulling the SCL bus line LOW. To resolve

this type of a problem, resetting the slaves or the system may be required.

When the SCL line stays LOW for a period equal to the time-out value, the PCU9669

concludes that this is a bus error and behaves in a manner described in Section 7.5.1.15

“TIMEOUT — Time-out register”.

The bus recovery function (setting the BR bit) will not have any effect on an SCL stuck

LOW error.

8.5.3 Illegal START or STOP (SSE)

The illegal START or STOP detection is active immediately after the CTRLRDY register is

set to 00h at device start-up. The SSE condition will be monitored and detected at any

time the bus controller is not the one initiating the transition.

An SSE occurs when a START or STOP condition is present at an illegal position.

Examples of illegal positions are during the serial transfer of an address byte, a data or an

acknowledge bit.

When an SSE condition is detected, the PCU9669 releases the SDA and SCL lines, sets

the interrupt flag, and sets the SSE bit in the channel status register (CHSTATUS).

8.6 Power-on reset

When power is applied to V_DD, an internal Power-On Reset holds the PCU9669 in a reset

condition until V_DDhas reached V_POR. At this point, the reset condition is released and the

PCU9669 goes to the power-up initialization phase where the following operations are

performed:

1. The oscillator and PLL will be re-initialized.

2. Internal register initialization is performed.

3. The memory space will be zeroed out.

PCU9669

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Product data sheet

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

The complete power-up initialization phase takes t_rstto be performed. During this time,

writes to the PCU9669 through the parallel port are ignored. However, the parallel port

can be read. This allows the device connected to the parallel port of the PCU9669 to poll

the CTRLRDY register.

8.7 Global reset

Reset of the PCU9669 to its default state can be performed in 2 different ways:

• By holding the RESET pin LOW for a minimum of t_w(rst)

• By using the Parallel Software Reset sequence as described in Figure 12. The host

must write to the CTRLPRESET register of the target channel in two successive

parallel bus writes to the bus controller. The first byte is A5h and the second byte is

5Ah.

CTRLPRESET register selected

A[7:0]

D[7:0]

data byte 1

A5h

data byte 2

5Ah

If D[7:0] ≠ A5h, following byte

is ignored and reset is aborted.

If D[7:0] ≠ 5Ah, reset is aborted.

If Data 1 = A5h and Data 2 = 5Ah,

PCU9669 is reset to its default state.

internal

global reset

signal

002aaf622

Fig 12. Parallel Software Reset sequence

The RESET hardware pin and the global software reset function behave the same as the

power-on reset. A complete power-up initialization phase will be performed as defined in

Section 8.6. The RESET pin has an internal pull-up resistor (through a series diode) to

guarantee proper operation of the device. This pin should not be left floating and should

always be driven.

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

8.8 Channel reset

In addition to the above chip reset options, each channel can be individually reset by

programming the PRESET register for that channel as described in Figure 13. The

channel will reset to its default power-up state. The host must write to the PRESET

The first byte is A5h and the second byte is 5Ah.

channel PRESET register selected

A[7:0]

D[7:0]

data byte 1

A5h

data byte 2

5Ah

If D[7:0] ≠ A5h, following byte

is ignored and reset is aborted.

If D[7:0] ≠ 5Ah, reset is aborted.

If Data 1 = A5h and Data 2 = 5Ah,

PCU9669 is reset to its default state.

internal

channel reset

signal

002aaf623

Fig 13. I²C-bus Channel Parallel Software Reset sequence

PCU9669

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

8.9 I²C-bus timing diagrams

The diagrams Figure 14 and Figure 15 illustrate typical timing diagrams for the PCU9669.

SCL

SDA

INT

(1)

7-bit address

interrupt

(after STOP)

(1)

first byte

n byte

R/W = 0

STOP

condition

START

condition

ACK

002aaf301

from slave receiver

PCU9669 writes data to slave.

(1) 7-bit address + R/W = 0 byte and number of bytes sent = value programmed in Transaction length

Fig 14. Bus timing diagram; write transactions

SCL

SDA

INT

interrupt

(after STOP)

7-bit address

R/W = 1

(1)

first byte

n byte

STOP

START

condition

ACK

no ACK

from PCU9669

condition

002aaf624

from slave

PCU9669 reads data from slave.

(1) Number of bytes received = value programmed in the Transaction length register in

TRANCONFIG.

Fig 15. Bus timing diagram; read transactions (does not apply to the UFm channel)

PCU9669

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Product data sheet

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 16).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 16. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 17).

SDA

SCL

STOP condition

START condition

mba608

Fig 17. Definition of START and STOP conditions

9.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 18).

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

PCU9669

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

RECEIVER

I C-BUS

MULTIPLEXER

SLAVE

TRANSMITTER/

RECEIVER

002aaf625

Fig 18. System configuration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 19. Acknowledgement on the I²C-bus

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

10. Characteristics of the I²C-bus — Ultra Fast-mode (UFm)

The PCU9669 UFm bus is a 2-wire push-pull serial bus that operates from 50 kHz to

5 MHz transmitting data in one direction. The UFm protocol is based on the I²C-bus

protocol that consists of a START, slave address, command bit, ninth clock, and a STOP

bit. The command bit is a ‘write’ only, and the data bit on the ninth clock is driven HIGH,

ignoring the ACK cycle due to the unidirectional nature of the bus. The 2-wire pull-pull

drivers consists of a UFm clock (USCL) and data (USDA), requiring external series

resistors to allow proper line termination. The UFm bus is designed to be used in high

performance single master multi-drop applications.

DD(IO)

USCL or

USDA pin

R , external

002aaf143

Fig 20. Simplified schematic of USCL, USDA outputs

The external resistors are chosen based upon the characteristic impedance of the UFm

bus. For example, if the characteristic input impedance of the line is 175 , a series

resistance of 175  can be used. Since the output resistance of the driver is

approximately 50 , the value of the series resistance used would then be 125 . The

final value of the resistance also depends upon the electrical length of the bus and the

signal settling time required to meet the UFm timing characteristics. Larger values result

in longer time for the signal to settle to its final valid value. Lower values can result in

overshoot and ringing on the bus. Careful consideration must be made in designing the

I²C-bus routing and selecting the series resistance.

10.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the USDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at this

time will be interpreted as control signals (see Figure 21).

USDA

SDADLY

USCL

change

data line

of data

allowed

stable

SCLPER

002aaf626

Fig 21. UFm I²C-bus bit transfer

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

10.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 22).

USDA

USCL

STOP condition

START condition

002aaf145

Fig 22. Definition of START and STOP conditions for UFm I²C-bus

10.3 Acknowledge (ninth clock)

The UFm bus functions as a transmitter only (unidirectional). The number of data bytes

transferred between the START and the STOP conditions from transmitter to receiver is

not limited. Each byte of eight bits of real data is followed by a dummy bit which is a HIGH

level put on the bus by the transmitter, which also generates an associated clock pulse.

Since the UFm bus is unidirectional, a slave receiver shall not generate an acknowledge

pulse. The slave USCLn and USDAn pins are input only.

data output

by transmitter

Master drives the line HIGH on 9th clock cycle.

Slave never drives the USDA line.

SCL from master

clock pulse for

acknowledgement

START

condition

002aaf144

Fig 23. Acknowledgement on the UFm I²C-bus

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

11. JTAG port

The PCU9669 has a JTAG IEEE 1149.1 compliant port. All signals (TDI, TMS, TCK, TRST

and TDO) are accessible. Only EXTEST functions are enabled, for example to conduct

board-level continuity tests. Device debug/emulation functionality such as INTEST

commands are not supported. The JTAG port is used for boundary scan testing (i.e.,

opens/shorts) during PCB manufacturing.

The following EXTEST JTAG instructions are supported:

• BYPASS

• EXTEST

• IDCODE

• SAMPLE

• PRELOAD

• CLAMP

• HIGHZ

If the JTAG boundary scan is not being used, then the JTAG pins must be held in the

following states:

• TDI, TCK, TMS: V_DD

• TRST: V_SS

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NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

12. Application design-in information

address bus

DD(IO)

SCL0

SDA0

80C51

PCU9669

SLAVE

INT

SLAVE

RESET

DECODER

ALE

USCL1

USDA1

D0 to D7

SLAVE

TRIG

USCL2

USDA2

INT

RESET

002aaf481

Fig 24. Application diagram using the 80C51

12.1 Specific applications

The PCU9669 is a parallel bus to I²C-bus controller that is designed to allow ‘smart’

devices to interface with I²C-bus or SMBus components, where the ‘smart’ device does

not have an integrated I²C-bus port and the designer does not want to ‘bit-bang’ the

I²C-bus port. The PCU9669 can also be used to add more I²C-bus ports to ‘smart’

devices, provide a higher frequency, lower voltage migration path for the PCF8584,

PCA9564 and PCA9665 and convert 8 bits of parallel data to a serial bus to avoid running

multiple traces across the printed-circuit board.

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

12.2 Add I²C-bus port

As shown in Figure 25, the PCU9669 converts 8-bits of parallel data into a single master

capable I²C-bus port for microcontrollers, microprocessors, custom ASICs, DSPs, etc.,

that need to interface with I²C-bus or SMBus components.

SDA0

SCL0

control signals

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

USDA1

USCL1

PCU9669

8 bits data

USDA2

USCL2

002aaf482

Fig 25. Adding I²C-bus port application

12.3 Add additional I²C-bus ports

The PCU9669 can be used to convert 8-bit parallel data into additional single master

capable I²C-bus port as shown in Figure 26. It is used if the microcontroller,

microprocessor, custom ASIC, DSP, etc., already have an I²C-bus port but need one or

more additional I²C-bus ports to interface with more I²C-bus or SMBus components or

components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves

on different buses so that each bus can operate at its maximum potential).

SDA0

control signals

8 bits data

SLAVE

SCL0

PCU9669

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

USDA1

USCL1

MASTER

USDA2

USCL2

SLAVE

002aaf483

I C-bus

Fig 26. Adding additional I²C-bus ports application

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

13. Limiting values

Table 37. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

0.3

Max

+4.6

+7.0

Unit

V_DD

supply voltage

V_DD(IO)

input/output supply voltage

power supply reference

for I²C-bus I/O pins

V_I

input voltage

parallel bus interface

I²C-bus pins

any input

0.3

10

+4.6

+7.0

+10

106

110

300

[1]

I_I

input current

C

I_O

output current

any output

I_OSH

I_OSL

P_tot

P/out

T_stg

T_amb

HIGH-level short-circuit output current

LOW-level short-circuit output current

total power dissipation

power dissipation per output

storage temperature

I/O D0 to D7

65

40

+150

+85

ambient temperature

operating

C

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

14. Static characteristics

Table 38. Static characteristics

V_DD= 3.0 V to 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Supply

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

monotonic supply during power-up

and power-down with a ramp time

(t_ramp): 5 s < t_r< 20 ms

3.0

3.6

(5 % V_DD(min)to 95 % V_DD(min)

)

V_DD(PLL)

V_DD(IO)

phase-locked loop

supply voltage

input/output supply voltage power supply reference for I²C-bus

I/O pins

power supply for PLL bias circuit

3.0

3.6

5.5

I_DD

supply current

operating mode; no load

I_DD(IO)

input/output supply current V_DD(IO)= 5.5 V; V_DD= 3.6 V;

I/O not switching

V_POR

power-on reset voltage

LOW to HIGH

HIGH to LOW

2.75

2.60

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PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

Table 38. Static characteristics …continued

V_DD= 3.0 V to 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Inputs WR, RD, A0 to A7, CE, TRIG

V_IL

V_IH

V_hys

I_L

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

0.3V_DD

3.6

[1]

0.7V_DD

0.1V_DD

1

leakage current

input; V_I= 0 V or 3.6 V

V_I= V_SSor V_DD

A

C_i

input capacitance

2.0

4.5

Input RESET

V_IL

V_IH

V_hys

I_L

LOW-level input voltage

0.3V_DD

3.6

[1]

HIGH-level input voltage

hysteresis voltage

leakage current

0.7V_DD

0.1V_DD

1

input; V_I= 0 V or 3.6 V

V_I= V_SSor V_DD

+75

4.5

A

C_i

input capacitance

2.0

Inputs/outputs D0 to D7

V_IL

V_IH

I_OH

I_OL

I_L

LOW-level input voltage

0.3V_DD

HIGH-level input voltage

HIGH-level output current

LOW-level output current

leakage current

0.7V_DD

3.2

2.0

1

3.6

V_OH= V_DD(IO) 0.4 V

V_OL= 0.4 V

A

input; V_I= 0 V or 5.5 V

V_I= V_SSor V_DD

C_io

input/output capacitance

2.8

USDAn and USCLn

I_OL

I_OH

C_io

R_ON

I_L

LOW-level output current

V_OL= 0.4 V



HIGH-level output current

input/output capacitance

ON resistance

V_OH= V_DD(IO) 0.4 V

V_I= V_SSor V_DD(IO)

4.8

5.6

leakage current

V_DD= 3.6 V

V_DD= 5.5 V

1

10

+10

A

SDAn and SCLn

V_IL

V_IH

I_L

LOW-level input voltage

0.3V_DD(IO)

[1]

HIGH-level input voltage

leakage current

0.7V_DD(IO)

5.5

input/output; V_I= 0 V or 3.6 V

input/output; V_I= 0 V or 5.5 V

V_OL= 0.4 V

75

A

I_OL

LOW-level output current

input/output capacitance

C_io

V_I= V_SSor V_DD(IO)

5.6

Output INT

I_OL

I_L

LOW-level output current

leakage current

V_OL= 0.4 V

6.0

1

A

V_O= 0 V or 3.6 V

V_I= V_SSor V_DD

+75

5.5

C_o

output capacitance

3.8

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

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15. Dynamic characteristics

Table 39. Dynamic characteristics (3.3 volt)^[1][2][3]

V_DD= 3.3 V  0.3 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Initialization timing

t_init(po)power-on initialization time

t_initinitialization time

Parameter

Conditions

Min

Typ

Max

Unit

V_DD 3.0 V

650

s

channel initialization time from

Channel Software Reset

controller initialization time from

POR, RESET, or Global Software

Reset inactive

650

s

RESET timing

t_w(rst)

reset pulse width

s

[4][5]

t_rst

reset time

1.5

INT timing

t_as(int)

interrupt assert time

500

100

t_das(int)

TRIG timing

t_w(trig)

interrupt de-assert time

trigger pulse width

HIGH or LOW

100

Bus timing (see Figure 27 and Figure 29)

t_su(A)

address set-up time

address hold time

to RD, WR LOW

from RD, WR LOW

to RD, WR LOW

from RD, WR LOW

t_h(A)

t_{su(CE_N)}

t_{h(CE_N)}

t_w(RDL)

t_w(WRL)

t_d(DV)

CE set-up time

CE hold time

RD LOW pulse width

WR LOW pulse width

data valid delay time

data output float delay time

data output set-up time

data output hold time

RD HIGH pulse width

WR HIGH pulse width

after RD and CE LOW

after RD or CE HIGH

before WR HIGH

t_d(QZ)

t_su(Q)

t_h(Q)

after WR HIGH

t_w(RDH)

t_w(WRH)

[1] Parameters are valid over specified temperature and voltage range.

[2] All voltage measurements are referenced to ground (V_SS). For testing, all inputs swing between 0 V and 3.0 V with a transition time of

5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 27 and Figure 29.

[3] Test conditions for outputs: C_L= 50 pF; R_L= 500 , except open-drain outputs.

Test conditions for open-drain outputs: C_L= 50 pF; R_L= 1 k pull-up to V_DD

[4] Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

[5] Upon reset, the full delay will be the sum of t_rstand the RC time constant of the SDA and SCL bus.

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A0 to A7

su(A)

h(A)

h(CE_N)

w(RDH)

su(CE_N)

w(RDL)

d(QZ)

d(DV)

D0 to D7

(read)

float

not valid

valid

float

002aaf458

Fig 27. Bus timing (read cycle)

A0 to A7

su(A)

h(A)

h(CE_N)

su(CE_N)

w(WRH)

w(WRL)

h(Q)

su(Q)

D0 to D7

(write)

valid

002aaf459

Fig 28. Parallel bus timing (write cycle)

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RD, CE input

d(QZL)

d(QLZ)

Dn output

LOW-to-float

float-to-LOW

d(QZH)

d(QHZ)

Dn output

HIGH-to-float

float-to-HIGH

outputs

enabled

outputs

enabled

outputs

floating

002aaf172

V_M= 1.5 V

V_X= V_OL+ 0.2 V

_Y= V_OH 0.2 V

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 29. Data timing

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 40. I²C-bus frequency and timing specifications

All the timing limits are valid within the operating supply voltage and ambient temperature range; V_DD= 2.5 V  0.2 V and 3.3 V  0.3 V; T_amb= 40 C to +85 C;

and refer to V_ILand V_IHwith an input voltage of V_SSto V_DD

Symbol Parameter Conditions

Standard-mode Fast-mode I²C-bus

I²C-bus

Fast-mode Plus Ultra Fast-mode Unit

I²C-bus I²C-bus

Min

Max

100

Min

Max

400

Min

Max

1000

Min

Max

[1]

f_SCL

t_BUF

SCL clock frequency

5000 kHz

bus free time between a STOP and

START condition

4.7

1.3

0.5

0.08

s

t_HD;STA

t_SU;STA

hold time (repeated) START condition

4.0

4.7

0.6

0.26

0.05

s

set-up time for a repeated START

condition

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

t_HIGH

t_f

set-up time for STOP condition

data hold time

4.0

0.6

0.26

0.05

s

0.45

[2]

[4]

[3]

data valid acknowledge time

data valid time

0.1

100

4.7

4.0

3.45

0.1

0.9

0.1

100

0.5

0.26

100

data set-up time

100

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

1.3

0.05

0.6

[5][6]

[9]

[7]

[8]

300

20 + 0.1C_b

300

120

[8]

t_r

1000 20 + 0.1C_b

[10]

t_SP

pulse width of spikes that must be

suppressed by the input filter

[1] Minimum SCL clock frequency is limited by the bus time-out feature, generates a CLE error if the SCL is held LOW for the TIMEOUT period.

[2] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3]

_VD;ACKis not applicable to the Ultra Fast-mode (UFm) I²C-bus.

[4] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[5] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to bridge the undefined region SCL’s falling

edge. Does not apply to the UFm channel.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at 250 ns. This allows series protection

resistors to be connected between the SDAn and the SCLn pins and the SDA/SCL bus lines without exceeding the maximum specified t_f. Does not apply to the UFm channel.

[7] C_b= total capacitance of one bus line in pF.

[8] Typical rise/fall times for UFm signals is 25 ns measured from the 20 % level to the 80 % (rise time) or from the 80 % level to the 20 % level (fall time).

[9] Input filters on the SDAn and SCLn inputs suppress noise spikes less than 50 ns.

[10] t_SPis not applicable to the Ultra Fast-mode (UFm) I²C-bus.

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SDA

BUF

LOW

SU;DAT

HD;STA

SCL

SU;STO

HD;STA

SU;STA

HIGH

HD;DAT

002aab271

Fig 30. Definition of timing on the I²C-bus

START

bit 7

STOP

condition

(P)

acknowledge

(A)

protocol

condition

(S)

bit 6

bit n

bit 0

MSB

HIGH

SU;STA

LOW

SCL

SDA

BUF

HD;DAT

VD;DAT

VD;ACK

SU;STO

HD;STA

SU;DAT

002aac696

Rise and fall times refer to V_ILand V_IH.

Fig 31. I²C-bus timing diagram

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16. Test information

open

× 2

500 Ω

PULSE

DUT

GENERATOR

500 Ω

50 pF

002aac694

Test data are given in Table 41.

R_L= load resistance.

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_Oof the pulse generators.

Fig 32. Test circuitry for switching times

Table 41. Test data

Test

Conditions

Load

C_L

R_L

t_d(DV), t_d(QZ)

Dn outputs active LOW

Dn outputs active HIGH

50 pF

500 

V_DD 2

open

1 kΩ

PULSE

DUT

GENERATOR

50 pF

002aac695

Test data are given in Table 42.

R_L= load resistance.

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_Oof the pulse generators.

Fig 33. Test circuitry for open-drain switching times

Table 42. Test data INT pin

Test

Load

C_L

R_L

t_as(int)

50 pF

1 k

V_DD

t_das(int)

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17. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

(A )

w M

pin 1 index

detail X

v M

w M

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

0.25

0.5

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 34. Package outline SOT313-2 (LQFP48)

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18. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

19. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

19.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

19.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

19.3 Wave soldering

Key characteristics in wave soldering are:

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• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

19.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 35) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 43 and 44

Table 43. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 44. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 35.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 35. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

20. Abbreviations

Table 45. Abbreviations

Acronym

ASIC

CDM

CPU

Description

Application Specific Integrated Circuit

Charged-Device Model

Central Processing Unit

Digital Signal Processor

ElectroStatic Discharge

Fast-mode Plus

DSP

ESD

Fm+

HBM

I²C-bus

I/O

Human Body Model

Inter-Integrated Circuit bus

Input/Output

LED

Light Emitting Diode

Phase-Locked Loop

PLL

SMBus

UFm

System Management Bus

Ultra Fast-mode

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21. Revision history

Table 46. Revision history

Document ID

PCU9669 v.2

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20110701

Product data sheet

PCU9669 v.1

• Table 40 “I²C-bus frequency and timing specifications”, Table note [8]: unit of measure is

corrected from “25 ms” to “25 ns”.

PCU9669 v.1

20110606

Product data sheet

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

22.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

67 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

24. Contents

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.5.2.5

CTRLRDY — Controller ready register . . . . . 33

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8.1

8.2

8.3

PCU9669 operation . . . . . . . . . . . . . . . . . . . . . 34

Sequence execution . . . . . . . . . . . . . . . . . . . 35

Read transactions (Fm+ channel only) . . . . . 39

Stopping a sequence . . . . . . . . . . . . . . . . . . . 39

Looping a sequence. . . . . . . . . . . . . . . . . . . . 39

Looping with REFRATE control . . . . . . . . . . . 40

Looping with Trigger control. . . . . . . . . . . . . . 40

Bus errors (Fm+ channel only). . . . . . . . . . . . 41

I²C-bus obstructed by a LOW level on

8.4

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8.4.1

8.4.2

8.5

7.1

7.2

7.3

7.3.1

7.3.2

7.4

7.5

7.5.1

7.5.1.1

Functional description . . . . . . . . . . . . . . . . . . . 6

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Internal oscillator and PLL . . . . . . . . . . . . . . . . 6

Buffer description . . . . . . . . . . . . . . . . . . . . . . . 6

Buffer management assumptions. . . . . . . . . . . 7

Buffer sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Error reporting and handling. . . . . . . . . . . . . . . 8

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Channel registers . . . . . . . . . . . . . . . . . . . . . . 13

STATUS0_[n], STATUS1_[n],

STATUS2_[n] — Transaction status registers 13

CONTROL — Control register . . . . . . . . . . . . 14

CHSTATUS — Channel status register . . . . . 17

INTMSK — Interrupt mask register. . . . . . . . . 19

SLATABLE — Slave address table register . . 20

TRANCONFIG — Transaction configuration

DATA — I²C-bus Data register . . . . . . . . . . . . 21

TRANSEL — Transaction data buffer

8.5.1

SDA (DAE). . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I²C-bus obstructed by a LOW level on

8.5.2

SCL (CLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Illegal START or STOP (SSE) . . . . . . . . . . . . 42

Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 42

Global reset . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Channel reset. . . . . . . . . . . . . . . . . . . . . . . . . 44

I²C-bus timing diagrams. . . . . . . . . . . . . . . . . 45

Characteristics of the I²C-bus . . . . . . . . . . . . 46

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

START and STOP conditions. . . . . . . . . . . . . 46

System configuration . . . . . . . . . . . . . . . . . . . 46

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5.3

8.6

8.7

8.8

8.9

9.1

9.1.1

9.2

9.3

7.5.1.2

7.5.1.3

7.5.1.4

7.5.1.5

7.5.1.6

Characteristics of the I²C-bus — Ultra

Fast-mode (UFm). . . . . . . . . . . . . . . . . . . . . . . 48

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

START and STOP conditions. . . . . . . . . . . . . 49

Acknowledge (ninth clock) . . . . . . . . . . . . . . . 49

10.1

10.2

10.3

7.5.1.7

7.5.1.8

select register . . . . . . . . . . . . . . . . . . . . . . . . . 22

TRANOFS — Transaction data buffer byte

JTAG port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.5.1.9

Application design-in information. . . . . . . . . 51

Specific applications. . . . . . . . . . . . . . . . . . . . 51

Add I²C-bus port . . . . . . . . . . . . . . . . . . . . . . 52

Add additional I²C-bus ports . . . . . . . . . . . . . 52

select register . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.5.1.10 BYTECOUNT — Transmitted and received

byte count register . . . . . . . . . . . . . . . . . . . . . 23

12.1

12.2

12.3

7.5.1.11 FRAMECNT — Frame count register. . . . . . . 23

7.5.1.12 REFRATE — Refresh rate register. . . . . . . . . 24

7.5.1.13 SCLL, SCLH and SCLPER, SDADLY —

Clock rate registers. . . . . . . . . . . . . . . . . . . . . 24

7.5.1.14 MODE — I²C-bus mode register . . . . . . . . . . 28

7.5.1.15 TIMEOUT — Time-out register. . . . . . . . . . . . 29

7.5.1.16 PRESET — I²C-bus channel parallel software

reset register. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 53

Static characteristics . . . . . . . . . . . . . . . . . . . 53

Dynamic characteristics. . . . . . . . . . . . . . . . . 55

Test information . . . . . . . . . . . . . . . . . . . . . . . 60

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61

Handling information . . . . . . . . . . . . . . . . . . . 62

7.5.2

7.5.2.1

7.5.2.2

Global registers . . . . . . . . . . . . . . . . . . . . . . . 30

CTRLSTATUS — Controller status register . . 30

CTRLINTMSK — Control Interrupt mask

DEVICE_ID — Device ID . . . . . . . . . . . . . . . . 32

CTRLPRESET — Parallel software reset

Soldering of SMD packages. . . . . . . . . . . . . . 62

Introduction to soldering. . . . . . . . . . . . . . . . . 62

Wave and reflow soldering. . . . . . . . . . . . . . . 62

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 62

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 63

19.1

19.2

19.3

19.4

7.5.2.3

7.5.2.4

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 64

continued >>

PCU9669

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 July 2011

68 of 69

PCU9669

NXP Semiconductors

Parallel bus to 1 channel Fm+ and 2 channel UFm I²C-bus controller

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 65

Legal information. . . . . . . . . . . . . . . . . . . . . . . 66

22.1

22.2

22.3

22.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 66

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contact information. . . . . . . . . . . . . . . . . . . . . 67

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 July 2011

Document identifier: PCU9669

PCU9669B [NXP]

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