PDI1394L41_技术文档

INTEGRATED CIRCUITS

PDI1394L41

1394 content protection AV link layer

controller

Preliminary specification

2000 Apr 15

Supersedes data of 1999 Sep 30

NOTICE: DTLA SENSITIVE INFORMATION HAS BEEN WITHHELD FROM THIS DATA SHEET. SEE SECTION 2.1 FOR DETAILS.

Philips

Semiconductors

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

1.0 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.0 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.0 QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.0 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.0 FUNCTIONAL DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.0 INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.0 APPLICATION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 AV Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 AV Interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4 Phy Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.0 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.0 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.0 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 AV interface and AV layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 IEC 61883 International Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.2 CIP Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.3 The AV Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.4 Content Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.5 mLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.6 SY – Sync Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.7 Programmable Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Bushold and Link/PHY single capacitor galvanic isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.1 Bushold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.2 Single capacitor isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5 The host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5.1 Read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5.2 Write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5.3 Big and little endianness, data invariance, and data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5.4 Accessing the asynchronous packet queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5.5 The CPU bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6 The Asynchronous Packet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6.1 Reading an Asynchronous Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6.2 Link Packet Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.0 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Link Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.1 ID Register (IDREG) – Base Address: 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.2 General Link Control (LNKCTL) – Base Address: 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008 . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018 . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.8 Timer (TIMER) – Base Address: 0x01C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 AV (Isochronous) Transmitter and Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 . . . . . . . . . . . . . . .

13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 . . . . . . . . . . .

13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028 . . . . . . . . . . .

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

26

40

41

46

48

49

50

51

52

53

i

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C . . . . . . . . . . . . . . . .

13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030 . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038 . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 . . . . . . . . . . . . . . . . . . . . . .

13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 . . . . . . . . . .

13.2.10 Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048 . . . . . . . . .

13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C . . . . . . . . . . . . . . . . .

13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050 . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.14 Isochronous Receiver Memory Status (IRXMEM) – Base Address: 0x058 . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 Asynchronous Control and Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084 . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 . . . . . . . . . . . . . . . . . . . . . .

13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) – Base Address: 0x08C . . . . . . . . . . . . . . . . . . . . . .

13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) – Base Address: 0x090 . . . . . . . . . . . . . . . . . . . . .

13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) – Base Address: 0x094 . . . . . . . . . . . . . . . . . . . . .

13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0 . . . . . . . . . . . . . . . . . .

13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.11 RDI Register – Base Address: 0x0B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.12 Shadow Register (SHADOW_REG) – Base Address: 0x0F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 Indirect Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

54

55

56

57

58

59

60

61

62

63

64

65

66

67

70

71

72

73

74

75

13.4.1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2 Indirect Address Register (INDADDR) – Base Address: 0x0F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.3 Indirect Data Register (INDDATA) – Base Address: 0x0FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.5 Indirect Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.5.1 Registers for FIFO Size Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 Pin Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.0 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.0 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.1 AV Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.2 AV Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.3 PHY-Link Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.4 Host Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.5 CYCLEIN/CYCLEOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.6 RESET Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ii

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

1.0 FEATURES

2.0 DESCRIPTION

The PDI1394L41, Philips Semiconductors Full Duplex 1394

• IEEE1394.a and IEEE1394–1995 Standard Link Layer Controller

Audio/Video (AV) Link Layer Controller, is an IEEE 1394–1995

compliant link layer controller featuring 2 embedded AV layer

interfaces. The AV layers are designed to encrypt and pack, or

unpack and decrypt application data packets for transmission over

the IEEE1394 bus using isochronous data transfers and the “5C”

content protection method.

• Hardware Support for the IEC61883 International Standard of

Digital Interface for Consumer Electronics

• Interface to any IEEE 1394–1995 or 1394.a Physical Layer

Interface

• 5V Tolerant I/Os

The application data is packetized according to the IEC 61883

International Standard of Interface for Consumer Electronic

Audio/Video Equipment. Both AV layer interfaces are byte-wide

ports capable of accommodating various MPEG–2 and DVC

codecs. A flexible host interface is provided for internal register

configuration as well as performing asynchronous data transfers.

Both 8 bit and 16 bit wide data paths, as well as

• Single 3.3V supply voltage

• Full-duplex isochronous operation

• Operates with 400/200/100 Mbps physical layer devices

• 12K byte fully programmable FIFO pool for isochronous and

multiplexed/non-multiplexed access modes are supported.

asynchronous data

The PDI1394L41 is powered by a single 3.3V power supply and the

inputs and outputs are 5V tolerant. It is available in the LQFP144

package.

• Supports single capacitor isolation mode and IEEE 1394–1995,

Annex J. isolation

• 6-field deep SYT buffer added to enhance real-time isochronous

2.1 Use restrictions

synchronization using the AVFSYNC pin

Due to rules set forth by the Digital Transmission Licensing

Administrator (DTLA) information concerning some features of the

L41 is the subject of a license issued by the DTLA. That information

has been omitted from this data sheet and is available only to DTLA

licensees on a restricted distribution basis. In order to obtain a copy

of the information, licensed parties should contact Philips

Semiconductors at 1394@philips.com and request data sheet

addendum AL41-1. Upon verification of the requestor’s DTLA

license status, a paper copy of the addendum will be sent to the

DTLA listed responsible person within the requesting company.

Distribution of samples and sales of the L41 chip are likewise

restricted to DTLA licensees. For information pertaining to the

procurement of a DTLA license please consult the DTLA website at

DTCP.com.

• Generates its own AV port clocks under software control. Select

one of three frequencies: 24.576, 12.288, or 6.144 MHz

• Hardware support for the “5C” content protection method

• On chip timer resources

• Flexible 8/16 bit multiplexed/non-multiplexed host interface

• Parallel AV interface

• Fast 56-bit M6 cipher/decipher blocks capable of operating at over

80 Mbps

• Hardware authentication acceleration to reduce software

processor loading

• Highly configurable 12 K byte FIFO

3.0 QUICK REFERENCE DATA

GND = 0V; T

= 25°C

amb

SYMBOL

PARAMETER

Functional supply voltage range

CONDITIONS

MIN

TYP

3.3

MAX

3.6

UNIT

V

DD

3.0

I

Supply current @ V = 3.3V

Operating

110

150

mA

MHz

DD

SCLK

Device clock

49.147

49.152

49.157

4.0 ORDERING INFORMATION

PACKAGES

144-pin LQFP144

TEMPERATURE RANGE

0°C to +70°C

OUTSIDE NORTH AMERICA

NORTH AMERICA

PKG. DWG. #

PDI1394L41BE

SOT486–1

NOTE:

This datasheet is subject to change.

Please visit out internet website www.semiconductors.philips.com/1394 for latest changes.

1

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

5.0 PIN CONFIGURATION

144

109

1

108

LQFP

36

73

37

72

Pin Function

1

2

3

4

5

6

7

8

9

HIF D15

HIF D14

HIF D13

HIF D12

GND

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

HIF WRN

HIF INTN

HIF ALE

HIF RDN

HIF WAIT

RESETN

GND

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

PHY D7*

PHY D6*

PHY D5*

PHY D4*

GND

109 AV1D1

110 AV1D2

111 AV1D3

112 GND

113

V

DD

V

114 AV1D4

115 AV1D5

116 AV1D6

117 AV1D7

118 AV1READY

119 GND

DD

HIF D11

HIF D10

HIF D9

HIF D8

GND

PHY D3*

PHY D2*

PHY D1*

PHY D0*

GND

V

DD

HIF 16BIT

HIF MUX

1394 MODE

PD

RESERVED

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V

120

V

DD

HIF AD7

HIF AD6

HIF AD5

HIF AD4

GND

PHY CTL1*

PHY CTL0*

LREQ

SCLK*

GND

V

DD

LPS*

LINKON

ISON

GND

121 AV2ERR0/LTLEND

122 AV2ERR1/DATINV

123 AV2ENDPCK

124 AV2CLK

125 AV2FSYNC

126 AV2 SY

127 AV2VALID

128 AV2SYNC

129 AV2EMI0

V

DD

HIF AD3

HIF AD2

HIF AD1

HIF AD0

GND

CLK50

CYCLEIN

CYCLEOUT

RESERVED

GND

130 AV2EMI1

131 GND

V

DD

V

AV1ERR0

AV1ERR1

AV1ENDPCK

AV1CLK

132

V

DD

HIF A8

HIF A7

HIF A6

HIF A5

HIF A4

HIF A3

HIF A2

HIF A1

HIF A0

GND

V

133 AV2D0

134 AV2D1

135 AV2D2

136 AV2D3

137 GND

DD

TESTPIN

RESERVED

GND

100 AV1FSYNC

101 AV1 SY

102 AV1VALID

103 AV1SYNC

104 AV1EMIO

105 AV1EMI1

106 GND

138

V

DD

139 AV2D4

140 AV2D5

141 AV2D6

142 AV2D7

143 AV2READY

144 RESERVED

V

DD

V

RESERVED

107

108 AV1D0

V

DD

HIF CSN

*

Indicates pin equipped with internal bus hold circuit activated by the state of the ISON pin.

SV01020

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

6.0 FUNCTIONAL DIAGRAM

HIF A[8:0]

HIF D[15:8]

HIF AD[7:0]

PHY D[0:7]

HIF WRN

HIF RDN

HIF CSN

HIF 16BIT

HIF MUX

RESETN

PHY CTL[0:1]

LPS

LREQ

ISON

LinkOn

SCLK

1394MODE

HIF ALE

HIF WAIT

HIF INTN

PD

VDD

GND

PDI1394L41

IEEE 1394

CONTENT PROTECTION

CYCLEIN

CYCLEOUT

CLK50

AV LINK LAYER CONTROLLER

AV1 D[7:0]

AV1CLK

AV2D[7:0]

AV2CLK

AV1VALID

AV2VALID

AV1SYNC

AV2SYNC

AV2FSYNC

AV2 SY

AV1FSYNC

AV1 SY

AV1READY

AV1EMI[1:0]

AV1ENDPCK

AV2READY

AV2EMI[1:0]

AV2ENDPCK

AV1ERR0

AV1ERR1

AV2ERR0/LTLEND

AV2ERR1/DATAINV

SV01021

7.0 INTERNAL BLOCK DIAGRAM

AV1 D[7:0]

AV1READY

AV1EMI[1:0]

AV1CLK

CYCLEOUT

LPS

CYCLEIN

AV1 LAYER

AV1SYNC

AV1VALID

AV1FSYNC

AV1ENDPCK

AV1ERR0

AV1ERR1

AV1SY

ISOCHRONOUS

TRANSMITTER/

RECEIVER

PHY D[0:7]

12KB BUFFER

MEMORY

(ISOCH & ASYNC

PHY CTL[0:1]

LREQ

LinkOn

LINK CORE

PACKETS)

ISON

PD

AV2 D[7:0]

AV2READY

AV2EMI[1:0]

AV2CLK

AV2SYNC

AV2VALID

SCLK

1394MODE

AV2 LAYER

ISOCHRONOUS

TRANSMITTER/

RECEIVER

NOTE: THERE IS ONE

ISOCHRONOUS RECEIVER

AND ONE ISOCHRONOUS

TRANSMITTER—THEREFORE,

WHEN EITHER AVPORT IS SET

TO TRANSMIT, THE OTHER

AVPORT IS AUTOMATICALLY

SET TO RECEIVE

AV2FSYNC

AV2ENDPCK

AV2ERR0/LTLEND

AV2ERR1/DATAINV

AV2SY

ASYNC

TRANSMITTER

AND

HIF A[8:0]

HIF D[15:8]

RECEIVER

HIF AD[7:0]

HIF 16BIT

HIF WRN

HIF ALE

CONTROL

AND

STATUS

RESETN

8-BIT

INTERFACE

REGISTERS

HIF RDN

HIF MUX

HIF CSN

HIF WAIT

HIF INTN

SV01022

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

8.0 APPLICATION DIAGRAM

AV

MPEG OR DVC

DECODER

INTERFACE

PDI1394L41

AV LINK

PDI1394Pxx

PHY

PHY–LINK

INTERFACE

1394 CABLE

INTERFACE

AV

MPEG OR DVC

DECODER

INTERFACE

DATA 16/

ADDRESS 9/

INTERRUPT & CONTROL

HOST CONTROLLER

SV01023

9.0 PIN DESCRIPTION

9.1 Host Interface

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

13, 14, 15, 16, 19,

20, 21, 22

HIF AD[7:0]

HIF D[15:8]

HIF A[7:0]

I/O

Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.

1, 2, 3, 4, 7, 8, 9,

10

Host Interface Data 15 (MSB) through 8. Only used in 16 bit access mode (HIF

16BIT = HIGH).

I/O

26, 27, 28, 29, 30,

31, 32, 33

Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal

registers. See description of Host Interface for addressing rules (Section 12.5).

Control bit used to indicate the first byte/word of a read function or the last byte/word of a write

function so that the data quadlet is fetched or stored. See Section 12.5 for more information

regarding the host interface.

25

36

HIF A8

I

Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control

and status registers.

HIF CSN

Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L41

internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in

conjunction with HIF CSN, then a write cycle takes place. This can be used to connect CPUs

that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the

R/W_N line to the HIF WRN and tie HIF RDN LOW.)

37

HIF WRN

I

Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L41. Read the General

Interrupt Register for more information. This pin is open drain and requires a 1KW pull-up

resistor.

38

HIF INTN

O

39

40

HIF ALE

HIF RDN

I

Address latch enable. Used in multiplex mode only.

Read enable. When asserted (LOW) in conjunction with HIF CSN, a read of the PDI1394L41

internal registers is requested.

41

42

HIF WAIT

RESETN

O

I

Wait signal. Signals Host interface in WAIT condition when HI. See Section 12.5.

Reset (active LOW). The asynchronous master reset to the PDI1394L41.

Host interface mode pin. When LOW HIF operates in 8 bit mode. When HIGH HIF operates in

16 bit mode.

45

HIF 16BIT

I

Host interface mode pin. When LOW HIF operates in non-multiplex mode, when HIGH HIF

operates in multiplex mode. When HIGH, the low-order eight address bits are multiplexed with

data on HIF AD[7:0], otherwise they are non-multiplexed and supplied on A[7:0].

46

HIF MUX

I

4

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

9.2 AV Interface 1

NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register

(0X018)—default is transmit.

PIN No.

PIN SYMBOL

I/O

O

I

NAME AND FUNCTION

CRC error. Indicates bus packet delivered on AV1 D[7:0] had a CRC error; the current AV

packet is unreliable.

96

AV1ERR0

97

AV1ERR1

Sequence Error. Indicates at least one source packet was lost before the current AV1 D [7:0] data.

End of application packet indication from data source. Required only if input packet is not

multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.

98

AV1ENDPCK

External application clock. Rising edge active. This pin can be programmed to be an output

and the application clock. Depending on the configuration of AV Port 1 as transmitter or receiver,

the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL register

(address 0x040).

99

AV1CLK

I/O

Programmable frame sync, is set to input when AV interface 1 is a transmitter and to output

when the interface is configured as a receiver. When the pin is an input, it is used to designate

a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT

field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.

100

AV1FSYNC

SY Value. When port AV1 is configured as a transmitter, this pin is an input. When the AV port

is configured to as a receiver, the pin is an output. See the description for bit 0 of the

ITXCTL (0x034) and IRXCTL (0x054) registers.

101

102

AV1 SY

I/O

AV1VALID

Indicates data on AV1 D [7:0] is valid.

Indicates that the data currently being clocked by the source under the condition of AV1VALID

is the start of an application packet. If the AV interface is configured as a receiver, then it will

assert AV1SYNC when an application packet becomes available and persist until the first data

of the packet is clocked out. Thus, AV1VALID may last for more than one cycle, but for exactly

one cycle in which AV1VALID is asserted.

103

AV1SYNC

I/O

Encryption Mode Indication pins. Outputs encryption mode when this AV port is in receive state

with decipher enabled.

105, 104

AV1EMI[1:0]

AV1 D[7:0]

O

117, 116, 115, 114,

111, 110, 109, 108

I/O

Audio/Video Data 7 (MSB) through 1. Part of byte-wide interface to the AV layer 1.

When the AV port is configured as a receiver, this pin is an input. This is a flow control signal

that allows the destination to indicate whether it is able to accept data flowing across

AV Interface 1. The AV interface responds to an inactive AV1READY by not asserting

AV1VALID, and thereby withholding data.

I

The AV1READY signal is processed through one level of pipelining, which means that the

AV Link will accept data on the cycle in which AV1READY is de-asserted and will not accept

data on the cycle in which AV1READY is asserted.

118

AV1READY

When the AV port is configured to transmit, this pin is an output. This is a flow control signal

that allows the destination to indicate whether it is able to accept data flowing across

AV Interface 1. The source of data, an external entity, responds to an inactive AV1READY by

not asserting AV1VALID, and thereby withholding data.

O

The AV1READY signal should be processed by the sink through one level of pipelining, which

means that the receiver must be able to accept data on the cycle in which AV1READY is

de-asserted. The receiving interface does not have to accept data on the cycle in which

AV1READY is asserted.

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

9.3 AV Interface 2

NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is

receive.

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

CRC error, indicates bus packet containing AV2 D [7:0] had a CRC error, the current AV packet

is unreliable. This pin is also used to input the mode of LTLEND (Little Endian) bit after a chip

reset. An appropriate pull-up or pull-down resistor (22 kΩ recommended) should be connected

to place the pin in the desired state during reset. Please see details related to use of the

LTLEND bit in the “Host Interface” section (of the datasheet (Section 12.5).

AV2ERR0/

LTLEND

121

I/O

Sequence Error. Indicates at least one source packet was lost before the current AV2 D [7:0]

data. This pin is also used to input the mode of DATINV (Data Invariant) bit after a chip reset.

An appropriate pull-up or pull-down resistor (22 kΩ recommended) should be connected to

place the pin in the desired state during reset. Please see details related to use of the DATINV

bit in the “Host Interface” section (of the datasheet (Section 12.5).

AV2ERR1/

DATINV

122

I/O

End of application packet indication from data source. Required only if input packet is not

multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.

123

124

AV2ENDPCK

AV2CLK

I

External application clock. Rising edge active. This pin can be programmed to be an output

and the application clock. Depending on the configuration of AV Port 2 as transmitter or

receiver, the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL

register (address 0x040).

I/O

Programmable frame sync, is set to input when AV interface 2 is a transmitter, and to output

when the interface is configures as a receiver. When the pin is an input, it is used to designate

a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT

field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.

125

AV2FSYNC

I/O

SY Value: When port AV2 is configured as a transmitter, this pin is an input. When the AV port

is configured to as a receiver, the pin is an output. See the description for bit 0 of the

ITXCTL (0x034) and IRXCTL (0x054) registers.

126

127

AV2 SY

I/O

AV2VALID

Indicates data on AV2 D [7:0] is valid.

Indicates that the data currently being clocked by the source under the condition of AV2VALID

is the start of an application packet. If the AV interface is configured as a receiver, then it will

assert AV2SYNC when an application packet becomes available and persist until the first data

of the packet is clocked out. Thus, AV2VALID may last for more than one cycle, but for exactly

one cycle in which AV2VALID is asserted.

128

AV2SYNC

I/O

Encryption Mode Indication pins. Outputs encryption mode when this AV port is in receive state

with decipher enabled.

130, 129

AV2EMI[1:0]

AV2 D[7:0]

O

142, 141, 140,

139, 136, 135,

134, 133

I/O

Audio/Video Data 7 (MSB) through 0. Part of byte-wide interface to the AV layer 2.

When the AV port is configured as a receiver, this pin is an input. This is a flow control signal

that allows the destination to indicate whether it is able to accept data flowing across

AV Interface 2. The AV interface responds to an inactive AV2READY by not asserting

AV2VALID, and thereby withholding data.

I

The AV2READY signal is processed through one level of pipelining, which means that the

AV Link will accept data on the cycle in which AV2READY is de-asserted and will not accept

data on the cycle in which AV2READY is asserted.

143

AV2READY

When the AV port is configured to transmit, this pin is an output. This is a flow control signal

that allows the destination to indicate whether it is able to accept data flowing across

AV Interface 2. The source of data, and external entity, responds to an inactive AV2READY by

not asserting AV2VALID, and thereby withholding data.

O

The AV2READY signal should be processed by the sink through one level of pipelining, which

means that the receiver must be able to accept data on the cycle in which AV2READY is

de-asserted. The receiving interface does not have to accept data on the cycle in which

AV2READY is asserted.

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

9.4 Phy Interface

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of

the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on

AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE 1394–1995

standard, Annex J for more information.

82, 81, 80, 79,

76, 75, 74, 73

PHY D[0:7]

I/O

86, 85

47

PHY CTL[0:1]

1394 MODE

I/O

I

Control Lines between Link and Phy. See 1394 Specification for more information.

1394–1995 Annex J PHY (HIGH), or 1394.a PHY (LOW)

Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more

information. (Used to request arbitration or read/write PHY registers).

87

LREQ

O

88

91

SCLK

LPS

I

System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency).

Link power status.

O

L41 generates a host interrupt when this pin receives a link on signal from the PHY. Interrupt is a

request from another node for the L41 to be powered up (see PD pin).

92

LINKON

I

Isolation mode. This pin is asserted (LOW) when an Annex J type isolation barrier is used.

See IEEE 1394–1995 Annex J. for more information. When tied HIGH, this pin enables internal

bushold circuitry on the affected PHY interface pins (see below). Active bushold circuits allow

either the direct connection to PHY pins or the use of the single capacitor isolation mode.

93

ISON

9.5 Other Pins

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

5, 11, 17, 23,

34, 43, 53, 60,

69, 77, 83, 89,

94, 106, 112,

119, 131, 137

GND

Ground reference

6, 12, 18, 24,

35, 44, 54, 61,

70, 78, 84, 90,

95, 107, 113,

120, 132, 138

V

DD

3.3V ± 0.3V power supply

Power Down. When asserted (high), the AV Link goes into a low power mode and de-asserts the

LPS pin. When in this state, reads and writes to the registers are not allowed. The AV Link will

resume operation when PD is de-asserted (low), all register settings and configurations are

restored to their pre power down values.

1,2,3,4

48

PD

I

49, 50, 51, 52,

58, 59, 65, 66,

67, 68, 71, 72

144

These pins are reserved for factory testing. For normal operation they should be connected to

ground.

RESERVED

NA

55

56

CLK50

O

I

Auxiliary clock, value is SCLK (usually 49.152 MHz)

Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus

cycles.

CYCLEIN

57

CYCLEOUT

TESTPIN

O

Reproduces the 8kHz cycle clock of the cycle master.

Test pins. These signals must be connected to ground.

62, 63, 64

NOTES:

Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the following state of operation:

1. The isochronous transmit FIFO is not receiving data for transmission

2. The isochronous transmitter is disabled

3. No asynchronous packets are being generated for transmission

4. Both the ASYNC request and response queues are empty

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

10.0 RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MAX.

MIN.

3.0

0

V

CC

DC supply voltage

Input voltage

3.6

5

V

I

V

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Input transition rise or fall time

Operating ambient temperature range

System clock

2.0

V

IH

V

0.8

4

V

IL

I

mA

ns/V

°C

OH

I

OL

–4

dT/dV

0

20

T

amb

0

49.147

0

+70

49.157

24

SCLK

MHz

ns

AVCLK

AV interface clock

t

Input rise time

10

r

t

f

input fall time

10

ns

1, 2

11.0 ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

UNIT

MIN

–0.5

–

MAX

+4.6

–50

V

I

V

mA

V

DD

DC input diode current

DC input voltage

IK

V

I

–0.5

–

+5.5

±50

I

DC output diode current

DC output voltage

mA

V

OK

V

O

–0.5

–

V

+0.5

DD

I

O

DC output source or sink current

±50

mA

°C

W

I

, I

DC V or GND current

–

±150

150

70

GND CC

CC

T

stg

Storage temperature range

Operating ambient temperature

Power dissipation per package

–60

0

T

amb

P

tot

0.6

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

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2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

12.0 FUNCTIONAL DESCRIPTION

12.1 Overview

The PDI1394L41 is an IEEE1394–1995 and IEEE1394.a compliant link layer controller. It provides a direct interface between a 1394 bus and

various MPEG–2 and DVC codecs. The AV Link maps and unmaps AV data streams and similar data onto 1394 isochronous packets. Data can

be ciphered or deciphered according to the ‘5C’ standard method of content protection. The AV Link also provides an 8 bit or 16 bit wide host

interface for an attached microcontroller. Through the host interface port, the host controller can configure the AV layer for transmission or

reception of AV datastreams. The host interface port also allows the host controller to transmit and receive 1394 asynchronous data packets.

12.2 AV interface and AV layer

The AV interface and AV layer format “application packets” according to the IEC 61883 specification for isochronous transport over the 1394

network. The AV transmitter and receiver within the AV layer perform all the functions required to pack and unpack AV packet data for transfer

over a 1394 network. Once the AV layer is properly configured for operation, no further host controller service should be required. The operation

of the AV layer is full-duplex, i.e., the AV layer can receive and transmit AV packets on the same bus cycle.

12.2.1 IEC 61883 International Standard

The PDI1394L41 is specifically designed to support the IEC61883 International Standard of Digital Interface for Consumer Electronic

Audio/Video Equipment. The IEC specification defines a scheme for mapping various types of AV datastreams onto 1394 isochronous data

packets. The standard also defines a software protocol for managing isochronous connections in a 1394 bus called Connection Management

Protocol (CMP). It also provides a framework for transfer of functional commands, called Function Control Protocol (FCP).

12.2.2 CIP Headers

A feature of the IEC61883 International Standard is the definition of Common Isochronous Packet (CIP) headers. These CIP headers contain

information about the source and type of datastream mapped onto the isochronous packets.

The AV Layer supports the use of CIP headers. CIP headers are added to transmitted isochronous data packets at the AV data source. When

receiving isochronous data packets, the AV layer automatically analyzes their CIP headers. The analysis of the CIP headers determines the

method the AV layer uses to unpack the AV data from the isochronous data packets.

The information contained in the CIP headers is accessible via registers in the host interface.

(See IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment for more details on CIP headers).

12.2.3 The AV Interface

The AV link’s 8-bit parallel interface is synchronous with AVxCLK, and was designed to interface with various MPEG-2 and DVC codecs. The

AV interface port buffer, if so programmed, can time stamp incoming AV packets. The AV packet data is stored in the embedded memory buffer,

along with its time stamp information. After the AV packet has been written into the AV layer, the AV layer creates an isochronous bus packet

with the appropriate CIP header. The bus packet along with the CIP header is transferred over the appropriate isochronous channel/packet.

The size and configuration of isochronous data packet payload transmitted is determined by the AV layer’s configuration registers accessible

through the host interface.

The AV interface port waits for the assertion for AVxVALID and AVxSYNC. AVxSYNC is aligned with the rising edge of AVxCLK and the first

byte of data on AVxDATA[7:0]. The duration of AVxSYNC is one AVxCLK cycle. AVxSYNC signals the AV layer that the transfer of an AV packet

has begun. At the time the AVxSYNC is asserted, the AV layer creates a new time stamp in the buffer memory. (This only happens if so

configured. The DVC format does not require these time stamps). The time stamp is then transmitted as part of the source packet header. This

allows the AV receiver to provide the AV packet for output at the appropriate time. Only one AVSYNC pulse is allowed per application packet; if

additional sync pulses are presented before the full packet is inputted, a new packet will be started and the previously inputted packet data will

be discarded (and not transmitted) in conjunction with the input error interrupt bit (INPERR, bit 3 of register 0x02C) being set to flag the error.

An additional synchronization mechanism is defined by the IEC 61883 specification, called frame sync. The frame synchronization signal

AVxFSYNC is time stamped and placed in the SYT field of the CIP header. The default delay value for the frame sync is 3 bus cycle times

(duration of 125 µs each) in the future, and is transmitted on the very next isochronous cycle regardless of available data. The PDI1394L41

allows this value to be programmable from 2 to 4 cycle times (see section 13.2.1). Additionally, for some audio applications, the SYT value can

be programmed to be appended only to isochronous cycles that have application data attached to them. This mode is enabled via the ‘mLAN’

bit (again, see section 13.2.1). When the mLAN mode is enabled, two additional cycle delays are automatically added to the SYT_DELAY value

(bits 6 and 5 of the ITXPKCLT register). On the receiver side, when the SYT stamp matches the cycle timer register, a pulse is generated on the

AVxFSYNC output. The timing for AVxFSYNC is independent of AVxCLK.

Some applications would like to create their own transmit timestamps independent of the AV Layer. On receive, these applications would like to

process the embedded time stamps instead of allowing the AV Layer to process these time stamps. This can be accommodated via the

ENXTMSTMP bit in the ITXPKCTL register for transmit and DIS_TSC bit in the IRXPKCTL register for receive. In conjunction with this mode,

additional means of flow control are enabled via the AVxREADY signal.

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PDI1394L41

Port Dir

AVxREADY

Description

Transmit

Out

The L41 is prepared to receive a byte. The attached device will not assert AVVALID for any cycle in which

AVxRDY is false.

Receive

In

The attached device is prepared to receive a byte. The L41 will not assert AVxVALID for any cycle in which

AVxREADY is false.

When the AV port is configured as a receiver, the AVxSYNC signal will be asserted as soon as the PDI1394L41 AVx port has an application

packet available for delivery (independent of AVxREADY) and will remain asserted until the first byte of the application packet is clocked from

the AV port.

12.2.4 Content Protection

The AV Layer incorporates features to implement the Digital Transmission Copy Protection (DTCP) scheme that is specified by the Digital

Transmission Licensing Authority (DTLA). The DTCP specification consists of two primary functions: stream ciphering and authentication. Refer

to “5C Digital Transmission Content Protection Specification – Volume 1” for more details about the DTCP scheme.

On the AV Link stream ciphering is accomplished by internal 56 bit M6 content cipher and decipher blocks. To ease software development effort

and reduce the loading on the controlling processor, the link chip also includes a cryptographic accelerator capable of doing elliptic curve

multiplications and Sign and Verify operations.

Due to the size and number of operands for the M6 and cryptographic accelerator blocks, the host interface register set has been extended to

provide additional control and data registers. These extensions have been implemented via an indirect addressing mechanism. This mechanism

allows software written for previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L41. Note, however, that

some extensions to the interrupt registers were made to accommodate interrupts originating from the content protection block.

For a full description of the use of the L41’s content protection features please see data sheet addendum AL41–1. AL41–1 addendum can be

requested from Philips by DTLA licensees by e-mailing 1394@philips.com. One paper copy of this addendum is available to each DTLA

licensee after verification of license status. Please see Section 2.1 of this data sheet for further information. DTLA license information is

available at DTCP.com.

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PDI1394L41

12.2.5 mLAN Support

The AV transmitter has some additional features to support mLAN (IEC 61883-6). These are enabled by setting bit 30 of ITXPKCTL (0x020) to

logic 1. At the rising edge of AVxFSYNC, a SYT time stamp will be generated and written into the SYT queue of the isochronous transmitter.

This stamp will point to a time in the future dictated by the following formula:

SYT[15:12] = CYCTM[15:12] + programmed SYT_DELAY value + 2

SYT[11:0] = CYCTM[11:0]

The additional delay of two cycles is specific to this mLAN mode. The oldest SYT time stamp in the SYT queue will be sent first, but only when

accompanied by a data payload. Any pending SYT time stamp will be held until the next non-empty bus packet is sent. At the moment of

transmission, the SYT time stamp should at least point one cycle in the future. If it points to a time that is less than one cycle in the future, it will

be discarded.

The SYT queue in the isochronous transmitter can store 4 entries, the SYT queue in the isochronous receiver can store six entries. This

supports the case where an 8 kHz signal is applied to AVxFSYNC, and mLAN = 1, and SYT_Delay = 2. Assuming there is data on every cycle,

the receiver will receive an SYT time stamp each cycle with the first SYT time stamp pointing just less than six cycles in the future. When the

SYT queue in the isochronous receiver is full, then the most recently received SYT time stamp is overwritten with the next arriving SYT time

stamp.

12.2.6 SY – Sync Support

This feature supports the 1394 digital camera specification. The state of this pin will be reflected in the SY bit (ITXCTL register 0x034) and will

be transmitted along with the isochronous data block that was entered with it. The intended use of this pin is to signal the start of a new frame of

video in the isochronous header section of the data payload. Similarly, the isochronous receiver will assert the AVxSY pin simultaneously with

the first byte of the isochronous bus packet in which the SY value was received. NOTE: The SY functionality is only intended to be used when

the M6 cipher and de-cipher are not enabled.

AV DATA

AV SYNC

AV SY

SV01787

Figure 1. Behavior of sysncr

12.2.7 Programmable Buffer Memory

The PDI1394L41 maintains six distinct buffers that are highly configurable to optimize bandwidth capabilities. Buffers can be increased or

decreased from the default value by accessing the indirect address range of 0x100 through 0x1FC (INDADDR, 0x0F8). If the AV Layer is

configured to transmit or receive DVB compliant MPEG-2 type data, the default Isochronous (AV) buffer sizes are recommended. FIFO sizes

cannot be changed dynamically; after a FIFO size change, transmitters and receivers must be reset.

Buffers can be programmed with 64 quadlet (256 Byte) granularity. Minimum buffer size is 64 quadlets, maximum buffer size is limited to 11 kB.

The sum of all buffers cannot exceed 12K Bytes, or 3K Quadlets.

DEFAULT BUFFER SIZE

SIZE

BUFFER MEMORY

(Quadlets)

Asynchronous Receive Response FIFO

Asynchronous Receive Request FIFO

Asynchronous Transmit Response FIFO

Asynchronous Transmit Request FIFO

Isochronous (AV) Transmit Buffer

256

1024

Isochronous (AV) Receive Buffer

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PDI1394L41

12.3 Bushold and Link/PHY single capacitor galvanic isolation

12.3.1 Bushold

The PDI1394L41 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by

a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal

oscillation and excess power supply current draw.

The following pins have bushold circuitry enabled when the ISON pin is in the logic “1” state:

Name

Function

PHY CTL0

PHY CTL1

PHY D0

PHY D1

PHY D2

PHY D3

PHY D4

PHY D5

PHY D6

PHY D7

PHY control line 0

PHY control line 1

PHY data bus bit 0

PHY data bus bit 1

PHY data bus bit 2

PHY data bus bit 3

PHY data bus bit 4

PHY data bus bit 5

PHY data bus bit 6

PHY data bus bit 7

Philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. This high resistance is easily overcome

by the driving device when its state is switched. Figure 2 shows a typical bushold circuit applied to a CMOS input stage. Two weak MOS

transistors are connected to the input. An inverter is also connected to the input pin and supplies gate drive to both transistors. When the input

is LOW, the inverter output drives the lower MOS transistor and turns it on. This re-enforces the LOW on the input pin. If the logic device which

normally drives the input pin were to be 3-Stated, the input pin would remain “pulled-down” by the weak MOS transistor. If the driving logic

device drives the input pin HIGH, the inverter will turn the upper MOS transistor on, re-enforcing the HIGH on the input pin. If the driving logic

device is then 3-Stated, the upper MOS transistor will weakly hold the input pin HIGH.

The PHY’s outputs can be 3-Stated and single capacitor isolation can be used with the Link; both situations will allow the Link inputs to float.

With bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this

arrangement keeps the inputs in known logical states.

INTERNAL

INPUT PIN

CIRCUITS

SV00911

Figure 2. Bushold circuit

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PDI1394L41

12.3.2 Single capacitor isolation

The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation.

NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits

provide local dc ground references to each side of the isolating/coupling capacitors. Also note that ground isolation/signal-coupling must be

provided in the form of a parallel combination of resistance and capacitance as indicated in the IEEE 1394 standard.

APPLICATION/LINK

+3.3V

ISOLATED/PHY

+3.3V

ISON

ISO–

SYSCLK

D0

D1

D2

D3

D4

D5

D6

C

c

SCLK

PHY D0

PHY D1

PHY D2

PHY D3

PHY D4

PHY D5

PHY D6

PHY D7

PHYCTL0

PHYCTL1

LREQ

LINK

PDI1394L41

PHY

PDI1394P2x

C

c

C

c

L

C

c

C

c

D7

PHYCTL0

PHYCTL1

LREQ

LPS

LINKON

LINK

3.3V

PHY

3.3V

C

L

APPLICATION AND LINK GROUND

ISOLATED PHY GROUND

13K

VALUES OF THESE RESISTORS DEPEND

ON PHY USED. SEE PHY DATASHEET.

9.1K

ALSO SEE APPLICATION NOTE AN2452

FOR MORE DETAILS

C

c

1MEG Ω

C

r

C

= 1 nF; C = 100 nF; C = 3.3nF

r L

C

SV01816

Figure 3. Single capacitor Link/PHY isolation

12.4 Power Management

The PDI1394L41 implements several features for power management as noted in the P1394a draft 5.0. These features include:

1. Reset of the Phy/Link interface by setting the RPL bit in the LNKCTL register.

2. Disable of the Phy/Link interface caused by either setting the SWPD bit in the RDI register –OR– asserting (high) the PD pin.

3. Initialization of the Phy/Link interface after it was disabled or reset.

The application can power up the Phy/Link interface by deasserting the PD pin –OR– clearing (low) the SWPD in the RDI register. This will

cause the L41 to produce a pulsing signal on the LPS pin. When the L41 is in power down mode, reads and writes to the host interface will be

restricted to those addressing only the RDI register (0x0B0). Please see Section 13.3.11 for further details.

There are 3 ways to power up the L41. (1) When the application wants the 1394 node to resume operation, it simply needs to de–assert the PD

pin, or (2) clear the SWPD bit in the RDI register. The link can also be awakened by another bus node sending a link–on packet to the PHY of

the application’s node. (3) The attached PHY will activate its LinkOn line and the L41 will see the signal and set the LOA bit of the RDI register

(assuming that the ELOA bit is in its enabled, ”1”, state). The L41 will generate an interrupt of the host processor. It will then be up to the host

processor to decide whether to honor the link–on request of the other node. Then the host processor will de–assert the PD pin –OR– clear the

SWPD bit in the RDI register. This activity will power up the L41 causing it to send the pulsing signal out on the LPS pin which notifies the

PHYchip of link activity and allows the PHY to discontinue directing the link on signal to the L41. Subsequently, the host processor must

acknowledge the LOA interrupt by writing a ”1” to the LOA bit position in the RDI register after the link on signal from the PHY has stopped.

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PDI1394L41

12.5 The host interface

The host interface allows an 8 bit or 16 bit CPU to access all registers and the asynchronous packet queues. It is designed to be easy to use

with a wide range of processors, including 8051, MIPS1900, ST20, PowerPC etc. The host interface can work with 8 bit or 16 bit wide data

paths, and offers multiplexed or non-multiplexed access. There are 64 register addresses (for quadlet wide registers). To access bytes rather

than quadlets the address space is 256 bytes, requiring 8 address lines.

The use of an 8 bit or 16 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be

used (control) or changed (status) at every internal clock tick. If such a field is accessed through an 8 bit or 16 bit interface it requires more than

one read or write cycle, and the value should not change in between to maintain consistency. To overcome this problem accesses to the chip’s

internal register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit

or 16 bit accesses. This is where the shadow register (0x0F4) is used.

12.5.1 Read accesses

To read an internal register the host interface can make a snapshot (copy) of that specific register which is then made available to the CPU 8 or

16 bits at a time. The register that holds the snapshot copy of the real register value inside the host interface is called the shadow register.

During an 8-bit read cycle address lines HIF A0 and HIF A1 are used to select which of the 4 bytes currently stored in the shadow register is

output onto the CPU data bus. This selection is done by combinatorial logic only, enabling external hardware to toggle these lines through

values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an

external quadlet register. During a 16 bit read cycle address line HIF A1 is used to select which pair of 4 bytes currently stored in the shadow

register is output to the CPU bus. Again the selection is by combinatorial logic, enabling external hardware to toggle HIF A1 while keeping the

chip in read access mode to get both words very quickly.

This solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as well as the internal

address of the target register. The register address is connected to input address lines HIF A2..HIF A7, and the update control line to input

address line HIF A8. To let the host interface take a new snapshot the target address must be presented on HIF A2..HIF A7 and HIF A8 must be

raised while executing a read access. The new value will be stored in the shadow register and the selected byte (HIF A0, HIF A1, 8 bit mode)

or word (HIF A1, 16 bit mode) appears on the output.

Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the

FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly

addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).

TR

MUX

Q

8/16

32

CPU

REGISTERS

HIF A0..1 (8 BIT MODE)

HIF A1 (16 BIT MODE)

32

HIF A2..7

HIF A8

UPDATE/COPY CONTROL

SV01034

NOTES:

1. It is not required to read all 4 bytes of a register before reading another register. For example, in 8 bit mode, if only byte 2 of register 0x54 is

required a read of byte address 0x100 + (0×54) + 2 = 0x156 is sufficient.

2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by

other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. This

makes the internal updating automatic for quadlet reading.

3. Reading the bytes of the shadow register can be done in any order and as often as needed.

4. It is possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an enable

bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of the

modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.

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PDI1394L41

12.5.2 Write accesses

To write to an internal register the host interface must collect the 4 byte values (8 bit mode) or 2 word values (16 bit mode) into a 32 bit value

and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is

ready to be written to the actual target register. This temporary register inside the host interface is called the shadow register. In 8 bit mode,

address lines HIF A0 and HIF A1 are used to select which of the 4 bytes of the shadow register is to be written with the value on the CPU data

bus. In 16 bit mode, HIF A1 is used to select which half of the shadow register is to be written with the value on the CPU data bus. Only one

byte (8 bit mode) or one word (16 bit mode) can be written in a single write access cycle.

Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the

FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly

addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).

TR

MUX

Q

MUX

8/16

32

CPU

REGISTERS

SV01035

HIF A0..1 (8 BIT MODE)

HIF A1 (16 BIT MODE)

32

HIF A2..7

HIF A8

UPDATE/COPY CONTROL

NOTES:

1. It is not required to write all 4 bytes, or both words of a register: those bytes that are either reserved (undefined) or don’t care do not have

to be written in which case they will be assigned the value that was left in the corresponding byte of the shadow register from a previous

write access. For example, to acknowledge an interrupt for the isochronous receiver in 8 bit mode, a single byte write to location

0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but

instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic

as soon as possible without CPU intervention.

2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by

other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3 or the

upper 16 bits. This makes the internal updating automatic for quadlet writing.

3. Writing the bytes or words of the shadow register can be done in any order and as often as needed (new writes simply overwrite the old

value).

4. It is now possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an

enable bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of

the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.

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PDI1394L41

12.5.3 Big and little endianness, data invariance, and data bus width

The host interface offers programmable endianness, data invariance, and selectable 8 and 16 bit data widths. LTLEND (pin 121) and DATINV

(pin 122) are multiplexed configuration pins that will be sampled on the trailing edge of RESET; the states of these pins are established by

connecting each pin to the proper logic state, ground or V , through a resistor, 22 kΩ is recommended. To verify the configuration, the shadow

DD

register (0x0F4) will be preset to a value of 0x0F0A0500 after a power reset. Table 1 describes the configurations.

Table 1. Configuration possible combinations

LTLEND (Little Endian)

DATINV (Data Invariant)

HIF 16BIT

Result

1

0

1

0

See Table 2

Byte/Word address is reversed

1

0

Bytes are swapped within the word

16-bit data bus, address as in PDI1394L21

8-bit data bus, address as in PDI1394L21

X

Table 2. Explanation of the mode LittleEnd = 1, DataInvariant = 1

HIF16 = 0

HIF16 = 1

Outside Address (A1, A0)

Inside Address (A1, A0)

Outside Address (A1, A0)

Inside Address (A1, A0)

00

01

10

11

10

01

00

0X

1X

0X

It is important to note that some operands in the indirect address space consist of more than one quadlet. For these operands, the lowest

address always contains the most significant quadlet.

In Bit Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as

shwon in Figure 4.

To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:

E = N ; to access the upper 8 bits of the register.

E = N + 1 ; to access the upper middle 8 bits of the register.

E = N + 2 ; to access the lower middle 8 bits of the register.

E = N + 3 ; to access the lower 8 bits of the register.

To access a register in 16 bit HIF mode, at internal address N, the CPU should use addresses E:

E = N ;to access the upper 16 bits of the register

E = N + 2 ;to access the lower 16 bits of the register

3130 29 28 27 2625 24 23 22 212019 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BYTE 0

BYTE 1

BYTE 2

BYTE 3

SV00656

Figure 4. Byte order in quadlets as implemented in the host interface, HIF LTLEND = LOW

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PDI1394L41

In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant)

as shown in Figure 5. To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:

E = N + 3 ;to access the upper 8 bits of the register

E = N + 2 ;to access the upper middle 8 bits of the register

E = N + 1 ;to access the lower middle 8 bits of the register

E = N ;to access the lower 8 bits of the register

To access a register in 16 bit HIF mode, at internal address N, the CPU should used addresses E:

E = N ;to access the lower 16 bits of the register

E = N + 2 ;to access the upper 16 bits of the register

3130 29 28 27 2625 24 23 22 212019 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BYTE 3

BYTE 2

BYTE 1

BYTE 0

SV01079

Figure 5. Byte order in quadlets as implemented in the host interface, HIF LTLEND = HIGH

12.5.4 Accessing the asynchronous packet queues

Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and

only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the

two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the

next stored data quadlet accessible.

With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow register. Once the data

is copied into the shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes, or both words, before

attempting any other read access (be careful with interrupt handlers for the PDI1394L41!).

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PDI1394L41

12.5.5 The CPU bus interface signals

The CPU interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. It uses

separate HIF RDN, HIF WRN, HIF ALE, and HIF CSN chip select lines. There are 9 address inputs (HIF A0..HIF A8) and 8 or 16 data in/out

lines HIF D[7:0] or HIF D [15:0]. The upper 8 bits of the data in/out lines are only used when the 8/16 bit mode pin (HIF16BIT) is held HIGH.

The CPU is not required to run a clock that is synchronous to the 1394 base clock. The control signals will be resampled by the host interface

before being used internally.

In non-multiplex mode (HIF MUX = LOW), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RDN = 0.

Typically the chip select signal is derived from the upper address lines of the CPU (address decode stage), but it could also be connected to a

port pin of the CPU to avoid the need for an external address decoder in very simple CPU systems. When both HIF CSN = 0 and HIF RDN = 0

the host interface will start a read access cycle, so the cycle is triggered at the falling edge of either HIF CSN or HIF RDN, whichever is later.

In multiplex mode (HIF MUX = HIGH), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RD_N = 0.

The address must now be presented on the HIF AD [7:0] lines, and will be latched on the falling edge of ALE. If HIF RDN = 0, data will be

offered after the falling edge of ALE. If HIF WRN = 0, data has to be presented by the microcontroller.

In both multiplexed and non-multiplexed mode, HIF WAIT can be used to signal to the controlling CPU that an extension of the current access

cycle is needed. This allows the PDI1394L41 to work in the same address space as peripherals with a shorter access time. HIF WAIT will

remain HIGH for the minimum duration of the access cycle. If HIF A[8] is HIGH, HIF WAIT will extend the access cycle to 120ns to allow for the

shadow register transfer to take place. Subsequent access to the same register which does not required A[8] to be raised, can be executed

much faster. By connecting HIF WAIT to the appropriate input on the controlling processor, the PDI1394L41 can be mapped in memory space

with faster devices. The PDI1394L41 should not be mapped in memory space with devices that require access faster than 15 ns.

HIF A[7:0] can be used as a simple demultiplexer. In multiplex mode, the address on AD[7:0] will appear on A[7:0] immediately, and will remain

there until the next rising edge of HIF ALE.

HIF CS_N

HIF RD_N

HIF WR_N

HIF A8

HIFA7–A0

HIFD15–D8

HIFAD7–AD0

HIF_WAIT

HIF_MUX

HIF16BIT

NOTE: ALE line is held LOW.

An extended read cycle may be implemented by holding CS_N and RD_N low (active)

and changing only the A7–A0 address. After each new address stabilizes, wait at least

t

and read the data. The extended read cycle can be used only following a read of

ACC

the first byte of the shadow register using the A8 transfer mechanism. See the section

on Read Accesses (12.5.1).

SV01088

Figure 6. 16 Bit Read Cycle Non-multiplexed

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PDI1394L41

HIF CS_N

HIF RD_N

HIF WR_N

HIFA7–A0

HIFD15–D8

HIFAD7–AD0

A8

HIF_WAIT

HIF_MUX

HIF16BIT

NOTE: ALE line is held LOW.

SV01089

Figure 7. 16 Bit Write Cycle Non-multiplexed

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PDI1394L41

HIF CS_N

HIF ALE

AD7–AD0

ADDR

DATA

ADDR

DATA

LATCHED

A7–A0

HIFD15–D8

A8

DATA

HIF RD_N

HIF WR_N

HIF_WAIT

HIF_MUX

HIF16BIT

Note: Second write cycle elongated by WAIT signal.

SV01090

Figure 8. 16 Bit Write Cycle Multiplexed

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HIF CS_N

HIF ALE

HIF AD7–AD0

ADDR

DA TA

ADDR

DA TA

HIF A7–A0

HIFD15–D8

A8

LATCHED

DATA

HIF RD_N

HIF WR_N

HIF_WAIT

HIF_MUX

HIF16BIT

SV01091

Figure 9. 16 Bit Read Cycle Multiplexed

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HIF CS_N

HIF ALE

AD7–AD0

A7–A0

ADDR

DATA

ADDR

DATA

LATCHED

A8

HIF RD_N

HIF WR_N

HIF_WAIT

HIF_MUX

HIF16BIT

SV01772

Figure 10. 8 Bit Write Cycle Multiplexed

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HIF CS_N

HIF ALE

HIF AD7–AD0

ADDR

DA TA

ADDR

DA TA

HIF A7–A0

A8

LATCHED

HIF RD_N

HIF WR_N

HIF_WAIT

HIF_MUX

HIF16BIT

SV01773

Figure 11. 8 Bit Read Cycle Multiplexed

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HIF CS_N

HIF RD_N

HIF WR_N

HIFA7–A0

HIFAD7–AD0

A8

HIF_WAIT

HIF_MUX

HIF16BIT

NOTE: ALE line is held LOW.

SV01774

Figure 12. 8 Bit Write Cycle Non-multiplexed

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HIF CS_N

HIF RD_N

HIF WR_N

HIF A8

HIFA7–A0

HIFAD7–AD0

HIF_WAIT

HIF_MUX

HIF16BIT

NOTE: ALE line is held LOW.

SV01775

Figure 13. 8 Bit Read Cycle Non-multiplexed

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12.6 The Asynchronous Packet Interface

The PDI1394L41 provides an interface to asynchronous data packets through the registers in the host interface. The format of the

asynchronous packets is specified in the following sections.

12.6.1 Reading an Asynchronous Packet

Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the

packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK)

register. The packet is transferred out of the FIFO by successive reads of the Asynchronous Receive Request (RREQ) or Asynchronous

Receive Response (RRSP) register. The end of the packet (the last quadlet) is indicated by either the RREQQLASTQ or RRSPQLASTQ bit set

in ASYINTACK. Attempting to read the FIFO when either RREQQQAV bit or RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt

acknowledge, ASYINTACK, register) will result in a queue read error.

12.6.2 Link Packet Data Formats

The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data

presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces.

12.6.2.1 Asynchronous Transmit Packet Formats

These sections describe the formats in which packets need to be delivered to the queues (FIFOs) for transmission. There are four basic formats

as follows:

TRANSACTION CODE

ITEM

FORMAT

No-packet data

USAGE

Quadlet read requests

(tCode)

4

2

0

6

5

1

7

9

1

Quadlet/block write responses

Quadlet write requests

Quadlet read responses

Block read requests

2

Quadlet packet

Block write requests

Block read responses

Lock requests

3

4

Block Packet

Lock responses

B

hex

A

hex

E

hex

Asynchronous streams

Concatenated self-ID / PHY packets

Unformatted transmit

Each packet format uses several fields (see names and descriptions below). More information about these fields (not the format) can be found

in the 1394 specification. Grey fields are reserved and should be set to zero values.

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Table 1. Asynchronous Transmit Fields

Field Name

Description

spd

This field indicates the speed at which this packet is to be sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs.

11 = undefined

tLabel

This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.

tLabels are also used as identifiers to associate a Link data confirmation (see 12.6.2.13) with the corresponding

request, response, or asynchronous stream packet.

rt

Only value 01 = retryX is supported.

The transaction code for this packet.

Contains a node ID value.

tCode

DestinationID

DestinationOffsetHigh

DestinationOffsetLow

The concatenation of these two field addresses a quadlet in the destination node’s address space.

Response code for write response packet.

rCode

Meaning

0

1–3

4

Node successfully completed requested operation.

Reserved

Resource conflict detected by responding agent. Request may be retried.

5

6

7

Hardware error. Data not available.

Field within request packet header contains unsupported or invalid value.

Address location within specified node not accessible.

Reserved

8–Fh

channel

tag

A channel allocated from the isochronous manager register CHANNELS_AVAILABLE.

Used only for Asynchronous stream transmit fields. Values supplied, as appropriate, by the user.

sy

priority

For responses, priority is set to 0000 if fair arbitration is to be used and to 0001 if priority arbitration is to be used, as

allowed by the 1394a supplement to Std IEEE 1394–1995.

Quadlet data

Data length

For quadlet write requests and quadlet read responses, this field holds the data to be transferred.

The number of bytes requested in a block read request.

dataLength

The number of bytes of data to be transmitted in this packet

extendedTcode

The tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this

packet.

block data

padding

The data to be sent. If dataLength=0, no data should be written into the FIFO for this field. Regardless of the

destination or source alignment of the data, the first byte of the block must appear in the high order byte of the first

quadlet.

If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a

whole number of quadlets is sent.

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12.6.2.2 No-data Transmit

The no-data transmit formats are shown in Figures 14 and 15. The first quadlet contains packet control information. The second and third

quadlets contain 16-bit destination ID and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for

responses).

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

destinationOffsetHigh

destinationOffsetLow

SV01080

Figure 14. Quadlet Read Request Transmit Format

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

rCode

SV01081

Figure 15. Quadlet/Block Write Response Packet Transmit Format

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12.6.2.3 Quadlet Transmit

Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third

quadlets contain 16-bit destination ID and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses).

The fourth quadlet contains the quadlet data for read response and write quadlet request formats, or the upper 16 bits contain the data length

for the block read request format.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

destinationOffsetHigh

destinationOffsetLow

quadlet data

SV01082

Figure 16. Quadlet Write Request Transmit Format

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

rCode

quadlet data

SV01083

Figure 17. Quadlet Read Response Transmit Format

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31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

destinationOffsetHigh

destinationOffsetLow

data length

SV01084

Figure 18. Block Read Request Transmit Format

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12.6.2.4 Block Transmit

The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information.

The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code

and reserved data (for responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except

for lock transaction). The block data, if any, follows the extended transaction code.

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

dataLength

destinationOffsetHigh

extendedTcode

destinationOffsetLow

Block data

padding (if needed)

SV01085

Figure 19. Block Packet Transmit Format

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

priority

destinationID

rCode

dataLength

extendedTcode

Block data

padding (if needed)

SV01086

Figure 20. Block Read or Lock Response Transmit Format

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12.6.2.5 Unformatted Transmit

The unformatted transmit format is shown in Figure 21. The first quadlet contains packet control information. The remaining quadlets contain

data that is transmitted without any formatting on the bus. No CRC is appended on the packet, nor is any data in the first quadlet sent. This is

used to send PHY configuration and Link-on packets. Note that the bit-inverted check quadlet must be included in the FIFO since the AV Link

core will not generate it.

31 3029 28 27 2625 24 23 22 212019 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

spd

tLabel

00

1110

priority

unformatted packet data

SV01087

Figure 21. Unformatted Transmit Format

12.6.2.6 Asynchronous Stream Transmit

The PDI1394L41 supports asynchronous stream as specified in IEEE1394.a. The asynchronous stream packet format is shown below. The first

quadlet contains packet control information. The second quadlet contains datalength, tag, channel number, and synchronization code. The third

quadlet contains the datalength in quadlets. The datalength can be zero for empty asynchronous stream packets.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

spd tLabel

channel

8 7 6 5 4 3 2 1 0

1

1110

1010

priority

sy

dataLength

tag

Block data

padding (if needed)

SV01050

Figure 22. Asynchronous Stream Packet Transmit Format

When a packet conforming to this format is written to either asynchronous transmit FIFO, an asynchronous stream packet (identical on the

cable to an isochronous packet) will be transmitted during the asynchronous phase of a bus cycle.

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12.6.2.7 Asynchronous Receive Packet Formats

This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist:

Table 2. Asynchronous Data Packet Formats

ITEM

FORMAT

USAGE

Quadlet read requests

TRANSACTION CODE

4

2

0

6

5

1

7

9

1

No-packet data

Quadlet/block write responses

Quadlet write requests

Quadlet read responses

Block read requests

2

Quadlet packet

Block Packet

Block write requests

3

Block read responses

Lock requests

Lock responses

B

E

hex

4

5

Self-ID / PHY packet

Confirmation packet

Concatenated self-ID / PHY packets

Confirmation of packet transmission

hex

8

Each packet format uses several fields. More information about most of these fields can be found in the 1394 specification.

Table 3. Asynchronous Receive Fields

Field Name

destinationID

Description

This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for

broadcast) for this node.

tLabel

This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.

tLables are also used as identifiers to associate a Link data confirmation (see 12.6.2.13) with the corresponding

request, response, or asynchronous stream packet.

rt

The retry code of the received packet; see the 1394 specification.

The transaction code for this packet.

tCode

priority

sourceID

The priority level for this packet (0000 for cable environment).

This is the node ID of the sender of this packet.

destinationOffsetHigh, The concatenation of these two field addresses a quadlet in this node’s address space.

destinationOffsetLow

rCode

Response code for the received packet; see the 1394 specification.

For quadlet write requests and quadlet read responses, this field holds the data received.

The number of bytes of data to be received in a block packet.

quadlet data

dataLength

extendedTcode

If the tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this

packet.

block data

padding

The data received. If dataLength=0, no data will be written into the FIFO for this field. Regardless of the destination

or source alignment of the data, the first byte of the block will appear in the high order byte of the first quadlet.

If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a

whole number of quadlets is sent.

u

Unsolicited response tag bit. This bit is set to one (1) if the received response was unsolicited.

ackSent

This field contains the acknowledge code that the link layer returned to the sender of the received packet. For

packets that do not need to be acknowledged (such as broadcasts) the field contains the acknowledge value that

would have been sent if an acknowledge had been required. The values for this field are listed in Table 4 (they also

can be found in the IEEE 1394 standard).

status

This field is used for asynchronous streams.

0000

0001

Reserved.

packet OK.

0010–1100

1101

1110–1111

Reserved.

Data CRC error and/or block size mismatch have been detected.

Reserved.

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Table 4. Acknowledge codes

Code

Name

Description

0001

ack_complete

The node has successfully accepted the packet. If the packet was a request subaction, the

destination node has successfully completed the transaction and no response subaction shall follow.

0010

0100

0101

0110

1101

ack_pending

ack_busy_X

ack_busy_A

ack_busy_B

ack_data_error

The node has successfully accepted the packet. If the packet was a request subaction, a response

subaction will follow at a later time. This code shall not be returned for a response subaction.

The packet could not be accepted. The destination transaction layer may accept the packet on a

retry of the subaction.

The packet could not be accepted. The destination transaction layer will accept the packet when the

node is not busy during the next occurrence of retry phase A.

The packet could not be accepted. The destination transaction layer will accept the packet when the

node is not busy during the next occurrence of retry phase B.

The node could not accept the block packet because the data field failed the CRC check, or because

the length of the data block payload did not match the length contained in the dataLength field. This

code shall not be returned for any packet that does not have a data block payload.

1110

ack_type_error

reserved

A field in the request packet header was set to an unsupported or incorrect value, or an invalid

transaction was attempted (e.g., a write to a read-only address).

0000, 0011,

0111 – 1100,

and 1111

This revision of the AV Link will not generate other acknowledge codes, but may receive them from

newer (1394 A) links. In that case, these new values will show up here.

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12.6.2.8 No-data Receive

The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second

and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for

responses). The last quadlet contains packet reception status.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

spd

ackSent

SV00257

Figure 23. Quadlet Read Request Receive Format

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

spd

u

ackSent

SV00258

Figure 24. Write Response Receive Format

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12.6.2.9 Quadlet Receive

The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second

and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for

responses). The fourth quadlet is the quadlet data for read responses and write quadlet requests, and is the data length and reserved for block

read requests. The last quadlet contains packet reception status.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

quadlet data

spd

ackSent

SV00259

Figure 25. Quadlet Write Request Receive Format

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

quadlet data

spd

u

ackSent

SV00260

Figure 26. Quadlet Read Response Receive Format

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313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

data length

spd

ackSent

SV00261

Figure 27. Block Read Request Receive Format

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12.6.2.10 Block receive

The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and

third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for

responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lock transactions).

The block data, if any, follows the extended code. The last quadlet contains packet reception status.

31 30 29 28 2726 25 24 23 22 21 2019 18 17 16 15 1413 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

dataLength

extendedTcode

Block data

padding (if needed)

spd

ackSent

SV00262

Figure 28. Block Write or Lock Request Receive Format

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

dataLength

extendedTcode

Block data

padding (if needed)

spd

u

ackSent

SV00263

Figure 29. Block Read or Lock Response Receive Format

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12.6.2.11 Asynchronous Stream Receive

The Asynchronous streaming receive packet format is shown below. The first quadlet contains dataLength, tag, and Channel number for source

identification, and synchronization information. The following quadlets contain (possibly zero) quadlets of block information. The last quadlet

contains transmission speed and status information. Asynchronous stream packets are placed in the Receive Response FIFO.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1 0

dataLength

tag

chanNum

1010

sy

2

Block data (possibly zero)

spd

status

SV01052

12.6.2.12 Self-ID and PHY packets receive

The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE

(hex). For self-ID information, the remaining quadlets contain data that is received from the time a bus reset ends to the first subaction gap. This

is the concatenation of all the self-ID packets received. Note that the bit-inverted check quadlet is included in the Read Request FIFO and the

application must check it.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

1110

0000

2

self ID packet data

00

ackSent

SV00264

Figure 30. Self-ID Receive Format

The “ackSent” field will either be “ACK_DATA_ERROR” if a non-quadlet-aligned packet is received or there was a data overrun, or

“ACK_COMPLETE” if the entire string of self-ID packets was received.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

1110

0000

2

PHY packet first quadlet

SV00265

Figure 31. PHY Packet Receive Format

For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified

and is not included.

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12.6.2.13 Link data confirmation formats

After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see

Figure 32) which is used to confirm the transmission to the higher layers. Packets transmitted from the Transmit Request FIFO are confirmed by

a confirmation written into the Receive Request FIFO and packets transmitted from the Transmit Response FIFO are confirmed by a

confirmation written into the Receive Response FIFO.

Outgoing packets and their confirmations are associated by their tLabels. It is the user’s responsibility to assure the uniqueness of active

tLabels.

313029 28 27 2625 24 23 22 21 2019 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

tLabel

01

1000

conf

SV01051

Figure 32. Request and response confirmation format

Table 5. Confirmation codes

1

CODE

DESCRIPTION

0

1

Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).

Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete

(transaction complete).

2

4

Non-broadcast packet transmitted; addressed node returned an acknowledge pending.

Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries

(transaction complete).

D

E

Acknowledge data error received (transaction complete).

Acknowledge type error received (transaction complete).

16

NOTE:

1. All other codes are reserved.

12.7 Interrupts

The PDI1394L41 provides a single interrupt line (HIF INTN) for connection to a host controller. Status indications from four major areas of the

device are collected and ORed together to activate HIF INTN. Status from four major areas of the device are collected in four status registers;

LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level

interrupt by activating HIF INTN. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt is

indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be acknowledged.

To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing the interrupt

status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.

12.7.1 Determining and Clearing Interrupts

When responding to an interrupt event generated by the PDI1394L41, or operating in polled mode, the first register examined is the GLOBCSR

register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,

the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all

the enabled interrupt status bits in their section of the AV Link Layer Controller.

Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy

diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication

will automatically clear in the GLOBCSR.

All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.

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12.7.1.1 Interrupt Hierarchy

HIF INT_N

3

2

1

0

GLOBCSR (0x018)

21 20 18 17 16 15 14 13 10 9

8 7 6 5 4 3 2 1 0

LNKPHYINTACK (0x008)

13 12 10 9

8

7

6

5

4

3

2 1 0

IRXINTACK (0x04C)

ITXINTACK (0x02C)

14 13 12

5

9

4 3 2 1 0

9

8 7

16 15 14 13 12 11 10

8 7 6 5 4 3 2 1 0

ASYINTACK (0x0A0)

SV00913

Figure 33. Interrupt Hierarchy

13.0 REGISTER MAP

Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the

lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored

and thus DON’T CARE.

A full bitmap of all registers is listed in Table 6. The meaning of shading and bit cell values is as follows:

A bit/field with no name written in it and dark shading is reserved and not used.

A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.

A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset.

Table 6. Full Bitmap of all Registers (consists of four tables shown on the following pages)

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1394 content protection AV link layer controller

PDI1394L41

REGISTER

ADDRESS

31

24 23

16 15

8

7

0

IDREG

PART CODE

VERSION CODE

BUS ID

NODE ID

0x000

1

0

1

LNKCTL

0x004

BSYCTRL

ATACK

0

1

0

1

P

0

LNKPHYINTACK

0x008

0

LNKPHYINTE

0x00C

0

CYCTM

0x010

CYCLE_SECONDS

CYCLE_NUMBER

CYCLE_OFFSET

0

PHYACS

0x014

PHYRGAD

PHYRGDATA

PHYRXAD

PHYRXDATA

0

GLOBCSR

0x018

0

1

0

PRELOAD

TIMER

0x01C

0

ITXPKCTL

0x020

TRDEL

MAXBL

PM

0

1

0

ITXHQ1

0x024

DBS

FN

QPC

0

ITXHQ2

0x028

FMT

FDF

SYT

0

ITXINTACK

0x02C

0

ITXINTE

0x030

0

SV01030

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Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

31

24 23

16 15

8

7

0

REGISTER

ADDRESS

ITXCTL

0x034

SPD

EMI

TAG

CHANNEL

0

ITXMEM

0x038

0x03C

IRXPKCTL

0x040

BPAD

0

1

0

1

0

IRXHQ1

0x044

SID

DBS

FDF

FN

QPC

IRXHQ2

0x048

FMT

SYT

IRXINTACK

0x04C

0

IRXINTE

0x050

0

IRXCTL

0x054

SPD TAG

CHANNEL

ERR

0

IRXMEM

0x058

0x05C

.

0x07C

SV01031

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Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

31

24 23

16 15

8

7

0

REGISTER

ADDRESS

ASYCTL

MAXRC

TOS

0

TOF

0

0x080

0

1

0

1

0

1

0

ASYMEM

0x084

FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE

(WRITE ONLY)

TX_RQ_NEXT

0x088

LAST QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE

(WRITE ONLY)

TX_RQ_LAST

0x08C

FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE

(WRITE ONLY)

TX_RP_NEXT

0x090

LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE

(WRITE ONLY)

TX_RP_LAST

0x094

RREQ

0x098

QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER)

RRSP

0x09C

QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER)

ASYINTACK

0x0A0

0

ASYINTE

0x0A4

0

0x0A8

0x0AC

RDI

0x0B0

0

SV01032

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Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

REGISTER

ADDRESS

31

24 23

16 15

8

7

0

0x0B4

.

0x0F0

SHADOW_REG

0x0F4

byte 0

byte 1

byte 2

byte 3

0

1

0

1

0

1

0

1

0

1

0

INDADDR

0x0F8

RESERVED

INDADDR

INDDATA

0x0FC

WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR

SV01033

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Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

13.1 Link Control Registers

13.1.1 ID Register (IDREG) – Base Address: 0x000

The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BUS ID

NODE ID

PART CODE

VERSION CODE

SV00915

Reset Value 0xFFFF1001

Bit 31..22:

R/W

BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to

accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.

Bit 21..16:

R/W

NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject

incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.

Bit 15..8:

Bit 7..0:

R

PART CODE: “02” designates PDI1394L41.

VERSION CODE: “01” shows this is revision level 1 of this part.

13.1.2 General Link Control (LNKCTL) – Base Address: 0x004

The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also

provides general link status.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BSYCTRL

ATACK

SV00892

Reset Value 0x46000002

Bit 31:

R/W

IDValid (IDVALID): When equal to one, the PDI1394L41 accepts the packets addressed to this node. This bit is

automatically set after selfID complete and node ID is updated.

Bit 30:

R/W

Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the

bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30

also enables the reception of PHY configuration packets in the asynchronous request queue.

Bit 29..27:

R/W

Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is

defined below:

000 = use protocol requested by received packet (either dual phase or single phase)

001 = RESERVED

010 = RESERVED

011 = use single phase retry protocol

100 = use protocol requested in packet, always send a busy ack (for all packets)

101 = RESERVED

110 = RESERVED

111 = use single phase retry protocol, always send a busy ack

Bit 26:

Bit 25:

Bit 23:

R/W

R

Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.

Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.

Data Invariant (DATAINV) refers to the byte ordering of data being presented to the Link through the host interface

(HIF) port and the handling of the address and data lines by the link chip. When DATAINV = 0, the Link is in address

invariant mode. When DATAINV = 1, the Link is in data invariant mode. This bit is only important if the LTLEND

(Little Endian) bit is set (1), otherwise it is ignored. Interpretation of address and data information varies with the

settings of these bits and with the data format being presented. See the section on Big and Little Endian Modes for

more information (Section 12.5.3).

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1394 content protection AV link layer controller

PDI1394L41

Bit 22:

R

Little Endian (LTLEND): Refers to the state of the endianess of the data and address lines connected to the ’L41.

This bit reflects the state of the AV2ERR0/LTLEND pin during power reset. The state of this pin is read during reset

and that state is latched into this bit position. When LTLEND = 0, the chip is set to receive BIG ENDIAN address and

data on its host interface (HIF). When LTLEND = 1, the Link chip will receive LITTLE ENDIAN oriented data

and address information. If this bit is set (1), the state of the DATAINV pin will also become important for

determination of data positions in the internal link registers. See the section on Big and Little Endian Modes for more

information (Section 12.5.3).

Bit 21:

Bit 20:

Bit 18:

R/W

Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.

Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.

Reset PHY-Link interface (RPL): Resets the PHY–Link interface in accordance with 1394a requirements.

Note: This bit automatically resets to “0” when the interface reset operation has been completed. The PHY–Link

reset operation occurs very quickly, reading this bit accurately is not usually possible.

Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the

following state of operation:

1) The isochronous transmit FIFO is not receiving data for transmission

2) The isochronous transmitter is disabled

3) No asynchronous packets are being generated for transmission

4) Both the ASYNC request and response queues are empty

Bit 12:

Bit 11:

R/W

Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified

isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified

cycles, a “0” accepts isochronous packets sent outside the specified cycle.

Cycle Master (CYMASTER): When asserted and the PDI1394L41 is attached to the root PHY (ROOT bit = 1), and

the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master

function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle

Master function in such a case, first reset CYMASTER, then set it again.

Bit 10:

Bit 9:

R/W

Cycle Source (CYSOURCE): When asserted, the cycle_count field increments and the cycle_offset field resets for each

positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over.

Cycle Timer Enable (CYTIMREN): When asserted, the cycle offset field increments. When deasserted, the Cycle

Timer Register (0x010, CYCTM) can be used as a general read write register for Host Interface Firmware testing.

Bit 6:

Bit 5:

Bit 4:

R

Transmitter Ready (TxRDY): The transmitter is idle and ready.

Root (ROOT): Indicates this device is the root on the bus. This automatically updates after the self_ID phase.

Busy Flag (BUSYFLAG): The type of busy acknowledge which will be sent next time an acknowledge is required.

0 = Busy A, 1 = Busy B (only meaningful during a dual-phase busy/retry operation).

Bit 3..0:

R

AT acknowledge received (ATACK): The last acknowledge received by the transmitter in response to a packet sent

from the transmit-FIFO interface while the ATF is selected (diagnostic purposes).

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Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008

The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to

generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished

by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no

effect on the register.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV01040

Reset Value 0x00000000

Bit 21:

R/W

Authentication Acceleration Done (AUTH DN). The authentication accelerator has finished an operation. Check the

status of ‘Valid’ in the Authentication Accelerator indirect register.

Bit 20:

R/W

Timer (TIMER): When TIMER = 1, this bit indicates that the timer has counted down to zero. This interrupt may occur

only once or may occur repeatedly, according to the setting of the TMCONT bit in the TIMER register. Acknowledge

this interrupt by writing a “1” back into this bit position.

Bit 18:

Bit 17:

R/W

Command Reset Received (CMDRST): A write request to RESET-START has been received.

Fair Gap (FAIRGAP): The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394

specification).

Bit 16:

Bit 15:

R/W

Arbitration Reset Gap (ARBGAP): The serial bus has been idle for an arbitration reset gap.

Phy Chip Int (PHYINT): The Phy chip has signaled an interrupt through the Phy interface after a bus reset or PHY

reset. This bit becomes active for any of the following reasons (1) PHY has detected a loop on the bus, (2) cable

power has fallen below the minimum voltage, (3) the PHY arbitration state machine has timed-out usually indicative

of a bus loop, (4) a bus cable has been disconnected. Typically, recognition and notification of any of the above

events by the PHY requires between 166 and 500 microseconds; therefore, this bit is not instantaneously set.

Bit 14:

Bit 13:

Bit 10:

Bit 9:

Bit 8:

Bit 7:

Bit 6:

Bit 5:

Bit 4:

R/W

Phy Register Information Received (PHYRRX): A register has been transferred by the Physical Layer device into the

Link.

Phy Reset Started (PHYRST): A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called

Bus Reset in the IEEE 1394 specification). The Async queues will be flushed during a bus reset.

Isochronous Transmitter is Stuck (ITBADFMT): The transmitter has detected invalid data at the transmit-FIFO

interface when the ITF is selected. Reset the isochronous transmitter to clear.

Asynchronous Transmitter is Stuck (ATBADFMT): The transmitter expected start of new async packet in queue, but

found other data (out of sync with user). Reset the asynchronous transmitter to clear.

Busy Acknowledge Sent by Receiver (SNT_REJ): The receiver was forced to send a busy acknowledge to a packet

addressed to this node because the receiver response/request FIFO overflowed.

Header Error (HDRERR): The receiver detected a header CRC error on an incoming packet that may have been

addressed to this node.

Transaction Code Error (TCERR): The transmitter detected an invalid transaction code in the data at the transmit

FIFO interface.

Cycle Timed Out (CYTMOUT): ISOCH cycle lasted more than 125µs from Cycle-Start to Fair Gap: Disables cycle

master function

Cycle Second incremented (CYSEC): The cycle second field in the cycle-timer register incremented. This occurs

approximately every second when the cycle timer is enabled.

Bit 3:

Bit 2:

R/W

Cycle Started (CYSTART): The transmitter has sent or the receiver has received a cycle start packet.

Cycle Done (CYDONE): A fair gap has been detected on the bus after the transmission or reception of a cycle start

packet. This indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.

Bit 1:

Bit 0:

R/W

Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and

stays asserted until the isochronous cycle has ended.

Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only

occurs when cycle master is not asserted.

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1394 content protection AV link layer controller

PDI1394L41

13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C

This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’

to the bit corresponding to the interrupt desired.

This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the

bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt

Acknowledge register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV00894

Reset Value 0x00000000

Bits 21..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).

13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010

Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the Link Control Register (LNKCTL, 0x004). If the

Cycle Timer Register is disabled, it can be used as a general read write register for Host Interface Firmware testing.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

CYCLE_SECONDS

CYCLE_NUMBER

CYCLE_OFFSET

SV00276

Reset Value 0x00000000

Bit 31..25:

Bit 24..12:

Bit 11..0:

R/W

Seconds count: 1-Hz cycle timer counter.

Cycle Number: 8kHz cycle timer counter.

Cycle Offset: 24.576MHz cycle timer counter.

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1394 content protection AV link layer controller

PDI1394L41

13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014

This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When

reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the

PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the address of the

register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is set in the

PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write is

complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the Self-ID

phase, PHY register 0 will be read automatically.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

PHYRGAD

PHYRGDATA

PHYRXAD

PHYRXDATA

SV00277

Reset Value 0x00000000

Bit 31:

R/W

Read Phy Chip Register (RDPHY): When asserted, the PDI1394L41 sends a read register request with address

equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.

Bit 30:

R/W

Write Phy Chip Register (WRPHY): When asserted, the PDI1394L41 sends a write register request with address

equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.

Bit 27..24:

Bit 23..16:

Bit 11..8:

Bit 7..0:

R/W

R

Phy Chip Register Address (PHYRGAD): This is the address of the Phy-chip register that is to be accessed.

Phy Chip Register Data (PHYRGDATA): This is the data to be written to the Phy-chip register indicated in Phy Rg Ad.

Phy Chip Register Received Address (PHYRXAD): Address of register from which Phy Rx Data came.

Phy Chip Register Received Data (PHYRXDATA): Data from register addressed by Phy Rx Ad.

R

13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018

This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV

Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the

appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.

Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register

in that module must be read to determine the exact cause of the interrupt.

A timer is available to aid the implementation of higher level protocols such as AV/C and HAVi. The timer can be started and stopped, and

automatically reloads with 1s (TIMLOAD = 1) or 100ms (TIMLOAD = 0). When the set time has expired, an interrupt will be generated through

TIMER (Bit 20, LNKPHYINTACK 0x008). In normal timer mode (TIMMODE = 0), the timer will generate an interrupt, reload and restart every

time it expires, until TIMRNSTP is cleared. In bus reset timer mode (TIMMODE = 1), even when already running the timer will reload with 1s

and restart automatically after a bus reset. If another bus reset occurs before the timer expires, the timer will again reload and restart. No

interrupt will be generated until the timer expires.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SV01024

NOTES

1. There can be more than one interrupt source active at the same time.

2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.

Reset Value 0x00010000

Bit 18:

Bit 17:

R/W

Enable output AVPORT2: A ‘1’ enables AVPORT2 as an output. A ‘0’ sets the 3-State condition on the port. In

3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).

Enable output AVPORT1: A ‘1’ enables AVPORT1 as an output. A ‘0’ sets the 3-State condition on the port. In

3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).

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1394 content protection AV link layer controller

PDI1394L41

Bit 16:

R/W

Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’

configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2

pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa.

Bit 11:

Bit 10:

Bit 9:

Bit 8:

Bit 3:

R/W

R

Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when

set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).

Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).

Disables such interrupts when clear (0) (regardless of ITXINTE contents).

Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1).

Disables such interrupts when clear (0) (regardless of IRXINTE contents).

Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such

interrupts when clear (0) (regardless of LNKPHYINTE contents).

Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source is in the Asynchronous Transmitter/

Receiver Interrupt Acknowledge/Source register.

Bit 2:

Bit 1:

Bit 0:

R

AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.

AV Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.

Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register.

13.1.8 Timer (TIMER) – Base Address: 0x01C

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

PRELOAD

SV01096

Reset Value

Bit 31:

R/W

TMGOSTOP: Timer Go/Stop, when = 1 start timer; when = 0 stop timer.

Bit 30:

TMCONT: Timer Continuous, when = 1 continuously operate timer; when = 0 operate timer for one timing cycle,

then stop.

Bit 29:

R/W

TMBRE: Timer Bus Reset Enable, when = 1, start the timer at the beginning of a bus reset; when = 0 start the timer

from the TMGOSTOP bit setting.

Bit 23..0:

Timer preload bits. Load a number into the timer preload bits with the most significant bit in the higher numbered bit

position; the least significant bit in the timer preload register is bit 0. The basic timing unit is 1/(2*CLK25) or 80.14

nanoseconds. The maximum timer time-out is about 1.34 seconds ((2^24)–1 units). The timer uses the preload

value inputted by the host into bits 0 through 23 of this register. The preload value is placed in the actual

timer/counter (invisible to outside world) and this value is decremented by 1 for each unit of time. The timer

eventually counts down to zero and then it sets the TIMER interrupt flag bit in register 0x008, LINKPHYINTACK

(assuming the interrupt was enabled by the ETIMER bit). Depending on the setting of the TMCONT bit in this

register, the timer preload value may be automatically reloaded into the timer/counter (when TMCONT = 1) with the

timing cycle automatically re-starting, or the timer will simply interrupt and stop (when TMCONT bit = 0). TMBRE

adds a mode to the timer operation which starts the timing automatically at the start of a 1394 bus reset. When

TMBRE is set (1), the TMGOSTOP bit function is disabled; the TMCONT bit function is still available.

NOTE: When TMCONT = 1, failing to acknowledge a TIMER interrupt has no effect on the starting/restarting of the

timer; if an interrupt is not acknowledged (bit reset), the timer will continue to time out and restart.

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1394 content protection AV link layer controller

PDI1394L41

13.2 AV (Isochronous) Transmitter and Receiver Registers

13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020

This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters

(TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the

MAXBL parameter when in MPEG-2 packing mode.

NOTE: When reset of isochronous transmitter is necessary, first disable the transmitter (place bit 4, EN_ITX, LOW), wait for FIFO to empty, then

reset the transmitter (place RST_ITX, bit 0, HIGH). This procedure will ensure that data in the FIFO is transmitted before reset.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

TRDEL

MAXBL

PM

SV00886

Reset Value 0x00000001

Bit 30:

R/W

mLAN mode bit: When = 1, SYT system is in mLAN mode. When mLAN = 0 normal SYT time stamping operation is

assumed. With mLAN = 1, the SYT time stamp for an FSYNC pulse will NOT be appended to an empty bus packet.

Any pending SYT stamp will be held until the next non-empty bus packet is sent. As an FSYNC pulse is input to the

transmitting node’s link chip, an SYT stamp will be made. This SYT stamp will point to a time in the future dictated by

the SYT DELAY value (in register 0x020) added to the current least significant nibble (lsn) of the cycle number, plus

the current cycle offset value. This mode automatically increases SYT_DELAY value by two additional cycles beyond

the value programmed in the SYT_DELAY bits.

Bit 29..28:

R/W

TXAP_CLK: Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an application

clock for the isochronous Transmitter (and output) by programming it to ‘01’, ‘10’, or ‘11’.

The programming values are:

00

01

10

11

Input

24.576MHz

12.288MHz

6.144MHz

Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as transmitter and enabled will output this

clock signal on its AVxCLK pin.

Bit 27..16:

R/W

TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper 4 bits of

cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field.

MAXBL: The (maximum) number of data blocks to be put in a payload.

Bit 15..8:

Bit 7:

R/W

ENXTMSTP: Enable External time stamp control. Allows an external time stamp (generated by the application) to be

inserted in place of the link-generated time stamp. Defaults to link generated time stamp. The application must present

the first byte of a quadlet-wide time stamp accompanied by the AVSYNC pulse (and AVVALID) to the AVPORT. The

external time stamp quadlet is inputted first, followed by the application data packet. The transmitted packet size is

now one quadlet larger than the original isochronous data packet—Set up the isochronous transmitter accordingly with

SPH = 1. CAUTION: Unless valid IEC 61883 time stamp format (based on the link cycle timer) is used, the receiving

node link chip must be equipped with a time stamp check disabling function similar to the DIS_TSC bit (register

0X040, Bit 7). Please see section 13.2.8 for details.

Bit 6..5:

R/W

SYT_DELAY: Programmable delay of AV1FSYNC and AV2FSYNC. Each cycle is 1 bus cycle, 125 ms.

Reset value is “00”, a 3 cycle delay.

01 = 2 cycles

00 = 3 cycles

10 = 4 cycles

11 = Reserved

Bit 4:

R/W

EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This bit

also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled (0),

the current packet will be transmitted and then the transmitter will shut down.

PM: packing mode:

Bit 3..2:

00 = variable sized bus packets, most generic mode.

01 = fixed size bus packets.

10 = MPEG–2 packing mode.

11 = No data, just CIP headers are transmitted.

Bit 1:

Bit 0:

R/W

EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.

Reset Isochronous Transmitter (RST_ITX): causes transmitter to be reset when ‘1’. In order for synchronous reset of

ITX to work properly, an AVxCLK (from either the internal or external source) must be present and ensure that the

reset bit is kept (programmed) HIGH for at least the duration of one AVxCLK period. Failure to do so may cause the

application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes will

be flushed from the FIFO and transmission will cease immediately.

52

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024

The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is

included in Common Isochronous Packet (CIP) header quadlet 1.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

DBS

FN

QPC

SV01747

Reset Value 0x00000000

Bit 16..23:

Bit 14..15:

R/W

DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.

FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided

(00 = 1, 01 = 2, 10 = 4, 11 = 8).

Bit 11..13:

Bit 10:

R/W

QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the

FN

specified size. The value QPC must be less than DBS and less than 2

.

SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.

13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028

The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

FMT

FDF

SYT

SV00281

Reset Value 0x00000000

Bit 29..24:

Bit 23..0:

R/W

FMT: Value to be inserted in the FMT field in the AV header.

FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register

(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on

AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits

of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status

Register is unset (=0), the full 24 bits can be set to any application specified value.

53

2000 Apr 15

Philips Semiconductors

Preliminary specification

1394 content protection AV link layer controller

PDI1394L41

13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C

The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter.

Bits 2, 3, and 4 “auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to

clear these interrupts to be alerted the next time.

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV01054

Reset Value 0x00000000

Bit 14:

R/W

M6 ERROR: Either the M6 cipher block has encountered an unrecoverable error. Proper operation will be resumed

by disabling and resetting the ITX.

Bit 13:

Bit 12:

R/W

ITO/E: An odd/even key change has occurred in the cipher, it is now OK to write in the new key set.

ITEMI: This bit indicates that the EMI bit value used to cipher outgoing transmission has changed.

Bits 9 .. 0 are interrupt acknowledge bits; and are defined as:

Bit 9:

Bit 8:

Bit 7:

R/W

IT100LFT: Interrupt when transmitter queue reaches 100 quadlets from full.

IT256LFT: Interrupt when transmitter queue reaches 256 quadlets from full.

IT512LFT: Interrupt when transmitter queue reaches 512 quadlets from full. This bit is disabled if 0.5K Byte buffer

size is set.

Bit 6:

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

R/W

TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2

TRMBP: Interrupt on payload transmission/discard complete.

DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss.

INPERR: Acknowledge interrupt on input error (input data discarded).

DISCARD: Interrupt on lost cycle (payload discarded).

ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error. The ITX transmitter will reset itself

automatically when this occurs.

Bit 0:

R/W

ITXEMPTY: Interrupt on isochronous memory bank empty.


型号：	PDI1394L41
厂家：	NXP
描述：	1394 content protection AV link layer controller 1394内容保护的AV链路层控制器控制器
文件：	总81页 (文件大小：305K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDI1394L41 [NXP]

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