PH1955L [NXP]
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.; 逻辑电平N沟道增强型场效应晶体管（ FET）使用的TrenchMOS技术的塑料包装。
| 型号： | PH1955L |
| 厂家： | 
NXP |
| 描述： | Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. |
| 文件： | 总12页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PH1955L
N-channel TrenchMOS logic level FET
Rev. 01 — 15 August 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
■ Logic level threshold
■ 175 °C rated
■ Low on-state resistance
■ Surface-mounted package
1.3 Applications
■ DC-to-DC converters
■ Motors, lamps and solenoids
■ General purpose power switching
■ 12 V and 24 V loads
1.4 Quick reference data
■ VDS ≤ 55 V
■ ID ≤ 40 A
■ RDSon ≤ 17.3 mΩ
■ QGD = 8 nC (typ)
2. Pinning information
Table 1:
Pin
Pinning
Description
source (S)
gate (G)
Simplified outline
Symbol
1, 2, 3
4
D
mb
mb
mounting base;
connected to drain (D)
G
mbb076
S
1
2 3 4
SOT669 (LFPAK)
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
plastic single-ended surface mounted package; 4 leads
Version
PH1955L
LFPAK
SOT669
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VDGR
VGS
ID
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
55
V
drain-gate voltage (DC)
gate-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
55
V
-
±15
40
V
Tmb = 25 °C; VGS = 5 V; see Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; see Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tmb = 25 °C; see Figure 1
-
A
-
28
A
IDM
Ptot
Tstg
Tj
peak drain current
-
160
75
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
+175
+175
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
40
A
A
ISM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
160
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 40 A;
tp = 0.06 ms; VDD ≤ 55 V; RGS = 50 Ω;
-
-
80
mJ
mJ
VGS = 10 V; starting at Tj = 25 °C
[1]
[2]
EDS(AL)R repetitive drain-source avalanche
energy
unclamped inductive load; ID = 4 A;
tp = 0.06 ms; VDD ≤ 55 V; RGS = 50 Ω;
0.8
VGS = 10 V
[1] Duty cycle is limited by the maximum junction temperature.
[2] Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short
bursts, not every switching cycle.
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
2 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
03aa16
03aa24
120
120
Ider
(%)
Pder
(%)
80
80
40
0
40
0
0
50
100
150
200
mb (°C)
0
50
100
150
200
Tmb ( C)
°
T
Ptot
ID
Pder
=
× 100 %
Ider
=
× 100 %
------------------------
--------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aaa642
103
ID
(A)
Limit RDSon = VDS / ID
102
tp = 10 µs
100 µs
10
1 ms
DC
10
10 ms
100 ms
1
1
1
02
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
3 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4:
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to mounting base see Figure 4
-
-
2
K/W
003aaa643
10
Zth(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
0.02
tp
P
10-1
δ =
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
1
10-6
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
4 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
55
50
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
1
1.5
2
V
V
V
Tj = 175 °C
0.5
-
-
-
-
Tj = −55 °C
2.3
IDSS
drain leakage current
gate leakage current
VDS = 55 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.02
1
µA
µA
nA
Tj = 175 °C
-
500
100
IGSS
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
2
RDSon
drain-source on-state
resistance
-
-
-
-
16.3 19
mΩ
mΩ
mΩ
Tj = 175 °C
-
-
40
21
VGS = 4.5 V; ID = 25 A; see Figure 6 and 8
VGS = 10 V; ID = 25 A; see Figure 6 and 8
14.3 17.3 mΩ
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 25 A; VDD = 44 V; VGS = 5 V; see
Figure 11
-
-
-
-
-
-
-
-
-
-
18
5
-
-
-
nC
nC
nC
8
VGS = 0 V; VDS = 25 V; f = 1 MHz; see
Figure 14
1494 1992 pF
217
86
260
pF
pF
ns
ns
ns
ns
118
VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω
18
-
-
-
-
180
44
td(off)
tf
turn-off delay time
fall time
134
Source-drain diode
VSD
trr
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 13
-
-
-
0.85 1.2
V
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V;
VR = 30 V
52
38
-
-
ns
nC
Qr
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
5 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
003aaa645
25
003aaa644
100
VGS (V) = 10
ID
RDSon
(mΩ)
5
(A)
80
60
4.5
4
20
3.8
3.6
3.4
3.2
40
20
15
10
3
2.8
0
12
4
6
8
10
2
0
1
4
2
3
VDS (V)
VGS (V)
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values
03ac63
003aaa646
3
45
VGS (V) =
RDSon
5
3.4
4.5
4
3.2
3.6 3.8
(mΩ)
38
a
2
31
24
17
10
10
1
0
180
-60
0
60
120
0
20
40
60
80
100
ID (A)
Tj (°C)
Tj = 25 °C
RDSon
a =
-----------------------------
RDSon(25
°
C)
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
6 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
03aa33
03aa36
2.5
VGS(th)
(V)
10-1
ID
(A)
2
10-2
10-3
10-4
10-5
10-6
max
1.5
typ
min
typ
max
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T ( C)
VGS (V)
°
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aaa648
003aaa649
5
60
VGS
(V)
ID
VDD = 14 V
4
(A)
VDD = 44 V
40
3
2
1
0
Tj = 175 °C
20
25 °C
0
0
5
10
15
20
0
1
2
3
4
QG (nC)
VGS (V)
ID = 25 A; VDD = 14 V and 44 V
Tj = 25 °C and 175 °C; VDS > ID × RDSon
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
7 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
003aaa647
003aaa650
100
IS
104
C
(A)
(pF)
80
60
Ciss
103
Tj = 175 °C
Coss
Crss
40
20
0
102
25 °C
10
10−1
102
0
0.4
1.2
0.8
1
10
VSD (V)
V
(V)
DS
Tj = 25 °C and 175 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
8 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-09-15
04-10-13
SOT669
MO-235
Fig 15. Package outline SOT669 (LFPAK)
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
9 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6:
Revision history
Document ID
Release date
Data sheet status
Change notice Doc. number
Supersedes
PH1955L_1
20050815
Product data sheet
-
-
-
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
10 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
9. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
PH1955L_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
11 of 12
PH1955L
Philips Semiconductors
N-channel TrenchMOS logic level FET
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information . . . . . . . . . . . . . . . . . . . . 11
3
4
5
6
7
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 15 August 2005
Document number: PH1955L_1
Published in The Netherlands
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