PH3230S_技术文档

PH3230S

N-channel TrenchMOS™ logic level FET

M3D748

Rev. 03 — 02 March 2004

Product data

1. Product proﬁle

1.1 Description

N-channel enhancement mode ﬁeld-effect power transistor in a plastic package using

TrenchMOS™ technology.

1.2 Features

■ Logic level compatible

■ High density mounting

■ Low gate charge

■ Very low on-state resistance.

1.3 Applications

■ DC-to-DC converters

■ Notebook computers

■ Switched-mode power supplies

■ Computer motherboards.

1.4 Quick reference data

■ V_DS≤ 30 V

■ I_D≤ 100 A

■ P_tot≤ 62.5 W

■ R_DSon≤ 3.2 mΩ.

2. Pinning information

Table 1:

Pinning - SOT669 (LFPAK), simpliﬁed outline and symbol

Description

source (s)

gate (g)

Simpliﬁed outline

Symbol

1,2,3

4

d

mb

drain (d)

g

s

MBB076

1

2

3

4

Top view

MBL286

SOT669 (LFPAK)

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

3. Ordering information

Table 2:

Ordering information

Type number

Package

Name

Description

Plastic single-ended surface mounted package, 4 leads

Version

PH3230S

LFPAK

SOT669

4. Limiting values

Table 3:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V_DS

V_GS

I_D

drain-source voltage (DC)

25 °C ≤ T_j≤ 150 °C

-

30

V

gate-source voltage (DC)

drain current (DC)

-

±20

100

63

V

T_mb= 25 °C; V_GS= 10 V; Figure 2 and 3

T_mb= 100 °C; V_GS= 10 V; Figure 2

T_mb= 25 °C; pulsed; t_p≤ 10 µs; Figure 3

T_mb= 25 °C; Figure 1

-

A

-

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

300

62.5

+150

A

total power dissipation

storage temperature

junction temperature

-

W

°C

−55

Source-drain diode

I_S

source (diode forward) current (DC) T_mb= 25 °C

-

52

A

I_SM

peak source (diode forward) current T_mb= 25 °C; pulsed; t_p≤ 10 µs

156

Avalanche ruggedness

E_DS(AL)Rrepetitive drain-source avalanche

energy

T_j= 25 °C; R_GS≥ 50 Ω; I_DS(AL)R= 5 A;

V_DD= 15 V; duty < 0.1%

-

2.5

mJ

E_DS(AL)Snon-repetitive drain-source

avalanche energy

unclamped inductive load; I_D= 50 A;

250

V_DD≤ 15 V; R_GS= 50 Ω; V_GS= 10 V;

starting T_j= 25 °C

9397 750 12756

Product data

Rev. 03 — 02 March 2004

2 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

03ah31

003aaa629

120

I

P

der

(%)

der

(%)

80

40

0

200

(°C)

50

100

150

0

50

100

150

200

(°C)

T

mb

V

_GS≥ 10 V

P_tot

P_der

=

× 100%

-----------------------

I_D

P

°

I_der

=

× 100%

-------------------

tot(25 C)

I

°

D(25 C)

Fig 1. Normalized total power dissipation as a

function of mounting base temperature.

Fig 2. Normalized continuous drain current as a

function of mounting base temperature.

03al32

3

10

I

D

Limit R

DSon

= V

/ I

DS D

(A)

t

p

= 10 s

µ

2

10

100 µs

1 ms

DC

10

10 ms

100 ms

1

-1

2

10

1

10

V

(V)

DS

T_mb= 25 °C; I_DMis single pulse.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 12756

Product data

Rev. 03 — 02 March 2004

3 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

5. Thermal characteristics

Table 4:

Thermal characteristics

Symbol Parameter

Conditions

Min Typ Max Unit

R_th(j-mb)thermal resistance from junction to mounting base Figure 4

-

2

K/W

5.1 Transient thermal impedance

03al31

10

Z

th(j-mb)

(K/W)

= 0.5

δ

1

0.2

0.1

0.05

-1

10

0.02

t

p

P

δ =

T

-2

10

single pulse

t

p

T

-3

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

10

1

t

p

(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

9397 750 12756

Product data

Rev. 03 — 02 March 2004

4 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

6. Characteristics

Table 5:

Characteristics

T_j= 25 °C unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min Typ Max Unit

Static characteristics

V_(BR)DSSdrain-source breakdown voltage

I_D= 10 mA; V_GS= 0 V

30

1

-

V

V_GS(th)

I_DSS

gate-source threshold voltage

drain-source leakage current

gate-source leakage current

drain-source on-state resistance

I_D= 1 mA; V_DS= V_GS; Figure 9

V_DS= 30 V; V_GS= 0 V

2

3

1

V

-

µA

I_GSS

V_GS= ±20 V; V_DS= 0 V

-

10

2.7

5.0

100 nA

R_DSon

V_GS= 10 V; I_D= 25 A; Figure 7 and 8

V_GS= 4.5 V; I_D= 25 A; Figure 8

-

3.2

6.5

mΩ

-

Dynamic characteristics

g_fs

forward transconductance

V_DS= 10 V; I_D= 25 A; Figure 11

39

-

75

42

21

13

-

S

Q_g(tot)

Q_gs

Q_gd

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

gate-source charge

gate-drain (Miller) charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

I_D= 50 A; V_DD= 10 V; V_GS= 5 V; Figure 14

nC

pF

ns

-

V_GS= 0 V; V_DS= 10 V; f = 1 MHz; Figure 12

-

4100 -

1150 -

-

750

14

-

V_DD= 10 V; I_D= 25 A; V_GS= 10 V; R_G= 4.7 Ω

-

37

t_d(off)

t_f

turn-off delay time

fall time

-

85

-

37

Source-drain (reverse) diode

V_SD

t_rr

source-drain (diode forward) voltage I_S= 25 A; V_GS= 0 V; Figure 13

-

0.8

46

1.2

-

V

reverse recovery time

I_S= 20 A; dI_S/dt = −50 A/µs; V_GS= 0 V

ns

9397 750 12756

Product data

Rev. 03 — 02 March 2004

5 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

03al33

03al36

100

80

10 V 5 V

4.5 V

V

> I x R

D DSon

DS

I

D

(A)

75

60

150

C

°

4 V

40

20

0

50

25

0

T = 25 C

°

j

V

= 3.5 V

GS

0

2

4

6

0

0.5

1

1.5

2

V

(V)

V

(V)

DS

GS

T_j= 25 °C

T_j= 25 °C and 150 °C; V_DS> I_D× R_DSon

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

03al34

03al35

10

2

4 V

4.5 V

R

a

DSon

(m )

Ω

7.5

1.5

5 V

5

2.5

0

1

0.5

0

V

= 10 V

GS

0

25

50

75

100

(A)

-60

0

60

120

180

I

D

T ( C)

°

j

T_j= 25 °C

R_DSon

a =

----------------------------

R

°

DSon(25 C)

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values.

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

9397 750 12756

Product data

Rev. 03 — 02 March 2004

6 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

03al41

03al42

-1

10

4

I

D

V

GS(th)

(V)

(A)

-2

10

3

2

1

0

max

-3

-4

-5

-6

min

typ

max

typ

min

-80

0

80

160

0

1

2

3

4

T ( C)

V

(V)

GS

°

j

I_D= 1 mA; V_DS= V_GS

T_j= 25 °C

Fig 9. Gate-source threshold voltage as a function of

junction temperature

Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

03al37

03al39

4

120

10

V

> I X R

D DSon

DS

C

g

fs

(S)

(pF)

C

iss

T = 25 C

°

j

80

150

C

°

3

10

C

oss

40

rss

2

0

10

-1

10

2

10

0

20

40

60

80

1

10

V

(V)

I

D

(A)

DS

T_j= 25 °C and 150 °C; V_DS> I_D× R_DSon

V_GS= 0 V; f = 1 MHz

Fig 11. Forward transconductance as a function of

drain current; typical values.

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values.

9397 750 12756

Product data

Rev. 03 — 02 March 2004

7 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

03al38

03al40

100

10

I

V

S

GS

(V)

(A)

8

6

4

2

0

75

150

C

°

T = 25 C

°

j

50

25

0

V

(V)

1.5

0

25

50

75

100

0.0

0.5

1.0

SD

Q

G

(nC)

T_j= 25 °C and 150 °C; V_GS= 0 V

T_j= 25 °C; I_D= 50 A; V_DD= 10 V

Fig 13. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

values.

Fig 14. Gate-source voltage as a function of gate

charge; typical values.

9397 750 12756

Product data

Rev. 03 — 02 March 2004

8 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

7. Package outline

Plastic single-ended surface mounted package (Philips version LFPAK); 4 leads

SOT669

A

2

E

A

C

c

E

b

2

1

2

L

3

1

mounting

base

b

4

D

1

D

H

L

2

1

2

3

4

X

e

w

M

c

A

b

1/2

e

A

(A )

3

C

A

1

θ

L

detail X

y

C

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

D

(1)

D

(1)

1

A

H

L

2

w

y

θ

UNIT

A

b

c

E

1

e

1

2

3

1

2

3

4

2

max

1.20 0.15 1.10

1.01 0.00 0.95

0.50 4.41 2.2 0.9 0.25 0.30 4.10

0.35 3.62 2.0 0.7 0.19 0.24 3.80

5.0 3.3

4.8 3.1

6.2 0.85 1.3 1.3

5.8 0.40 0.8 0.8

8°

0°

mm

0.25

4.20

1.27

0.25 0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-02-05

03-09-15

SOT669

MO-235

Fig 15. SOT669 (LFPAK).

9397 750 12756

Product data

Rev. 03 — 02 March 2004

9 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

8. Revision history

Table 6:

Revision history

CPCN

Rev Date

Description

03 20040302

-

Product data (9397 750 12756)

Modiﬁcations:

• I_Ddata corrected in Section 1.4 “Quick reference data”

• g_fstypical value modiﬁed Table 5 “Characteristics”

• V_SDcondition and typical values modiﬁed Table 5 “Characteristics”

• trr condition modiﬁed Table 5 “Characteristics”

• t_rand t_fdata corrected in Table 5 “Characteristics”

• I_Sdata added in Table 3 “Limiting values”

• I_SM, I_Dand I_DMdata corrected in Table 3 “Limiting values”

• Correction to Figure 2 and Figure 3

• Section 3 “Ordering information” added

Product data (9397 750 11279)

02 20030423

-

Modiﬁcations:

• Avalanche ruggedness data added in Table 3

• Correction to Figure 6

• Correction to Figure 11

• Correction to Figure 13

Preliminary data (9397 750 11078)

01 20030212

9397 750 12756

Product data

Rev. 03 — 02 March 2004

10 of 12

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

9. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

12. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

11 of 12

9397 750 12756

Product data

Rev. 03 — 02 March 2004

PH3230S

N-channel TrenchMOS™ logic level FET

Philips Semiconductors

Contents

1

Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

Transient thermal impedance . . . . . . . . . . . . . . 4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

4

5

5.1

6

7

8

9

10

11

12

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 02 March 2004

Document order number: 9397 750 12756


型号：	PH3230S
厂家：	NXP
描述：	N-channel TrenchMOS⑩ logic level FET N沟道的TrenchMOS ™逻辑电平FET
文件：	总12页 (文件大小：96K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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