PH4330L,115 [NXP]
PH4330L - N-channel TrenchMOS logic level FET SOIC 4-Pin;
| 型号： | PH4330L,115 |
| 厂家： | 
NXP |
| 描述： | PH4330L - N-channel TrenchMOS logic level FET SOIC 4-Pin 开关 脉冲 晶体管 |
| 文件： | 总12页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PH4330L
N-channel TrenchMOS logic level FET
Rev. 01 — 22 October 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features and benefits
100 % gate resistance tested
100 % ruggedness tested
Lead-free package
Optimized for use in DC-DC
converters
Very low switching and conduction
losses
Logic level threshold
1.3 Applications
DC-to-DC convertors
PC motherboards
Switched-mode power supplies
Voltage regulators
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
Min
Typ
Max Unit
VDS
ID
-
-
-
-
30
V
A
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
95.9
Dynamic characteristics
QGD gate-drain charge
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 11;
see Figure 12
-
-
5.4
3.6
-
nC
Static characteristics
RDSon
drain-source
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 9; see
Figure 10
4.3
mΩ
on-state resistance
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
1, 2, 3
4
S
G
D
source
gate
mb
D
mb
mounting base; connected to
drain
G
mbb076
S
1
2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
PH4330L
LFPAK
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
30
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 150 °C
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
V
V
V
A
VDGR
VGS
-
30
-20
-
20
ID
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure
3
95.9
V
GS = 10 V; Tmb = 100 °C; see Figure 1
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
60.1
240
62.5
150
150
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
-55
-55
junction temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
52
A
A
ISM
tp = 10 µs; pulsed; Tmb = 25 °C
208
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 49 A; Vsup ≤ 25 V;
-
121
mJ
drain-source avalanche tp = 0.12 ms; RGS = 50 Ω; unclamped inductive
energy load
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
2 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab555
003aab937
120
120
I
P
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
T (°C)
j
T
mb
(°C)
Fig 1. Normalized continuous drain current as a
function of solder point temperature
Fig 2. Normalized total power dissipation as a
function of solder point temperature
003aab773
3
10
I
Limit R
= V / I
DS
D
DSon
D
(A)
t
p
= 100 μs
2
10
100 μs
1 ms
10
10 ms
DC
100 ms
1
−1
10
10
−1
2
1
10
10
V
DS
(V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
3 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from see Figure 4
junction to mounting
base
-
-
2
K/W
003aab772
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
t
p
0.05
P
1
−1
δ =
10
10
T
0.02
single pulse
t
t
p
T
−2
10
−5
−4
−3
−2
−1
10
10
10
10
10
t
p
(s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
4 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
27
30
1.3
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; see
1.7
2.5
voltage
Figure 7; see Figure 8
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 7; see Figure 8
-
-
-
2.6
-
V
V
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 7; see Figure 8
0.8
IDSS
drain leakage current
gate leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
1
µA
µA
nA
mΩ
-
100
100
4.3
IGSS
-
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 25 °C; see
Figure 9; see Figure 10
3.6
VGS = 10 V; ID = 25 A; Tj = 150 °C; see
Figure 9; see Figure 10
-
-
-
6
6.8
7
mΩ
mΩ
Ω
VGS = 4.5 V; ID = 25 A; see Figure 9; see
5.6
0.51
Figure 10
RG
gate resistance
f = 1 MHz
-
Dynamic characteristics
QG(tot)
QGS
total gate charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see
Figure 11; see Figure 12
-
-
-
22.9
9
-
-
-
nC
nC
nC
gate-source charge
QGS1
pre-threshold
5.5
gate-source charge
QGS2
post-threshold
-
3.5
-
nC
gate-source charge
QGD
gate-drain charge
-
-
5.4
2.8
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 11; see
Figure 12
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
-
-
2786
3300
-
-
pF
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
Coss
Crss
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
-
-
579
297
-
-
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
-
-
-
28
43
35
19
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
5 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Symbol
Characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; see
Figure 14
-
0.85
-
V
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V
-
-
47
17
-
-
ns
Qr
nC
003aab714
003aab716
100
80
V
GS
(V) = 10
5
4.5
I
D
(A)
I
D
(A)
3.8
3.4
80
60
60
40
20
0
40
20
0
3.2
3
T = 150 °C
25 °C
j
0
0.2
0.4
0.6
0.8
V
1
0
1
2
3
4
(V)
V
(V)
DS
GS
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab272
003aab938
−1
3
10
I
D
(A)
V
GS(th)
(V)
−2
−3
−4
−5
−6
10
max
2
10
10
10
10
typ
min
typ
max
1.5
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T (°C)
j
V
(V)
GS
Fig 8. Sub-threshold drain current as a function of
gate-source voltage
Fig 7. Gate-source threshold voltage as a function of
junction temperature
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
6 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab467
003aab715
2
a
20
3
3.2 3.4
V
GS
(V) = 2.8
R
DSon
(mΩ)
1.6
1.2
0.8
0.4
0
15
10
5
3.8
4.5
10
0
−60
0
60
120
180
0
25
50
75
100
T (°C)
j
I (A)
D
Fig 10. Drain-source on-state resistance as a function
of drain current; typical values
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aac425
10
ID = 25 A
V
DS
VGS
(V)
Tj = 25° C
VDS = 12 V
8
I
D
V
GS(pl)
6
4
2
0
V
GS(th)
V
GS
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig 11. Gate charge waveform definitions
0
12.5
25
37.5
50
G (nC)
Q
Fig 12. Gate-source voltage as a function of gate
charge; typical values
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
7 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab719
003aab718
4
10
80
I
S
(A)
C
(pF)
60
C
iss
3
10
40
20
0
T = 150 °C
j
25 °C
C
C
oss
rss
2
10
−1
2
10
1
10
10
0
0.3
0.6
0.9
1.2
V
(V)
V
SD
(V)
DS
Fig 14. Source current as a function of source-drain
voltage; typical values
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
8 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 15. Package outline SOT669 (LFPAK)
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
9 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PH4330L_1
20081022
Product data sheet
-
-
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
10 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Document status [1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
9.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PH4330L_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 22 October 2008
11 of 12
PH4330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 October 2008
Document identifier: PH4330L_1
相关型号：
©2020 ICPDF网 联系我们和版权申明