PHB153NQ08LT,118 [NXP]
PHB153NQ08LT;
| 型号： | PHB153NQ08LT,118 |
| 厂家： | 
NXP |
| 描述： | PHB153NQ08LT 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Rev. 01 — 31 March 2004
Product data
1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package
using TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Very low on-state resistance.
1.3 Applications
■ Motors, lamps, solenoids
■ DC-to-DC converters
■ Uninterruptable power supplies
■ General industrial applications.
1.4 Quick reference data
■ VDS ≤ 75 V
■ Ptot ≤ 300 W
■ ID ≤ 75 A
■ RDSon ≤ 5.5 mΩ.
2. Pinning information
Table 1:
Pin Description
Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outline and symbol
Simplified outline
Symbol
1
2
3
gate (g)
d
s
mb
mb
[1]
drain (d)
source (s)
g
mb mounting base;
connected to
drain (d)
MBB076
2
1
3
MBK116
MBK106
1
2 3
SOT78 (TO-220AB)
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PHP153NQ08LT
PHB153NQ08LT
TO-220AB Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78
D2-PAK
Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
75
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
75
V
-
±15
75
V
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3
Tmb = 100 °C; VGS = 10 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
A
-
75
A
IDM
Ptot
Tstg
Tj
peak drain current
-
240
300
175
175
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
75
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
240
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 75 A;
tp = 0.15 ms; VDD ≤ 75 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C
-
560
mJ
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
2 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03aa16
03ap24
120
120
I
P
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
( C)
0
50
100
150
200
( C)
T
T
mb
°
°
mb
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
-----------------------
-------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ap17
3
10
I
D
(A)
Limit R
= V
/ I
DS D
DSon
t
p
= 10 s
µ
2
10
1 ms
10 ms
DC
10
100 ms
1 s
1
2
3
10
1
10
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
3 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
5. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
Rth(j-mb) thermal resistance from junction to mounting base Figure 4
-
-
0.5
K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT78
vertical in still air
-
-
60
50
-
-
K/W
K/W
SOT404
mounted on printed-circuit
board; minimum footprint;
vertical in still air.
5.1 Transient thermal impedance
03ap16
1
Z
th(j-mb)
(K/W)
= 0.5
δ
0.2
0.1
-1
10
0.05
0.02
t
p
P
δ =
single pulse
T
t
t
p
T
-2
10
-4
10
-3
10
-2
10
-1
10
1
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
4 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
75
68
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
1.5
2
V
V
V
Tj = 175 °C
0.5
-
-
-
-
Tj = −55 °C
2.2
IDSS
VDS = 75 V; VGS = 0 V
Tj = 25 °C
-
-
-
-
1
µA
µA
nA
Tj = 175 °C
-
500
100
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
2
RDSon
drain-source on-state resistance
-
-
-
-
5.2
6.1
mΩ
Tj = 175 °C
10.9 12.8 mΩ
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A; Figure 7 and 8
-
6.6
5.5
mΩ
mΩ
4.7
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 25 A; VDD = 60 V; VGS = 5 V; Figure 13
-
-
-
-
-
-
-
-
-
-
95
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
17
37
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 11
8770
840
335
68
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 5.6 Ω
144
273
116
td(off)
tf
turn-off delay time
fall time
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
-
-
-
0.8
68
1.2
V
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
-
-
ns
nC
Qr
176
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
5 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03ap18
03ap20
240
75
10 V 3.8 V
T = 25 C
°
V
> I x R
D DSon
j
DS
I
I
3.4 V
D
D
(A)
(A)
5 V
160
50
3.2 V
3 V
25
80
2.8 V
V
3
= 2.6 V
GS
T = 175 C
°
25 C
°
j
0
0
0
1
2
3
0
1
2
4
V
(V)
DS
V
(V)
GS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ap19
03ac63
20
3
3.4 V
T = 25 C
V
= 3.2 V
GS
°
R
j
DSon
(m
)
Ω
a
2
15
10
5
3.8 V
1
0
5 V
10 V
0
0
80
160
240
-60
0
60
120
180
°
T ( C)
I
(A)
j
D
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
6 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03aa33
03aa36
-1
-2
-3
-4
-5
-6
2.5
10
I
V
D
(A)
10
GS(th)
(V)
2
1.5
1
max
10
10
10
10
typ
min
typ
max
min
0.5
0
-60
0
60
120
180
0
1
2
3
°
T ( C)
V
(V)
GS
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ap22
1E+5
C
(pF)
4
10
C
C
iss
3
10
oss
C
rss
2
10
-1
2
10
10
1
10
V
(V)
DS
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
7 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03ap21
03ap23
75
10
V
I = 25 A
D
GS
(V)
V
= 0 V
GS
I
S
T = 25 C
°
j
(A)
8
6
4
2
0
50
14 V
V
= 60 V
DD
25
175 C
°
T = 25 C
°
j
0
0
0.3
0.6
0.9
1.2
0
50
100
150
200
Q
(nC)
G
V
(V)
SD
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 25 A; VDD = 14 V and 60 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
8 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 14. SOT78 (TO-220AB).
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
9 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 15. SOT404 (D2-PAK).
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
10 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
8. Revision history
Table 6:
Revision history
CPCN
Rev Date
Description
01 20040331
-
Product data (9397 750 12721)
9397 750 12721
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 31 March 2004
11 of 13
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
9. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12 of 13
9397 750 12721
Product data
Rev. 01 — 31 March 2004
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
5
5.1
6
7
8
9
10
11
12
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 31 March 2004
Document order number: 9397 750 12721
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