PHB45N03LTT/R [NXP]

TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power;


型号：	PHB45N03LTT/R
厂家：	NXP
描述：	TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power 开关脉冲晶体管
文件：	总6页 (文件大小：45K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

V_DSS= 30 V

I_D= 45 A

_DS(ON)≤ 24 mΩ (V_GS= 5 V)

R_DS(ON)≤ 21 mΩ (V_GS= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB45N03LT is supplied in the SOT404 surface mounting package.

The PHD45N03LT is supplied in the SOT428 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

SOT428

DESCRIPTION

tab

gate

drain¹

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 15

180

˚C

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

- 55

175

1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction

to mounting base

1.75 K/W

R_{th j-a}

Thermal resistance junction SOT78 package, in free air

K/W

to ambient

SOT404 and SOT428 packages, pcb

mounted, minimum footprint

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

V_GS(TO)

Drain-source breakdown

voltage

Gate threshold voltage

V_GS= 0 V; I_D= 0.25 mA;

0.5

mΩ

µA

T_j= -55˚C

V_DS= V_GS; I_D= 1 mA

1.5

0.05

T_j= 175˚C

T_j= -55˚C

2.3

500

100

R_DS(ON)

Drain-source on-state

resistance

V_GS= 5 V; I_D= 25 A

V_GS= 10 V; I_D= 25 A

V_GS= 5 V; I_D= 25 A; T_j= 175˚C

g_fs

I_DSS

Forward transconductance

Zero gate voltage drain

current

V_DS= 25 V; I_D= 25 A

V_DS= 30 V; V_GS= 0 V;

T_j= 175˚C

I_GSS

Gate source leakage current V_GS= ±5 V; V_DS= 0 V

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 40 A; V_DD= 24 V; V_GS= 5 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 15 V; I_D= 25 A;

V_GS= 5 V; R_G= 5 Ω

Resistive load

130

L_d

Internal drain inductance

Measured tab to centre of die

Measured from drain lead to centre of die

(SOT78 package only)

3.5

4.5

L_s

Internal source inductance

Measured from source lead to source

bond pad

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

1050

270

140

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

I_SM

V_SD

180

I_F= 25 A; V_GS= 0 V

I_F= 40 A; V_GS= 0 V

0.95

1.0

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 40 A; -dI_F/dt = 100 A/µs;

V_GS= -10 V; V_R= 25 V

0.08

µC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

W_DSS

Drain-source non-repetitive

I_D= 25 A; V_DD≤ 15 V;

unclamped inductive turn-off V_GS= 10 V; R_GS= 50 Ω; T_mb= 25 ˚C

energy

Normalised Power Derating

PD%

Normalised Current Derating

ID%

120

110

100

110

100

Tmb /

100 120 140 160 180

Tmb /

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 5 V

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

Drain-Source on resistance, RDS(on) (Ohms)

0.06

PHP42N03LT

ID, Drain current (Amps)

1000

4.5 V

3.5 V

4 V

3 V

0.05

0.04

0.03

0.02

0.01

tp = 10us

100 us

100

RDS(ON) = VDS/ID

5 V

1 ms

10 V

10 ms

100 ms

VGS = 15 V

Tj = 25 C

Tmb = 25 C

100

ID, Drain current (Amps)

PHP45N03LT

VDS, Drain-source voltage (Volts)

Fig.3. Safe operating area

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance

R_DS(ON)= f(I_D); parameter V_GS

Zth j-mb / (K/W)

7528-30

PHP45N03LT

Drain current, ID (A)

VDS = 25 V

D =

0.1

0.5

0.2

0.1

0.05

D =

0.02

Tj = 25 C

175 C

0.01

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

Gate-source voltage, VGS (V)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Fig.7. Typical transfer characteristics.

I_D= f(V_GS)

ID, Drain current (Amps)

15 V

5 V

10 V

PHP45N03LT

Transconductance, gfs (S)

VDS = 25 V

Tj = 25 C

4.5 V

4 V

175 C

3.5 V

3 V

VGS = 2.5 V

VDS, Drain-Source voltage (Volts)

Drain current, ID (A)

Fig.5. Typical output characteristics

I_D= f(V_DS); parameter V_GS

Fig.8. Typical transconductance

g_fs= f(I_D)

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

C / pF

9528-30

Ciss

30V TrenchMOS

10000

1000

100

1.5

0.5

Coss

Crss

-100

100

200

-50

Tj / C

150

0.1

100

VDS / V

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 25 A; V_GS= 5 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); V_GS= 0 V; f = 1 MHz

BUK959-60

VGS(TO) / V

max.

PHP45N03LT

VGS, Gate-Source voltage (Volts)

2.5

VDS = 24 V

ID = 40 A

Tj = 25 C

typ.

1.5

min.

0.5

-100

-50

Tj / C

100

150

200

Qg, Gate charge (nC)

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

Sub-Threshold Conduction

IF / A

9528-30

1E-01

1E-02

1E-03

1E-04

1E-05

Tj / C = 175

typ

98%

0.5

1.5

VSDS / V

0.5

1.5

2.5

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); V_DS= V_GS

Fig.14. Typical reverse diode current.

I_F= f(V_SDS

)

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP45N03LT, PHB45N03LT, PHD45N03LT

WDSS%

120

VDD

110

100

VDS

VGS

-ID/100

T.U.T.

R 01

RGS

shunt

100

120

140

160

180

Tmb /

Fig.16. Avalanche energy test circuit.

Fig.15. Normalised avalanche energy rating.

W_DSS% = f(T_mb); I_D= 25 A

W_DSS= 0.5 LI_D²BV_DSS/(BV_DSS− V_DD

)

January 1998

Rev 1.300

PHB45N03LTT/R [NXP]

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