PHD10N10E/T3 [NXP]
11A, 100V, 0.25ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC PACKAGE-3;型号: | PHD10N10E/T3 |
厂家: | NXP |
描述: | 11A, 100V, 0.25ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC PACKAGE-3 开关 脉冲 晶体管 |
文件: | 总7页 (文件大小:60K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suuitable for
surface mounting. The device is
intended for use in Switched Mode
Power Supplies (SMPS), motor
control, welding, DC/DC and AC/DC
converters, and in general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state resistance
100
11
V
A
W
˚C
Ω
Ptot
Tj
60
175
0.25
RDS(ON)
PINNING - SOT428
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
tab
d
gate
2
drain
g
3
source
2
s
tab drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
Drain-source voltage
-
-
100
100
30
V
V
Drain-gate voltage
RGS = 20 kΩ
-
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
-
-
V
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
11
A
ID
-
7.7
44
A
IDM
Ptot
Tstg
Tj
-
A
-
- 55
-
60
W
˚C
˚C
175
175
-
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction to
-
2.5
K/W
mounting base
Rth j-a
Thermal resistance junction to
ambient
pcb mounted, minimum
footprint
50
-
K/W
September 1997
1
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
100
-
-
V
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
2.1
3.0
1
4.0
10
1.0
100
0.25
V
µA
mA
nA
Ω
IDSS
Zero gate voltage drain current VDS = 100 V; VGS = 0 V; Tj = 25 ˚C
Zero gate voltage drain current VDS = 100 V; VGS = 0 V; Tj = 125 ˚C
Gate source leakage current
Drain-source on-state
resistance
-
-
-
-
IDSS
0.1
10
IGSS
VGS = ±30 V; VDS = 0 V
VGS = 10 V; ID = 5.5 A
RDS(ON)
0.22
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 5.5 A
VGS = 0 V; VDS = 25 V; f = 1 MHz
3
4.2
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
400
90
35
500
120
50
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 10 V; RGS = 50 Ω;
Rgen = 50 Ω
-
-
-
-
9
14
40
45
40
ns
ns
ns
ns
25
30
20
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from source lead solder
point to source bond pad
-
-
4.5
7.5
-
-
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
-
-
-
11
A
current
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
44
1.5
A
V
IF = 11 A ; VGS = 0 V
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 11 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
90
0.35
-
-
ns
µC
AVALANCHE LIMITING VALUE
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 11 A ; VDD ≤ 50 V ;
VGS = 10 V ; RGS = 50 Ω
-
-
35
mJ
September 1997
2
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
Normalised Power Derating
PD%
120
Zth j-mb / (K/W)
1E+01
1E+00
1E-01
1E-02
110
100
90
80
70
60
50
40
30
20
10
0
0.5
0.2
0.1
0.05
0.02
p
t
tp
P
D =
D
T
0
t
T
0
20
40
60
80
Tmb /
100 120 140 160 180
C
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
120
110
100
90
80
70
60
50
40
30
20
10
0
20
15
10
5
20
15
10
VGS / V =
8
7
6
5
4
0
0
20
40
60
80
100 120 140 160 180
0
2
4
6
8
10
Tmb /
C
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
RDS(ON) / Ohm
ID / A
B
100
10
1
1.0
0.8
0.6
0.4
0.2
0
A
B
4.5
5
5.5
6
VGS / V =
7.5
6.5
7
tp = 10 us
RDS(ON) = VDS/ID
8
10
100 us
1 ms
DC
20
10 ms
100 ms
0.1
1
10
100
0
2
4
6
8
10 12 14 16 18 20
ID / A
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
September 1997
3
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
VGS(TO) / V
ID / A
20
max.
4
3
2
1
0
25
Tj / C =
typ.
16
150
12
8
min.
4
0
-60
-20
20
60
Tj /
100
140
180
0
2
4
6
8
10
C
VGS / V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
gfs / S
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
5
4
3
2
1
0
2 %
typ
98 %
0
1
2
3
4
0
2
4
6
8
10
12
14
16
18
VGS / V
ID / A
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
C / pF
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10000
1000
100
Ciss
Coss
Crss
10
-60
-20
20
60
Tj /
100
140
180
0
20
40
C
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
September 1997
4
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
WDSS%
VGS / V
12
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS / V =20
80
10
8
6
4
2
0
20
40
60
80
100
120
140
160
180
0
2
4
6
8
10
Tmb /
C
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 11 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 11 A
IF / A
VDD
+
L
20
10
0
VDS
-
VGS
-ID/100
T.U.T.
0
Tj / C =
25
150
R 01
RGS
shunt
0
1
2
VSDS / V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
September 1997
5
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane
1.1
2.38 max
0.93 max
5.4
6.73 max
tab
4 min
4.6
6.22 max
0.5 min
10.4 max
0.5
2
0.3
0.5
3
1
0.8 max
(x2)
2.285 (x2)
Fig.17. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.18. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
September 1997
6
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1997
7
Rev 1.000
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