PHD6N10E [NXP]

PowerMOS transistor; 功率MOS晶体管


型号：	PHD6N10E
厂家：	NXP
描述：	PowerMOS transistor 功率MOS晶体管晶体晶体管
文件：	总7页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

field-effect power transistor in a

plastic envelope suitable for surface

mounting featuring high avalanche

energy capability, stable blocking

voltage, fast switching and high

thermalcycling performance withlow

thermal resistance. Intended for use

in Switched Mode Power Supplies

(SMPS), motor control circuits and

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Drain-source on-state resistance

100

6.3

Ω

P_tot

R_DS(ON)

0.54

general

purpose

switching

applications.

PINNING - SOT428

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I_D

Continuous drain current

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

6.3

4.5

I_DM

P_D

Pulsed drain current

Total dissipation

T_mb= 25 ˚C

∆P_D/∆T_mbLinear derating factor

T_mb> 25 ˚C

0.33

± 30

W/K

V_GS

E_AS

Gate-source voltage

Single pulse avalanche

energy

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

I_AS

Peak avalanche current

6.3

T_j, T_stg

Operating junction and

storage temperature range

- 55

175

˚C

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction to

K/W

mounting base

R_{th j-a}

Thermal resistance junction to

ambient

pcb mounted, minimum

footprint

K/W

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

ELECTRICAL CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

Drain-source breakdown

voltage

V_GS= 0 V; I_D= 0.25 mA

100

∆V_(BR)DSS

∆T_j

Drain-source breakdown

voltage temperature coefficient

Drain-source on resistance

Gate threshold voltage

Forward transconductance

Drain-source leakage current

V_DS= V_GS; I_D= 0.25 mA

0.15

V/K

R_DS(ON)

V_GS(TO)

g_fs

V_GS= 10 V; I_D= 3.4 A

V_DS= V_GS; I_D= 0.25 mA

V_DS= 50 V; I_D= 3.4 A

V_DS= 100 V; V_GS= 0 V

V_DS= 80 V; V_GS= 0 V; T_j= 150 ˚C

V_GS= ±30 V; V_DS= 0 V

2.0

1.3

0.25

3.0

0.1

0.54

4.0

250

100

Ω

µA

I_DSS

I_GSS

Gate-source leakage current

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 5.6 A; V_DD= 80 V; V_GS= 10 V

9.2

1.7

4.7

t_d(on)

t_r

t_d(off)

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 50 V; I_D= 5.6 A;

R_G= 24 Ω; R_D= 8.4 Ω

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from tab to centre of die

Measured from source lead solder

point to source bond pad

3.5

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

222

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

T_mb= 25˚C

6.3

(body diode)

I_SM

Pulsed source current (body

diode)

Diode forward voltage

T_mb= 25˚C

V_SD

t_rr

I_S= 5.6 A; V_GS= 0 V

1.5

Reverse recovery time

I_S= 5.6 A; V_GS= 0 V;

dI/dt = 100 A/µs

Q_rr

Reverse recovery charge

0.4

µC

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

Normalised Power Derating

Zth j-mb, Transient Thermal Impedance (K/W)

PD%

120

110

100

0.5

0.2

0.1

0.05

0.1

0.01

0.02

D =

Tmb /

100 120 140 160 180

10us

1ms

100us 10ms

tp, pulse widtht (s)

1us

0.1s

10s

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Normalised Current Derating

ID%

ID, Drain current (Amps)

10 V

PHP5N10

7 V

120

110

100

Tj = 25 C

6.5 V

6 V

5.5 V

5 V

VGS = 4.5 V

100 120 140 160 180

VDS, Drain-Source voltage (Volts)

Tmb /

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 5 V

Fig.5. Typical output characteristics.

I_D= f(V_DS); parameter V_GS

ID, Drain current (Amps)

PHP5N10E

RDS(on), Drain-Source on resistance (Ohms)

PHP5N10

7 V

100

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

5 V

5.5 V

6 V

6.5 V

tp = 10 us

100 us

1 ms

VGS = 10 V

10 ms

100 ms

Tj = 25 C

0.1

100

1000

VDS, Drain-source voltage (Volts)

ID, Drain current (Amps)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance.

R_DS(ON)= f(I_D); parameter V_GS

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

VGS(TO) / V

PHP5N10E

Tj = 175 C

ID, Drain current (Amps)

Tj = 25 C

VDS = 30 V

max.

typ.

min.

-60

-20

Tj /

100

140

180

VGS, Gate-source voltage (Volts)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS); parameter T_j

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 0.25 mA; V_DS= V_GS

SUB-THRESHOLD CONDUCTION

ID / A

PHP5N10E

gfs, Transconductance (S)

VDD = 30 V

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

Tj = 25 C

2 %

typ

98 %

Tj = 175 C

ID, Drain current (Amps)

VGS / V

Fig.8. Typical transconductance.

g_fs= f(I_D); parameter T_j

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised RDS(ON) = f(Tj)

Ciss, Coss, Crss, Junction capacitances (pF)

PHP5N10E

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

1000

100

Ciss

Coss

Crss

-60

-20

Tj /

100

140

180

100

VDS, Drain-source voltage (Volts)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 5.6 A; V_GS= 5 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

VGS, Gate-Source voltage (Volts)

PHP5N10E

80 V

IF, Source-drain diode current (Amps)

VGS = 0 V

PHP5N10E

ID = 5.6 A

Tj = 25 C

VDS = 20 V

50 V

Tj = 25 C

Tj = 175 C

0.5

1.5

Qg, Gate charge (nC)

VSDS, Source-drain voltage (Volts)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); parameter V_DS

Fig.16. Source-Drain diode characteristic.

I_F= f(V_SDS); parameter T_j

EAS, Normalised unclamped inductive energy (%)

Switching times (ns)

PHP5N10E

100

120

110

100

td(off)

td(on)

VDD = 50 V

VGS = 10 V

RD = 8.4 Ohms

ID = 5.6 A

Tj = 25 C

100

100 120 140 160 180

RG, Gate resistance (Ohms)

Starting Tj ( C)

Fig.14. Normalised drain-source breakdown voltage.

V_(BR)DSS/V_{(BR)DSS 25 ˚C}= f(T_j)

Fig.17. Normalised unclamped inductive energy.

E_AS% = f(T_j)

Normalised Drain-source breakdown voltage

V(BR)DSS @ Tj

1.15

VDD

V(BR)DSS @ 25 C

1.1

1.05

VDS

VGS

-ID/100

T.U.T.

0.95

0.9

R 01

RGS

shunt

0.85

-100

-50

100

150

Tj, Junction temperature (C)

Fig.18. Unclamped inductive test circuit.

Fig.15. Normalised drain-source breakdown voltage.

V_(BR)DSS/V_{(BR)DSS 25 ˚C}= f(T_j)

E_AS= 0.5 LI_D²V_(BR)DSS/(V_(BR)DSS− V_DD

)

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

MECHANICAL DATA

Dimensions in mm : Net Mass: 1.4 g

seating plane

1.1

2.38 max

0.93 max

5.4

6.73 max

tab

4 min

4.6

6.22 max

0.5 min

10.4 max

0.5

0.3

0.5

0.8 max

(x2)

2.285 (x2)

Fig.19. SOT428 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

7.0

2.15

2.5

1.5

4.57

Fig.20. SOT428 : soldering pattern for surface mounting.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

September 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD6N10E

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

September 1997

Rev 1.000

相关型号：