PHD77NQ03T,118 [NXP]
PHD77NQ03T - N-channel TrenchMOS standard level FET DPAK 3-Pin;
| 型号： | PHD77NQ03T,118 |
| 厂家： | 
NXP |
| 描述： | PHD77NQ03T - N-channel TrenchMOS standard level FET DPAK 3-Pin 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHD/PHU77NQ03T
N-channel TrenchMOS FET
Rev. 01 — 28 November 2006
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using
TrenchMOS technology.
1.2 Features
I Fast switching
I Low thermal resistance
I Computer motherboard
1.3 Applications
I DC-to-DC converters
1.4 Quick reference data
I VDS ≤ 25 V
I ID ≤ 75 A
I RDSon ≤ 9.5 mΩ
I QGD = 3.2 nC (typ)
2. Pinning information
Table 1.
Pinning
Pin
1
Description
gate (G)
Simplified outline
Symbol
mb
[1]
2
drain (D)
mb
3
source (S)
D
S
mb
mounting base; connected to
drain (D)
G
2
mbb076
1
3
1
2
3
SOT428 (DPAK)
SOT533 (IPAK)
[1] It is not possible to make a connection to pin 2 of the SOT428 package.
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
PHD77NQ03T
PHU77NQ03T
DPAK
plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
SOT428
IPAK
plastic single-ended package; 3 leads (in-line)
SOT533
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VDGR
VGS
ID
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
25
V
drain-gate voltage (DC)
gate-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
-
±20
75
V
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3
Tmb = 100 °C; VGS = 10 V; see Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tmb = 25 °C; see Figure 1
-
A
-
55.9
240
107
+175
+175
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
75
A
A
ISM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
240
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 32 A;
tp = 0.17 ms; VDS ≤ 25 V; RGS = 50 Ω;
-
100
mJ
VGS = 10 V; starting at Tj = 25 °C
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
2 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
03aa16
003aab282
120
120
Pder
(%)
Ider
(%)
80
40
0
80
40
0
0
50
100
150
200
0
50
100
150
200
mb (°C)
T
Tmb ( C)
°
Ptot
ID
Pder
=
× 100 %
Ider
=
× 100 %
-----------------------
-------------------
Ptot(25°C)
ID(25°C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab283
103
ID
Limit RDSon = VDS / ID
(A)
t =
p
10 µs
102
100 µs
DC
10
1 ms
1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
3 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
5. Thermal characteristics
Table 4.
Symbol Parameter
Rth(j-mb) thermal resistance from junction to mounting base see Figure 4
Thermal characteristics
Conditions
Min
Typ
Max Unit
-
-
1.4
K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT428
[1]
[1]
minimum footprint
-
-
-
75
50
70
-
-
-
K/W
K/W
K/W
SOT404 minimum footprint
vertical in free air
SOT533
[1] Mounted on a printed-circuit board; vertical in still air.
003aab284
10
Zth(j-mb)
(K/W)
1
δ =0.5
0.2
0.1
tp
T
10-1
P
0.05
δ =
0.02
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
4 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
25
25
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain leakage current
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
2.1
1.35
-
2.65 3.2
V
V
V
Tj = 175 °C
-
-
-
Tj = −55 °C
3.65
IDSS
VDS = 25 V; VGS = 0 V
Tj = 25 °C
-
-
-
-
-
10
500
100
-
µA
µA
nA
Ω
Tj = 175 °C
-
IGSS
RG
gate leakage current
gate resistance
VGS = ±20 V; VDS = 0 V
f = 1 MHz
-
1.2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
-
-
8.3
15
9.5
mΩ
Tj = 175 °C
17.1 mΩ
Dynamic characteristics
QG(tot)
QGS
QGS1
QGS2
QGD
VGS(pl)
QG(tot)
Ciss
total gate charge
ID = 25 A; VDS = 12 V; VGS = 10 V;
see Figure 11 and 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17.1
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
gate-source charge
pre-VGS(th) gate-source charge
post-VGS(th) gate-source charge
gate-drain charge
3.2
2.8
3.2
5
gate-source plateau voltage
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
6.2
860
400
165
1200
8.3
7.6
24.8
6.6
nC
pF
pF
pF
pF
ns
ns
ns
ns
input capacitance
VGS = 0 V; VDS = 12 V; f = 1 MHz;
see Figure 14
Coss
Crss
output capacitance
reverse transfer capacitance
input capacitance
Ciss
VGS = 0 V; VDS = 0 V; f = 1 MHz
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 10 V;
RG = 5.6 Ω
turn-off delay time
fall time
Source-drain diode
VSD
trr
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 13
-
-
-
0.9
34
1.2
V
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V
-
-
ns
nC
Qr
12.5
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
5 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
003aab285
003aab286
80
20
RDSon
(mΩ)
8
7
5.6
6
VGS (V) = 10
VGS (V) = 5.2
ID
(A)
60
15
6
5.6
5.2
7
8
40
20
0
10
5
10
4.8
4.4
4
3.8
0
0
0.2
0.4
0.6
0.8
1
0
20
40
60
80
ID (A)
V
DS (V)
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aab287
03af18
80
2
ID
a
(A)
60
40
20
1.5
1
0.5
0
Tj = 150 °C
25 °C
0
0
2
4
6
8
-60
0
60
120
180
Tj (°C)
VGS (V)
Tj = 25 °C and 175 °C; VDS > ID × RDSon
RDSon
a =
-----------------------------
RDSon(25°C)
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
6 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
003aab303
003aab304
4
10-3
VGS(th)
ID
(A)
(V)
max
3
min
typ
max
typ
10-4
min
2
10-5
1
0
10-6
-60
0
60
120
180
0
1
2
3
4
Tj (°C)
V
GS (V)
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab288
10
ID = 25 A
VGS
(V)
Tj = 25 °C
8
6
4
2
0
V
DS
12 V
VDS = 19 V
I
D
V
GS(pl)
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
0
4
8
12
16
20
QG (nC)
003aaa508
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
7 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
003aab289
003aab290
80
104
IS
(A)
C
60
40
(pF)
103
Ciss
Coss
20
150 °C
Tj = 25 °C
Crss
0
0.2
102
10-1
0.4
0.6
0.8
1
1.2
SD (V)
1
10
102
V
VDS (V)
Tj = 25 °C and 175 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aab291
104
C
(pF)
Ciss
103
Crss
102
10-1
1
10
V
GS (V)
VGS = 0 V; f = 1 MHz
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
8 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A
b
2
E
1
1
mounting
base
D
2
D
1
H
D
2
L
L
2
L
1
1
3
b
1
b
M
c
w
A
e
e
1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
y
max
D
min
E
min
L
1
min
2
1
UNIT
A
A
1
b
b
b
c
D
E
e
e
1
H
D
L
L
2
w
1
2
1
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
6.73
6.47
10.4
9.6
2.95
2.55
0.9
0.5
4.0
4.45
0.5
mm
2.285 4.57
0.2
0.2
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
06-02-14
06-03-16
SOT428
SC-63
TO-252
Fig 16. Package outline SOT428 (DPAK)
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
9 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
Plastic single-ended package (IPAK); 3 leads (in-line)
SOT533
E
A
E
A
1
1
D
1
mounting
base
D
2
L
1
Q
L
1
2
3
e
1
c
M
b
w
e
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(2)
L
1
UNIT
A
A
1
b
c
D
D
E
E
e
e
1
L
Q
w
1
2
1
max
2.38 0.93 0.89 0.56 1.10 6.22 6.73 5.21
2.22 0.46 0.71 0.46 0.96 5.98 6.47 5.00
4.57
BSC
2.285 9.6
(1)
1.1
1.0
2.7
0.3
mm
(1)
9.2
BSC
Notes
1. Basic spacing between centers.
2. Terminal dimensions are uncontrolled within zone L .
1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
05-02-11
06-02-14
SOT533
TO-251
Fig 17. Package outline SOT533 (IPAK)
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
10 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHD_PHU77NQ03T_1
20061128
Product data sheet
-
-
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
11 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PHD_PHU77NQ03T_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 28 November 2006
12 of 13
PHD/PHU77NQ03T
NXP Semiconductors
N-channel TrenchMOS FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 November 2006
Document identifier: PHD_PHU77NQ03T_1
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