PHD97NQ03LT [NXP]
N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET
| 型号： | PHD97NQ03LT |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS logic level FET |
| 文件： | 总12页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHD97NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 — 24 March 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Fast switching
Low on-state resistance
Lead-free packing
Logic level threshold
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
Computer motherboard high
Switched-mode power supplies
Voltage regulators
frequency DC-to-DC convertors
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
Min
Typ
Max Unit
VDS
ID
-
-
-
-
25
75
V
A
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
-
107
-
W
Dynamic characteristics
QGD gate-drain charge
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 9;
see Figure 10
1.9
nC
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 7;
see Figure 8
-
5.3
6.3
mΩ
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
2
drain
source
3
G
mb
mounting base; connected to
drain
mbb076
S
2
1
3
SOT428
(SC-63; DPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PHD97NQ03LT
SC-63; DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads SOT428
(one lead cropped)
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
25
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
VDGR
VGS
-
25
V
-20
20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
69
A
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
75
A
IDM
Ptot
Tstg
Tj
peak drain current
-
300
107
175
175
A
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
-55
-55
junction temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
75
A
A
ISM
tp ≤ 10 µs; pulsed; Tmb = 25 °C
240
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 35 A; Vsup ≤ 25 V;
-
60
mJ
drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 Ω
energy
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
2 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab533
03aa16
120
120
I
P
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
T (°C)
j
T
mb
(°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aab556
3
10
I
D
R
DSon
= V / I
DS D
(A)
t
p
= 10 μs
2
10
100 μs
DC
10
1 ms
10 ms
1
10
−1
2
1
10
10
V
DS
(V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
3 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to
mounting base
see Figure 4
-
-
1.4
K/W
Rth(j-a)
thermal resistance from junction to
ambient
minimum footprint
[1]
-
75
-
K/W
[1] Mounted on a printed-circuit board; vertical in still air
003aab535
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
tp
δ =
P
10-1
0.05
0.02
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
1
10
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
4 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
25
22
1.3
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.7
2.15
voltage
see Figure 5; see Figure 6
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 5
0.7
-
-
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 5
2.6
IDSS
IGSS
drain leakage current
gate leakage current
VDS = 25 V; VGS = 0 V; Tj = 25 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
1
µA
nA
nA
mΩ
-
100
100
12
-
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 7; see Figure 8
10.1
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 7; see Figure 8
-
-
8
10.6
6.3
mΩ
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
5.3
see Figure 7; see Figure 8
VDS = 25 V; VGS = 0 V; Tj = 175 °C
f = 1 MHz
IDSS
RG
drain leakage current
gate resistance
-
-
-
100
-
µA
1.5
Ω
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 9; see Figure 10
-
11.7
-
nC
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
-
-
10.2
6.2
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 9; see Figure 10
QGS1
pre-threshold
3.4
gate-source charge
QGS2
post-threshold
-
2.8
-
nC
gate-source charge
QGD
gate-drain charge
-
-
1.9
3.1
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 9; see
Figure 10
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 11
-
-
1570
1800
-
-
pF
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
Coss
Crss
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 11
-
-
380
160
-
-
pF
pF
reverse transfer
capacitance
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
5 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Symbol
td(on)
tr
Characteristics …continued
Parameter
Conditions
Min
Typ
18
Max
Unit
ns
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
-
-
-
-
-
-
-
33
ns
td(off)
tf
turn-off delay time
fall time
20
ns
12
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 12
-
0.87
1.2
V
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V
-
-
38
14
-
-
ns
Qr
nC
003aab272
003aab271
−3
3
10
I
V
GS(th)
(V)
D
(A)
max
−4
2
10
max
min
typ
typ
1.5
min
−5
1
10
0.5
−6
0
-60
10
0
60
120
180
0
0.5
1
1.5
2
2.5
(V)
T (°C)
j
V
GS
Fig 5. Gate-source threshold voltage as a function of
junction temperature
Fig 6. Sub-threshold drain current as a function of
gate-source voltage
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
6 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab467
003aab537
2
a
25
RDSon
(mΩ)
3.3
VGS (V) =
1.6
1.2
0.8
0.4
0
20
15
10
5
3.7
4.1
4.5
5
6
10
0
0
20
40
60
80
−60
0
60
120
180
ID (A)
T (°C)
j
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
Fig 7. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aab539
10
ID = 25 A
V
DS
VGS
Tj = 25 °C
(V)
I
8
6
4
2
0
D
V
GS(pl)
VDS = 19 V
12 V
V
GS(th)
V
GS
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig 10. Gate charge waveform definitions
0
10
20
30
Q
G (nC)
Fig 9. Gate-source voltage as a function of gate
charge; typical values
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
7 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab542
003aab541
104
80
IS
(A)
C
(pF)
60
Ciss
103
40
20
0
Tj = 25 °C
175 °C
Coss
Crss
102
10-1
1
10
102
0
0.4
0.8
1.2
VDS (V)
VSD (V)
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 12. Source current as a function of source-drain
voltage; typical values
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
8 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A
1
b
2
E
1
mounting
base
D
2
D
1
H
D
2
L
L
2
L
1
1
3
b
1
b
M
c
w
A
e
e
1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
y
max
D
min
E
min
L
1
min
2
1
UNIT
A
A
1
b
b
1
b
2
c
D
E
e
e
1
H
L
L
2
w
1
D
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
6.73
6.47
10.4
9.6
2.95
2.55
0.9
0.5
4.0
4.45
0.5
mm
2.285 4.57
0.2
0.2
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
06-02-14
06-03-16
SOT428
SC-63
TO-252
Fig 13. Package outline SOT428 (DPAK)
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
9 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHD97NQ03LT_1
20090324
Product data sheet
-
-
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
10 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Document status [1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
9.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PHD97NQ03LT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 March 2009
11 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 March 2009
Document identifier: PHD97NQ03LT_1
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