PHK24NQ04LT_技术文档

PHK24NQ04LT

TrenchMOS™ logic level FET

M3D315

Rev. 01 — 12 September 2003

Product data

1. Product proﬁle

1.1 Description

N-channel logic level ﬁeld-effect transistor in a plastic package using TrenchMOS™

technology.

Product availability:

PHK24NQ04LT in SOT96-1 (SO8).

1.2 Features

■ Logic level compatible

■ Low gate charge.

1.3 Applications

■ DC-to-DC converters

■ Switched-mode power supplies.

1.4 Quick reference data

■ V_DS≤ 40 V

■ I_D≤ 21.2 A

■ P_tot≤ 6.25 W

■ R_DSon≤ 7.7 mΩ.

2. Pinning information

Table 1:

Pinning - SOT96-1 (SO8) simpliﬁed outline and symbol

Description

source (s)

gate (g)

Simpliﬁed outline

Symbol

1,2,3

4

d

8

5

5,6,7,8 drain (d)

g

1

4

s

MBB076

Top view

MBK187

SOT96-1 (SO8)

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

3. Limiting values

Table 2:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

40

Unit

V

V_DS

V_DGR

V_GS

I_D

drain-source voltage (DC)

25 °C ≤ T_j≤ 150 °C

-

drain-gate voltage (DC)

gate-source voltage (DC)

drain current (DC)

25 °C ≤ T_j≤ 150 °C; R_GS= 20 kΩ

-

40

V

-

±20

21.2

15.9

60

V

T_sp= 25 °C; V_GS= 10 V; Figure 2 and 3

T_sp= 80 °C; V_GS= 10 V; Figure 2

T_sp= 25 °C; pulsed; t_p≤ 10 µs; Figure 3

T_sp= 25 °C; Figure 1

-

A

-

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

A

total power dissipation

storage temperature

junction temperature

-

6.25

+150

W

°C

−55

Source-drain diode

I_S

source (diode forward) current (DC) T_sp= 25 °C

-

5.2

A

I_SM

peak source (diode forward) current T_sp= 25 °C; pulsed; t_p≤ 10 µs

20.8

9397 750 11709

Product data

Rev. 01 — 12 September 2003

2 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

03aa25

03aa17

120

I

P

der

(%)

der

(%)

80

40

0

50

100

150

200

( C)

0

50

100

150

200

T

°

sp

T

(°C)

sp

P_tot

I_D

P_der

=

× 100%

I_der

=

× 100%

-----------------------

-------------------

P

I

°

tot(25 C)

D(25 C)

Fig 1. Normalized total power dissipation as a

function of solder point temperature.

Fig 2. Normalized continuous drain current as a

function of solder point temperature.

03aj99

2

10

Limit R

= V

/ I

DS D

DSon

t

p

= 10 µs

I

D

(A)

100 µs

10

1 ms

10 ms

DC

100 ms

1

-1

10

-1

2

10

1

10

V

(V)

DS

T_sp= 25 °C; I_DMis single pulse; V_GS= 10 V.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 11709

Product data

Rev. 01 — 12 September 2003

3 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

4. Thermal characteristics

Table 3: Thermal characteristics

Symbol Parameter

Conditions

Min Typ Max Unit

R_th(j-sp)thermal resistance from junction to solder point Figure 4

-

20

K/W

4.1 Transient thermal impedance

03aj98

2

10

Z

th(j-sp)

(K/W)

δ = 0.5

10

0.2

0.1

0.05

t

p

1

P

δ =

T

0.02

t

p

T

single pulse

10

-1

10

-4

10

-3

-2

10

-1

10

2

1

10

t

p

(s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

9397 750 11709

Product data

Rev. 01 — 12 September 2003

4 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

5. Characteristics

Table 4:

Characteristics

T_j= 25 °C unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min Typ Max Unit

Static characteristics

V_(BR)DSSdrain-source breakdown voltage

I_D= 250 µA; V_GS= 0 V

T_j= 25 °C

40

36

-

V

T_j= −55 °C

V_GS(th)

gate-source threshold voltage

drain-source leakage current

I_D= 1 mA; V_DS= V_GS; Figure 9

T_j= 25 °C

1

1.5

2

V

T_j= 150 °C

0.6

-

T_j= −55 °C

2.2

I_DSS

V_DS= 40 V; V_GS= 0 V

T_j= 25 °C

-

0.05

-

1

µA

T_j= 150 °C

500 µA

I_GSS

gate-source leakage current

V_GS= ±16 V; V_DS= 0 V

V_GS= 4.5 V; I_D= 12 A; Figure 7 and 8

T_j= 25 °C

10

100 nA

R_DSon

drain-source on-state resistance

-

7.8

14

9.2

mΩ

T_j= 150 °C

16.6 mΩ

V_GS= 10 V; I_D= 14 A; Figure 7 and 8

6.5

7.7

mΩ

Dynamic characteristics

Q_g(tot)

Q_gs

Q_gd

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

gate-source charge

gate-drain (Miller) charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

I_D= 14 A; V_DD= 20 V; V_GS= 10 V; Figure 13

V_GS= 0 V; V_DS= 25 V; f = 1 MHz; Figure 11

V_DD= 20 V; I_D= 1 A; V_GS= 5 V; R_G= 6 Ω

-

64

-

nC

pF

ns

7.7

11.5

2985 -

490

240

30

-

30

t_d(off)

t_f

turn-off delay time

fall time

60

40

Source-drain diode

V_SD

t_rr

source-drain (diode forward) voltage I_S= 2.3 A; V_GS= 0 V; Figure 12

-

0.75 1.2

V

reverse recovery time

recovered charge

I_S= 2 A; dI_S/dt = −100 A/µs; V_GS= 0 V

49

36

-

ns

nC

Q_r

9397 750 11709

Product data

Rev. 01 — 12 September 2003

5 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

03ak00

03ak02

20

10 V 4.5 V 3.2 V 3 V

2.8 V

V

> I x R

D DSon

DS

I

D

(A)

15

2.6 V

10

5

10

5

2.4 V

°

25 C

T = 150 C

j

V

= 2.2 V

GS

0.4

0

0.1

0.2

0.3

0.5

(V)

0

1

2

3

V

(V)

V

GS

DS

T_j= 25 °C

T_j= 25 °C and 150 °C; V_DS> I_Dx R_DSon

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

03ak01

03ak06

30

2

°

T = 25 C

j

R

DSon

(mΩ)

a

V

= 2.8 V

GS

1.5

20

3 V

1

0.5

0

3.2 V

10

4.5 V

10 V

0

-60

0

60

120

180

0

5

10

15

20

°

T ( C)

j

I

(A)

D

T_j= 25 °C

R_DSon

a =

----------------------------

R_{DSon(25 C)}

°

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values.

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

9397 750 11709

Product data

Rev. 01 — 12 September 2003

6 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

03aa33

03aa36

-1

-2

-3

-4

-5

-6

2.5

10

I

V

D

(A)

10

GS(th)

(V)

2

1.5

1

max

10

typ

min

typ

max

min

0.5

0

-60

0

60

120

180

0

1

2

3

°

T ( C)

V

(V)

GS

j

I_D= 1 mA; V_DS= V_GS

T_j= 25 °C; V_DS= 5 V

Fig 9. Gate-source threshold voltage as a function of

junction temperature.

Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

03ak04

4

10

C

(pF)

C

iss

3

10

C

oss

rss

2

10

-1

2

10

1

10

V

(V)

DS

V_GS= 0 V; f = 1 MHz

Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.

9397 750 11709

Product data

Rev. 01 — 12 September 2003

7 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

03ak03

03ak05

20

10

V

= 0 V

I = 14 A

D

GS

(V)

GS

I

S

(A)

°

T = 25 C

j

8

6

4

2

0

15

V

= 20 V

DD

10

5

°

150 C

°

T = 25 C

j

0

0.3

0.6

0.9

1.2

0

20

40

60

80

Q

(nC)

V

(V)

G

SD

T_j= 25 °C and 150 °C; V_GS= 0 V

I_D= 14 A; V_DD= 20 V

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

values.

Fig 13. Gate-source voltage as a function of gate

charge; typical values.

9397 750 11709

Product data

Rev. 01 — 12 September 2003

8 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

6. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 14. SOT96-1 (SO8).

9397 750 11709

Product data

Rev. 01 — 12 September 2003

9 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

7. Revision history

Table 5:

Revision history

CPCN

Rev Date

Description

01 20030912

-

Product data (9397 750 11709)

9397 750 11709

Product data

Rev. 01 — 12 September 2003

10 of 12

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

8. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

9. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

11. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

10. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

11 of 12

9397 750 11709

Product data

Rev. 01 — 12 September 2003

PHK24NQ04LT

TrenchMOS™ logic level FET

Philips Semiconductors

Contents

1

Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

Transient thermal impedance . . . . . . . . . . . . . . 4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

4

4.1

5

6

7

8

9

10

11

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 12 September 2003

Document order number: 9397 750 11709


型号：	PHK24NQ04LT
厂家：	NXP
描述：	TrenchMOS logic level FET 的TrenchMOS逻辑电平FET 晶体小信号场效应晶体管开关光电二极管
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