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PHKD6N02LT/T3 [NXP]

TRANSISTOR 10900 mA, 20 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, PLASTIC, MS-012, SOP-8, FET General Purpose Small Signal;
PHKD6N02LT/T3
型号： PHKD6N02LT/T3
厂家： NXP    NXP
描述：

TRANSISTOR 10900 mA, 20 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, PLASTIC, MS-012, SOP-8, FET General Purpose Small Signal

开关 光电二极管 晶体管
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PHKD6N02LT  
Dual N-channel TrenchMOS logic level FET  
Rev. 03 — 19 November 2009  
Product data sheet  
1. Product profile  
1.1 General description  
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic  
package using TrenchMOS technology. This product is designed and qualified for use in  
computing, communications, consumer and industrial applications only.  
1.2 Features and benefits  
„ Low conduction losses due to low  
„ Suitable for logic level gate drive  
on-state resistance  
sources  
1.3 Applications  
„ Battery chargers  
„ Notebook computers  
„ Portable equipment  
„ DC-to-DC convertors  
1.4 Quick reference data  
Table 1.  
Quick reference  
Symbol Parameter  
Conditions  
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C  
Min  
Typ  
Max Unit  
VDS  
ID  
-
-
-
-
20  
V
A
drain current  
Tsp = 25 °C; Single device  
10.9  
conducting; see Figure 1 and 3  
Ptot  
total power  
dissipation  
Tsp = 25 °C; see Figure 2  
-
-
-
-
4.17  
-
W
Dynamic characteristics  
QGD gate-drain charge  
VGS = 5 V; ID = 6 A; VDS = 16 V;  
Tj = 25 °C; see Figure 11  
6
nC  
mΩ  
Static characteristics  
RDSon  
drain-source  
VGS = 2.5 V; ID = 3 A; Tj = 25 °C  
25  
35  
on-state resistance  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
2. Pinning information  
Table 2.  
Pinning information  
Pin  
1
Symbol Description  
Simplified outline  
Graphic symbol  
S1  
G1  
S2  
G2  
D2  
D2  
D1  
D1  
source1  
gate1  
8
5
4
D1 D1  
D2 D2  
2
3
source2  
gate2  
4
5
drain2  
drain2  
drain1  
drain1  
1
6
SOT96-1 (SO8)  
S1  
G1  
S2  
G3  
7
mbk725  
8
3. Ordering information  
Table 3.  
Ordering information  
Type number  
Package  
Name  
SO8  
Description  
plastic small outline package; 8 leads; body width 3.9 mm  
Version  
PHKD6N02LT  
SOT96-1  
4. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDS  
Parameter  
Conditions  
Min  
Max  
20  
Unit  
drain-source voltage  
drain-gate voltage  
gate-source voltage  
drain current  
Tj ≥ 25 °C; Tj ≤ 150 °C  
Tj ≤ 150 °C; Tj ≥ 25 °C; RGS = 20 kΩ  
-
V
V
V
A
A
VDGR  
VGS  
-
20  
-12  
12  
ID  
Tsp = 100 °C; Single device conducting; see Figure 1  
-
-
6.8  
10.9  
Tsp = 25 °C; Single device conducting; see Figure 1  
and 3  
IDM  
peak drain current  
Tsp = 25 °C; tp ≤ 100 µs; pulsed; Single device  
-
44  
A
conducting; see Figure 3  
Ptot  
Tstg  
Tj  
total power dissipation Tsp = 25 °C; see Figure 2  
storage temperature  
-
4.17  
150  
150  
W
-55  
-55  
°C  
°C  
junction temperature  
Source-drain diode  
IS  
source current  
peak source current  
Tsp = 25 °C  
-
-
3.5  
44  
A
A
ISM  
Tsp = 25 °C; tp ≤ 10 µs; pulsed  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
2 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
03aa25  
03aa17  
120  
120  
I
P
der  
der  
(%)  
(%)  
80  
80  
40  
40  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
sp  
(°C)  
T
sp  
(°C)  
Fig 1. Normalized continuous drain current as a  
function of solder point temperature  
Fig 2. Normalized total power dissipation as a  
function of solder point temperature  
003aaa300  
2
10  
Limit R  
= V /I  
DS D  
DSon  
I
t
= 10 μs  
D
p
(A)  
100 μs  
10  
1 ms  
10 ms  
100 ms  
1
DC  
−1  
10  
−2  
10  
−1  
2
10  
1
10  
10  
V
(V)  
DS  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
3 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
5. Thermal characteristics  
Table 5.  
Symbol  
Rth(j-sp)  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
thermal resistance from junction see Figure 4  
to solder point  
-
-
30  
K/W  
Rth(j-a)  
thermal resistance from junction minimum footprint; mounted on  
-
70  
-
K/W  
to ambient  
printed-circuit board  
003aaa301  
2
10  
Z
th(j-sp)  
(K/W)  
δ = 0.5  
10  
0.2  
0.1  
0.05  
0.02  
single pulse  
1
t
p
P
δ =  
T
t
t
p
T
−1  
10  
−4  
−3  
−2  
−1  
10  
10  
10  
10  
1
10  
t
(s)  
p
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
4 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
6. Characteristics  
Table 6.  
Symbol  
Characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Static characteristics  
V(BR)DSS  
VGS(th)  
IDSS  
drain-source  
breakdown voltage  
ID = 250 µA; VGS = 0 V; Tj = 25 °C  
20  
-
-
-
V
V
gate-source threshold ID = 250 µA; VDS = 10 V; Tj = 25 °C;  
voltage  
0.5  
1.5  
see Figure 8  
drain leakage current  
VDS = 20 V; VGS = 0 V; Tj = 25 °C  
VDS = 20 V; VGS = 0 V; Tj = 150 °C  
VGS = 12 V; VDS = 0 V; Tj = 25 °C  
VGS = -12 V; VDS = 0 V; Tj = 25 °C  
VGS = 2.5 V; ID = 3 A; Tj = 25 °C  
-
-
-
-
-
-
0.05  
10  
µA  
µA  
nA  
-
500  
100  
100  
35  
IGSS  
gate leakage current  
-
-
nA  
RDSon  
drain-source on-state  
resistance  
25  
-
mΩ  
mΩ  
VGS = 5 V; ID = 3 A; Tj = 150 °C;  
see Figure 9 and 10  
35  
VGS = 5 V; ID = 3 A; Tj = 25 °C;  
see Figure 9 and 10  
-
16  
20  
mΩ  
Dynamic characteristics  
QG(tot)  
QGS  
QGD  
Ciss  
total gate charge  
gate-source charge  
gate-drain charge  
input capacitance  
output capacitance  
ID = 6 A; VDS = 16 V; VGS = 5 V;  
Tj = 25 °C; see Figure 11  
-
-
-
-
-
-
15.3  
2.2  
6
-
-
-
-
-
-
nC  
nC  
nC  
pF  
pF  
pF  
VDS = 10 V; VGS = 0 V; f = 1 MHz;  
Tj = 25 °C; see Figure 12  
950  
355  
256  
Coss  
Crss  
reverse transfer  
capacitance  
td(on)  
tr  
td(off)  
tf  
turn-on delay time  
rise time  
VDS = 10 V; RL = 3.3 Ω; VGS = 5 V;  
RG(ext) = 4.7 Ω; Tj = 25 °C  
-
-
-
-
15  
49  
50  
23  
-
-
-
-
ns  
ns  
ns  
ns  
turn-off delay time  
fall time  
Source-drain diode  
VSD  
source-drain voltage  
IS = 6 A; VGS = 0 V; Tj = 25 °C;  
see Figure 13  
-
-
1.2  
V
trr  
reverse recovery time  
recovered charge  
IS = 6 A; dIS/dt = -100 A/µs; VGS = 0 V;  
VDS = 20 V; Tj = 25 °C  
-
-
40  
7
-
-
ns  
Qr  
nC  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
5 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
003aaa302  
003aaa303  
10  
8
4.5 V  
V
GS  
= 4.5 V  
I
D
I
D
(A)  
2.1 V  
(A)  
8
6
4
2
0
6
1.9 V  
T = 150 °C  
j
4
2
0
1.8 V  
1.7 V  
25 C  
°
1.6 V  
1.5 V  
0
1
2
3
0
0.5  
1
1.5  
2
V
(V)  
V
(V)  
GS  
DS  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values  
Fig 6. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
003aaa417  
003aaa416  
−1  
10  
2
I
D
V
GS(th)  
(V)  
(A)  
−2  
10  
max  
1.5  
max  
min  
−3  
10  
1
0.5  
0
−4  
−5  
−6  
10  
10  
10  
min  
−60  
0
60  
120  
180  
0
1
1.5  
2
0.5  
V
(V)  
T (°C)  
j
GS  
Fig 7. Sub-threshold drain current as a function of  
gate-source voltage  
Fig 8. Gate-source threshold voltage as a function of  
junction temperature  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
6 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
03aa27  
003aaa304  
2
100  
1.7 V  
1.8 V  
1.9 V  
2.0 V  
R
DSon  
a
(mΩ)  
1.5  
75  
1
50  
25  
0
2.1 V  
2.2 V  
2.5 V  
0.5  
0
V
GS  
= 4.5 V  
0
2
4
6
8
10  
−60  
0
60  
120  
180  
T ( C)  
°
j
I
(A)  
D
Fig 9. Drain-source on-state resistance as a function  
of drain current; typical values  
Fig 10. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
003aaa305  
003aaa307  
4
10  
6
V
C
GS  
(pF)  
(V)  
4
3
10  
C
iss  
2
0
C
C
oss  
rss  
2
10  
−1  
2
0
5
10  
15  
20  
10  
1
10  
10  
Q
(nC)  
V
(V)  
G
DS  
Fig 11. Gate-source voltage as a function of gate  
charge; typical values  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical val  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
7 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
003aaa306  
5
I
S
(A)  
4
3
2
1
0
150 °C  
T = 25 °C  
j
0.2  
0.4  
0.6  
0.8  
1
V
(V)  
SD  
Fig 13. Source current as a function of source-drain voltage; typical values  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
8 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
7. Package outline  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 14. Package outline SOT96-1 (SO8)  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
9 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
8. Revision history  
Table 7.  
Revision history  
Document ID  
PHKD6N02LT_3  
Modifications:  
Release date  
Data sheet status  
Change notice  
Supersedes  
20091119  
Product data sheet  
-
PHKD6N02LT-02  
• The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
• Legal texts have been adapted to the new company name where appropriate.  
PHKD6N02LT-02  
PHKD6N02LT-01  
20030812  
Product data  
-
PHKD6N02LT-01  
20010907  
Product data  
-
-
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
10 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
9. Legal information  
9.1 Data sheet status  
Document status [1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term 'short data sheet' is explained in section "Definitions".  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product  
status information is available on the Internet at URL http://www.nxp.com.  
Applications — Applications that are described herein for any of these  
9.2 Definitions  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
9.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Export control — This document as well as the item(s) described herein may  
be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
9.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
TrenchMOS — is a trademark of NXP B.V.  
10. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PHKD6N02LT_3  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 03 — 19 November 2009  
11 of 12  
PHKD6N02LT  
NXP Semiconductors  
Dual N-channel TrenchMOS logic level FET  
11. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
1.1  
1.2  
1.3  
1.4  
General description . . . . . . . . . . . . . . . . . . . . . .1  
Features and benefits. . . . . . . . . . . . . . . . . . . . .1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
Quick reference data . . . . . . . . . . . . . . . . . . . . .1  
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2  
Ordering information. . . . . . . . . . . . . . . . . . . . . .2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2  
Thermal characteristics . . . . . . . . . . . . . . . . . . .4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10  
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
9.1  
9.2  
9.3  
9.4  
10  
Contact information. . . . . . . . . . . . . . . . . . . . . .11  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 19 November 2009  
Document identifier: PHKD6N02LT_3  

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