PHKD6N02LT [NXP]
Dual TrenchMOS logic level FET; 双重的TrenchMOS逻辑电平FET
| 型号： | PHKD6N02LT |
| 厂家： | 
NXP |
| 描述： | Dual TrenchMOS logic level FET |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHKD6N02LT
Dual TrenchMOS™ logic level FET
M3D315
Rev. 02 — 12 August 2003
Product data
1. Description
Dual N-channel enhancement mode field-effect transistors in a plastic surface mount
package using TrenchMOS™ technology.
Product availability:
PHKD6N02LT in SOT96-1 (SO8).
2. Features
■ Low on-state resistance
■ Logic level compatible
■ Dual device
■ Surface mount package.
3. Applications
■ DC-to-DC converters
■ Notebook computers
■ Portable appliances
■ Battery chargers.
4. Pinning information
Table 1:
Pinning - SOT96-1 (SO8), simplified outline and symbol
Pin
1
Description
source1 (s1)
gate1 (g1)
Simplified outline
Symbol
d
d
d
d
2
2
8
5
1
1
2
3
source2 (s2)
gate2 (g2)
4
1
4
5, 6
7, 8
drain2 (d2)
drain1 (d1)
Top view
MBK187
s
g
s
g
1
2
1
2
SOT96-1 (SO8)
MBK725
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
20
Unit
V
VDS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
Tsp = 25 °C
-
[1]
drain current (DC)
-
10.9
4.17
150
20
A
Ptot
Tj
total power dissipation
junction temperature
Tsp = 25 °C
-
W
-
°C
mΩ
mΩ
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 3 A
VGS = 2.5 V; ID = 3 A
16
25
35
[1] Single device conducting.
6. Ordering information
Table 3:
Ordering information
Type number
Package
Name
SO8
Description
Plastic small outline package; 8 leads
Version
SOT96-1
PHKD6N02LT
7. Limiting values
Table 4:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VDGR
VGS
ID
drain-source voltage (DC)
Tj = 25 to 150 °C
-
20
V
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
Tj = 25 to 150 °C; RGS = 20 kΩ
-
20
V
-
±12
10.9
6.8
V
[1]
[1]
[1]
Tsp = 25 °C; Figure 2 and 3
Tsp = 100 °C; Figure 2
-
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
Tsp = 25 °C; tp ≤ 100 µs; Figure 3
Tsp = 25 °C; Figure 1
-
44
A
total power dissipation
storage temperature
junction temperature
-
4.17
+150
+150
W
°C
°C
−55
−55
Source-drain (reverse) diode
IS
source (diode forward) current (DC) Tsp = 25 °C
peak (diode forward) source current Tsp = 25 °C; tp ≤ 10 µs
-
-
3.5
44
A
A
ISM
[1] Single device conducting.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
2 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
03aa25
03aa17
120
120
I
der
(%)
P
der
(%)
80
80
40
40
0
0
0
50
100
150
200
( C)
0
50
100
150
200
T
°
sp
T
(°C)
sp
VGS ≥ 4.5 V
Ptot
ID
Pder
=
× 100%
-----------------------
Ider
=
× 100%
-------------------
P
I
°
tot(25 C)
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
003aaa300
2
10
Limit R
DSon
= V /I
DS D
I
D
t
= 10 µs
p
(A)
100 µs
10
1 ms
10 ms
100 ms
1
DC
-1
10
-2
10
-1
10
2
10
1
10
V
(V)
DS
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
3 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
8. Thermal characteristics
Table 5:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-sp) thermal resistance from junction to solder point
Figure 4
-
-
-
30
-
K/W
K/W
Rth(j-a)
thermal resistance from junction to ambient
minimum footprint;
70
mounted on printed-circuit board
8.1 Transient thermal impedance
003aaa301
2
10
Z
th(j-sp)
(K/W)
δ = 0.5
10
0.2
0.1
0.05
0.02
single pulse
1
t
p
P
δ =
T
t
t
p
T
-1
10
-4
10
-3
10
-2
10
-1
10
1
10
t
p
(s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
4 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
9. Characteristics
Table 6:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
ID = 250 µA; VDS = 10 V; Figure 9
VDS = 20 V; VGS = 0 V
Tj = 25 °C
20
-
-
-
V
V
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
0.5
1.5
-
-
-
0.05 10
µA
Tj = 150 °C
-
-
500 µA
±100 nA
IGSS
gate-source leakage current
VGS = ±12 V; VDS = 0 V
VGS = 5 V; ID = 3 A; Figure 7 and 8
Tj = 25 °C
RDSon
drain-source on-state resistance
-
-
-
16
-
20
35
35
mΩ
mΩ
mΩ
Tj = 150 °C
VGS = 2.5 V; ID = 3 A
25
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 6 A; VDD = 16 V; VGS = 5 V; Figure 13
VGS = 0 V; VDD = 10 V; f = 1 MHz; Figure 11
VDS = 10 V; RD = 3.3 Ω; VGS = 5 V; RG = 4.7 Ω
-
-
-
-
-
-
-
-
-
-
15.3
2.2
6
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
950
355
256
15
49
td(off)
tf
turn-off delay time
fall time
50
23
Source-drain (reverse) diode
VSD
trr
source-drain (diode forward) voltage IS = 6 A; VGS = 0 V; Figure 12
-
-
-
-
1.2
V
reverse recovery time
recovered charge
IS = 6 A; dIS/dt = −100 A/µs; VR = 20 V;
VGS = 0 V
40
7
-
-
ns
nC
Qr
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
5 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
003aaa303
003aaa302
8
10
4.5 V
V
= 2 V
I
D
(A)
GS
I
D
2.1 V
(A)
8
6
1.9 V
6
4
2
0
T = 150 °C
j
4
2
0
1.8 V
1.7 V
25 C
°
1.6 V
1.5 V
0
2
0.5
1
1.5
0
1
2
3
V
(V)
V
(V)
GS
DS
Tj = 25 °C
Tj = 25 °C and 150 °C; VDS > ID × RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
003aaa304
03aa27
100
2
1.7 V
1.8 V
1.9 V
2.0 V
R
DSon
(mΩ)
a
75
1.5
50
25
0
1
0.5
0
2.1 V
2.2 V
2.5 V
VGS = 4.5 V
0
2
4
6
8
10
-60
0
60
120
180
I
D
(A)
°
T ( C)
j
Tj = 25 °C
RDSon
-----------------------------
RDSon(25°C)
a=
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain source on-state resistance
factor as a function of junction temperature.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
6 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
003aaa417
003aaa416
-1
10
2
I
D
V
GS(th)
(V)
(A)
-2
-3
10
max
1.5
1
max
min
10
-4
-5
-6
10
10
10
min
0.5
0
0
1
1.5
2
0.5
-60
0
60
120
180
V
(V)
GS
T ( C)
°
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa305
4
003aaa306
10
5
I
S
C
(pF)
(A)
4
3
2
1
0
150 C
°
3
10
C
iss
T = 25 C
°
j
C
oss
C
rss
2
10
-1
10
2
10
1
10
0.2
0.4
0.6
0.8
1
V
(V)
V
(V)
DS
SD
VGS = 0 V; f = 1 MHz
Tj = 25 °C and 150 °C; VGS = 0 V
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
7 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
003aaa307
6
V
GS
(V)
4
2
0
0
5
10
15
20
Q
G
(nC)
ID = 6 A; VDD = 16 V
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
8 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
10. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 14. SOT96-1 (SO8).
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
9 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
11. Revision history
Table 7:
Revision history
CPCN
Rev Date
Description
02 20030812 200209008 Product data (9397 750 10688).
Modifications:
• ID data updated in Table 2 and 4.
• Ptot data updated in Table 2 and 4.
• RDSon data updated in Table 2.
• Rth(j-a) data added in Table 5.
• Characteristics updated in Table 6.
• Figure 3, 5, 6, 7, 9, 10, 11, 12 and 13 updated.
01 20010907
-
Product data (9397 750 08522)
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
10 of 12
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
12. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
13. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
15. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
14. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 12
9397 750 10688
Product data
Rev. 02 — 12 August 2003
PHKD6N02LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
3
4
5
6
7
8
8.1
9
10
11
12
13
14
15
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 12 August 2003
Document order number: 9397 750 10688
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