PHP109/T3 [NXP]

TRANSISTOR 5 A, 30 V, 0.09 ohm, P-CHANNEL, Si, POWER, MOSFET, MS-012AA, PLASTIC, SO-8, FET General Purpose Power;
PHP109/T3
型号: PHP109/T3
厂家: NXP    NXP
描述:

TRANSISTOR 5 A, 30 V, 0.09 ohm, P-CHANNEL, Si, POWER, MOSFET, MS-012AA, PLASTIC, SO-8, FET General Purpose Power

开关 脉冲 光电二极管 晶体管
文件: 总12页 (文件大小:81K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DISCRETE SEMICONDUCTORS  
DATA SHEET  
PHP109  
P-channel enhancement mode  
MOS transistor  
1997 Jun 18  
Product specification  
Supersedes data of 1996 Jun 11  
File under Discrete Semiconductors, SC13b  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
FEATURES  
PINNING - SO8 (SOT96-1)  
High-speed switching  
No secondary breakdown  
Very low on-resistance.  
PIN  
SYMBOL  
DESCRIPTION  
1
2
3
4
5
6
7
8
n.c.  
s
not connected  
source  
source  
gate  
s
APPLICATIONS  
g
d
drain  
drain  
drain  
drain  
Motor and actuator driver  
Power management  
d
d
Synchronized rectification.  
d
DESCRIPTION  
P-channel enhancement mode MOS transistor in an 8-pin  
plastic SO8 (SOT96-1) package.  
d
d
d
d
handbook, halfpage  
8
5
CAUTION  
The device is supplied in an antistatic package.  
The gate-source input must be protected against static  
discharge during transport or handling.  
1
4
n.c. s  
s
g
MAM115  
Fig.1 Simplified outline and symbol.  
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
MAX.  
30  
UNIT  
VDS  
VSD  
VGS  
VGSth  
ID  
drain-source voltage (DC)  
source-drain diode forward voltage  
gate-source voltage (DC)  
gate-source threshold voltage  
drain current (DC)  
V
V
V
V
A
IS = 1.25 A  
1.3  
±20  
2.8  
5  
ID = 1 mA; VDS = VGS  
Ts = 80 °C  
1  
RDSon  
Ptot  
drain-source on-state resistance  
total power dissipation  
ID = 2.5 A; VGS = 10 V  
Ts = 80 °C  
0.09  
4
W
1997 Jun 18  
2
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
PARAMETER  
drain-source voltage (DC)  
CONDITIONS  
MIN.  
MAX.  
30  
UNIT  
VDS  
VGS  
ID  
V
V
A
A
gate-source voltage (DC)  
drain current (DC)  
±20  
5  
Ts = 80 °C; note 1  
note 2  
IDM  
Ptot  
peak drain current  
20  
4
total power dissipation  
Ts = 80 °C  
W
W
W
°C  
°C  
T
amb = 25 °C; note 3  
amb = 25 °C; note 4  
2.7  
T
1.15  
+150  
+150  
Tstg  
Tj  
storage temperature  
65  
65  
operating junction temperature  
Source-drain diode  
IS  
source current (DC)  
peak pulsed source current  
Ts = 80 °C  
3  
A
A
ISM  
note 2  
12  
Notes  
1. Ts is the temperature at the soldering point of the drain lead.  
2. Pulse width and duty cycle limited by maximum junction temperature.  
3. Value based on a printed-circuit board with a Rth a-tp (ambient to tie-point) of 27.5 K/W.  
4. Value based on a printed-circuit board with a Rth a-tp (ambient to tie-point) of 90 K/W.  
MGD381  
MGD382  
2
10  
10  
handbook, halfpage  
handbook, halfpage  
P
tot  
(W)  
I
D
(A)  
8
t
p =  
10 µs  
10  
(1)  
100 µs  
6
4
2
1 ms  
DC  
δ =  
10 ms  
t
p
1  
P
T
100 ms  
t
t
p
T
1  
0
0
10  
10  
50  
100  
150  
200  
1  
2
o
1  
10  
10  
T
( C)  
s
V
(V)  
DS  
δ = 0.01; TS = 80 °C.  
(1) RDSon limitation  
.
Fig.2 Power derating curve.  
Fig.3 SOAR.  
1997 Jun 18  
3
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
THERMAL CHARACTERISTICS  
SYMBOL  
Rth j-s  
PARAMETER  
VALUE  
UNIT  
thermal resistance from junction to soldering point  
17.5  
K/W  
MGD392  
2
10  
R
th j-s  
(K/W)  
δ =  
0.75  
10  
0.5  
0.33  
0.2  
0.1  
1
1  
2  
0.05  
0.02  
0.01  
t
p
P
δ =  
T
10  
10  
0
t
t
p
T
6  
5  
4  
3  
2  
1  
10  
10  
10  
10  
10  
10  
1
t
(s)  
p
Fig.4 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.  
1997 Jun 18  
4
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
30  
TYP.  
MAX. UNIT  
V(BR)DSS drain-source breakdown voltage  
VGS = 0; ID = 10 µA  
VGS = VDS; ID = 1 mA  
VGS = 0; VDS = 24 V  
VGS = ±20 V; VDS = 0  
VGS = 4.5 V; ID = 1.25 A  
V
VGSth  
IDSS  
gate-source threshold voltage  
drain-source leakage current  
gate leakage current  
1  
2.8  
100  
±100  
0.15  
0.09  
V
nA  
nA  
IGSS  
RDSon  
drain-source on-state resistance  
V
GS = 10 V; ID = 2.5 A  
Ciss  
Coss  
Crss  
QG  
input capacitance  
VGS = 0; VDS = 24 V; f = 1 MHz  
VGS = 0; VDS = 24 V; f = 1 MHz  
VGS = 0; VDS = 24 V; f = 1 MHz  
825  
350  
150  
30  
pF  
pF  
pF  
nC  
output capacitance  
reverse transfer capacitance  
total gate charge  
VGS = 10 V; VDD = 15 V;  
ID = 2.5 A  
40  
QGS  
QGD  
gate-source charge  
gate-drain charge  
VGS = 10 V; VDD = 15 V;  
ID = 2.5 A  
3
nC  
nC  
VGS = 10 V; VDD = 15 V;  
ID = 2.5 A  
12  
Switching times (see Fig.11)  
td(on)  
tf  
turn-on delay time  
fall time  
VGS = 0 to 10 V; VDD = 15 V;  
ID = 1 A; RL = 15 ; Rgen = 6 Ω  
7
ns  
ns  
ns  
ns  
ns  
ns  
10  
17  
60  
40  
100  
ton  
turn-on switching time  
turn-off delay time  
rise time  
35  
td(off)  
tr  
VGS = 10 to 0 V; VDD = 15 V;  
ID = 1 A; RL = 15 ; Rgen = 6 Ω  
toff  
turn-off switching time  
200  
Source-drain diode  
VSD  
trr  
source-drain forward voltage  
reverse recovery time  
VGD = 0; IS = 1.25 A  
1.3  
V
IS = 1.25 A; di/dt = 100 A/µs  
70  
ns  
1997 Jun 18  
5
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
MGD386  
MGD384  
10  
24  
handbook, halfpage  
handbook, halfpage  
I
D
(A)  
20  
V
GS  
(V)  
8  
V
=
GS  
10 V  
7.5 V  
5 V  
16  
6  
4  
4 V  
12  
8  
3.5 V  
2  
4  
3 V  
2.5 V  
0
0
0
0
5  
10  
15  
20  
25  
Q
30  
(nC)  
2  
4  
6  
8  
10  
(V)  
V
DS  
g
VDD = 15 V: ID = 2.5 A.  
Tj = 25 °C.  
Fig.5 Gate-source voltage as a function of total  
gate charge; typical values.  
Fig.6 Output characteristics; typical values.  
MGD387  
MGD385  
20  
20  
handbook, halfpage  
handbook, halfpage  
I
I
D
SD  
(A)  
(A)  
16  
16  
12  
8  
4  
0
12  
8  
4  
(1) (2)  
(3)  
0
0
0
2  
4  
6  
8  
0.4  
0.8  
1.2  
1.6  
2.0  
V
2.4  
(V)  
V
(V)  
GS  
SD  
VGD = 0.  
(1) Tj = 150 °C.  
(2) Tj = 25 °C.  
(3) Tj = 65 °C.  
VDS = 10 V; Tj = 25 °C.  
Fig.8 Source current as a function of source-drain  
diode forward voltage; typical values.  
Fig.7 Transfer characteristics; typical values.  
1997 Jun 18  
6
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
MGD383  
MGD388  
3
10  
2500  
handbook, halfpage  
handbook, halfpage  
(1)  
(2)  
(3)  
C
(pF)  
R
(4)  
(5)  
(6)  
DSon  
(m)  
2000  
1500  
1000  
2
10  
C
iss  
500  
C
oss  
C
rss  
0
0
10  
0
2  
4  
6  
8  
V
10  
(V)  
8  
16  
24  
V
(V)  
DS  
GS  
VDS ID × RDSon; Tj = 25 °C.  
(1) ID = 100 mA.  
(2) ID = 500 mA.  
(3) ID = 1.25 A.  
(4) ID = 2.5 A.  
(5) ID = 5 A.  
(6) ID = 7 A.  
VGS = 0; f = 1 MHz; Tj = 25 °C.  
Fig.9 Drain source on-state resistance as a  
function of gate-source voltage; typical  
values.  
Fig.10 Capacitance as a function of drain-source  
voltage; typical values.  
0
10 %  
V  
DD  
V
in  
90 %  
R
L
V
0
out  
10 %  
10 %  
V
out  
V
in  
90 %  
90 %  
t
t
d(on)  
t
d(off)  
t
t
t
f
r
MGD391  
on  
off  
Fig.11 Switching times test circuit and input and output waveforms.  
7
1997 Jun 18  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
MGD389  
MGD390  
1.4  
1.8  
handbook, halfpage  
handbook, halfpage  
k
k
(1)  
(2)  
1.2  
1.4  
1.0  
0.8  
0.6  
1.0  
0.6  
75  
75  
25  
25  
75  
125  
175  
25  
25  
75  
125  
175  
o
o
T ( C)  
T ( C)  
j
j
RDSon at Tj  
k =  
-----------------------------------------  
RDSon at 25 °C  
VGSth at Tj  
k =  
--------------------------------------  
RDSon at:  
VGSth at 25°C  
(1) VGS = 10 V; ID = 2.5 A.  
(2) VGS = 4.5 V; ID = 1.25 A.  
VGSth at VDS =VGS ; ID = 1 mA.  
Fig.12 Temperature coefficient of gate-source  
threshold voltage as a function of junction  
temperature; typical values.  
Fig.13 Temperature coefficient of drain-source  
on-resistance as a function of junction  
temperature; typical values.  
1997 Jun 18  
8
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
PACKAGE OUTLINE  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.050  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
97-05-22  
SOT96-1  
076E03S  
MS-012AA  
1997 Jun 18  
9
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
DEFINITIONS  
Data Sheet Status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1997 Jun 18  
10  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
PHP109  
NOTES  
1997 Jun 18  
11  
Philips Semiconductors – a worldwide company  
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Middle East: see Italy  
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,  
Internet: http://www.semiconductors.philips.com  
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1997  
SCA54  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
137107/00/02/pp12  
Date of release: 1997 Jun 18  
Document order number: 9397 750 02384  

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NXP

PHP110NQ06LT,127

TRANSISTOR 75 A, 55 V, 0.0093 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, PLASTIC, SC-46, 3 PIN, FET General Purpose Power
NXP

PHP110NQ08LT

N-channel TrenchMOS logic level FET
NXP

PHP110NQ08LT,127

PHP110NQ08LT
NXP

PHP110NQ08T

N-channel TrenchMOS standard level FET
NXP