PHP125N06LT [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | PHP125N06LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总9页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
VDSS = 55 V
d
s
ID = 75 A
R
DS(ON) ≤ 8 mΩ (VGS = 5 V)
g
R
DS(ON) ≤ 7 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB125N06LT is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
PIN
DESCRIPTION
tab
tab
1
2
gate
drain 1
3
source
drain
2
tab
1
3
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
55
55
± 13
75
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
75
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
240
250
175
- 55
March 1998
1
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
0.6
K/W
Rth j-a
Thermal resistance junction SOT78 package, in free air
to ambient SOT404 package, pcb mounted, minimum
60
50
-
-
K/W
K/W
footprint
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge
capacitor voltage, all pins
Human body model (100 pF, 1.5 kΩ)
-
2
kV
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
V(BR)GSS
VGS(TO)
Drain-source breakdown
voltage
Gate-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA;
55
50
10
-
-
-
-
-
-
V
V
V
Tj = -55˚C
IG = ±1 mA;
Gate threshold voltage
VDS = VGS; ID = 1 mA
1.0
0.5
-
-
-
-
10
-
-
-
1.5
-
-
6.5
4.9
-
45
0.02
-
2.0
-
2.3
8
7
17
-
1
20
10
500
V
V
V
Tj = 175˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
Tj = 175˚C
gfs
IGSS
Forward transconductance
Gate source leakage current VGS = ±5 V; VDS = 0 V
VDS = 25 V; ID = 25 A
Tj = 175˚C
Tj = 175˚C
IDSS
Zero gate voltage drain
current
VDS = 55 V; VGS = 0 V;
0.05
-
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 50 A; VDD = 44 V; VGS = 5 V
-
-
-
84
18
39
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
-
-
-
45
60
ns
ns
ns
ns
120
225
100
170
300
135
Ld
Ld
Internal drain inductance
Internal drain inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
-
-
3.5
4.5
-
-
nH
nH
Ls
Internal source inductance
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
5200 6900
840 1000
pF
pF
pF
350
480
March 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
75
A
A
ISM
VSD
240
IF = 25 A; VGS = 0 V
IF = 75 A; VGS = 0 V
-
-
0.85
1.0
1.2
-
V
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 75 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
65
0.18
-
-
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
500
UNIT
WDSS
Drain-source non-repetitive ID = 75 A; VDD ≤ 25 V; VGS = 5 V;
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy
-
mJ
Normalised Power Derating
PD%
Current Derating
ID (A)
120
150
125
110
100
90
80
70
60
50
40
30
20
10
0
Limited by package
100
75
50
25
0
0
20
40
60
80
Tmb /
100 120 140 160 180
C
0
20
40
60
80
Tmb /
100 120 140 160 180
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
March 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
RDS(ON) / mOhm
3.4
15
10
5
1000
VGS / V =
3
3.2
ID / A
3.6
RDS(ON) = VDS/ID
100
tp = 10 us
100 us
4
5
1 ms
10
DC
10 ms
10
100 ms
0
11
0
20
40
60
ID / A
80
100
120
10
100
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Zth / (K/W)
1E+00
100
ID/A
80
60
40
0.5
1E-01
0.2
0.1
0.05
t
T
p
tp
P
0.02
D =
D
Tj/C =
175
25
1E-02
20
0
0
t
T
1E-03
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
0
1
2
3
4
VGS/V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Drain current, ID (A)
Transconductance, gfs (S)
120
100
80
60
40
20
0
10
3.4
4.0
110
100
90
80
70
60
50
40
30
20
10
0
VGS = 3.2 V
3.0
2.8
2.6
2.4
2.2
0
20
40
60
80
100
0
2
4
6
8
10
Drain-source voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
March 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
12
10
8
Rds(on) normlised to 25degC
a
2.5
2
1.5
1
6
Ciss
hTuonad(spF)
4
2
0.5
-100
Coss
Crss
100
-50
0
50
Tmb / degC
100
150
200
0
VDS/V
0.01
0.1
1
10
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6
VGS(TO) / V
max.
2.5
2
VGS/V
5
VDS = 14V
VDS = 44V
4
3
2
1
0
typ.
1.5
1
min.
0.5
0
0
10
20
30
40
50
QG/nC
60
70
80
90
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
100
IF/A
80
Sub-Threshold Conduction
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
60
2%
typ
98%
Tj/C = 175
25
40
20
0
0
0.2
0.4
0.6
VSDS/V
0.8
1
1.2
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
March 1998
5
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
WDSS%
120
VDD
110
100
90
80
70
60
50
40
30
20
10
0
+
L
VDS
-
VGS
0
-ID/100
T.U.T.
R 01
RGS
shunt
20
40
60
80
100
120
140
160
180
Tmb /
C
Fig.16. Avalanche energy test circuit.
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
)
March 1998
6
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
March 1998
7
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
March 1998
8
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP125N06LT, PHB125N06LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
March 1998
9
Rev 1.400
相关型号：
©2020 ICPDF网 联系我们和版权申明