PHP12N10E [NXP]

PowerMOS transistor; 功率MOS晶体管
PHP12N10E
型号: PHP12N10E
厂家: NXP    NXP
描述:

PowerMOS transistor
功率MOS晶体管

晶体 晶体管
文件: 总7页 (文件大小:76K)
中文:  中文翻译
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Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode  
field-effect power transistor in a  
plastic envelope. The device is  
intended for use in Switched Mode  
Power Supplies (SMPS), motor  
control, welding, DC/DC and AC/DC  
converters, and in general purpose  
switching applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Junction temperature  
Drain-source on-state resistance  
100  
14  
V
A
W
˚C  
Ptot  
Tj  
75  
175  
0.16  
RDS(ON)  
PINNING - TO220AB  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
tab  
gate  
2
drain  
g
3
source  
tab drain  
1 2 3  
s
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
Drain-source voltage  
-
-
100  
100  
30  
V
V
Drain-gate voltage  
RGS = 20 kΩ  
-
Gate-source voltage  
Drain current (DC)  
Drain current (DC)  
Drain current (pulse peak value)  
Total power dissipation  
Storage temperature  
Junction Temperature  
-
-
V
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
-
-
14  
A
ID  
-
10  
A
IDM  
Ptot  
Tstg  
Tj  
-
56  
A
-
- 55  
-
75  
W
˚C  
˚C  
175  
175  
-
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
Rth j-mb  
Rth j-a  
Thermal resistance junction to  
-
-
-
2
-
K/W  
K/W  
mounting base  
Thermal resistance junction to  
ambient  
60  
September 1997  
1
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
STATIC CHARACTERISTICS  
Tj = 25 ˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
Drain-source breakdown  
voltage  
VGS = 0 V; ID = 0.25 mA  
100  
-
-
V
VGS(TO)  
Gate threshold voltage  
VDS = VGS; ID = 1 mA  
2.1  
3.0  
1
4.0  
10  
1.0  
100  
0.16  
V
µA  
mA  
nA  
IDSS  
Zero gate voltage drain current VDS = 100 V; VGS = 0 V; Tj = 25 ˚C  
Zero gate voltage drain current VDS = 100 V; VGS = 0 V; Tj = 125 ˚C  
Gate source leakage current  
Drain-source on-state  
resistance  
-
-
-
-
IDSS  
0.1  
10  
IGSS  
VGS = ±30 V; VDS = 0 V  
VGS = 10 V; ID = 5 A  
RDS(ON)  
0.15  
DYNAMIC CHARACTERISTICS  
Tj = 25 ˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
gfs  
Forward transconductance  
VDS = 25 V; ID = 5 A  
4.0  
5.5  
-
S
Ciss  
Coss  
Crss  
Input capacitance  
Output capacitance  
Feedback capacitance  
VGS = 0 V; VDS = 25 V; f = 1 MHz  
-
-
-
660  
140  
60  
825  
200  
100  
pF  
pF  
pF  
td on  
tr  
td off  
tf  
Turn-on delay time  
Turn-on rise time  
Turn-off delay time  
Turn-off fall time  
VDD = 30 V; ID = 3 A;  
VGS = 10 V; RGS = 50 ;  
Rgen = 50 Ω  
-
-
-
-
10  
25  
60  
40  
20  
40  
90  
55  
ns  
ns  
ns  
ns  
Ld  
Ld  
Ls  
Internal drain inductance  
Internal drain inductance  
Internal source inductance  
Measured from contact screw on  
tab to centre of die  
Measured from drain lead 6 mm  
from package to centre of die  
Measured from source lead 6 mm  
from package to source bond pad  
-
-
-
3.5  
4.5  
7.5  
-
-
-
nH  
nH  
nH  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25 ˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
IDR  
Continuous reverse drain  
-
-
-
14  
A
current  
IDRM  
VSD  
Pulsed reverse drain current  
Diode forward voltage  
-
-
-
-
56  
1.5  
A
V
IF = 14 A ; VGS = 0 V  
1.2  
trr  
Qrr  
Reverse recovery time  
Reverse recovery charge  
IF = 14 A; -dIF/dt = 100 A/µs;  
VGS = 0 V; VR = 30 V  
-
-
90  
0.6  
-
-
ns  
µC  
AVALANCHE LIMITING VALUE  
Tmb = 25 ˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
WDSS  
Drain-source non-repetitive  
unclamped inductive turn-off  
energy  
ID = 14 A ; VDD 50 V; VGS = 10 V ;  
RGS = 50Ω  
-
-
70  
mJ  
September 1997  
2
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
Normalised Power Derating  
PD%  
120  
Zth j-mb / (K/W)  
1E+01  
1E+00  
1E-01  
1E-02  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.5  
0.2  
0.1  
0.05  
t
p
t
P
0.02  
p
D =  
D
T
0
t
T
0
20  
40  
60  
80  
Tmb /  
100 120 140 160 180  
C
1E-07  
1E-05  
1E-03  
t / s  
1E-01  
1E+01  
Fig.1. Normalised power dissipation.  
PD% = 100 PD/PD 25 ˚C = f(Tmb)  
Fig.4. Transient thermal impedance.  
Zth j-mb = f(t); parameter D = tp/T  
Normalised Current Derating  
ID%  
ID / A  
10  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
28  
24  
20  
16  
12  
8
20  
VGS / V =  
15  
8
7
6
5
4
4
0
0
20  
40  
60  
80  
100 120 140 160 180  
0
2
4
6
8
10  
Tmb /  
C
VDS / V  
Fig.2. Normalised continuous drain current.  
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS 10 V  
Fig.5. Typical output characteristics, Tj = 25 ˚C.  
ID = f(VDS); parameter VGS  
ID / A  
tp = 10 us  
RDS(ON) / Ohm  
100  
10  
1
1.0  
0.8  
0.6  
0.4  
0.2  
0
A
B
5
5.5  
6
VGS / V =  
4.5  
6.5  
RDS(ON) = VDS/ID  
100 us  
1 ms  
7
7.5  
DC  
10 ms  
100 ms  
8
10  
20  
0.1  
1
10  
100  
0
4
8
12  
16  
20  
24  
28  
VDS / V  
ID / A  
Fig.3. Safe operating area. Tmb = 25 ˚C  
ID & IDM = f(VDS); IDM single pulse; parameter tp  
Fig.6. Typical on-state resistance, Tj = 25 ˚C.  
RDS(ON) = f(ID); parameter VGS  
September 1997  
3
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
VGS(TO) / V  
ID / A  
28  
max.  
4
3
2
1
0
24  
Tj / C =  
25  
150  
typ.  
20  
16  
12  
8
min.  
4
0
-60  
-20  
20  
60  
Tj /  
100  
140  
180  
0
2
4
6
8
10  
C
VGS / V  
Fig.7. Typical transfer characteristics.  
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj  
Fig.10. Gate threshold voltage.  
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS  
SUB-THRESHOLD CONDUCTION  
ID / A  
gfs / S  
1E-01  
1E-02  
1E-03  
1E-04  
1E-05  
1E-06  
7
6
5
4
3
2
1
0
2 %  
typ  
98 %  
0
1
2
3
4
0
4
8
12  
16  
20  
24  
28  
VGS / V  
ID / A  
Fig.8. Typical transconductance, Tj = 25 ˚C.  
gfs = f(ID); conditions: VDS = 25 V  
Fig.11. Sub-threshold drain current.  
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS  
Normalised RDS(ON) = f(Tj)  
a
C / pF  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
10000  
1000  
100  
Ciss  
Coss  
Crss  
10  
-60  
-20  
20  
60  
Tj /  
100  
140  
180  
0
20  
40  
C
VDS / V  
Fig.9. Normalised drain-source on-state resistance.  
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 10 V  
Fig.12. Typical capacitances, Ciss, Coss, Crss.  
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz  
September 1997  
4
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
WDSS%  
VGS / V  
12  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VDS / V =20  
80  
10  
8
6
4
2
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
0
2
4
6
8
10  
12  
14  
16  
Tmb /  
C
QG / nC  
Fig.13. Typical turn-on gate-charge characteristics.  
VGS = f(QG); conditions: ID = 14 A; parameter VDS  
Fig.15. Normalised avalanche energy rating.  
WDSS% = f(Tmb); conditions: ID = 14 A  
IF / A  
30  
20  
10  
0
VDD  
+
L
VDS  
-
VGS  
-ID/100  
T.U.T.  
0
Tj / C = 150  
25  
R 01  
RGS  
shunt  
0
1
2
VSDS / V  
Fig.16. Avalanche energy test circuit.  
WDSS = 0.5 LID2 BVDSS/(BVDSS VDD  
Fig.14. Typical reverse diode current.  
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj  
)
September 1997  
5
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
MECHANICAL DATA  
Dimensions in mm  
Net Mass: 2 g  
4,5  
max  
10,3  
max  
1,3  
3,7  
2,8  
5,9  
min  
15,8  
max  
3,0 max  
not tinned  
3,0  
13,5  
min  
1,3  
1 2 3  
max  
(2x)  
0,9 max (3x)  
0,6  
2,4  
2,54 2,54  
Fig.17. TO220AB; pin 2 connected to mounting base.  
Notes  
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent  
damage to MOS gate oxide.  
2. Refer to mounting instructions for TO220 envelopes.  
3. Epoxy meets UL94 V0 at 1/8".  
September 1997  
6
Rev 1.000  
Philips Semiconductors  
Product Specification  
PowerMOS transistor  
PHP12N10E  
DEFINITIONS  
Data sheet status  
Objective specification  
This data sheet contains target or goal specifications for product development.  
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.  
Product specification  
This data sheet contains final product specifications.  
Limiting values  
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and  
operation of the device at these or at any other conditions above those given in the Characteristics sections of  
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
Philips Electronics N.V. 1997  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the  
copyright owner.  
The information presented in this document does not form part of any quotation or contract, it is believed to be  
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under patent or other  
industrial or intellectual property rights.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices or systems where malfunction of these  
products can be reasonably expected to result in personal injury. Philips customers using or selling these products  
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting  
from such improper use or sale.  
September 1997  
7
Rev 1.000  

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