PHX1N40E [NXP]
PowerMOS transistor Isolated version of PHP2N40E; PHP2N40E的功率MOS晶体管隔离版本
| 型号： | PHX1N40E |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Isolated version of PHP2N40E |
| 文件： | 总5页 (文件大小：26K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Objective specification
PowerMOS transistor
Isolated version of PHP2N40E
PHX1N40E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
field-effect power transistor in a full
pack, plastic envelope featuring high
avalanche energy capability, stable
blocking voltage, fast switching and
high thermal cycling performance
withlowthermalresistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
400
1.75
25
V
A
W
Ω
Ptot
RDS(ON)
3.5
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
case
gate
2
drain
g
3
source
case isolated
1
2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
Drain-source voltage
-
-
-
-
-
-
400
400
30
V
V
V
A
A
A
Drain-gate voltage
Gate-source voltage
Drain current (DC)
RGS = 20 kΩ
Ths = 25 ˚C
Ths = 100 ˚C
Ths = 25 ˚C
1.75
1.1
IDM
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
7.0
IDR
Ths = 25 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
-
-
1.75
7.0
A
A
IDRM
Ptot
Tstg
Tj
-
-55
-
25
150
150
W
˚C
˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
WDSS
Drain-source non-repetitive ID = 2.5 A ; VDD ≤ 50 V ; VGS = 10 V ;
unclamped inductive turn-off RGS = 50 Ω
energy
Tj = 25˚C prior to surge
Tj = 100˚C prior to surge
-
-
-
120
20
3.6
mJ
mJ
mJ
1
WDSR
Drain-source repetitive
ID = 2.5 A ; VDD ≤ 50 V ;
unclamped inductive turn-off VGS = 10 V ; RGS= 50 Ω ; Tj ≤ 150 ˚C
energy
1. Pulse width and frequency limited by Tj(max)
November 1996
1
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHX1N40E
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol
Cisol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
-
2500
V
three terminals to external
heatsink
waveform;
R.H. ≤ 65% ; clean and dustfree
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-hs
Rth j-a
Thermal resistance junction to with heatsink compound
-
-
-
5
-
K/W
K/W
heatsink
Thermal resistance junction to
ambient
55
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
400
-
-
V
VGS(TO)
IDSS
Gate threshold voltage
Drain-source leakage current
VDS = VGS; ID = 0.25 mA
VDS = 400 V; VGS = 0 V; Tj = 25 ˚C
2.0
3.0
10
4.0
100
1.0
100
3.5
V
µA
mA
nA
Ω
-
-
-
-
V
DS = 320 V; VGS = 0 V; Tj = 125 ˚C
0.1
10
IGSS
RDS(ON)
Gate-source leakage current
Drain-source on-state
resistance
Source-drain diode forward
voltage
VGS = ±30 V; VDS = 0 V
VGS = 10 V; ID = 1.25 A
3.1
VSD
IF = 2.5 A ;VGS = 0 V
-
1.4
2.0
V
November 1996
2
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHX1N40E
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 15 V; ID = 1.25 A
VGS = 0 V; VDS = 25 V; f = 1 MHz
0.5
0.9
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
225
30
6.0
315
42
12
pF
pF
pF
Qg(tot)
Qgs
Qgd
Total gate charge
Gate to source charge
Gate to drain (Miller) charge
VGS = 10 V; ID = 2.5 A; VDS = 320 V
-
-
-
12
2
6
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 2.2 A;
VGS = 10 V; RGS = 50 Ω;
RGEN = 50 Ω
-
-
-
-
10
30
30
20
15
45
40
30
ns
ns
ns
ns
trr
Source-drain diode reverse
recovery time
Source-drain diode reverse
recovery charge
IF = 2.5 A; -dIF/dt = 100 A/µs;
-
-
350
2.5
-
-
ns
Qrr
VGS = 0 V; VR = 100 V
µC
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
4.5
7.5
-
-
nH
nH
November 1996
3
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHX1N40E
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
6.4
2.5
0.8 max. depth
15.8
max
seating
plane
15.8
max.
19
max.
3 max.
not tinned
3
2.5
13.5
min.
1
2
3
M
0.4
1.0 (2x)
0.6
2.5
0.9
0.7
2.54
0.5
5.08
1.3
Fig.1. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
November 1996
4
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHX1N40E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1996
5
Rev 1.000
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