PHX2N50 [PHILIPS]
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET,;型号: | PHX2N50 |
厂家: | PHILIPS SEMICONDUCTORS |
描述: | Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET, 局域网 开关 脉冲 晶体管 |
文件: | 总7页 (文件大小:53K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
field-effect power transistor in an
isolated plastic envelope featuring
high avalanche energy capability,
stable off-state characteristics, fast
switching and high thermal cycling
performance. The isolated envelope
eliminates the need for additional
insulating hardware. These devices
are intended for use in Switched
Mode Power Supplies (SMPS),
motor control circuits and general
purpose switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
500
2.1
30
3
V
A
W
Ω
Ptot
RDS(ON)
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
case
gate
2
drain
g
3
source
case isolated
1
2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
ID
Continuous drain current
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
-
-
-
-
-
-
-
2.1
1.3
A
A
IDM
PD
Pulsed drain current
Total dissipation
8.4
A
Ths = 25 ˚C
30
W
∆PD/∆Tmb Linear derating factor
Ths > 25 ˚C
0.244
± 30
110
W/K
V
VGS
EAS
Gate-source voltage
Single pulse avalanche
energy
V
DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
mJ
IAS
Peak avalanche current
V
-
2.1
A
Tj, Tstg
Operating junction and
storage temperature range
- 55
150
˚C
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol
Cisol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
-
2500
V
three terminals to external
heatsink
waveform;
R.H. ≤ 65% ; clean and dustfree
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
May 1997
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-hs
Rth j-a
Thermal resistance junction to with heatsink compound
-
-
-
4.1
-
K/W
K/W
heatsink
Thermal resistance junction to
ambient
55
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
500
-
-
-
-
V
∆V(BR)DSS
∆Tj
/
Drain-source breakdown
voltage temperature coefficient
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current
VDS = VGS; ID = 0.25 mA
0.6
V/K
RDS(ON)
VGS(TO)
gfs
VGS = 10 V; ID = 1.3 A
VDS = VGS; ID = 0.25 mA
VDS = 30 V; ID = 1.3 A
VDS = 500 V; VGS = 0 V
VDS = 400 V; VGS = 0 V; Tj = 125 ˚C
VGS = ±30 V; VDS = 0 V
-
2.0
1
2.5
3.0
2
1
30
10
3
4.0
-
25
250
200
Ω
V
S
µA
µA
nA
IDSS
-
-
IGSS
Gate-source leakage current
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2.1 A; VDD = 400 V; VGS = 10 V
-
-
-
26
2
13
30
3
17
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 250 V; ID = 2.1 A;
RG = 18 Ω; RD = 100 Ω
-
-
-
-
10
29
66
32
-
-
-
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
4.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
310
50
28
-
-
-
pF
pF
pF
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
Ths = 25˚C
-
-
2.1
A
(body diode)
ISM
Pulsed source current (body
diode)
Diode forward voltage
Ths = 25˚C
-
-
8.4
A
VSD
trr
IS = 2.1 A; VGS = 0 V
-
-
-
1.2
-
V
Reverse recovery time
IS = 2.1 A; VGS = 0 V;
dI/dt = 100 A/µs
370
ns
Qrr
Reverse recovery charge
-
2.7
-
µC
May 1997
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
Normalised Power Derating
with heatsink compound
PD%
120
Zth j-hs, Transient thermal impedance (K/W)
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D = 0.5
0.2
0.1
0.05
0.02
0.1
t
T
p
t
P
p
D =
single pulse
D
0.01
t
T
0.001
1us
10us
100us
1ms
1s
10ms
100ms
0
20
40
60
80
Ths /
100
120
140
C
tp, pulse width (s)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ths)
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID, Drain current (Amps)
Tj = 25 C
8
7
6
5
4
3
2
1
0
120
110
100
90
80
70
60
50
40
30
20
10
0
with heatsink compound
10 V
7 V
6 V
5.5 V
5 V
VGS = 4.5 V
0
20
40
60
80
Ths /
100
120
140
0
5
10
15
20
25
30
VDS, Drain-Source voltage (Volts)
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
ID, Drain current (Amps)
10 V
RDS(on), Drain-Source on resistance (Ohms)
100
10
6
VGS = 6 V
5 V
5.5 V
4.5 V
5
4
3
2
1
0
7 V
Tj = 25 C
tp = 10 us
RDS(ON) = VDS/ID
DC
100 us
1
1 ms
10 ms
0.1
0.01
100 ms
1
10
100
1000
10000
0
1
2
3
4
5
6
7
8
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
May 1997
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
VGS(TO) / V
Tj = 25 C
ID, Drain current (Amps)
8
VDS = 30 V
7
max.
4
3
2
1
0
6
5
4
3
2
1
0
typ.
Tj = 150 C
min.
-60 -40 -20
0
20
40
60
80 100 120 140
0
2
4
6
8
10
VGS, Gate-Source voltage (Volts)
Tj /
C
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
gfs, Transconductance (S)
VDS = 30 V
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
3
2.5
2
2 %
typ
98 %
1.5
1
150 C
Tj = 25 C
0.5
0
0
1
2
3
4
0
1
2
3
4
5
6
7
8
ID, Drain current (A)
VGS / V
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
Junction capacitances (pF)
1000
100
10
Ciss
2
1
0
Coss
Crss
1
-60 -40 -20
0
20 40 60 80 100 120 140
1
10
100
1000
Tj /
C
VDS, Drain-Source voltage (Volts)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 2.1 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
May 1997
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
IF, Source-Drain diode current (Amps)
VGS = 0 V
VGS, Gate-Source voltage (Volts)
20
15
10
5
15
ID = 2.1 A
240 V
100 V
Tj = 25 C
VDD = 400 V
10
5
150 C
Tj = 25 C
0
0
0
10
20
Qg, Gate charge (nC)
30
40
0
0.5
1
1.5
VSDS, Source-Drain voltage (Volts)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
120
Switching times (ns)
1000
100
10
VDD = 250 V
VGS = 10 V
RD = 100 Ohms
ID = 2.1 A
Tj = 25 C
110
100
90
80
70
60
50
40
30
20
10
0
td(off)
tf
tr
td(on)
1
0
10
20
30
40
50
60
20
40
60
80
100
120
140
RG, Gate resistance (Ohms)
Starting Tj ( C)
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
1.15
1.1
VDD
V(BR)DSS @ 25 C
+
L
1.05
1
VDS
-
VGS
-ID/100
T.U.T.
0
0.95
0.9
R 01
RGS
shunt
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.18. Unclamped inductive test circuit.
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
EAS = 0.5 LID2 V(BR)DSS/(V(BR)DSS − VDD
)
May 1997
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
6.4
2.5
0.8 max. depth
15.8
max
seating
plane
15.8
max.
19
max.
3 max.
not tinned
3
2.5
13.5
min.
1
2
3
M
0.4
1.0 (2x)
0.6
2.5
0.9
0.7
2.54
0.5
5.08
1.3
Fig.19. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
May 1997
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHX2N50
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
May 1997
7
Rev 1.000
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