PHX3055E [NXP]
N-channel TrenchMOS transistor; N沟道晶体管的TrenchMOS
| 型号： | PHX3055E |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS transistor |
| 文件： | 总8页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Low on-state resistance
• Fast switching
VDSS = 55 V
ID = 9 A
• Isolated mounting tab
g
RDS(ON) ≤ 150 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
PINNING
SOT186A
N-channel enhancement mode,
field-effect power transistor in a
plastic envelope with an electrically
isolated mounting tab. The device
uses’trench’technologytoachieve
low on-state resistance.
PIN
DESCRIPTION
case
1
2
gate
drain
3
source
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
tab
isolated
1
2 3
The PHX3055E is supplied in the
SOT186A (isolated TO220AB)
conventional leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
55
55
± 20
9
5.6
36
21
V
V
V
A
A
A
W
˚C
Ths = 25 ˚C
Ths = 100 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
- 55
150
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
-
2500
V
three terminals to external
heatsink
waveform;
R.H. ≤ 65% ; clean and dustfree
Cisol
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 3.3 A;
tp = 220 µs; Tj prior to avalanche = 25˚C;
-
25
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:15
IAS
Peak non-repetitive
avalanche current
-
9
A
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-hs
Thermal resistance junction
to heatsink
-
6
K/W
Rth j-a
Thermal resistance junction
to ambient
55
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
55
50
2.0
1.1
-
-
-
-
-
V
V
V
V
V
voltage
Tj = -55˚C
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
3.0
-
-
4.0
-
6
Tj = 150˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current VGS = ±10 V; VDS = 0 V
Zero gate voltage drain
current
VGS = 10 V; ID = 5.5 A
VDS = 25 V; ID = 5.5 A
-
-
120
210
3.2
10
0.05
-
150
263
-
100
10
100
mΩ
mΩ
S
nA
µA
µA
Tj = 150˚C
gfs
IGSS
IDSS
1.5
-
-
VDS = 55 V; VGS = 0 V;
Tj = 150˚C
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 10 A; VDD = 44 V; VGS = 10 V
-
-
-
5.8
1.5
3.2
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 2.7 Ω;
RG = 5.6 Ω; VGS = 10 V
Resistive load
-
-
-
-
3
26
8
10
35
15
20
ns
ns
ns
ns
10
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
4.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
190
55
40
250
80
50
pF
pF
pF
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
-
9
A
A
V
ISM
36
VSD
IF = 10 A; VGS = 0 V
1.1
1.5
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 10 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
32
50
-
-
ns
nC
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
Transient thermal impedance, Zth j-hs (K/W)
Normalised Power Derating, PD (%)
100
10
90
80
70
60
50
40
30
20
10
0
D = 0.5
0.2
1
0.1
P
0.05
0.02
D = tp/T
D
tp
single pulse
T
0.1
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00 1E+01
0
25
50
75
100
125
150
Pulse width, tp (s)
Heatsink temperature, Ths (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ths)
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
Drain Current, ID (A)
Tj = 25 C
15
14
13
12
11
10
9
8
7
6
5
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
VGS = 10V
8 V
7 V
6.5 V
6 V
5.5 V
5 V
4
3
2
1
4.5 V
0
0
25
50
75
100
125
150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Heatsink temperature, Ths (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
100
Drain-Source On Resistance, RDS(on) (Ohms)
0.5
5.5V
5 V
Tj = 25 C
RDS(on) = VDS/ ID
0.45
0.4
6 V
tp = 10 us
0.35
0.3
10
6.5 V
0.25
0.2
100 us
7 V
8 V
1 ms
D.C.
1
0.15
0.1
10 ms
100 ms
VGS = 10V
0.05
0
0.1
0
1
2
3
4
5
6
7
8
9
10
1
10
Drain-Source Voltage, VDS (V)
100
Drain Current, ID (A)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
10
4.5
4
VDS > ID X RDS(ON)
9
maximum
8
7
6
5
4
3.5
3
typical
2.5
2
minimum
1.5
1
3
175 C
2
Tj = 25 C
0.5
0
1
0
0
1
2
3
4
5
6
7
8
9
10
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Drain current, ID (A)
4
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
3.5
3
Tj = 25 C
minimum
2.5
2
175 C
typical
1.5
1
maximum
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
7
8
9
10
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.4
2.2
2
Capacitances, Ciss, Coss, Crss (pF)
1000
1.8
1.6
1.4
1.2
1
Ciss
100
Coss
Crss
0.8
0.6
0.4
0.2
0
10
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0.1
1
10
100
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
Gate-source voltage, VGS (V)
15
Maximum Avalanche Current, IAS (A)
100
10
1
ID = 10A
14
13
12
11
10
9
Tj = 25 C
VDD = 11 V
VDD = 44 V
8
7
6
5
4
3
25 C
Tj prior to avalanche = 125 C
2
1
0
0.1
0
1
2
3
4
5
6
7
8
0.001
0.01
0.1
Avalanche time, tAV (ms)
1
10
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
10
VGS = 0 V
9
8
7
6
5
4
3
2
1
0
175 C
Tj = 25 C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Source-Drain Voltage, VSDS (V)
1
1.1 1.2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220
SOT186A
E
P
A
A
1
q
D
1
T
D
j
L
L
2
1
K
Q
b
b
1
L
2
1
2
3
b
w
M
c
e
e
1
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
(1)
(2)
L
A
A
b
b
b
c
D
D
E
e
e
j
K
L
L
1
P
Q
q
T
w
UNIT
mm
2
1
1
2
1
1
max.
1.1
0.9
1.4
1.2
2.7
2.3
0.6 14.4 3.30
0.4 13.5 2.79
2.6
2.3
4.6 2.9
4.0 2.5
0.9
0.7
3.0
2.6
0.7 15.8 6.5 10.3
0.4 15.2 6.3 9.7
3.2
3.0
3
5.08
2.54
2.5
0.4
Notes
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
2. Both recesses are 2.5 × 0.8 max. depth
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-06-11
SOT186A
TO-220
Fig.16. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX3055E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
8
Rev 1.000
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