PIMXRT106FDVN4A_技术文档

Document Number: IMXRT1015CEC

Rev. 2, 03/2021

NXP Semiconductors

Data Sheet: Technical Data

MIMXRT1015DAF5A

i.MX RT1015 Crossover

Processors Data Sheet

for Consumer Products

Package Information

Plastic Package

100-Pin LQFP, 14 x 14 mm, 0.5 mm pitch

Ordering Information

See Table 1 on page 4

1 i.MX RT1015 introduction

The i.MX RT1015 is a processor of i.MX RT family

featuring NXP’s advanced implementation of the Arm

1. i.MX RT1015 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 4

2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1. Special signal considerations . . . . . . . . . . . . . . . 12

3.2. Recommended connections for unused analog

®

Cortex -M7 core, which operates at speeds up to 500

MHz to provide high CPU performance and real-time

response.

The i.MX RT1015 processor has 128 KB on-chip RAM,

which can be flexibly configured as TCM or

interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14

4.2. System power and clocks . . . . . . . . . . . . . . . . . . 20

4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.5. External memory interface . . . . . . . . . . . . . . . . . 36

4.6. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.7. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.8. Communication interfaces . . . . . . . . . . . . . . . . . . 51

4.9. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 57

5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 57

5.2. Boot device interface allocation . . . . . . . . . . . . . . 57

6. Package information and contact assignments . . . . . . . 60

6.1. 14 x 14 mm package information . . . . . . . . . . . . 60

7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

general-purpose on-chip RAM. The i.MX RT1015

integrates advanced power management module with

DCDC and LDO that reduces complexity of external

power supply and simplifies power sequencing. The

i.MX RT1015 also provides various memory interfaces,

including Quad SPI, and a wide range of connectivity

interfaces including UART, SPI, I2C, and USB; for

connecting peripherals including Bluetooth™, and GPS.

The i.MX RT1015 also has rich audio features, including

SPDIF and I2S audio interface. Various analog IP

integration, including ADC, temperature sensor, etc.

NXP reserves the right to change the production detail specifications as may be required

to permit improvements in the design of its products.

i.MX RT1015 introduction

The i.MX RT1015 is specifically useful for applications such as:

•

Industrial

Motor Control

Home Appliance

Audio

IoT

1.1

Features

The i.MX RT1015 processors are based on Arm Cortex-M7 Core™ Platform, which has the following

features:

•

Supports single Arm Cortex-M7 with:

— 16 KB L1 Instruction Cache

— 16 KB L1 Data Cache

— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

— Support the Armv7-M Thumb instruction set

Integrated MPU, up to 16 individual protection regions

Up to 128 KB I-TCM and D-TCM in total

•

Frequency of 500 MHz

Cortex M7 CoreSight™ components integration for debug

Frequency of the core, as per Table 9, "Operating ranges," on page 16.

The SoC-level memory system consists of the following additional components:

— Boot ROM (96 KB)

— On-chip RAM (128 KB)

– Configurable RAM size up to 128 KB shared with CM7 TCM

•

External memory interfaces:

— SPI NOR/NAND FLASH

— Parallel NOR FLASH with XIP support

— Single/Dual channel Quad SPI FLASH with XIP support

Timers and PWMs:

— Two General Programmable Timers

– 4-channel generic 32-bit resolution timer

– Each support standard capture and compare operation

— Four Periodical Interrupt Timers

– Generic 32-bit resolution timer

– Periodical interrupt generation

— One Quad Timer

– 4-channel generic 16-bit resolution timer

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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NXP Semiconductors

i.MX RT1015 introduction

– Each support standard capture and compare operation

– Quadrature decoder integrated

— One FlexPWM

– Up to 8 individual PWM channels

– 16-bit resolution PWM suitable for Motor Control applications

— One Quadrature Encoder/Decoder

Each i.MX RT1015 processor enables the following interfaces to external devices (some of them are

muxed and not available simultaneously):

•

Audio:

— S/PDIF input and output

— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and

codec/DSP interfaces

— MQS interface for medium quality audio via GPIO pads

Connectivity:

•

— One USB 2.0 OTG controller with integrated PHY interface

— Four universal asynchronous receiver/transmitter (UARTs) modules

— Two I2C modules

— Two SPI modules

•

GPIO and Pin Multiplexing:

— General-purpose input/output (GPIO) modules with interrupt capability

— Input/output multiplexing controller (IOMUXC) to provide centralized pad control

— 57 GPIOs

— One FlexIO

The i.MX RT1015 processors integrate advanced power management unit and controllers:

•

Full PMIC integration, including on-chip DCDC and LDOs

Temperature sensor with programmable trip points

GPC hardware power management controller

The i.MX RT1015 processors support the following system debug:

•

Arm CortexM7 CoreSight debug and trace architecture

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse

Security functions are enabled and accelerated by the following hardware:

•

High Assurance Boot (HAB)

Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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3

i.MX RT1015 introduction

•

Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

True random number generation (TRNG)

Secure Non-Volatile Storage (SNVS)

— Secure real-time clock (RTC)

— Zero Master Key (ZMK)

•

Secure JTAG Controller (SJC)

NOTE

The actual feature set depends on the part numbers as described in Table 1.

Functions such as display and camera interfaces, connectivity interfaces,

and security features are not offered on all derivatives.

1.2

Ordering information

Table 1 provides examples of orderable part numbers covered by this data sheet.

Table 1. Ordering information

Junction

Temperature T_j(C)

Part Number

Feature

Features supports:

Package

MIMXRT1015DAF5A

14 x 14 mm, 0.5 mm pitch,

0 to +95

• 500 MHz, consumer grade for general 100-pin LQFP

purpose

• 128K RAM

• USB OTG x1

• SAI x3

• SPDIF x1

• General Purpose Timer x2

• PWM x1

• UART x4

• I²C x2

• SPI x2

• ADC x1

• MQS x1

• FlexIO x1

• QTimer x1

• ENC x1

• DCDC

• TRNG x1

• Quad-SPI x1

• WDOG x4

• Security RTC

• 57 GPIOs

Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be

identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The

primary characteristic which describes which data sheet applies to a specific part is the temperature grade

(junction) field.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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NXP Semiconductors

i.MX RT1015 introduction

Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field

and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or

contact an NXP representative for details.

M

IMX X X

@

##

%

+

VV

$

A

Qualification Level

M

Silicon Rev

A

B

Prototype Samples

Mass Production

Special

P

M

S

A0

A1

Core Frequency

400 MHz

$

4

5

6

Part # series

XX

i.MX RT

RT

500 MHz

@

1

Family

600 MHz

First Generation RT family

Reserved

Package Type

VV

2-8

225MAPBGA, 13 x 13 mm, 0.8 mm pitch

VN

Sub-Family

RT101x

##

196MAPBGA, 12 x 12 mm, 0.8 mm pitch

196MAPBGA, 10 x 10 mm, 0.65 mm pitch

169MAPBGA, 11 x 11 mm, 0.8 mm pitch

169MAPBGA, 9 x 9 mm, 0.65 mm pitch

144LQFP, 20 x 20 mm, 0.5 mm pitch

100LQFP, 14 x 14 mm, 0.5 mm pitch

80LQFP, 12 x 12 mm, 0.5 mm pitch

VJ

VL

JM

FP

AG

AF

AE

01

02

04

05

06

RT102x

RT104x

Tie

%

1

RT105x

Standard Feature

Full Feature

RT106x

2

4MB Flash SIP

Enhanced Feature

Far Field AFE

4

5

Temperature (Tj)

+

D

C

X

A

F

L

Consumer: 0 to + 95 °C

Facial Recognition

Local Voice Control (audio input models)

Industrial: -40 to +105 °C

Extended Industrial: -40 to +125 eC

Local Voice Control (text input models)

S

Figure 1. Part number nomenclature—i.MX RT10XX family

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

5

Architectural overview

2 Architectural overview

The following subsections provide an architectural overview of the i.MX RT1015 processor system.

2.1

Block diagram

1

Figure 2 shows the functional modules in the i.MX RT1015 processor system .

System Control

CPU Platform

Connectivity

Secure JTAG

ARM Cortex-M7

UART x4

PLL / OSC

16 KB D-cache

NVIC

16 KB I-cache

FPU MPU

4 x 4 Keypad

I2C x2

RTC and Reset

Enhanced DMA

IOMUX

Up to 128 KB TCM

SPI x2

GP Timer x6

(GPT x2 + PIT x4)

External Memory

GPIO

Quadrature ENC x1

QuadTimer x1

Dual-Channel Quad-SPI

(FlexSPI)

I2S / SAI x3

FlexPWM x1

USB2.0 OTG with PHY

S/PDIF Tx/Rx

Security

Watch Dog x4

HAB

eFUSE

Internal Memory

128 KB OCRAM

shared with TCM

ADC

Secure RTC

Ciphers and RNG

ADC (9-Channel) x1

96 KB ROM

DCDC

Power Management

LDO

Temp Monitor

.

Figure 2. i.MX RT1015 system block diagram

1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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NXP Semiconductors

Modules list

3 Modules list

The i.MX RT1015 processors contain a variety of digital and analog modules. Table 2 describes these

modules in alphabetical order.

Table 2. i.MX RT1015 modules list

Block mnemonic

Block name

Subsystem

Analog

Brief description

ADC1

Analog to Digital

Converter

The ADC is a 12-bit general purpose analog to digital

converter.

AOI

Arm

And-Or-Inverter

Arm Platform

Cross Trigger

The AOI provides a universal boolean function

generator using a four team sum of products expression

with each product term containing true or complement

values of the four selected inputs (A, B, C, D).

Arm

The Arm Core Platform includes 1x Cortex-M7 core. It

also includes associated sub-blocks, such as Nested

Vectored Interrupt Controller (NVIC), Floating-Point

Unit (FPU), Memory Protection Unit (MPU), and

CoreSight debug modules.

BEE

Bus Encryption Engine

Security

On-The-Fly FlexSPI Flash Decryption

CCM

GPC

SRC

Clock Control Module,

General Power

Controller, System Reset

Controller

Clocks, Resets, and These modules are responsible for clock and reset

Power Control

distribution in the system, and also for the system

power management.

CSU

DAP

Central Security Unit

Debug Access Port

Security

The Central Security Unit (CSU) is responsible for

setting comprehensive security policy within the i.MX

RT1015 platform.

System Control

Peripherals

The DAP provides real-time access for the debugger

without halting the core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan

chains. The DAP module is internal to the Cortex-M7

Core Platform.

DCDC

DCDC Converter

Analog

The DCDC module is used for generating power supply

for core logic. Main features are:

• Adjustable high efficiency regulator

• Supports 3.3 V input voltage

• Supports nominal run and low power standby modes

• Supports at 0.9 ~ 1.3 V output in run mode

• Supports at 0.9 ~ 1.0 V output in standby mode

• Over current and over voltage detection

eDMA

enhanced Direct Memory System Control

Access Peripherals

There is an enhanced DMA (eDMA) engine and two

DMA_MUX.

• The eDMA is a 32 channel DMA engine, which is

capable of performing complex data transfers with

minimal intervention from a host processor.

• The DMA_MUX is capable of multiplexing up to 128

DMA request sources to the 32 DMA channels of

eDMA.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Modules list

Table 2. i.MX RT1015 modules list (continued)

Block mnemonic

Block name

Subsystem

Brief description

ENC

Quadrature

Encoder/Decoder

Timer Peripherals

The enhanced quadrature encoder/decoder module

provides interfacing capability to position/speed

sensors. There are five input signals: PHASEA,

PHASEB, INDEX, TRIGGER, and HOME. This module

is used to decode shaft position, revolution count, and

speed.

EWM

External Watchdog

Monitor

Timer Peripherals

The EWM modules is designed to monitor external

circuits, as well as the software flow. This provides a

back-up mechanism to the internal WDOG that can

reset the system. The EWM differs from the internal

WDOG in that it does not reset the system. The EWM,

if allowed to time-out, provides an independent trigger

pin that when asserted resets or places an external

circuit into a safe mode.

FlexIO1

Flexible Input/output

Connectivity and

Communications

The FlexIO is capable of supporting a wide range of

protocols including, but not limited to: UART, I2C, SPI,

I2S, camera interface, display interface, PWM

waveform generation, etc. The module can remain

functional when the chip is in a low power mode

provided the clock it is using remain active.

FlexPWM1

FlexRAM

Pulse Width Modulation Timer Peripherals

The pulse-width modulator (PWM) contains four PWM

sub-modules, each of which is set up to control a single

half-bridge power stage. Fault channel support is

provided. The PWM module can generate various

switching patterns, including highly sophisticated

waveforms.

RAM

Memories

The i.MX RT1015 has 128 KB of on-chip RAM which

could be flexible allocated to I-TCM, D-TCM, and

on-chip RAM (OCRAM) in a 32 KB granularity. The

FlexRAM is the manager of the 128 KB on-chip RAM

array. Major functions of this blocks are: interfacing to

I-TCM and D-TCM of Arm core and OCRAM controller;

dynamic RAM arrays allocation for I-TCM, D-TCM, and

OCRAM.

FlexSPI

Quad Serial Peripheral

Interface

Connectivity and

Communications

FlexSPI acts as an interface to one or two external

serial flash devices, each with up to four bidirectional

data lines.

GPIO1

GPIO2

GPIO3

GPIO5

General Purpose I/O

Modules

System Control

Peripherals

Used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Modules list

Table 2. i.MX RT1015 modules list (continued)

Block mnemonic

Block name

General Purpose Timer

Subsystem

Brief description

GPT1

GPT2

Timer Peripherals

Each GPT is a 32-bit “free-running” or “set and forget”

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured

to trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured to

operate in “set and forget” mode, it is capable of

providing precise interrupts at regular intervals with

minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at

comparison. This timer can be configured to run either

on an external clock or on an internal clock.

KPP

Keypad Port

Human Machine

Interfaces

The KPP is a 16-bit peripheral that can be used as a

keypad matrix interface or as general purpose

input/output (I/O). It supports 4 x 4 external key pad

matrix. Main features are:

• Multiple-key detection

• Long key-press detection

• Standby key-press detection

• Supports a 2-point and 3-point contact key matrix

LPI2C1

LPI2C2

Low Power

Inter-integrated Circuit

Connectivity and

Communications

The LPI2C is a low power Inter-Integrated Circuit (I2C)

module that supports an efficient interface to an I2C bus

as a master.

The I2C provides a method of communication between

a number of external devices. More detailed

information, see Section 4.8.2, LPI2C module timing

parameters.

LPSPI1

LPSPI2

Low Power Serial

Peripheral Interface

Connectivity and

Communications

The LPSPI is a low power Serial Peripheral Interface

(SPI) module that support an efficient interface to an

SPI bus as a master and/or a slave.

• It can continue operating while the chip is in stop

modes, if an appropriate clock is available

• Designed for low CPU overhead, with DMA off

loading of FIFO register access

LPUART1

LPUART2

LPUART3

LPUART4

UART Interface

Connectivity

Peripherals

Each of the UART modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 20 Mbps.

MQS

Medium Quality Sound

Multimedia

Peripherals

MQS is used to generate 2-channel medium quality

PWM-like audio via two standard digital GPIO pins.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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9

Modules list

Table 2. i.MX RT1015 modules list (continued)

Block mnemonic

Block name

Subsystem

Brief description

QuadTimer1

QuadTimer

Timer Peripherals

The quad-timer provides four timer channels with a

variety of controls affecting both individual and

multi-channel features.Specific features include

up/down count, cascading of counters, programmable

module, count once/repeated, counter preload,

compare registers with preload, shared use of input

signals, prescaler controls, independent

capture/compare, fault input control, programmable

input filters, and multi-channel synchronization.

ROMCP

ROM Controller with

Patch

Memories and

The ROMCP acts as an interface between the Arm

Memory Controllers advanced high-performance bus and the ROM. The

on-chip ROM is only used by the Cortex-M7 core during

boot up. Size of the ROM is 96 KB.

RTC OSC

RTWDOG

Real Time Clock

Oscillator

Clock Sources and The RTC OSC provides the clock source for the

Control

Real-Time Clock module. The RTC OSC module, in

conjunction with an external crystal, generates a 32.768

kHz reference clock for the RTC.

Watch Dog

Timer Peripherals

The RTWDG module is a high reliability independent

timer that is available for system to use. It provides a

safety feature to ensure software is executing as

planned and the CPU is not stuck in an infinite loop or

executing unintended code. If the WDOG module is not

serviced (refreshed) within a certain period, it resets the

MCU. Windowed refresh mode is supported as well.

SAI1

SAI2

SAI3

Synchronous Audio

Interface

Multimedia

Peripherals

The SAI module provides a synchronous audio

interface (SAI) that supports full duplex serial interfaces

with frame synchronization, such as I2S, AC97, TDM,

and codec/DSP interfaces.

SA-TRNG

SJC

StandaloneTrueRandom Security

Number Generator

The SA-TRNG is hardware accelerator that generates

a 512-bit entropy as needed by an entropy consuming

module or by other post processing functions.

System JTAG Controller System Control

Peripherals

The SJC provides JTAG interface, which complies with

JTAG TAP standards, to internal logic. The i.MX

RT1015 processors use JTAG port for production,

testing, and system debugging. In addition, the SJC

provides BSR (Boundary Scan Register) standard

support, which complies with IEEE1149.1 and

IEEE1149.6 standards.

The JTAG port is accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX RT1015 SJC incorporates

three security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

SNVS

Secure Non-Volatile

Storage

Security

Secure Non-Volatile Storage, including Secure Real

Time Clock, Security State Machine, and Master Key

Control.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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10

Modules list

Table 2. i.MX RT1015 modules list (continued)

Block name Subsystem Brief description

Multimedia

Block mnemonic

SPDIF

Sony Philips Digital

Interconnect Format

A standard audio file transfer format, developed jointly

by the Sony and Phillips corporations. Has Transmitter

and Receiver functionality.

Peripherals

Temp Monitor

USBO2

Temperature Monitor

Analog

The temperature sensor implements a temperature

sensor/conversion function based on a

temperature-dependent voltage to time conversion.

Universal Serial Bus 2.0 Connectivity

Peripherals

USBO2 (USB OTG1) contains:

• One high-speed OTG 2.0 module with integrated HS

USB PHYs

• Support eight Transmit (TX) and eight Receive (Rx)

endpoints, including endpoint 0

WDOG1

WDOG2

Watch Dog

Cross BAR

Timer Peripherals

The Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the Arm

core, and a second point evokes an external event on

the WDOG line.

XBAR

Cross Trigger

Each crossbar switch is an array of muxes with shared

inputs. Each mux output provides one output of the

crossbar. The number of inputs and the number of

muxes/outputs are user configurable and registers are

provided to select which of the shared inputs are routed

to each output.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Modules list

3.1

Special signal considerations

Table 3 lists special signal considerations for the i.MX RT1015 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, Package information and contact

assignments. Signal descriptions are provided in the i.MX RT1015 Reference Manual (IMXRT1015RM).

Table 3. Special signal considerations

Signal name

Remarks

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected the ground to bypass DCDC.

To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 M). This will debias the amplifier and cause a reduction of

startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must

remain unconnected or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical

conditions.

In case when high accuracy real time clock are not required system may use internal low

frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep

RTC_XTALO unconnected.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO. External load capacitance

value depends on the typical load capacitance of crystal used and PCB design.

The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series

resistance) of typical 80  is recommended. NXP SDK software requires 24 MHz on

XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF

capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

GPANAIO

This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX RT1015 reference manual. Both names refer

to the same signal. JTAG_MOD must be externally connected to GND for normal operation.

Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD

set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD

set to low configures the JTAG interface for common SW debug adding all the system TAPs to the

chain.

NC

These signals are No Connect (NC) and should be disconnected by the user.

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NXP Semiconductors

Modules list

Table 3. Special signal considerations (continued)

Signal name

POR_B

Remarks

This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF

ONOFF can be configured in debounce, off to on time, and max time-out configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to

generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than

the debounce time, the power off interrupt is generated. Off to on time supports the time it takes

to request power on after a configured button press time has been reached. While in the OFF

state, if ONOFF button is pressed longer than the off to on time, the state will transition from OFF

to ON. Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out

configuration supports the time it takes to request power down after ONOFF button has been

pressed for the defined time.

TEST_MODE

WAKEUP

TEST_MODE is for NXP factory use. The user can leave this signal floating or tie it to ground.

A GPIO powered by SNVS domain power supply which can be configured as wakeup source in

SNVS mode.

Table 4. JTAG controller interface summary

JTAG

I/O type

On-chip termination

100 kpull-down

JTAG_TCK

JTAG_TMS

JTAG_TDI

Input

47 kpull-up

Keeper

Input

JTAG_TDO

JTAG_TRSTB

JTAG_MOD

3-state output

Input

47 kpull-up

100 kpull-down

Input

3.2

Recommended connections for unused analog interfaces

Table 5 shows the recommended connections for unused analog interfaces.

Table 5. Recommended connections for unused analog interfaces

Recommendations

if unused

Module

Pad name

USB

ADC

USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS

VDDA_ADC_3P3

Not connected

VDDA_ADC_3P3

must be powered

even if the ADC is

not used.

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Electrical characteristics

4 Electrical characteristics

This section provides the device and module-level electrical characteristics for the i.MX RT1015

processors.

4.1

Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference

to the individual tables and sections.

Table 6. i.MX RT1015 chip-Level conditions

For these characteristics

Topic appears

Absolute maximum ratings

Thermal resistance

on page 14

on page 15

on page 16

on page 17

on page 18

on page 19

Operating ranges

External clock sources

Maximum supply currents

Low power mode supply currents

USB PHY current consumption

4.1.1

Absolute maximum ratings

CAUTION

Stress beyond those listed under Table 7 may cause permanent damage to the device. These are stress

ratings only. Functional operation of the device at these or any other conditions beyond those indicated

under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated

conditions for extended periods may affect device reliability.

Table 7 shows the absolute maximum operating ratings.

Table 7. Absolute maximum ratings

Parameter Description

Core supplies input voltage

Symbol

VDD_SOC_IN

Min

Max

Unit

-0.3

1.6

3.7

3.6

V

VDD_HIGH_IN supply voltage

Power for DCDC

VDD_HIGH_IN

DCDC_IN

Supply input voltage to Secure Non-Volatile Storage VDD_SNVS_IN

and Real Time Clock

USB VBUS supply

USB_OTG1_VBUS

VDDA_ADC

—

3

5.5

3.6

V

Supply for 12-bit ADC

IO supply for GPIO bank (3.3 V mode)

NVCC_GPIO

3

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Electrical characteristics

Table 7. Absolute maximum ratings (continued)

ESD Damage Immunity:

Vesd

Human Body Model (HBM)

Charge Device Model (CDM)

—

1000

500

V

Input/Output Voltage range

Storage Temperature range

V_in/Vout

-0.5

-40

OVDD + 0.3¹

150

V

T_STORAGE

^oC

1

OVDD is the I/O supply voltage.

4.1.2

Thermal resistance

Following sections provide the thermal resistance data.

4.1.2.1 14 x 14 mm package thermal resistance

Table 8 displays the 14 x 14 mm LQFP package thermal resistance data.

Table 8. 14 x 14 mm package thermal resistance data

Rating

Test Conditions

Single-layer board (1s)

Symbol

R_JA

Value

Unit

^oC/W

Notes

1,2

Junction to Ambient

Natural convection

63

52

53

46

1,2

1,3

Junction to Ambient

Natural convection

Four-layer board (2s2p)

R_JA

^oC/W

Junction to Ambient (@200 Single layer board (1s)

ft/min)

R_JMA

Junction to Ambient (@200 Four layer board (2s2p)

ft/min)

4

5

6

Junction to Board

—

R_JB

R_JC

_JT

36

19

3

^oC/W

Junction to Case

—

Junction to Package Top

Natural Convection

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

3

4

5

6

Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or

2s2p board, respectively.

Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or

2s2p board, respectively.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

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15

Electrical characteristics

4.1.3

Operating ranges

Table 9 provides the operating ranges of the i.MX RT1015 processors. For details on the chip's power

structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1015 Reference Manual

(IMXRT1015RM).

Table 9. Operating ranges

Parameter

Description

Operating

Conditions

Symbol

Min

Typ Max¹Unit

Comment

Run Mode

VDD_SOC_IN

Overdrive

1.25

1.15

—

1.3

V

—

M7 core at 396

MHz

M7 core at 132

MHz

1.15

0.925

1.15

—

1.3

M7 core at 24

MHz

IDLE Mode

VDD_SOC_IN

M7 core

V

—

operation at 396

MHz or below

SUSPEND (DSM) VDD_SOC_IN

Mode

—

0.925

—

1.3

V

Refer to Table 12 Low power mode

current and power consumption

SNVS Mode

VDD_SOC_IN

DCDC_IN

—

0

1.3

3.6

—

Power for DCDC

3.0

3.3

—

VDD_HIGH

VDD_HIGH_IN²

V

Must match the range of voltages

that the rechargeable backup

battery supports.

internal regulator

Backup battery

supply range

VDD_SNVS_IN³

—

2.40

—

3.6

Can be combined with

VDDHIGH_IN, if the system does

not require keeping real time and

other data on OFF state.

USB supply

voltages

USB_OTG1_VBUS —

4.40

3.0

—

5.5

3.6

V

—

GPIO supplies

A/D converter

NVCC_GPIO

—

3.3

All digital I/O supplies

(NVCC_xxxx) must be powered

(unless otherwise specified in this

data sheet) under normal

conditions whether the associated

I/O pins are in use or not.

VDDA_ADC_3P3

—

3.0

3.3

3.6

V

VDDA_ADC_3P3 must be

powered even if the ADC is not

used.

VDDA_ADC_3P3 cannot be

powered when the other SoC

supplies (except VDD_SNVS_IN)

are off.

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Electrical characteristics

Table 9. Operating ranges (continued)

System frequency/ F_SYS/F_BUS

Bus frequency

—

500/ 396/ 24/

MHz

—

125

132

24

Temperature Operating Ranges

Junction

temperature

Tj

Standard

Commercial

0

—

95

^oC

See the application note, i.MX

RT1015 Product Lifetime Usage

Estimates for information on

product lifetime (power-on years)

for this processor.

1

2

3

Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (V_min+ the supply tolerance). This result in an optimized power/speed ratio.

Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited

to below 3.49 V.

In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1015 Hardware

Development Guide (IMXRT1015HDG).

4.1.4

External clock sources

Each i.MX RT1015 processor has two external input system clocks: a low frequency (RTC_XTALI) and

a high frequency (XTALI).

The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watch-dog counters. The clock input can be

connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is

an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using internal

oscillator amplifier.

Table 10 shows the interface frequency requirements.

Table 10. External input clock frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^2,4

f_ckil

f_xtal

—

32.768³/32.0

24

—

kHz

MHz

1

External oscillator or a crystal with internal oscillator amplifier.

2

The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware

Development Guide for i.MX RT1015 Crossover Processors (IMXRT1015HDG).

3

4

Recommended nominal frequency 32.768 kHz.

External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 10 are required for use with NXP SDK to ensure precise time keeping

and USB operation. For RTC_XTALI operation, two clock sources are available.

•

On-chip 40 kHz ring oscillator—this clock source has the following characteristics:

— Approximately 25 µA more Idd than crystal oscillator

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Electrical characteristics

— Approximately ±50% tolerance

— No external component required

— Starts up quicker than 32 kHz crystal oscillator

External crystal oscillator with on-chip support circuit:

•

— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit

switches over to the crystal oscillator automatically.

— Higher accuracy than ring oscillator

— If no external crystal is present, then the ring oscillator is utilized

The decision of choosing a clock source should be taken based on real-time clock use and precision

time-out.

4.1.5

Maximum supply currents

The data shown in Table 11 represent a use case designed specifically to show the maximum current

consumption possible. All cores are running at the defined maximum frequency and are limited to L1

cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited

practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to

specifically show the worst case power consumption.

See the i.MX RT1015 Power Consumption Measurement Application Note for more details on typical

power consumption under various use case definitions.

Table 11. Maximum supply currents

Power Rail

Conditions

Max Current

Unit

DCDC_IN

Max power for chip at 95 ^oC with core 90

mark run on FlexRAM

mA

VDD_HIGH_IN

VDD_SNVS_IN

Include internal loading in analog

—

50

mA

A

250

25

USB_OTG1_VBUS

VDDA_ADC_3P3

25 mA for each active USB interface

mA

3.3 V power supply for 12-bit ADC, 600 40

A typical, 750 A max, for each ADC.

100 Ohm max loading for touch panel,

cause 33 mA current.

NVCC_GPIO

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F).

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

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Electrical characteristics

4.1.6

Low power mode supply currents

Table 12 shows the current core consumption (not including I/O) of i.MX RT1015 processors in selected

low power modes.

Table 12. Low power mode current and power consumption

Mode

Test Conditions

Supply

Typical¹

Units

mA

SYSTEM IDLE

• LDO_ARM and LDO_SOC set to the Bypass

mode

• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V

• CPU in WFI, CPU clock gated

• 24 MHz XTAL is ON

• System PLL is active, other PLLs are power down

• Peripheral clock gated, but remain powered

DCDC_IN (3.3 V)

VDD_HIGH_IN (3.3 V)

VDD_SNVS_IN (3.3 V)

Total

3.82

5.93

0.025

32.258

mW

mA

LOW POWER IDLE

• LDO_SOC is in the Bypass mode, LDO_ARM is DCDC_IN (3.3 V)

in the PG mode

• LDO_2P5 and LDO_1P1 are set to Weak mode

• CPU in Power Gate mode

• All PLLs are power down

• 24 MHz XTAL is off, 24 MHz RCOSC used as

clock source

• Peripheral are powered off

1.13

0.287

0.046

4.828

VDD_HIGH_IN (3.3 V)

VDD_SNVS_IN (3.3 V)

Total

mW

mA

SUSPEND

(DSM)

• LDO_SOC is in the Bypass mode, LDO_ARM is DCDC_IN (3.3 V)

in the PG mode

• LDO_2P5 and LDO_1P1 are shut off

0.19

0.09

VDD_HIGH_IN (3.3 V)

• CPU in Power Gate mode

• All PLLs are power down

• 24 MHz XTAL is off, 24 MHz RCOSC is off

• All clocks are shut off, except 32 kHz RTC

• Peripheral are powered off

VDD_SNVS_IN (3.3 V)

0.018

1.019

Total

mW

mA

SNVS (RTC)

• All SOC digital logic, analog module are shut off DCDC_IN (0 V)

0

• 32 kHz RTC is alive

VDD_HIGH_IN (0 V)

0

VDD_SNVS_IN (3.3 V)

Total

0.018

0.059

mW

1

The typical values shown here are for information only and are not guaranteed. These values are average values measured

on a typical process wafer at 25^oC.

4.1.7

USB PHY current consumption

Power down mode

4.1.7.1

In power down mode, everything is powered down, including the USB VBUS valid detectors in typical

condition. Table 13 shows the USB interface current consumption in power down mode.

Table 13. USB PHY current consumption in power down mode

VDD_USB_CAP (3.0 V)

5.1 A

VDD_HIGH_CAP (2.5 V)

1.7 A

NVCC_PLL (1.1 V)

< 0.5 A

Current

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Electrical characteristics

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level

shifters.

4.2

System power and clocks

This section provide the information about the system power and clocks.

4.2.1

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor (worst-case scenario)

4.2.1.1

Power-up sequence

The below restrictions must be followed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_HIGH_IN supply.

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

When internal DCDC is enabled, external delay circuit is required to delay the

“DCDC_PSWITCH” signal 1 ms after DCDC_IN is stable.

Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used

for DCDC_PSWITCH and RC must be longer than 1 ms.

POR_B should be held low during the entire power up sequence.

NOTE

The POR_B input (if used) must be immediately asserted at power-up and

remain asserted until after the last power rail reaches its working voltage. In

the absence of an external reset feeding the POR_B input, the internal POR

module takes control. See the i.MX RT1015 Reference Manual

(IMXRT1015RM) for further details and to ensure that all necessary

requirements are being met.

NOTE

Need to ensure that there is no back voltage (leakage) from any supply on

the board towards the 3.3 V supply (for example, from the external

components that use both the 1.8 V and 3.3 V supplies).

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NXP Semiconductors

Electrical characteristics

NOTE

USB_OTG1_VBUS and VDDA_ADC_3P3 are not part of the power

supply sequence and may be powered at any time.

4.2.1.2

Power-down sequence

The following restrictions must be followed:

•

VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted)

with VDD_HIGH_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply

is switched off.

4.2.1.3

Power supplies usage

All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.

This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O

power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information

and contact assignments.”

4.2.2

Integrated LDO voltage regulator parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins

named *_CAP must be connected to external capacitors. The on-board LDOs are intended for internal use

only and should not be used to power any external circuitry. See the i.MX RT1015 Reference Manual

(IMXRT1015RM) for details on the power tree scheme.

NOTE

The *_CAP signals should not be powered externally. These signals are

intended for internal LDO operation only.

4.2.2.1

Digital regulators (LDO_SNVS)

There are one digital LDO regulator (“Digital”, because of the logic loads that they drive, not because of

their construction). The advantages of the regulator is to reduce the input supply variation because of its

input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the

on-chip logics.

The regulator has two basic modes:

•

Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.

The analog part of the regulator is powered down here limiting the power consumption.

•

Analog regulation mode. The regulation FET is controlled such that the output voltage of the

regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV

steps.

For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM).

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Electrical characteristics

4.2.2.2

Regulators for analog modules

LDO_1P1

4.2.2.2.1

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A

programmable brown-out detector is included in the regulator that can be used by the system to determine

when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting

can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can

also be enabled for systems requiring this feature.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX RT1015 Crossover Processors (IMXRT1015HDG).

For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM).

4.2.2.2.2

LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V

to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse module, and

PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to

determine when the load capability of the regulator is being exceeded, to take the necessary steps.

Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.

Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased

low-precision weak-regulator is included that can be enabled for applications needing to keep the output

voltage alive during low-power modes where the main regulator driver and its associated global bandgap

reference module are disabled. The output of the weak-regulator is not programmable and is a function of

the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output

is 2.525 V and its output impedance is approximately 40 .

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX RT1015 Crossover Processors (IMXRT1015HDG).

For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM).

4.2.2.2.3

LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the USB VUSB

voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector

is included in the regulator that can be used by the system to determine when the load capability of the

regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows

the user to select to run the regulator from USB VBUS supply. Current limit is also included to help the

system meet in-rush current targets.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX RT1015 Crossover Processors (IMXRT1015HDG).

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22

NXP Semiconductors

Electrical characteristics

For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM).

4.2.2.2.4 DCDC

DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During

the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a

minimum quiescent current to maintain high efficiency.

DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,

DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly

detect the current loading.

DCDC also includes the following protection functions:

•

Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in

the P-type power switch. In power save mode, DCDC stop charging inductor when detecting large

current in the P-type power switch. The threshold is also different in run mode and in power save

mode: the former is 1 A–2A, and the latter is 200 mA–250 mA.

•

Over voltage protection. DCDC shuts down when detecting the output voltage is too high.

Low voltage detection. DCDC shuts down when detecting the input voltage is too low.

For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM).

4.2.3

PLL’s electrical characteristics

This section provides PLL electrical characteristics.

4.2.3.1

Audio/Video PLL’s electrical parameters

Table 14. Audio/video PLL’s electrical parameters

Parameter Value

Clock output range

Reference clock

Lock time

650 MHz–1.3 GHz

24 MHz

< 11250 reference cycles

4.2.3.2

System PLL

Table 15. System PLL’s electrical parameters

Parameter

Value

Clock output range

Reference clock

Lock time

528 MHz PLL output

24 MHz

< 11250 reference cycles

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Electrical characteristics

4.2.3.3

Ethernet PLL

Table 16. Ethernet PLL’s electrical parameters

Parameter

Value

Clock output range

Reference clock

Lock time

1 GHz

24 MHz

< 11250 reference cycles

4.2.3.4

USB PLL

Table 17. USB PLL’s electrical parameters

Parameter

Value

Clock output range

Reference clock

Lock time

480 MHz PLL output

24 MHz

< 383 reference cycles

4.2.4

On-chip oscillators

OSC24M

4.2.4.1

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.2.4.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implement a low power oscillator. It also implements a power mux such that it can be powered

from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when

VDD_HIGH_IN is lost.

In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K

will automatically switch to a crude internal ring oscillator. The frequency range of this block is

approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.

The OSC32k runs from VDD_SNVS_CAP supply, which comes from the

VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type

is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when

connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For

example, for Panasonic ML621:

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NXP Semiconductors

Electrical characteristics

•

Average Discharge Voltage is 2.5 V

Maximum Charge Current is 0.6 mA

For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.

Table 18. OSC32K main characteristics

Min

Typ

Max Comments

Fosc

—

32.768 KHz

—

This frequency is nominal and determined mainly by the crystal selected.

32.0 K would work as well.

Current consumption

—

4 A

—

The 4 A is the consumption of the oscillator alone (OSC32k). Total supply

consumption will depend on what the digital portion of the RTC consumes.

The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A

when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in

the power_detect block. So, the total current is 6.5 A on vdd_rtc when the

ring oscillator is not running.

Bias resistor

—

14 M

—

This integrated bias resistor sets the amplifier into a high gain state. Any

leakage through the ESD network, external board leakage, or even a

scope probe that is significant relative to this value will debias the amp. The

debiasing will result in low gain, and will impact the circuit's ability to start

up and maintain oscillations.

Crystal Properties

Cload

—

10 pF

—

Usually crystals can be purchased tuned for different Cloads. This Cload

value is typically 1/2 of the capacitances realized on the PCB on either side

of the quartz. A higher Cload will decrease oscillation margin, but

increases current oscillating through the crystal.

ESR

50 k

100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher

value will decrease the oscillating margin.

4.3

I/O parameters

This section provide parameters on I/O interfaces.

4.3.1

I/O DC parameters

This section includes the DC parameters of the following I/O types:

•

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

General Purpose I/O (GPIO)

NOTE

The term ‘NVCC_XXXX’in this section refers to the associated supply rail

of an input or output.

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Electrical characteristics

Figure 3. Circuit for parameters Voh and Vol for I/O cells

4.3.1.1

XTALI and RTC_XTALI (clock inputs) DC parameters

Table 19 shows the DC parameters for the clock inputs.

1

Table 19. XTALI and RTC_XTALI DC parameters

Symbol Test Conditions Min

Parameter

Max

Unit

XTALI high-level DC input voltage

XTALI low-level DC input voltage

Vih

Vil

—

0.8 x NVCC_PLL

NVCC_PLL

V

0

0.2

1.1

0.2

RTC_XTALI high-level DC input voltage

RTC_XTALI low-level DC input voltage

Vih

Vil

0.8

0

1

The DC parameters are for external clock input only.

4.3.1.2

Single voltage general purpose I/O (GPIO) DC parameters

Table 20 shows DC parameters for GPIO pads. The parameters in Table 20 are guaranteed per the

operating ranges in Table 9, unless otherwise noted.

Table 20. Single voltage GPIO DC parameters

Parameter

Symbol

V_OH

Test Conditions

Min

Max

Units

High-level output voltage¹

Ioh = -0.1 mA (ipp_dse =

001,010)

NVCC_XXXX -

0.2

–

V

Ioh= -1 mA

(ipp_dse = 011,100,101,110,111)

Low-level output voltage¹

VOL

Iol = 0.1 mA (ipp_dse = 001,010) –

Iol= 1 mA

0.2

V

(ipp_dse = 011,100,101,110,111)

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Electrical characteristics

Table 20. Single voltage GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output current

I_OH

V_DDE= 3.3 V, V_OH= V_DDE- 0.45

—

mA

V, ipp_dse as follows:

001

010

011

110

101

110

111

-1

-2

-4

Low-level output current

I_OL

V_DDE= 3.3 V, V_OL= 0.45 V,

—

mA

ipp_dse as follows:

001

010

011

110

101

110

111

1

2

4

High-Level input voltage^1,2

Low-Level input voltage^1,2

VIH

—

0.7 x

NVCC_XXXX

V

VIL

0

0.3 x

V

NVCC_XXXX

Input Hysteresis

(NVCC_XXXX= 1.8V)

VHYS_LowV NVCC_XXXX = 1.8 V

DD

250

—

mV

Input Hysteresis

(NVCC_XXXX=3.3V)

VHYS_High NVCC_XXXX = 3.3 V

VDD

Schmitt trigger VT+^2,3

Schmitt trigger VT-^2,3

VTH+

—

0.5 x

NVCC_XXXX

VTH-

—

0.5 x

NVCC_XXXX

Pull-up resistor (22_k PU)

Pull-up resistor (47_k PU)

Pull-up resistor (100_k PU)

RPU_22K

RPU_47K

Vin = 0 V

—

-1

212

1

A

k

Vin = NVCC_XXXX

Vin = 0 V

100

1

Vin = NVCC_XXXX

RPU_100K Vin = 0 V

48

1

RPU_100K Vin = NVCC_XXXX

Pull-down resistor (100_k PD) RPD_100K Vin = NVCC_XXXX

Pull-down resistor (100_k PD) RPD_100K Vin = 0V

48

1

Input current (no PU/PD)

Keeper Circuit Resistance

IIN

VI = 0, VI = NVCC_XXXX

1

R_Keeper

VI =0.3 x NVCC_XXXX, VI = 0.7 105

x NVCC_XXXX

175

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Electrical characteristics

1

Overshoot and undershoot conditions (transitions above NVCC_XXXX and below GND) on switching pads must be held

below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/

undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line

termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage

to the device.

2

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

3

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.3.2

I/O AC parameters

This section includes the AC parameters of the following I/O types:

General Purpose I/O (GPIO)

Figure 4 shows load circuit for output, and Figure 5 show the output transition time waveform.

•

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load circuit for output

OVDD

0 V

80%

20%

80%

20%

tr

Output (at pad)

tf

Figure 5. Output transition time waveform

4.3.2.1

General purpose I/O AC parameters

The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 21 and Table 22,

respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the

IOMUXC control registers.

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Electrical characteristics

Table 21. General purpose I/O AC parameters 1.8 V mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, ipp_dse=111)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.72/2.79

1.51/1.54

—

Output Pad Transition Times, rise/fall

(High Drive, ipp_dse=101)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.20/3.36

1.96/2.07

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, ipp_dse=100)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.64/3.88

2.27/2.53

Output Pad Transition Times, rise/fall

(Low Drive. ipp_dse=011)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

4.32/4.50

3.16/3.17

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Table 22. General purpose I/O AC parameters 3.3 V mode

Parameter

Symbol

Test condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall tr, tf

(Max Drive, ipp_dse=101)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

1.70/1.79

1.06/1.15

—

Output Pad Transition Times, rise/fall tr, tf

(High Drive, ipp_dse=011)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.35/2.43

1.74/1.77

—

ns

Output Pad Transition Times, rise/fall tr, tf

(Medium Drive, ipp_dse=010)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.13/3.29

2.46/2.60

Output Pad Transition Times, rise/fall tr, tf

(Low Drive. ipp_dse=001)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

5.14/5.57

4.77/5.15

—

ns

Input Transition Times¹

trm

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

4.3.3

Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX RT1015 processors for the following I/O

types:

•

Single Voltage General Purpose I/O (GPIO)

NOTE

GPIO I/O output driver impedance is measured with “long” transmission

line of impedance Ztl attached to I/O pad and incident wave launched into

transmission line. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to NVCC_XXXX. Output driver

impedance is calculated from this voltage divider (see Figure 6).

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Electrical characteristics

OVDD

PMOS (Rpu)

Ztl , L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

(do)

Vin

VDD

t,(ns)

0

OVDD

Vref

U,(V)

Vout (pad)

Vref2

Vref1

t,(ns)

0

Vovdd - Vref1

Vref1

Vref2

Vovdd - Vref2

Rpu =

 Ztl

Rpd =

 Ztl

Figure 6. Impedance matching load for measurement

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Electrical characteristics

4.3.3.1

Single voltage GPIO output buffer impedance

Table 23 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V).

Table 23. GPIO output buffer average impedance (NVCC_XXXX 1.8 V)

Symbol Drive strength (DSE) Typ value

Parameter

Unit

001

010

011

100

101

110

111

260

130

88

65

52

Output Driver

Impedance

Rdrv



43

37

Table 24 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).

Table 24. GPIO Output buffer average impedance (NVCC_XXXX 3.3 V)

Parameter

Symbol Drive strength (DSE) Typ value

Unit

001

010

011

100

101

110

111

157

78

53

39

32

26

23

Output Driver

Impedance

Rdrv



4.4

System modules

This section contains the timing and electrical parameters for the modules in the i.MX RT1015 processor.

4.4.1

Reset timings parameters

Figure 7 shows the reset timing and Table 25 lists the timing parameters.

POR_B

(Input)

CC1

Figure 7. Reset timing diagram

Table 25. Reset timing parameters

ID

CC1

Parameter

Min Max

Unit

Duration of POR_B to be qualified as valid.

1

—

RTC_XTALI cycle

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Electrical characteristics

4.4.2

WDOG reset timing parameters

Figure 8 shows the WDOG reset timing and Table 26 lists the timing parameters.

WDOGn_B

(Output)

CC3

Figure 8. WDOGn_B timing diagram

Table 26. WDOGn_B timing parameters

ID

CC3

Parameter

Duration of WDOGn_B Assertion

Min

Max

Unit

1

—

RTC_XTALI cycle

NOTE

RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or

approximately 30 s.

NOTE

WDOGn_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the IOMUX

manual for detailed information.

4.4.3

SCAN JTAG Controller (SJC) timing parameters

Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing.

Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 27.

SJ1

SJ2

JTAG_TCK

(Input)

VM

VIH

VIL

SJ3

Figure 9. Test clock input timing diagram

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Electrical characteristics

JTAG_TCK

(Input)

VIH

SJ5

VIL

SJ4

Input Data Valid

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 10. Boundary scan (JTAG) timing diagram

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Electrical characteristics

JTAG_TCK

(Input)

VIH

SJ9

VIL

SJ8

Input Data Valid

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 11. Test access port timing diagram

JTAG_TCK

(Input)

SJ13

JTAG_TRST_B

(Input)

SJ12

Figure 12. JTAG_TRST_B timing diagram

Table 27. JTAG timing

All frequencies

Min Max

ID

Parameter^1,2

Unit

1

SJ0

JTAG_TCK frequency of operation 1/(3•T_DC

)

0.001

45

22.5

—

22

—

3

MHz

SJ1

SJ2

SJ3

SJ4

SJ5

SJ6

SJ7

SJ8

JTAG_TCK cycle time in crystal mode

ns

2

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

5

—

40

—

24

—

5

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Electrical characteristics

Table 27. JTAG timing (continued)

Parameter^1,2

All frequencies

Min Max

ID

Unit

SJ9

JTAG_TMS, JTAG_TDI data hold time

JTAG_TCK low to JTAG_TDO data valid

JTAG_TCK low to JTAG_TDO high impedance

JTAG_TRST_B assert time

25

—

44

—

ns

SJ10

SJ11

SJ12

SJ13

ns

—

100

40

JTAG_TRST_B set-up time to JTAG_TCK low

= target frequency of SJC

1

T

DC

2

V_M= mid-point voltage

4.4.4

Debug trace timing specifications

Table 28. Debug trace operating behaviors

Symbol

Description

Min

Max

Unit

T1

T2

T3

T4

T5

T6

T7

T8

ARM_TRACE_CLK frequency of operation

ARM_TRACE_CLK period

Low pulse width

—

1/T1

6

70

—

1

MHz

ns

High pulse width

6

ns

Clock and data rise time

Clock and data fall time

Data setup

—

2

ns

1

ns

—

ns

Data hold

0.7

ns

!2-?42!#%?#,+

4ꢀ

T6

T4

4ꢂ

4ꢁ

Figure 13. ARM_TRACE_CLK specifications

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Electrical characteristics

ARM_TRACE_CLK

ARM_TRACE0-3

T7

T8

T7

T8

Figure 14. Trace data specifications

4.5

External memory interface

The following sections provide information about external memory interfaces.FlexSPI parameters

Measurements are with a load 15 pf and input slew rate of 1 V/ns.

4.5.1

FlexSPI input/read timing

There are four sources for the internal sample clock for FlexSPI read data:

• Dummy read strobe generated by FlexSPI controller and looped back internally

(FlexSPIn_MCR0[RXCLKSRC] = 0x0)

• Dummy read strobe generated by FlexSPI controller and looped back through the

DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)

• Read strobe provided by memory device and input from DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x3)

The following sections describe input signal timing for each of these four internal sample clock sources.

4.5.1.0.1

SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 29. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

8.67

0

60

—

MHz

ns

T_IS

T_IH

Setup time for incoming data

Hold time for incoming data

ns

Table 30. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

2

133

—

MHz

ns

T_IS

T_IH

Setup time for incoming data

Hold time for incoming data

1

—

ns

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Electrical characteristics

SCK

TIS

TIH

TIS

TIH

SIO[0:7]

Internal Sample Clock

Figure 15. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge, and FlexSPI controller sampling read data on the falling edge.

4.5.1.0.2

SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

• A1–Memory generates both read data and read strobe on SCK rising edge (or falling

edge)

• A2–Memory generates read data on SCK falling edge and generates read strobe on

SCK rising edgeSCK rising edge

Table 31. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

Value

Symbol

Parameter

Unit

Min

Max

—

Frequency of operation

—

-2

166

—

2

MHz

ns

T_SCKD

Time from SCK to data valid

Time from SCK to DQS

T_SCKDQS

ns

T_{SCKD -}T_SCKDQS

Time delta between T_SCKDand T_SCKDQS

ns

SCK

TSCKD

SIO[0:7]

TSCKDQS

DQS

Figure 16. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A1)

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Electrical characteristics

NOTE

Timing shown is based on the memory generating read data and read strobe

on the SCK rising edge. The FlexSPI controller samples read data on the

DQS falling edge.

Table 32. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

Value

Symbol

Parameter

Unit

Min

Max

—

Frequency of operation

—

-2

166

—

2

MHz

ns

T_SCKD

Time from SCK to data valid

Time from SCK to DQS

T_SCKDQS

ns

T_{SCKD -}T_SCKDQS

Time delta between T_SCKDand T_SCKDQS

ns

SCK

TSCKD

SIO[0:7]

TSCKDQS

DQS

Internal Sample Clock

Figure 17. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A2)

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge and read strobe on the SCK rising edge. The FlexSPI controller

samples read data on a half cycle delayed DQS falling edge.

4.5.1.0.3

DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 33. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

8.67

0

30

—

MHz

ns

T_IS

T_IH

Setup time for incoming data

Hold time for incoming data

ns

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Electrical characteristics

Table 34. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

2

66

—

MHz

ns

T_IS

T_IH

Setup time for incoming data

Hold time for incoming data

1

ns

SCLK

TIS

TIH

TIS

TIH

SIO[0:7]

Internal Sample Clock

Figure 18. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.5.1.0.4

DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in DDR mode:

• B1–Memory generates both read data and read strobe on SCK edge

• B2–Memory generates read data on SCK edge and generates read strobe on SCK2

edge

Table 35. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

-1

166

—

1

MHz

ns

T_SCKD

Time from SCK to data valid

Time from SCK to DQS

T_SCKDQS

ns

T_{SCKD -}T_SCKDQS

Time delta between T_SCKDand T_SCKDQS

ns

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Electrical characteristics

SCK

TSCKD

SIO[0:7]

TSCKDQS

DQS

Figure 19. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)

Table 36. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

Symbol

Parameter

Frequency of operation

Min

Max

Unit

—

-1

166

—

1

MHz

ns

T_SCKD

Time from SCK to data valid

T_{SCKD -}T_SCKDQS

Time delta between T_SCKDand T_SCKDQS

ns

SCK

SIO[0:7]

SCK2

TSCKD

TSCK2DQS

DQS

Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

4.5.1.1

FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

4.5.1.1.1

SDR mode

Table 37. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

SCK clock period

—

6.0

—

166¹

—

MHz

ns

T_ck

T_DVO

T_DHO

Output data valid time

Output data hold time

1

ns

-1

—

ns

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Electrical characteristics

Table 37. FlexSPI output timing in SDR mode (continued)

Symbol

Parameter

Min

Max

Unit

T_CSS

T_CSH

Chip select output setup time

Chip select output hold time

3 x T_CK-1

—

ns

3 x T_CK+ 2

1

The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE

T_CSSand T_CSHare configured by the FlexSPIn_FLSHAxCR1

register, the default values are shown above. Please refer to the i.MX

RT1015 Reference Manual (IMXRT1015RM) for more details.

SCK

TCSH

T

CSS

T

CK

CS

TDVO

SIO[0:7]

TDHO

Figure 21. FlexSPI output timing in SDR mode

4.5.1.1.2

DDR mode

Table 38. FlexSPI output timing in DDR mode

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation¹

—

166

—

MHz

ns

T_ck

SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)

Output data valid time

6.0

—

T_DVO

T_DHO

T_CSS

T_CSH

2.2

—

ns

Output data hold time

0.8

ns

Chip select output setup time

Chip select output hold time

3 x T_CK/ 2 - 0.7

3 x T_CK/ 2 + 0.8

—

ns

—

ns

1

The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE

T_CSSand T_CSHare configured by the FlexSPIn_FLSHAxCR1

register, the default values are shown above. Please refer to the i.MX

RT1015 Reference Manual (IMXRT1015RM) for more details.

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Electrical characteristics

SCK

T

CSS

T

CK

TCSH

CS

TDVO

SIO[0:7]

TDHO

Figure 22. FlexSPI output timing in DDR mode

4.6

Audio

This section provide information about SAI/I2S and SPDIF.

4.6.1

SAI/I2S switching specifications

This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.

All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]

= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock

and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

Table 39. Master mode SAI timing

Num

Characteristic

SAI_MCLK cycle time

Min

2 x t_sys

Max

Unit

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

—

ns

SAI_MCLK pulse width high/low

SAI_BCLK cycle time

40%

4 x t_sys

40%

—

60%

—

MCLK period

ns

SAI_BCLK pulse width high/low

SAI_BCLK to SAI_FS output valid

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

60%

15

BCLK period

ns

0

—

15

SAI_BCLK to SAI_TXD invalid

0

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

15

—

0

—

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Electrical characteristics

Figure 23. SAI timing—master modes

Table 40. Slave mode SAI timing

Num

Characteristic

SAI_BCLK cycle time (input)

Min

4 x t_sys

Max

Unit

S11

S12

S13

S14

S15

S16

S17

S18

—

ns

SAI_BCLK pulse width high/low (input)

SAI_FS input setup before SAI_BCLK

SAI_FA input hold after SAI_BCLK

40%

10

2

60%

—

BCLK period

ns

—

SAI_BCLK to SAI_TXD/SAI_FS output valid

SAI_BCLK to SAI_TXD/SAI_FS output invalid

SAI_RXD setup before SAI_BCLK

—

0

20

—

10

2

—

SAI_RXD hold after SAI_BCLK

—

Figure 24. SAI timing—slave modes

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Electrical characteristics

4.6.2

SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 41 and Figure 25 and Figure 26 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

Table 41. SPDIF timing parameters

Timing parameter range

Characteristics

Symbol

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

ns

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT1 output (Load = 30pf)

• Skew

• Transition rising

—

ns

—

1.5

13.6

18.0

• Transition falling

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

40.0

16.0

40.0

16.0

—

ns

srckph

srckpl

stclkp

stclkph

stclkpl

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

srckph

V_M

SPDIF_SR_CLK

V_M

(Output)

Figure 25. SPDIF_SR_CLK timing diagram

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 26. SPDIF_ST_CLK timing diagram

4.7

Analog

The following sections provide information about analog interfaces.

4.7.1

DCDC

Table 42 introduces the DCDC electrical specification.

Table 42. DCDC electrical specifications

Buck mode only, one output

3.3 V

Mode

Notes

Input voltage

Output voltage

Max loading

± 10%

1.1 V

Configurable 0.8 ~ 1.575 with 25 mV one step

500 mA

—

Loading in low power modes

Efficiency

200 A ~ 30 mA

90% max

—

@150 mA

Low power mode

Run mode

Open loop mode

Ripple is about 15 mV

Configurable by register

• Always continuous mode

• Support discontinuous mode

Inductor

4.7 H

33 F

1.6 V

—

Capacitor

Over voltage protection

Detect VDDSOC, when the voltage is higher

than 1.6 V, shutdown DCDC.

Over Current protection

Low battery detection

1 A

Detect the peak current

• Run mode: when the current is larger than

1 A, shutdown DCDC.

• Stop mode: when the current is larger than

250 mA, stop charging the inductor.

2.6 V

Detect the battery, when battery is lower than

2.6 V, shutdown DCDC.

4.7.2

A/D converter

This section introduces information about A/D converter.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

4.7.2.1

12-bit ADC electrical characteristics

The section provide information about 12-bit ADC electrical characteristics.

4.7.2.1.1

12-bit ADC operating conditions

Table 43. 12-bit ADC operating conditions

Typ¹

Characteristic

Conditions

Absolute

Symb

Min

Max

Unit

Comment

Supply voltage

V_DDA

3.0

-

3.6

V

—

Delta to VDD

(VDD-VDDA)²

V_DDA

-100

0

100

mV

Ground voltage

Delta to VSS

V_SSAD

-100

0

100

mV

—

(VSS-VSSAD)

Ref Voltage High

Ref Voltage Low

Input Voltage

—

V_DDA

V_SS

1.13

V_SS

—

V_DDA

V_SS

—

V_DDA

V_SS

V_DDA

2

V

—

V

—

V_ADIN

C_ADIN

R_ADIN

V

Input Capacitance

Input Resistance

8/10/12 bit modes

ADLPC=0, ADHSC=1

ADLPC=0, ADHSC=0

ADLPC=1, ADHSC=0

1.5

5

pF

—

7

kohms

—

12.5

25

15

—

30

Analog Source

Resistance

12 bit mode f_ADCK

40MHz ADLSMP=0,

=

R_AS

—

1

T_samp=150

ns

ADSTS=10, ADHSC=1

R_ASdepends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum

Sample Time vs R_AS

ADC Conversion Clock ADLPC=0, ADHSC=1

f_ADCK

4

—

40

30

20

MHz

—

Frequency

12 bit mode

ADLPC=0, ADHSC=0

12 bit mode

ADLPC=1, ADHSC=0

12 bit mode

1

2

Typical values assume VDDAD = 3.0 V, Temp = 25°C, f_ADCK=20 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

DC potential differences

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NXP Semiconductors

Electrical characteristics

Figure 27. 12-bit ADC input impedance equivalency diagram

12-bit ADC characteristics

Table 44. 12-bit ADC characteristics (V

= V

, V

= V

)

SSAD

REFH

DDA

REFL

Characteristic

Conditions¹

Symb

I_DDA

Min

Typ²

Max

Unit

Comment

Supply Current

ADLPC=1,

ADHSC=0

—

250

350

400

0.01

—

µA

ADLSMP= 0,ADSTS

= 10, ADCO = 1

ADLPC=0,

ADHSC=0

ADLPC=0,

ADHSC=1

Supply Current

Stop, Reset, Module I_DDA

Off

—

0.8

µA

—

ADC Asynchronous

Clock Source

ADHSC=0

ADHSC=1

f_ADACK

—

10

20

—

MHz

t_ADACK= 1/f_ADACK

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

Table 44. 12-bit ADC characteristics (V

= V

, V

= V

) (continued)

Unit Comment

REFH

DDA

REFL

SSAD

Characteristic

Conditions¹

Symb

Min

Typ²

Max

Sample Cycles

ADLSMP=0,

Csamp

—

2

—

cycles

—

ADSTS=00

ADLSMP=0,

ADSTS=01

4

ADLSMP=0,

ADSTS=10

6

ADLSMP=0,

ADSTS=11

8

ADLSMP=1,

ADSTS=00

12

16

20

24

28

30

32

34

38

42

46

50

ADLSMP=1,

ADSTS=01

ADLSMP=1,

ADSTS=10

ADLSMP=1,

ADSTS=11

Conversion Cycles

ADLSMP=0

ADSTS=00

Cconv

—

cycles

—

ADLSMP=0

ADSTS=01

ADLSMP=0

ADSTS=10

ADLSMP=0

ADSTS=11

ADLSMP=1

ADSTS=00

ADLSMP=1

ADSTS=01

ADLSMP=1

ADSTS=10

ADLSMP=1,

ADSTS=11

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

) (continued)

Table 44. 12-bit ADC characteristics (V

= V

, V

= V

REFL SSAD

REFH

DDA

Characteristic

Conditions¹

Symb

Tconv

Min

Typ²

0.7

Max

Unit

Comment

Conversion Time

ADLSMP=0

—

µs

Fadc = 40 MHz

ADSTS=00

ADLSMP=0

ADSTS=01

0.75

0.8

ADLSMP=0

ADSTS=10

ADLSMP=0

ADSTS=11

0.85

0.95

1.05

1.15

1.25

ADLSMP=1

ADSTS=00

ADLSMP=1

ADSTS=01

ADLSMP=1

ADSTS=10

ADLSMP=1,

ADSTS=11

Total Unadjusted

Error

12 bit mode

10 bit mode

8 bit mode

TUE

—

3.4

1.5

1.2

—

LSB

1 LSB =

AVGE = 1, AVGS = 11

(V_REFH

V_REFL)/2

N

-

Differential

Non-Linearity

12 bit mode

10bit mode

8 bit mode

DNL

INL

—

0.76

0.36

0.14

2.78

0.61

0.14

-1.14

-0.25

-0.19

-1.06

-0.03

-0.02

10.7

—

LSB

AVGE = 1, AVGS = 11

Integral Non-Linearity 12 bit mode

10bit mode

8 bit mode

Zero-Scale Error

Full-Scale Error

12 bit mode

10bit mode

8 bit mode

12 bit mode

10bit mode

8 bit mode

E_ZS

E_FS

Effective Number of 12 bit mode

Bits

ENOB

SINAD

10.1

Bits

dB

AVGE = 1, AVGS = 11

Signal to Noise plus See ENOB

Distortion

SINAD = 6.02 x ENOB + 1.76

1

All accuracy numbers assume the ADC is calibrated with V_REFH=V_DDAD

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

2

Typical values assume V_DDAD= 3.0 V, Temp = 25°C, F_adck=20 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

NOTE

The ADC electrical spec is met with the calibration enabled configuration.

Figure 28. Minimum Sample Time Vs Ras (Cas = 2 pF)

Figure 29. Minimum Sample Time Vs Ras (Cas = 5 pF)

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Electrical characteristics

Figure 30. Minimum Sample Time Vs Ras (Cas = 10 pF)

4.8

Communication interfaces

The following sections provide the information about communication interfaces.

4.8.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% V and 80% V thresholds, unless noted, as well as input

DD

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Table 45. LPSPI Master mode timing

Number

Symbol

Description

Frequency of operation

Min.

Max.

Units

Note

1

2

3

4

5

6

7

8

9

f_SCK

t_SCK

t_Lead

t_Lag

t_WSCK

t_SU

—

f_periph/ 2

Hz

ns

2

SCK period

2 x t_periph

—

8

Enable lead time

1

t_periph

ns

—

Enable lag time

1

Clock (SCK) high or low time

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SCK edge)

Data hold time (outputs)

t_SCK/ 2 - 3

10

2

ns

t_HI

ns

t_V

—

0

ns

t_HO

—

ns

1

2

Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for f_periphmust be

guaranteed this limit is not exceeded.

t_periph= 1 / f_periph

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Electrical characteristics

1

PCS

(OUTPUT)

3

2

4

SCK

(CPOL=0)

(OUTPUT)

5

SCK

(CPOL=1)

(OUTPUT)

6

7

SIN

(INPUT)

2

LSB IN

BIT 6 . . . 1

MSB IN

8

9

SOUT

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 31. LPSPI Master mode timing (CPHA = 0)

1

PCS

(OUTPUT)

2

4

3

SCK

(CPOL=0)

(OUTPUT)

5

7

SCK

(CPOL=1)

(OUTPUT)

6

SIN

(INPUT)

MSB IN²

BIT 6 . . . 1

LSB IN

9

8

MASTER MSB OUT²

SOUT

(OUTPUT)

PORT DATA

BIT 6 . . . 1

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 32. LPSPI Master mode timing (CPHA = 1)

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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Electrical characteristics

s

Table 46. LPSPI Slave mode timing

Number

Symbol

Description

Frequency of operation

Min.

Max.

Units

Note

1

2

f_SCK

t_SCK

t_Lead

t_Lag

t_WSCK

t_SU

0

f_periph/ 2

—

Hz

ns

2

SCK period

2 x t_periph

3

Enable lead time

1

—

t_periph

ns

—

4

Enable lag time

1

—

5

Clock (SCK) high or low time

Data setup time (inputs)

Data hold time (inputs)

Slave access time

t_SCK/ 2 - 5

—

6

2.7

3.8

—

0

—

ns

7

t_HI

—

ns

—

3

8

t_a

t_periph

14.5

—

ns

4

9

t_dis

Slave MISO disable time

Data valid (after SCK edge)

Data hold time (outputs)

ns

10

11

t_V

ns

—

t_HO

ns

1

Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for f_periphmust be

guaranteed this limit is not exceeded.

2

3

4

t_periph= 1 / f_periph

Time to data active from high-impedance state

Hold time to high-impedance state

PCS

(INPUT)

2

4

SCK

(CPOL=0)

(INPUT)

5

3

SCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

SIN

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

SOUT

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 33. LPSPI Slave mode timing (CPHA = 0)

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Electrical characteristics

PCS

(INPUT)

4

2

3

SCK

(CPOL=0)

(INPUT)

5

SCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

SIN

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

8

6

7

SOUT

MSB IN

(INPUT)

NOTE: Not defined

Figure 34. LPSPI Slave mode timing (CPHA = 1)

4.8.2

LPI2C module timing parameters

This section describes the timing parameters of the LPI2C module.

Table 47. LPI2C module timing parameters

Symbol

Description

Standard mode (Sm)

Min

Max

100

Unit

Notes

1, 2

f_SCL

SCL clock frequency

0

kHz

Fast mode (Fm)

400

Fast mode Plus (Fm+)

Ultra Fast mode (UFm)

High speed mode (Hs-mode)

1000

5000

3400

1

Hs-mode is only supported in slave mode.

See General switching specifications.

2

4.8.2.1

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 20,

"Single voltage GPIO DC parameters," on page 26.

4.8.3

LPUART electrical specifications

Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

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Electrical characteristics

4.8.4

USB PHY parameters

This section describes the USB-OTG PHY parameters.

The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision

2.0 OTG with the following amendments.

•

USB ENGINEERING CHANGE NOTICE

— Title: 5V Short Circuit Withstand Requirement Change

— Applies to: Universal Serial Bus Specification, Revision 2.0

Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

USB ENGINEERING CHANGE NOTICE

•

— Title: Pull-up/Pull-down resistors

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

•

— Title: Suspend Current Limit Changes

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

— Title: USB 2.0 Phase Locked SOFs

— Applies to: Universal Serial Bus Specification, Revision 2.0

On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

— Revision 2.0 plus errata and ecn June 4, 2010

Battery Charging Specification (available from USB-IF)

— Revision 1.2, December 7, 2010

•

— Portable device only

4.9

Timers

This section provide information on timers.

4.9.1

Pulse Width Modulator (PWM) characteristics

This section describes the electrical information of the PWM.

Table 48. PWM timing parameters

Parameter

Symbo

Min

Typ

Max

Unit

PWM Clock Frequency

Power-up Time

—

80

—

120

—

MHz

t_pu

25

s

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Electrical characteristics

4.9.2

Quad timer timing

Table 49 listed the timing parameters.

Table 49. Quad Timer Timing

Min¹

Characteristic

Symbo

Max

Unit

See Figure

Timer input period

T_IN

T_INHL

T_OUT

2T + 6

—

ns

Timer input high/low period

Timer output period

1T + 3

33

Timer output high/low period

T_OUTHL

16.7

1

T = clock cycle. For 60 MHz operation, T = 16.7 ns.

4IMER )NPUTS

4

).(,

4

).

4IMER /UTPUTS

4

/54(,

4

/54

Figure 35. Quad timer timing

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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56

Boot mode configuration

5 Boot mode configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot mode configuration pins

Table 50 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1015

Fuse Map document and the System Boot chapter in i.MX RT1015 Reference Manual (IMXRT1015RM).

Table 50. Fuses and associated pins used for boot

Pad

Default setting on reset

eFuse name

Details

GPIO_EMC_16

GPIO_EMC_17

GPIO_EMC_18

GPIO_EMC_19

GPIO_EMC_20

GPIO_EMC_21

GPIO_EMC_22

GPIO_EMC_23

GPIO_EMC_24

GPIO_EMC_25

GPIO_EMC_26

GPIO_EMC_27

100 K pull-down

src.BOOT_MODE0

src.BOOT_MODE1

src.BT_CFG[0]

src.BT_CFG[1]

src.BT_CFG[2]

src.BT_CFG[3]

src.BT_CFG[4]

src.BT_CFG[5]

src.BT_CFG[6]

src.BT_CFG[7]

src.BT_CFG[8]

src.BT_CFG[9]

Boot Options, Pin value overrides fuse

settings for BT_FUSE_SEL = ‘0’.

Signal Configuration as Fuse Override

Input at Power Up.

These are special I/O lines that control

the boot up configuration during

product development. In production,

the boot configuration can be

controlled by fuses.

5.2

Boot device interface allocation

The following tables list the interfaces that can be used by the boot process in accordance with the specific

boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

Table 51. Boot through FlexSPI

PAD Name

GPIO_SD_B1_00

IO Function

flexspi.B_DATA[3]

Mux Mode

Comments

ALT 1

—

GPIO_SD_B1_03

GPIO_SD_B1_04

GPIO_SD_B1_02

flexspi.B_DATA[2]

flexspi.B_DATA[1]

flexspi.B_DATA[0]

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Boot mode configuration

PAD Name

Table 51. Boot through FlexSPI (continued)

IO Function Mux Mode

flexspi.B_SCLK

Comments

GPIO_SD_B1_01

GPIO_SD_B0_05

GPIO_SD_B0_04

GPIO_SD_B0_01

GPIO_SD_B1_05

GPIO_SD_B1_11

GPIO_SD_B0_00

GPIO_SD_B1_07

GPIO_SD_B1_08

GPIO_SD_B1_10

GPIO_SD_B1_09

GPIO_SD_B1_06

ALT 1

ALT 6

ALT 1

ALT 6

ALT 1

—

flexspi.B_DQS

flexspi.B_SS0_B

flexspi.B_SS1_B

flexspi.A_DQS

flexspi.A_SS0_B

flexspi.A_SS1_B

flexspi.A_SCLK

flexspi.A_DATA[0]

flexspi.A_DATA[1]

flexspi.A_DATA[2]

flexspi.A_DATA[3]

Table 52. Boot through FlexSPI (second option)

IO Function Mux Mode

flexspi.A_DATA[3]

PAD Name

Comments

GPIO_AD_B1_00

GPIO_AD_B1_01

GPIO_AD_B1_02

GPIO_AD_B1_03

GPIO_AD_B1_04

GPIO_AD_B1_05

ALT 1

—

flexspi.A_SCLK

flexspi.A_DATA[0]

flexspi.A_DATA[2]

flexspi.A_DATA[1]

flexspi.A_SS0_B

Table 53. FlexSPI reset

PAD Name

IO Function

Mux Mode

Comments

GPIO_AD_B1_13

gpio1.IO[29]

ALT 5

—

Table 54. Boot through SPI-1

IO Function

PAD Name

GPIO_AD_B0_10

GPIO_AD_B0_11

GPIO_AD_B0_12

GPIO_AD_B0_13

lpspi1.SCK

lpspi1.PCS0

lpspi1.SDO

lpspi1.SDI

ALT 1

—

ALT 1

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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58

Boot mode configuration

Comments

Table 55. Boot through SPI-2

IO Function

PAD Name

GPIO_SD_B1_07

Mux Mode

lpspi2.SCK

lpspi2.SDO

lpspi2.SDI

ALT 4

—

GPIO_SD_B1_08

GPIO_SD_B1_09

GPIO_SD_B1_06

ALT 4

lpspi2.PCS0

Table 56. Boot through UART1

IO Function

PAD Name

Comments

GPIO_AD_B0_06

GPIO_AD_B0_07

GPIO_AD_B0_08

GPIO_AD_B0_09

lpuart1.TX

ALT 2

—

lpuart1.RX

ALT 2

lpuart1.CTS_B

lpuart1.RTS_B

Table 57. Boot through UART2

IO Function

PAD Name

Comments

GPIO_AD_B1_06

GPIO_AD_B1_07

GPIO_AD_B1_08

GPIO_AD_B1_09

lpuart2.CTS_B

lpuart2.RTS_B

lpuart2.TX

ALT 2

—

ALT 2

lpuart2.RX

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

59

Package information and contact assignments

6 Package information and contact assignments

This section includes the contact assignment information and mechanical package drawing.

6.1

14 x 14 mm package information

14 x 14 mm, 0.5 mm pitch, ball matrix

6.1.1

Figure 36 shows the top and side views of the 14 x 14 mm LQFP package.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

60

NXP Semiconductors

Package information and contact assignments

ꢁ

ꢊM

ꢋꢅꢆM ꢇM

3M ꢃꢁM

ꢃꢈM <'6:M

ꢀEM

ꢉ

ꢀEM

ꢁꢂꢃꢁM %M ꢄꢅꢆM ꢇM

3M

7'0M ꢌM '0ꢇꢍFꢎKM

ꢀꢀꢁꢀꢀ

ꢀꢂꢁ ꢃꢄꢅꢂꢆꢁ ꢁꢇꢁꢈꢉꢊ

ꢀꢁ

ꢇꢈꢉ

ꢀꢁꢁꢁꢁꢁꢁꢂꢃꢄꢅꢆꢆꢆꢆꢆ

A'ꢍDM ꢋ

L

ꢀꢁ ꢄꢅꢆ

ꢂꢃ

ꢇꢃ

ꢀꢁꢂꢃꢄꢌꢃHꢏM

ꢀꢁ

ꢂ

ꢁ

_:ꢍꢊ<'0#Mꢀꢁ _ꢀꢈꢉ_ꢁꢊꢋꢌꢃ ꢍꢎꢏꢐꢃ

ꢀ

ꢌꢁꢐEM

ꢁM

ꢑꢒꢓ

ꢀꢁꢂꢃꢄꢅ

ꢉM

IM

JM

Jꢔ

6+ꢊ0ꢍM

ꢑꢅꢒꢆꢃ ꢄꢅꢆꢇꢃ

Figure 36. 14 x 14 mm LQFP, case x package top and side Views

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

61

Package information and contact assignments

6.1.2

14 x 14 mm supplies contact assignments and functional contact

assignments

Table 58 shows the device connection list for ground, sense, and reference contact signals.

Table 58. 14 x 14 mm supplies contact assignment

Supply Rail Name

Pin(s) Position(s)

Remark

DCDC_IN

23

27

24

25

—

DCDC_IN_Q

DCDC_GND

DCDC_LP

DCDC_PSWITCH 26

NVCC_GPIO

NGND_KEL0

NVCC_PLL

5, 20, 58, 71, 80, 95

43

50

44

48

VDD_HIGH_CAP

VDD_HIGH_IN

VDD_SNVS_CAP 35

VDD_SNVS_IN

VDD_SOC_IN

VDD_USB_CAP

VDDA_ADC_3P3

VSS

34

18, 28, 69, 81, 91

40

51

19, 29, 39, 49, 59, 70, 79, 92

Table 59 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.

Table 59. 14 x 14 mm functional contact assignments

Default Setting

14 x 14

Power

Group

Type

Pin Name

Default

Mode

Default

Function

Input/

Output

Value

GPIO_AD_B0_00

GPIO_AD_B0_01

GPIO_AD_B0_02

GPIO_AD_B0_03

GPIO_AD_B0_04

78

77

76

75

74

NVCC_GPIO

Digital

GPIO

ALT0

jtag_mux.TMS

Input

47 K PU

Digital

GPIO

jtag_mux.TCK

jtag_mux.MOD

jtag_mux.TDI

jtag_mux.TDO

100 K PD

47 K PU

Keeper

Digital

GPIO

Digital

GPIO

Digital

GPIO

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

62

Package information and contact assignments

Table 59. 14 x 14 mm functional contact assignments (continued)

GPIO_AD_B0_05

GPIO_AD_B0_06

GPIO_AD_B0_07

GPIO_AD_B0_08

GPIO_AD_B0_09

GPIO_AD_B0_10

GPIO_AD_B0_11

GPIO_AD_B0_12

GPIO_AD_B0_13

GPIO_AD_B0_14

GPIO_AD_B0_15

GPIO_AD_B1_10

GPIO_AD_B1_11

GPIO_AD_B1_12

GPIO_AD_B1_13

GPIO_AD_B1_14

GPIO_AD_B1_15

GPIO_EMC_04¹

GPIO_EMC_05

73

72

68

67

66

65

64

63

62

61

60

57

56

55

54

53

52

7

NVCC_GPIO

Digital

GPIO

ALT0

ALT5

jtag_mux.TRSTB

GPIO1.IO[6]

GPIO1.IO[7]

GPIO1.IO[8]

GPIO1.IO[9]

GPIO1.IO[10]

GPIO1.IO[11]

GPIO1.IO[12]

GPIO1.IO[13]

GPIO1.IO[14]

GPIO1.IO[15]

GPIO1.IO[26]

GPIO1.IO[27]

GPIO1.IO[28]

GPIO1.IO[29]

GPIO1.IO[30]

GPIO1.IO[31]

GPIO2.IO[4]

GPIO2.IO[5]

GPIO2.IO[6]

GPIO2.IO[7]

Input

47 K PU

Keeper

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

6

Digital

GPIO

GPIO_EMC_06

4

Digital

GPIO

GPIO_EMC_07

3

Digital

GPIO

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

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63

Package information and contact assignments

Table 59. 14 x 14 mm functional contact assignments (continued)

GPIO_EMC_08

GPIO_EMC_09

GPIO_EMC_16

GPIO_EMC_17

GPIO_EMC_18

GPIO_EMC_19

GPIO_EMC_20

GPIO_EMC_21

GPIO_EMC_22

GPIO_EMC_23

GPIO_EMC_24

GPIO_EMC_25

GPIO_EMC_26

GPIO_EMC_27

GPIO_EMC_32

GPIO_EMC_33

GPIO_EMC_34

GPIO_EMC_35

GPIO_SD_B1_00

GPIO_SD_B1_01

GPIO_SD_B1_02

2

NVCC_GPIO

Digital

GPIO

ALT5

ALT6

ALT5

GPIO2.IO[8]

Input

Keeper

100 k PD

Keeper

1

Digital

GPIO

GPIO2.IO[9]

100

99

98

97

96

94

93

90

89

88

87

86

85

84

83

82

22

21

17

Digital

GPIO

src.BOOT_MODE[0]

src.BOOT_MODE[1]

GPIO2.IO[18]

GPIO2.IO[19]

GPIO2.IO[20]

GPIO2.IO[21]

GPIO2.IO[22]

GPIO2.IO[23]

GPIO2.IO[24]

GPIO2.IO[25]

GPIO2.IO[26]

GPIO2.IO[27]

GPIO3.IO[0]

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

GPIO3.IO[1]

Digital

GPIO

GPIO3.IO[2]

Digital

GPIO

GPIO3.IO[3]

Digital

GPIO

GPIO3.IO[20]

GPIO3.IO[21]

GPIO3.IO[22]

Digital

GPIO

Digital

GPIO

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

64

Package information and contact assignments

Table 59. 14 x 14 mm functional contact assignments (continued)

GPIO_SD_B1_03

GPIO_SD_B1_04

GPIO_SD_B1_05

GPIO_SD_B1_06

GPIO_SD_B1_07

GPIO_SD_B1_08

GPIO_SD_B1_09

GPIO_SD_B1_10

GPIO_SD_B1_11

ONOFF

16

15

14

13

12

11

10

9

NVCC_GPIO

VDD_SNVS_IN

Digital

GPIO

ALT5

ALT0

GPIO3.IO[23]

GPIO3.IO[24]

GPIO3.IO[25]

GPIO3.IO[26]

GPIO3.IO[27]

GPIO3.IO[28]

GPIO3.IO[29]

GPIO3.IO[30]

GPIO3.IO[31]

src.RESET_B

Input

Keeper

100 K PU

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

8

Digital

GPIO

30

33

31

Digital

GPIO

PMIC_ON_REQ

POR_B

Digital

GPIO

snvs_lp.PMIC_ON_REQ Input

Digital

GPIO

src.POR_B

Output 100 K PU

RTC_XTALI

RTC_XTALO

TEST_MODE

36

37

32

—

VDD_SNVS_IN

Digital

GPIO

ALT0

tcu.TEST_MODE

Input

100 K PD

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_VBUS

XTALI

45

41

42

38

46

47

—

XTALO

1

This pin output is in a high level until the system reset is complete.

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

65

Package information and contact assignments

6.1.3

14 x 14 mm package pin assignments

Figure 37 shows the pin assignments of the 14 x 14 mm package.

ꢉ

ꢇꢀ

ꢇꢈ

ꢇꢂ

ꢇꢁ

ꢇꢉ

ꢇꢄ

ꢃꢅ

ꢃꢆ

ꢃꢇ

ꢃꢃ

ꢃꢀ

ꢃꢈ

ꢃꢂ

ꢃꢁ

ꢃꢉ

ꢃꢄ

ꢀꢅ

ꢀꢆ

ꢀꢇ

ꢀꢃ

ꢀꢀ

ꢀꢈ

ꢀꢂ

ꢀꢁ

ꢀꢉ

'0)/?%-#?ꢄꢅ

'0)/?%-#?ꢄꢆ

'0)/?%-#?ꢄꢇ

'0)/?%-#?ꢄꢃ

.6##?'0)/

'0)/?!$?"ꢄ?ꢄꢂ

'0)/?!$?"ꢄ?ꢄꢈ

'0)/?!$?"ꢄ?ꢄꢀ

'0)/?!$?"ꢄ?ꢄꢃ

.6##?'0)/

ꢁ

ꢂ

ꢈ

ꢀ

ꢃ

633

'0)/?%-#?ꢄꢀ

'0)/?%-#?ꢄꢈ

'0)/?3$?"ꢉ?ꢉꢉ

'0)/?3$?"ꢉ?ꢉꢄ

'0)/?3$?"ꢉ?ꢄꢅ

'0)/?3$?"ꢉ?ꢄꢆ

'0)/?3$?"ꢉ?ꢄꢇ

'0)/?3$?"ꢉ?ꢄꢃ

'0)/?3$?"ꢉ?ꢄꢀ

'0)/?3$?"ꢉ?ꢄꢈ

'0)/?3$?"ꢉ?ꢄꢂ

'0)/?3$?"ꢉ?ꢄꢁ

6$$?3/#?).

633

ꢇ

6$$?3/#?).

ꢆ

'0)/?!$?"ꢄ?ꢄꢇ

'0)/?!$?"ꢄ?ꢄꢆ

'0)/?!$?"ꢄ?ꢄꢅ

'0)/?!$?"ꢄ?ꢉꢄ

'0)/?!$?"ꢄ?ꢉꢉ

'0)/?!$?"ꢄ?ꢉꢁ

'0)/?!$?"ꢄ?ꢉꢂ

'0)/?!$?"ꢄ?ꢉꢈ

'0)/?!$?"ꢄ?ꢉꢀ

633

ꢅ

ꢉꢄ

ꢉꢉ

ꢉꢁ

ꢉꢂ

ꢉꢈ

ꢉꢀ

ꢉꢃ

ꢉꢇ

ꢉꢆ

ꢉꢅ

ꢁꢄ

ꢁꢉ

ꢁꢁ

ꢁꢂ

ꢁꢈ

ꢁꢀ

.6##?'0)/

'0)/?!$?"ꢉ?ꢉꢄ

'0)/?!$?"ꢉ?ꢉꢉ

'0)/?!$?"ꢉ?ꢉꢁ

'0)/?!$?"ꢉ?ꢉꢂ

'0)/?!$?"ꢉ?ꢉꢈ

'0)/?!$?"ꢉ?ꢉꢀ

6$$!?!$#?ꢂ0ꢂ

.6##?'0)/

'0)/?3$?"ꢉ?ꢄꢉ

'0)/?3$?"ꢉ?ꢄꢄ

$#$#?).

$#$#?'.$

$#$#?,0

Figure 37. The pin assignments of the 14 x 14 mm package

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

66

Revision history

7 Revision history

Table 60 provides a revision history for this data sheet.

Table 60. i.MX RT1015 data sheet document revision history

Rev. Number

Date

Substantive Change(s)

Rev. 2

03/2021

• Updated the M7 Core and external memory descriptions in the Section 1.1, Features

• Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the frequency of RTC OSC and baud rates of LPUART in the Table 2, i.MX

RT1015 modules list

• Updated the descriptions about TEST_MODE in the Table 3, Special signal

considerations

• Added system and bus frequencies in the Table 9, Operating ranges

• Updated the test conditions and max current of DCDC_IN in the Table 11, Maximum

supply currents

• Added a note in the Section 4.2.1.1, Power-up sequence

• Updated the value of reference clock in the Table 16, Ethernet PLL’s electrical

parameters

• Added the high-level and low-level output current in the Table 20, Single voltage GPIO

DC parameters

• Added a footnote for GPIO_EMC_04 in the Table 59, 14 x 14 mm functional contact

assignments

Rev. 1

04/2019

03/2019

• Updated the SNVS descriptions in the Table 2, i.MX RT1015 modules list

• Updated the Section 4.8.1, LPSPI timing parameters

Rev. 0.1

• Added audio information in the Section 1, i.MX RT1015 introduction

• Updated FlexPWMs and Quadrature Encoder/Decoder in the Section 1.1, Features

• Updated the Table 1, Ordering information

• Updated keypad and GP timer numbers in the Figure 2, "i.MX RT1015 system block

diagram"

• Changed keypad to 4 x 4 in the Table 2, i.MX RT1015 modules list

• Removed the USB OTG2 from the Table 2, i.MX RT1015 modules list, Table 7, Absolute

maximum ratings, and Section 4.2.1.1, Power-up sequence

• Updated on-chip termination information for the JTAG_TCK and JTAG_MOD in the

Table 4, JTAG controller interface summary

• Updated descriptions in the Section 4.2.2.2.3, LDO_USB

• Changed the 528 MHz PLL to System PLL in the Table 15, System PLL’s electrical

parameters

• Changed the 480 MHz PLL to USB PLL in the Table 17, USB PLL’s electrical

parameters

Rev. 0

01/2019

• Initial version

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021

NXP Semiconductors

67

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is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other

industrial or intellectual property rights.

Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V

may appear when operating this product, depending on settings and application. Customers incorporating or otherwise

using these products in applications where such high voltages may appear during operation, assembly, test etc. of such

application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting

from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60

950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.

Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up

to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation

conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are

no post-packing tests performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.

Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems

after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and

qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering

into a written die sale agreement with NXP Semiconductors through its legal department.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and

Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein may be subject to export control regulations.

Export might require a prior authorization from competent authorities.

Evaluation products —This product is provided on an “as is” and “with all faults” basis for evaluation purposes only.

NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or

statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a

particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with

customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special,

indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business,

business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the

product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or

any other theory, even if advised of the possibility of such damages.

Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all

damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates

and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred

by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product

or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent

permitted by applicable law, even if any remedy fails of its essential purpose.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail

in case of any discrepancy between the translated and English versions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,EMBRACE,

GREENCHIP, HITAG, ICODE, JCOP, LIFE, VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE

PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX,

SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, CodeWarrior, ColdFire,

ColdFire+, the Energy Efficient Solutions logo, Kinetis, Layerscape, mobileGT, PEG, PowerQUICC, Processor Expert,

QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,

BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, Tower, TurboLink, EdgeScale, EdgeLock,

eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names are the property of their

respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight,

Table continues on the next page...

Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,

Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks

or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may

registered trademarks of Oracle and/or its affiliates. M, M Mobileye and other Mobileye trademarks or logos appearing

herein are trademarks of Mobileye Vision Technologies Ltd. in the United States, the EU and/or other jurisdictions.

©

NXP B.V. 2021.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 April 2021

Document identifier: IMXRT1015CEC


型号：	PIMXRT106FDVN4A
厂家：	NXP
描述：	i.MX RT1015 Crossover Processors Data Sheet for Consumer Products
文件：	总71页 (文件大小：1093K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIMXRT106FDVN4A [NXP]

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