PIMXRT595SFFOXCR [NXP]

i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum;


型号：	PIMXRT595SFFOXCR
厂家：	NXP
描述：	i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum
文件：	总119页 (文件大小：1702K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Document Number: IMXRT500EC

Rev. 0.1, 04/2021

NXP Semiconductors

Data Sheet

i.MX RT500 Low-Power

Crossover Processor Data Sheet with

Addendum

Rev. 0.1 of the i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum has two parts:

•

Revision 0 of the data sheet, immediately following this cover page. The changes described in the

addendum have not been implemented in the specified pages.

•

The addendum to revision 0 of the data sheet.

NXP Semiconductors

IMXRT500EC

Data Sheet: Technical Data

Rev. 0, 02/2021

i.MX RT500 Low-Power

Crossover Processor

MIMXRT5XXSFFOC

MIMXRT5XXSFFOCR

MIMXRT5XXSFAWCR

The i.MX RT500 is a family of dual-core microcontrollers for

embedded applications featuring an Arm Cortex-M33 CPU

combined with a Cadence® Xtensa® Fusion F1 Audio Digital

Signal Processor CPU. The Cortex-M33 includes two hardware

coprocessors providing enhanced performance for an array of

complex algorithms along with a 2D Vector GPU with LCD

Interface and MIPI DSI PHY. The family offers a rich set of

peripherals and very low power consumption. The device has up

to 5 MB SRAM, two FlexSPIs (Octal/Quad SPI Interfaces) each

with 32 KB cache, one with dynamic decryption, high-speed USB

device/host + PHY, 12-bit 1 MS/s ADC, Analog Comparator,

Audio subsystems supporting up to 8 DMIC channels, 2D GPU

and LCD Controller with MIPI DSI PHY, SDIO/eMMC; FlexIO;

AES/SHA/Crypto M33 coprocessor and PUF key generation

249 FOWLP 7.0mm x 141 WLCSP 4.525mm

7.0mm x 0.725mm, x 4.525mm x 0.49mm,

0.4mm pitch

0.35mm pitch

Control processor core

Communication interface

• Arm Cortex-M33 processor, running at frequencies of

up to 200 MHz

• Arm TrustZone

• Arm Cortex-M33 built-in Memory Protection Unit (MPU)

supporting eight regions

• Single-precision Hardware Floating Point Unit (FPU).

• Arm Cortex-M33 built-in Nested Vectored Interrupt

Controller (NVIC).

• Non-maskable Interrupt (NMI) input.

• Two coprocessors for the Cortex-M33: a hardware

accelerator for fixed and floating point DSP functions

(PowerQuad) and a Crypto/FFT engine (Casper). The

DSP coprocessor uses a bank of four dedicated 2 KB

SRAMs. The Crypto/FFT engine uses a bank of two 2

KB SRAMs that are also AHB accessible by the CPU

and the DMA engine.

• Serial Wire Debug with eight break points, four watch

points, and a debug timestamp counter. It includes

Serial Wire Output (SWO) trace and ETM trace.

• Cortex-M33 System tick timer

• 9 configurable universal serial interface modules

(Flexcomm Interfaces). Each module contains an

integrated FIFO and DMA support. Each of the nine

modules can be configured as:

• A USART with dedicated fractional baud rate

generation and flow-control handshaking

signals. The USART can optionally be clocked

at 32 kHz and operated when the chip is in

reduced power mode, using either the 32 kHz

clock or an externally supplied clock. The

USART also provides partial support for

LIN2.2.

• An I2C-bus interface with multiple address

recognition, and a monitor mode. It supports

400 Kb/sec Fast-mode and 1 Mb/sec Fast-

mode Plus. It also supports 3.4 Mb/sec high-

speed when operating in slave mode.

• An SPI interface.

• An I2S (Inter-IC Sound) interface for digital

audio input or output. Each I2S supports up to

four channel-pairs.

DSP processor core

• Two additional high-speed SPI interfaces supporting

50 MHz operation

• One additional I2C interface with open-drain pads

• Two I3C bus interfaces

• Cadence Tensilica Fusion F1 DSP processor, running

at frequencies of up to 200 MHz.

• Hardware Floating Point Unit.

• Serial Wire Debug (shared with Cortex-M33 Control

Domain CPU).

• A digital microphone interface supporting up to 8

channels with associated decimators and Voice

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Five I/O Power Rails

Activation Detect. One pair of channels can be

streamed directly to I2S. The DMIC supports DMA.

• Five independent supplies powering different clusters

of pins to permit interfacing directly to off-chip

peripherals operating at different supply levels.

Timers

• One 32-bit SCTimer/PWM module (SCT). Multi-

purpose timer with extensive event-generation,

match/compare, and complex PWM and output

control features.

On-chip memory

• Up to 5 MB of system SRAM accessible by both CPUs,

both DMA engines, the Graphics Subsystem and all

other AHB masters.

• Additional SRAMs for USB traffic (16 KB), Cortex-M33

co-processors (4 x 2 KB), SDIO FIFOs (2 x 512 B dual-

port), PUF secure key generation (2 KB), FlexSPI

caches (32 KB each), SmartDMA commands (32 KB),

and a variety of dual and single port RAMs for

graphics.

• 10 general-purpose/PWM outputs, 8 general-

purpose inputs

• It supports DMA and can trigger external DMA

events

• It supports fractional match values for high

resolution

• Five general purpose, 32-bit timer/counter modules

with PWM capability

• 16 kbits OTP fuses

• Up to 192 KB ROM memory for factory-programmed

drivers and APIs

• 24-bit multi-rate timer module with 4 channels each

capable of generating repetitive interrupts at

different, programmable frequencies.

• Two Windowed Watchdog Timers (WDT) with

dedicated watchdog oscillator (1 MHz LPOSC)

• Frequency measurement module to determine the

frequency of a selection of on-chip or off-chip clock

sources.

• System boot from High-speed SPI, FlexSPI Flash, HS

USB, I2C, UART or eMMC via on-chip bootloader

software included in ROM. FlexSPI boot mode will

include an option for Execute-in-place start-up for non-

secure boot.

Digital peripherals

• Real-Time Clock (RTC) with independent power

supply and dedicated oscillator. Integrated wake-up

timer can be used to wake the device up from low-

power modes. The RTC resides in the “always-on”

voltage domain. RTC includes eight 32-bit general-

purpose registers which can retain contents when

power is removed from the rest of the chip.

• Ultra-low power micro-tick Timer running from the

Watchdog oscillator with capture capability for

timestamping. Can be used to wake up the device

from low-power modes.

• Two general purpose DMA engines, each with 37

channels and up to 27 programmable request/trigger

sources.

• Can be configured such that one DMA is secure

and the other non-secure and/or one can be

designated for use by the M33 CPU and the

other by the DSP

• Smart DMA Controller with dedicated 32KB code RAM

• USB high-speed host/device controller with on-chip

PHY and dedicated DMA controller.

• Two FlexSPI (Octal/Quad) Interfaces up to 200 MHz

DDR/SDR (target). 32 KB caches with selectable

cache policies based on programmable address

regions. One of the FlexSPI interface will include on-

the-fly decryption for execute-in-place and address-

remapping to support dual-image boot. DMA supported

(both modules).

• 64-bit OS/Event Timer common to both processors

with individual match/capture and interrupt

generation logic. Enabled on POR

Clocks

• Crystal oscillator with an operating range of 4 MHz

to 26 MHz.

• Two SD/eMMC memory card interfaces with dedicated

DMA controllers. One supports eMMC 5.0 with

HS400/DDR operation.

• Dual trim option: Internal 192/96 MHz FRO

oscillator. Trimmed to 1% accuracy.

• FRO capable of being tuned using an accurate

reference clock (eg. XTAL Osc) to 0.1% accuracy

with 46% duty cycle to support MIPI PHY and

FlexSPI.

• Internal 1 MHz low-power oscillator with 5%

accuracy. Serves as the watchdog oscillator and

clock for the OS/Event Timer and the Systick among

others. Also available as the system clock to both

domains.

Analog peripherals

• One 12-bit ADC with sampling rates of 1 Msamples/sec

and an enhanced ADC controller. It supports up to 10

single-ended channels or 5 differential channels. The

ADC supports DMA.

• Temperature sensor.

• Analog comparator

• 32 kHz real-time clock (RTC) oscillator that can

optionally be used as a system clock.

• Main System PLL:

• allows CPU operation up to the maximum rate

without the need for a high-frequency crystal.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Graphics/Multimedia

May be run from the FRO, the crystal

oscillator or the CLKIN pin.

• 2D Vector Graphics Processing Unit, running at

frequencies of up to 200 MHz.

• LCD Display Interface supporting smart LCD displays

and video mode.

• MIPI DSI Interface with on-chip PHY supporting

transfer rates up to 895.1 Mbps.

• a second, independent PLL output provides

alternate high-frequency clock source for the

DSP CPU if the required frequency is different

from the main system clock. (Note: 2nd PFD

output from Main System PLL)

• FlexIO can be configured to provide a parallel interface

to an LCD

• two additional PLL outputs provide potential

clock sources to various peripherals.

• Audio PLL for the audio subsystem.

I/O Peripherals

• Up to 136 general purpose I/O (GPIO) pins with

configurable pull-up/pull-down resistors. Ports can be

written as words, half-words, bytes, or bits.

• Mirrored, secure GPIO0.

• Individual GPIO pins can be used as edge and level

sensitive interrupt sources, each with its own interrupt

vector.

• All GPIO pins can contribute to one of two ganged

(OR’d) interrupts from the GPIO_HS module.

• A group of up to 7 GPIO pins (from Port0/1) can be

selected for Boolean pattern matching which can

generate interrupts and/or drive a “pattern-match”

output.

Power Control

• Main external power supply: 1.8V 5%

• Vddcore supply (from PMIC or internal PMU):

adjustable from 0.6 V to 1.1 V (including retention

mode)

• Analog supply: 1.71-3.6 V

• Five VDDIO supplies (can be shared or

independent): 1.71 - 3.6 V

• USB Supply: 3.0-3.6 V

• Reduced power modes:

• Sleep mode: CPU clock shut down (each CPU

independently)

• Deep_sleep mode: User-selectable

configuration via PDSLEEPCFG

• Deep_powerdown mode: Internal power

removed from entire chip except “always-on”

domain

• Adjustable output driver slew rates.

• JTAG boundary scan

Security

• Secure Isolation: Protection from software and remote

attacks using Trustzone for armV8M. Hardware

isolation of AES keys

• Each individual SRAM partition can be

independently powered-off or put into a low-

power retain mode

• Secure Boot: firmware in ROM providing immutable

root of trust

• DSP Domain can be powered-off

independently from the rest of the system.

• Ability to operate the synchronous serial

interfaces in sleep or deep-sleep as a slave or

USART clocked by the 32 kHz RTC oscillator

• Wake-up from low-power modes via interrupts

from various peripherals including the RTC

and the OS/Event timer

• Secure Storage: Physically Unclonable Function

(PUF) based key store, On-the-fly-AES decryption

(OTFAD) of off-chip flash for code storage

• Secure Debug: Certificate based debug authentication

mechanism

• Secure Loader: Supports firmware update mechanism

with authenticity (RSA signed) and confidentiality

(AES-CTR encrypted) protection

• RBB/FBB to provide additional control over power/

performance trade-offs

• Secure Identity: 128-bit Universal Unique Identifier

(UUID), 256-bit Compound Device Identifier (CDI) per

TCG DICE specification

• Power-On Reset (POR).

Operating characteristics

• Temperature range (ambient): -20 °C to +70 °C

• VDDCORE: 0.7 V - 1.155 V

• VDDIO_0/1/2/4: 1.71 V - 1.89 V

• VDDIO_3: 1.71 V - 3.6 V

• Cryptographic Accelerators

• Symmetric cryptography (AES) with

128/192/256-bit key strength and protection

against Side-channel analysis (Differential Power

Analysis and Template attacks)

• Asymmetric cryptography acceleration using

CASPER co-processor

• NIST SP 800-90b compliant TRNG design with

512-bit output per call

• Hash engine with SHA-256 and SHA1

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Connectivity

System Control

CPU Platform

10x Frac rate gen

8-Ch DMIC

2x PLL

ARM® Cortex-^®M33

(up to 200 MHz)

1x I2C

FlexIO

FRO/OSC

PMC

FPU

DSP Accelerator

Crypto Accelerators

TrustZone^®M

2xMIPI-I³

GPIOs

MPU

NVIC

2x SDIO/

eMMC/SD

2x HS SPI

Semaphore

Up to 9x Flexcomm

(UART/I C/SPI/I S)

HS USB Host/Device

+ DCD w/ PHY

DSP Processor

Message unit

Timers

Fusion F1 DSP

(up to 200 MHz)

2x DMA

RTC

OS/Event Timer

2x Watch Dog

FPU

5x Counter Timers

Multi-Rate Timer

CRC engine

Multimedia

2D GPU (up to 200 MHz)

32-bit SCTimer/PWM

Frequency Measure

JTAG/SWD

System Tick Timers

MIPI^®-DSI

(2 lane)

Display LCD

Controller

Internal Memory

Upto 5 MB shared

low-leakage SRAM

Analog

External Memory

Analog Comparator

12-bit, 1MSPS ADC

2x Temp Sensor

FlexSPI(Quad/Octal) with

On-The-Fly OTFAD Decryption

192 KB ROM

2x 32 KB FlexSPI Cache

16 KB USB RAM

FlexSPI (Quad/Octal)

Security

RNG

SRAM PUF

SHA-1/SHA-2

AES-256

Available on certain product families

Figure 1. i.MX RT500 Block Diagram

The following table provides examples of orderable sample part numbers covered by this data sheet.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Orderable part number table

Orderable part

number

Part number¹

SRAM DSP Graphics Security

(MB)

USB I2S

Package

MIMXRT595SFFOC

MIMXRT555SFFOC

MIMXRT533SFFOC

MRT595SFFOC

MRT555SFFOC

MRT533SFFOC

Yes Yes

SRAM PUF, AES256, HS

HASH

FOWLP249²

FOWLP249

FOWLP249²

FOWLP249

WLCSP141

Yes

SRAM PUF, AES256, HS

HASH

SRAM PUF, AES256, HS

HASH

MIMXRT595SFFOCR MRT595SFFOC

MIMXRT555SFFOCR MRT555SFFOC

MIMXRT533SFFOCR MRT533SFFOC

MIMXRT533SFAWCR MRT533SFAWC

MIMXRT555SFAWCR MRT555SFAWC

MIMXRT595SFAWCR MRT595SFAWC

Yes Yes

SRAM PUF, AES256, HS

HASH

Yes

SRAM PUF, AES256, HS

HASH

SRAM PUF, AES256, HS

HASH

SRAM PUF, AES256, HS

HASH

Yes

SRAM PUF, AES256, HS

HASH

Yes Yes

SRAM PUF, AES256, HS

HASH

1. As marked on package

2. 249-pin Fan-out wafer-level package

Device revision number

Device Mask Set Number

SILICONREV_ID

JTAG_ID[CHIPREV]

2P43B

0x000B0002

0x2

Package markings for i.MX RT devices consist of 4 sets of identifiers as shown below.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Figure 2. Package markings

• The 1st identifier defines the Part Number and is composed of 11 characters.

• The 2nd and 4th identifiers define the Traceability markings.

• The 3rd identifier defines the Date Code for the week of manufacture is a subset of the standard 5

character format.

The standard date code format is “xYYWW”:

• The leading digit represented by “x” can be ignored and “YYWW” indicate the Date Code.

• “YY" represents an encoding of the calendar year (for example, 19 corresponds to year 2019).

• “WW” represents an encoding of the work week within the calendar year (for example, 07 corresponds to

work week 7).

Please provide this information to your local NXP representative for further details.

The following figure explains the part number for this device.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

IMXRT

# A AA

Packing Method

Reel

SiliconRevision

QualificationLevel

Rev A

Rev B

Rev C

MassProduction

Prototype

Feature4 (Optional)

Speed/Power

IMXRT

Family

Package

Series

FO FOWLP 249

AW WLCSP 141

RT500 series

TemperatureRange

-20 – 70 C

Feature1

no DSP, no Graphic

no DSP, w Graphic

w DSP, w Graphic

Reserved

Feature2 (SRAM)

Feature3

3MB

5MB

Security

Figure 3. Part number diagram

Related Resources

Description

Type

Selector Guide

The Solution Advisor is a web-based tool that features interactive application wizards and a

dynamic product selector.

Product Brief

The Product Brief contains concise overview/summary information to enable quick evaluation of a

device for design suitability.

Reference Manual The i.MX RT500 Low-Power Crossover MCU Reference Manual contains a comprehensive

description of the structure and function (operation) of a device.

Data Sheet

Chip Errata

Refers to this document which includes electrical characteristics and signal connections.

The chip mask set Errata provides additional or corrective information for a particular device mask

set.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Table of Contents

1 Electrical characteristics........................................................10

1.1 Chip-level conditions......................................................10

1.7.5

High-Speed SPI interface (Flexcomm

interface 14).....................................................51

SD/MMC and SDIO......................................... 53

DMIC subsystem............................................. 56

USB interface characteristics.......................... 57

USB DCD electrical specifications...................57

1.1.1

1.1.2

1.1.3

1.1.4

Thermal handling ratings................................. 10

Moisture handling ratings................................ 10

ESD handling ratings.......................................11

Absolute maximum voltage and current

1.7.6

1.7.7

1.7.8

1.7.9

ratings..............................................................11

Thermal specifications.....................................13

General operating conditions...........................14

I/O parameters.................................................17

Power consumption operating behavior.......... 19

CoreMark data.................................................23

1.7.10 USB High Speed Transceiver and PHY

specifications................................................... 58

1.7.11 Improved Inter-Integrated Circuit Interface

(MIPI-I3C) specifications................................. 58

1.8 Timer modules............................................................... 60

1.1.5

1.1.6

1.1.7

1.1.8

1.1.9

1.8.1

SCTimer/PWM output timing........................... 61

1.2 System power and clocks.............................................. 24

2 Architectural overview...........................................................61

2.1 Detailed block diagram.................................................. 61

2.2 Shared system SRAM................................................... 62

2.3 RT500 modules list........................................................ 63

3 Application information..........................................................72

3.1 Current consumption vs. memory partitions.................. 72

3.2 Standard I/O pin configuration....................................... 73

3.3 I/O power consumption..................................................74

3.4 RTC oscillator................................................................ 74

1.2.1

1.2.2

Power sequence..............................................24

Free-running oscillator FRO-192/96M

specifications................................................... 27

Crystal oscillator.............................................. 28

RTC oscillator.................................................. 29

External Clock Input (CLKIN) pin.....................29

Internal low-power oscillator (1 MHz).............. 29

1.2.3

1.2.4

1.2.5

1.2.6

1.3 System modules............................................................ 30

1.3.1

1.3.2

Reset timing parameters................................. 30

Serial Wire Debug (SWD) timing

3.4.1

RTC Printed Circuit Board (PCB) design

guidelines........................................................ 76

specifications .................................................. 30

JTAG timing specifications.............................. 31

Wake-up process.............................................34

3.5 XTAL oscillator...............................................................76

1.3.3

1.3.4

3.5.1

XTAL Printed Circuit Board (PCB) design

guidelines........................................................ 78

Thermally compensated crystal oscillator

(TCXO)............................................................ 79

1.4 External memory interface.............................................35

1.4.1 FlexSPI Flash interface................................... 35

1.5 Display and graphics..................................................... 38

3.5.2

3.6 Suggested USB interface solutions............................... 79

4 Abbreviations........................................................................ 81

5 Pinouts.................................................................................. 81

5.1 Signal multiplexing and pinouts..................................... 81

5.2 i.MXRT500 Pinouts: 249 FOWLP package................... 82

5.3 i.MX RT500 Pinouts: 141 CSP package........................97

5.4 249-pin FOWLP and 141-pin WLCSP ballmaps............106

5.5 Termination of unused pins........................................... 107

5.6 Pin states in different power modes...............................108

5.7 Obtaining package dimensions......................................108

6 Power supply for pins............................................................108

7 Revision history.....................................................................110

1.5.1

1.5.2

1.5.3

LCDIF.............................................................. 38

MIPI DSI timing................................................38

Flexible IO controller (FlexIO)..........................38

1.6 Analog characteristics....................................................39

1.6.1

1.6.2

1.6.3

12-bit ADC characteristics............................... 39

Temperature sensor........................................ 42

Comparator characteristics..............................43

1.7 Communication interfaces............................................. 45

1.7.1

1.7.2

1.7.3

1.7.4

USART interface..............................................45

I2C-bus............................................................ 46

I2S-bus interface............................................. 47

SPI interfaces (Flexcomm interfaces 0-8)....... 49

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Electrical characteristics

1 Electrical characteristics

1.1 Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See the

following table for a quick reference to the individual tables and sections.

Table 1. i.MX RT500 chip-level conditions

For these charateristics

Absolute maximum voltage and current ratings

Thermal handling ratings

Topic appears

Absolute maximum voltage and current ratings

Thermal handling ratings

Moisture handling ratings

ESD handling ratings

Thermal characteristics

General operating conditions

I/O parameters

General operating conditions

I/O parameters

Power consumption operating behavior

1.1.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

T_SDR

—

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.1.2 Moisture handling ratings

Symbol

MSL

Description

Min.

—

Max.

Unit

—

Notes

Moisture sensitivity level (FOWLP)

Moisture sensitivity level (WLCSP)

MSL

—

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Electrical characteristics

1.1.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

-2000

-500

Max.

2000

500

Unit

Notes

Electrostatic discharge voltage, human body model

V_CDM

Electrostatic discharge voltage, charged-device

model

I_LAT

Latch-up current at ambient temperature of 70 °C

-100

100

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.1.4 Absolute maximum voltage and current ratings

Caution

Stress beyond those listed under the following table may

cause permanent damage to the device. These are stress

ratings only. Functional operation of the device at these or

any other conditions beyond those indicated under

“recommended operating conditions” is not implied.

Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

Table 2. Absolute maximum ratings1

Symbol

Parameter

Conditions

Notes

Min.

Max.

Unit

VDD_AO1V8

Supply 1.8 V

supply for

“always on”

features

-0.3

1.98

VDD1V8

1.8 V supply

voltage for on-

chip analog

functions

other than the

ADC and

-0.3

1.98

comparator.

VDD1V8_1

1.8 V supply

voltage for on-

chip digital

logic

Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Electrical characteristics

Table 2. Absolute maximum ratings1 (continued)

Symbol

Parameter

Conditions

Notes

Min.

Max.

Unit

VDDCORE

1.1 V input

supply for

core logic

On-chip regulator

not used.

LDO_ENABLE=0.

Power supplied

by an off-chip

power

-0.3

1.155

management IC

(PMIC).

VDDIO_0/1/2/4

VDDIO_3

Supply

voltage for

GPIO pins

-0.3

1.98

3.96

1.98

Supply

voltage for

GPIO pins

VDDA_ADC1V8

1.8 V analog

supply voltage

for ADC and

comparator

VDDA_BIAS

VREFP

Bias voltage

for ADC and

comparator

-0.3

3.96

1.98

ADC positive

reference

voltage

USB1_VDD3V3

USB1_VBUS

USB1 analog

3.3 V supply

-0.3

3.96

5.6

USB1_VBUS

detection

MIPI_DSI_VDD11

MIPI DSI 1.1

V PHY input

core voltage

supply

1.155

MIPI_DSI_VDD18

MIPI DSI 1.8

V PHY IO

input voltage

supply

-0.3

1.98

MIPI_DSI_VDDA_CAP MIPI DSI 1.1

1.155

V capacitor

output voltage

supply

I_DD

supply current per supply pin,

(FOWLP249)

100

1.71 V ≤ V_DD

3.6 V

supply current per supply pin,

(WCLSP141)

1.71 V ≤ V_DD

3.6 V

Table continues on the next page...

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

Thermal specifications

Table 2. Absolute maximum ratings1 (continued)

Symbol

Parameter

Conditions

Notes

Min.

Max.

Unit

I_SS

ground current per ground pin,

(FOWLP249)

100

1.71 V ≤ V_DD

3.6 V

ground current per ground pin,

(WLCSP141)

100

1.86

1.71 V ≤ V_DD

3.6 V

I_latch

I/O latch-up

current

-(0.5V_DD) < V_I<

(1.5V_DD);

T_j< 105 °C

P_tot(pack)

total power

dissipation

FOWLP 249,

based on

(per package) package heat

transfer, not

device power

consumption

total power

dissipation

WLCSP141

1.42

(per package)

1. In accordance with the Absolute Maximum Rating System (IEC 60134). The following applies to the limiting values:

• This product includes circuitry specifically designed for the protection of its internal devices from the damaging

effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid

applying greater than the rated maximum.

• Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect

to VSS unless otherwise noted.

• The limiting values are stress ratings only and operating the part at these values is not recommended and

proper operation is not guaranteed. The conditions for functional operation are specified in Table 1.

2. Maximum/minimum voltage above the maximum operating voltage (see Table 1) and below ground that can be

applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of

reliability and shorter lifetime of the device.

3. The peak current should not exceed the total supply current.

4. Determined in accordance to JEDEC JESD51-2A natural convection environment (still air).

1.1.5 Thermal specifications

1.1.5.1 Thermal operating requirements

Table 3. Thermal operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_j

Die junction

temperature

-20

105

°C

T_A

Ambient

-20

°C

temperature

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis: T_J= T_A+ R_ΘJA× chip power dissipation.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

1.1.5.2 Thermal characteristics

The average chip junction temperature, T_j(°C), can be calculated using the following

equation:

(1)

• T_amb= ambient temperature (°C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (°C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation

of the I/O pins is often small and many times can be negligible. However it can be

significant in some applications.

Table 4. Thermal resistance1

Symbol

Parameter

Conditions

Max/Min

Unit

249 FOWLP Package

R_th(j-a)

R_Ψ(JT)

thermal resistance from JESD51-9, 2s2p, still

junction to ambient air

29.6

0.2

°C/W

thermal resistance from JESD51-9, 2s2p, still

junction to package top air

141 WCLSP Package

R_th(j-a)

R_Ψ(JT)

thermal resistance from JESD51-9, 2s2p, still

35.3

0.1

°C/W

junction to ambient

air

thermal resistance from JESD51-9, 2s2p, still

junction to package top air

1. Determined in accordance to JEDEC JESD51-2A natural convection environment (still air). Thermal resistance data in

this report is solely for a thermal performance comparison of one package to another in a standardized specified

environment. It is not meant to predict the performance of a package in an application-specific environment

1.1.6 General operating conditions

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 5. General operating conditions

Symbol

Parameter

Conditions

Min.

Typ.¹

Max. Unit

f_clk

CPU (Cortex-

M33) clock

frequency

200 MHz

Table continues on the next page...

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

Thermal specifications

Table 5. General operating conditions (continued)

Symbol

Parameter

Conditions

Min.

Typ.¹

Max. Unit

CPU (Cortex-

M33) clock

frequency

For USB high-speed device

and host operations

200 MHz

For OTP programming only -

120 MHz

200 MHz

f_clk

DSP clock

frequency

GPU clock

frequency

200 MHz

VDD_AO1V8

VDD1V8

Supply 1.8 V

supply for

“always on”

features.

1.71

1.89

1.8 V supply

voltage for on-

chip analog

functions other

than the ADC

and comparator

1.71

1.89

VDD1V8_1²

1.8 V supply

voltage for on-

chip digital

logic

1.89

VDDCORE³, ⁴, ⁵, ⁶1.1 V supply for

core logic. On-

chip regulator

Retention mode

0.6

0.7

1.155

Active Mode (M33 Max

Freq = 60 MHz, FBB)⁷

not used.

LDO_ENABLE

=0. Power

supplied by an

off-chip power

management

Active Mode (M33 Max

Freq = 100 MHz, FBB)

0.8

0.9

1.0

1.1

Active Mode (M33 Max

Freq = 192 MHz, FBB)

Active Mode (M33 Max

Freq = 230 MHz⁸, FBB)

IC (PMIC).

Active Mode (M33 Max

Freq = 275 MHz⁸, FBB)

VDDCORE³

1.1 V supply for Retention mode

0.6

0.7

1.155

core logic. On-

chip regulator

not used.

LDO_ENABLE

=0. Power

Active Mode (DSP Max

Freq = 60 MHz, FBB)⁷

Active Mode (DSP Max

Freq = 100 MHz, FBB)

0.8

0.9

supplied by an

off-chip power

management

IC (PMIC).

Active Mode (DSP Max

Freq = 192 MHz, FBB)

Active Mode (DSP Max

Freq = 230 MHz⁸, FBB)

1.0

Active Mode (DSP Max

Freq = 275 MHz⁸, FBB)

1.1

VDDIO_0/1/2/4

supply voltage

for GPIO rail

1.71

1.89

Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

Symbol

Table 5. General operating conditions (continued)

Parameter

Conditions

Min.

Typ.¹

Max. Unit

VDDIO_3

supply voltage

for GPIO rail

1.71

3.6

VDDA_1V8

1.8 V analog

supply voltage

for ADC and

comparator

1.71

1.89

VDDA_BIAS⁹

VREFP

Bias for ADC

and comparator

1.71

3.6

ADC positive

reference

voltage

1.89

USB1_VDD3V3

USB0_VBUS

USB1 analog

3.3 V supply

3.0

4.0¹⁰or 3.0^{, 11}

0.85

5.0

3.6

5.5

USB0_VBUS

detection

MIPI_DSI_VDD11 MIPI DSI 1.1V

1.155

digital core

input voltage

supply

MIPI_DSI_VDD18 MIPI DSI 1.8V

PHY IO input

1.71

-0.3

1.89

voltage supply

MIPI_DSI_VDDA_C MIPI DSI 1.1V

1.155

digital core

output voltage

supply

1. Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.

2. 1.8 V supply voltage for on-chip digital logic during active mode. In deep-sleep mode, this pin can be powered off to

conserve additional current (~20 uA).

3. The maximum frequency for the specified VDDCORE voltage is the frequency of the main clock. This is before the CPU

CLOCK Divider. The VDDCORE voltage has to be set according to the chosen main clock frequency.

4. When LDO_ENABLE is externally tied low, the user must boot at VDDCORE = 1.0 V or higher (Low power/Normal clock

mode - OTP setting - BOOT_CLK_SPEED) or VDDCORE = 1.13 V (High Speed clock - OTP setting -

BOOT_CLK_SPEED). Thereafter, the VDDCORE can be adjusted to the desired level.

5. When LDO_ENABLE is externally tied high, the on-chip regulator to the VDDCORE Core voltage in PMC is set to the

default value 1.05 V (Low power/Normal clock mode - OTP setting - BOOT_CLK_SPEED) or 1.13 V (High Speed clock -

OTP setting - BOOT_CLK_SPEED). Thereafter, the POWER_SetLdoVoltageForFreq API function can be used to

internally configure the on-chip regulator voltage to the VDDCORE.

6. When performing any OTP read/write function, the VDDCORE voltage must be set to 1.0 V or higher when

LDO_ENABLE is externally tied high or low.

7. GPU, SPI, and CTIMER are disabled.

8. Although i.MX RT500 is targeted to operate up to 200 MHz for low power operation, it can operate up to 275 MHz;

however, there will be an increase in current consumption.

9. VDD_BIAS must be equal to maximum ADC input voltage or maximum comparator input voltage.

10. The USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or

• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID comparator is

used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid VBUS.

The programmable range is 4.0V to 4.4V (default).

11. The USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or

• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V

USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector

is used, the detector voltage is not programmable.

1.1.7 I/O parameters

1.1.7.1 I/O DC parameters

T_amb= -20 °C to +70 °C, unless otherwise specified. Values tested in production unless otherwise specified.

Table 6. I/O DC characteristics

Sym

bol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

RESET pin, LDO_ENABLE pin, PMIC_IRQ_N pin, PMIC_MODE pins

V_IHHIGH-level input

voltage

0.7 x VDD_AO1V8

-0.3

VDD_AO1V8

V_ILLOW-level input

voltage

0.3 x

VDD_AO1V8

V_OHHIGH-level output I_OL= -2.9 mA;

voltage

0.8 x VDD_AO1V8

1.71 V ≤ VDD_AO1V8

< 1.89 V

V_OLLOW-level output I_OL= 2.9 mA;

voltage

0.2 x

VDD_AO1V8

1.71 V ≤ VDD_AO1V8

< 1.89 V

V_hyshysteresis voltage

0.06 x

VDD_AO1V8

Standard I/O pins and PMIC I2C pins

Input characteristics

I_IL

LOW-level input

current

V_I= 0 V; on-chip pull-

up resistor disabled.

-1

μA

1.71 V ≤ VDD < 1.98 V

V_I= 0 V; on-chip pull-

up resistor disabled.

-1

3.0 V ≤ VDD < 3.6 V

I_IHHIGH-level input

current

VI = VDD; on-chip pull-

down resistor disabled.

1.71 V ≤ VDD < 1.98 V

-1

0.5

μA

VI = VDD; on-chip pull-

down resistor disabled.

3.0 V ≤ VDD < 3.6 V

Table continues on the next page...

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Thermal specifications

Table 6. I/O DC characteristics (continued)

Sym

bol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

V_I

input voltage

pin configured to

provide a digital

function, except the

following pins:

V_DDIO= 0 V

0.7 x VDDIO

-0.3

3.6

V_IHHIGH-level input

voltage

1.71 V ≤ V_DD< 1.98 V

3.0 V ≤ V_DD≤ 3.6 V

1.71 V ≤ V_DD< 1.98 V

3.0 V ≤ V_DD≤ 3.6 V

VDDIO

V_ILLOW-level input

voltage

0.3 x VDDIO

-0.3

0.7

V_hyshysteresis voltage 1.71 V ≤ V_DD< 1.98 V

3.0 V ≤ V_DD≤ 3.6 V

0.15

Output characteristics

V_OHHIGH-level output IOH = -2.9 mA;

voltage (Normal

0.8 x VDDIO

1.71 V ≤ VDD < 1.98 V

IOH = -4 mA;

drive)

0.8 x VDDIO

3.0 V ≤ VDD ≤ 3.6 V

V_OHHIGH-level output IOH = -5.8 mA;

voltage (Full drive)

0.8 x VDDIO

1.71 V ≤ VDD < 1.98 V

IOH = -8 mA;

0.8 x VDDIO

3.0 V ≤ VDD ≤ 3.6 V

V_OLLOW-level output IOL = 2.9 mA;

0.2 x VDDIO

voltage (Normal

Drive)

1.71 V ≤ VDD < 1.98 V

IOL = 4 mA;

3.0 V ≤ VDD ≤ 3.6 V

LOW-level output IOL = 5.8 mA;

voltage (Full Drive)

1.71 V ≤ VDD < 1.98 V

IOL = 8 mA;

3.0 V ≤ VDD ≤ 3.6 V

Weak input pull-up/pull-down characteristics

I_pdpull-down current V_I= V_DD

V_I= 3.6 V

180

-180

μA

kΩ

-34

I_pupull-up current

V_I= 0 V

R_pdpull-down

resistance

R_pupull-up resistance

kΩ

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.

2. Guaranteed by design, not tested in production.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

3. All GPIO pins are fail safe up to 3.6 V when VDDIO supply = 0 V except following pins: PIO1_18 to PIO1_29, PIO1_30

to PIO1_31, PIO2_0 to PIO2_8, PIO2_24 to PIO2_31, PIO3_8 to PIO3_18, PIO4_11 to PIO4_17, and PIO5_15 to

PIO5_18.

4. Based on characterization. Not tested in production.

1.1.8 Power consumption operating behavior

NOTE

For the lowest power consumption, use the lowest SRAM

partition number.

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 7. Power consumption in active mode

Symbol

Parameter

Conditions

Notes Min.

Typ.¹,

Max.

Unit

Cortex M33 in Active mode, DSP no clock⁴

enhanced while (1) code executed from SRAM partition 30⁵; Internal LDO disabled

I_DDVDDCOREVDDCORE supply HCLK = 12 MHz

1.62

2.50

current

VDDCORE = 0.7 V

HCLK = 24 MHz

VDDCORE = 0.7 V

HCLK = 48 MHz

4.33

VDDCORE = 0.7 V

HCLK = 96 MHz

9.35

VDDCORE = 0.8 V

HCLK = 192 MHz

VDDCORE = 0.9 V

HCLK = 192 MHz

VDDCORE = 1.0 V

HCLK = 192 MHz

VDDCORE = 1.1 V

20.73

23.97

28.01

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =

VDDIO_0/1/2/3/4 = VDDA_ADC1V8 = 1.8 V. VDDA_BIAS = VREFP = 1.8 V. USB1_VDD3V3 = 3.3

2. Characterized through bench measurements using typical samples.

3. Compiler settings: IAR C/C++ Compiler for Arm ver 8.40.1. High, Speed, No Size Constraints. The optimization level is

Low, Balanced.

4. Based on the power API library from the SDK software package available on nxp.com

5. SRAM partition 30 represents the worst case partition.

6. FRO clock source, FBB enabled

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 8. Power consumption in active mode

Symbol

Parameter

Conditions

Min

Typ¹, ²,

Max

Unit

Cortex M33 in Active mode, DSP no clock⁴

CoreMark code executed from SRAM partition 30⁵

I_DDVDDCOREVDDCORE supply HCLK = 12 MHz

1.61

2.51

current

VDDCORE = 0.7 V

HCLK = 24 MHz

VDDCORE = 0.7 V

HCLK = 48 MHz

4.26

VDDCORE = 0.7 V

HCLK = 96 MHz

9.28

VDDCORE = 0.8 V

HCLK = 192 MHz

VDDCORE = 0.9 V

HCLK = 192 MHz

VDDCORE = 1.0 V

HCLK = 192 MHz

VDDCORE = 1.1 V

20.44

23.73

27.87

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =

VDDIO_0/1/2/3/4 = VDDA_ADC1V8 = 1.8 V. VDDA_BIAS = VREFP = 1.8 V. USB1_VDD3V3 = 3.3 V

2. Characterized through bench measurements using typical samples.

3. Compiler settings: IAR C/C++ Compiler for Arm ver 8.40. High Speed, No Size constraints. The optimization level is

Low, Balanced.

4. Based on the power API library from the SDK software package available on nxp.com

5. SRAM partition 30 represents the worst case partition.

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 9. Power consumption in active mode

Symbol

Parameter

Conditions

Notes Min

Typ¹, ², ³

Max

Unit

FFT code executed from SRAM partition 30 and 31⁴; Internal LDO disabled

DSP in Active mode, M33 in WFI⁵

I_DDVDDCOREVDDCORE

supply current

HCLK = 10 MHz

VDDCORE = 0.7 V

HCLK = 40 MHz

1.80

5.30

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Thermal specifications

Table 9. Power consumption in active mode (continued)

Symbol

Parameter

Conditions

VDDCORE = 0.8 V

Notes Min

Typ¹, ², ³

Max

Unit

HCLK = 100 MHz

VDDCORE = 0.8 V

HCLK = 150 MHz

VDDCORE = 0.9 V

HCLK = 200 MHz

VDDCORE = 0.9 V

10.74

17.81

22.94

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =

VDDIO_0/1/2/3/4 = VDDA_ADC1V8 = 1.8 V. VDDA_BIAS = VREFP = 1.8 V. USB1_VDD3V3 = 3.3 V

2. Characterized through bench measurements using typical samples.

3. Compiler settings: IAR C/C++ Compiler for Arm ver 8.40. High Speed, No Size constraints. The optimization level is

Low, Balanced.

4. SRAM partitions 30 and 31 represent the worst case partitions. The Fusion F1 DSP requires DRAM and IRAM in

different partitions. DSP_DRAM is in partition 30, DSP_IRAM is in partition 31.

5. Based on the power API library from the SDK software package available on nxp.com

6. PLL clock source, FBB enabled

Table 10. Power consumption in sleep mode

Symbol

Parameter

Conditions

Notes

Min.

Typ.

Max.

Unit

Cortex-M33 in Sleep mode, DSP no clock¹

I_DDVDDCOREsupply

current

HCLK=12 MHz

2, 3, 4, 5

1.8

VDDCORE=0.7 V

HCLK=12 MHz

2, 3, 4, 5

4.27

4.78

5.78

7.78

9.66

11.74

VDDCORE=1.0 V

HCLK=24 MHz

VDDCORE=1.0 V

HCLK=48 MHz

VDDCORE=1.0 V

HCLK=96 MHz

VDDCORE=1.0 V

HCLK=192 MHz

VDDCORE=0.9 V

HCLK=192 MHz

VDDCORE=1.0 V

1. 256 KB SRAM, internal LDO enabled

2. All peripheral clocks gated

3. PLL disabled

4. FRO used as clock source

5. IAR C/C++ Compiler for Arm ver 8.4.2.1.236

T_amb= -20 °C to +70 °C, unless otherwise specified.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

Symbol Parameter

Table 11. Power consumption in deep sleep mode

Conditions

Not Min Typ¹, ²

Max³

Unit

μA

I_VDD1V8supply

current

Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

8.5

I_VDDCOREsupply

current

Deep-sleep mode; SRAM (32 KB) powered, Internal

LDO disabled. Array On, Periphery Off

40.7

μA

T_amb= 25 °C

Deep-sleep mode; SRAM (32 KB) powered, Internal

LDO disabled. Array On, Periphery Off

200

42.0

210

μA

T_amb= 70 °C

I_VDDCOREsupply

current

Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

T_amb= 25 °C

Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

120

T_amb= 70 °C

I_VDDCOREsupply

current

Deep-sleep mode; SRAM (5 MB) powered, Internal

LDO disabled. Array On, Periphery Off

T_amb= 25 °C

Deep-sleep mode; SRAM (5 MB) powered, Internal

LDO disabled. Array On, Periphery Off

432

T_amb=70 °C

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,

except USB1_VDD3V3=3.3 V

2. Characterized through bench measurements using typical samples.

3. Guaranteed by characterization, not tested in production.

4. VDDCORE = 0.6 V, RBB Enabled

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 12. Power consumption in deep sleep mode

Symbol

Parameter

Conditions

Min Typ¹, ²

Max³

Unit

μA

I_{VDD_AO1V}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

0.79

LDO disabled. Array On, Periphery Off

I_{VDDIO_0}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

2.4

1.7

μA

I_{VDDIO_1}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

I_{VDDIO_2}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

0.35

0.8

I_{VDDIO_3}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

I_{VDDIO_4}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

0.36

Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

Table 12. Power consumption in deep sleep mode (continued)

Symbol

Parameter

Conditions

Min Typ¹, ²

Max³

Unit

μA

I_{VDDA_1V8}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

11.8

I_VREFP

supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

0.02

1.10

μA

I_{USB1_VDD}supply current Deep-sleep mode; SRAM (128 KB) powered, Internal

LDO disabled. Array On, Periphery Off

3V3

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,

except USB1_VDD3V3=3.3 V

2. Characterized through bench measurements using typical samples.

3. Guaranteed by characterization, not tested in production.

T_amb= -20 °C to +70 °C, unless otherwise specified.

Table 13. Power consumption in deep power-down mode and full deep power-down modes

Symbol

Parameter

Conditions

Min Typ¹, ²

Max³

Unit

I_{VDD_AO1}supply current Full Deep power-down mode; Internal LDO disabled.

0.51

μA

RTC Off

T_amb= 25 °C

Full Deep power-down mode; Internal LDO disabled.

RTC Off

1.79

μA

T_amb= 70 °C

I_{VDDIO_0}supply curent Deep power-down mode; Internal LDO disabled. RTC

Off

2.4

1.68

0.45

0.37

0.44

7.8

μA

I_{VDDIO_1}supply current Deep power-down mode; Internal LDO disabled. RTC

Off

I_{VDDIO_2}supply current Deep power-down mode; Internal LDO disabled. RTC

Off

I_{VDDIO_3}supply current Deep power-down mode; Internal LDO disabled. RTC

Off

I_{VDDIO_4}supply current Deep power-down mode; Internal LDO disabled. RTC

Off

I_VDD1V8

supply current Deep power-down mode; Internal LDO disabled. RTC

Off

I_VREFP

supply current Deep power-down mode; Internal LDO disabled. RTC

Off

0.01

1.1

I_{USB1_VDD}supply current Deep power-down mode; Internal LDO disabled. RTC

Off

3V3

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,

except USB1_VDD3V3=3.3V

2. Characterized through bench measurements using typical samples.

3. Guaranteed by characterization, not tested in production.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Thermal specifications

1.1.9 CoreMark data

Table 14. Coremark data

Parameters

Conditions

Notes

Typ.¹, ², ³

Unit

ARM Cortex-M33 in active mode

CoreMark Score

CoreMark code executed from

3.85

(Iterations/s) / MHz

SRAM; HCLK = 12 MHz

HCLK = 24 MHz

3.85

(Iterations/s) / MHz

HCLK = 48 MHz

HCLK = 96 MHz

HCLK = 192 MHz

1. Characterized through bench measurements using typical samples.

2. Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.

3. VDD_AO1V8 = VDD1V8 = VDDIO_0/1/2/3/4 = VDDA_ADC1V8 = VREFP = 1.8 V. VDDA_BIAS = USB1_VDD3V3 = 3.3

4. Clock source FRO. PLL disabled

5. Clock source external clock to XTALIN (bypass mode). PLL enabled.

1.2 System power and clocks

1.2.1 Power sequence

Following power-on sequence should be followed when using the internal LDO in i.MX

RT500:

1. VDD_AO1V8, VDD1V8, and VDD1V8_1 pins should be powered first. There is

no power sequence requirement between powering the VDD_AO1V8 and

VDD1V8 pins.

2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8

and VDD1V8 or later

3. VDDIO_x and VDDA_BIAS pins can be powered concurrently with

VDD_AO1V8 and VDD1V8 if these pins are 1.8 V range or later if these pins are

3.3 V range. If the VDDIO_x is not powered concurrently with the VDD1V8, the

delta voltage between VDDIO_x and VDD1V8 must be 1.89 V or less.

The VDDCORE pin will be supplied from the internal LDO and the LDO is powered

from the VDD1V8. An external capacitor (4.7 uF) must be connected on the

VDDCORE pin. USB1_VDD3V3 can be powered at any time, independent of the other

supplies.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

Following power-on sequence should be followed when using an external PMIC or

external IC to drive the VDDCORE pin (internal LDO is disabled, see timing diagram

below):

1. VDD_AO1V8, VDD1V8, and VDD1V8_1 pins should be powered first. There is

no power sequence requirement between powering the VDD_AO1V8 and

VDD1V8 pins.

2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8

and VDD1V8 or later.

3. VDDIO_x and VDDA_BIAS pins can be powered concurrently with VDD1V8 if

these pins are 1.8 V range or later if these pins are 3.3 V range. If the VDDIO_x

is not powered concurrently with the VDD1V8, the delta voltage between

VDDIO_x and VDD1V8 must be 1.89 V or less.

4. Power up the VDDCORE. The external RESETN should be held low until

VDDCORE is valid in the timing diagram.VDDCORE should not be ramped up

until after all the other supplies have completed ramp up.

USB1_VDD3V3 can be powered at any time, independent of the other supplies.

Sequence of operations is handled internally so there is no specific timing requirement

between the supplies. The time delays caused by any of the bypass capacitors will

have no effect on the operation of the part. The internal POR detectors on

VDD_AO1V8, VDD1V8 pins, and the Low Voltage Detector on VDDCORE pin,

require a fall time of at least 10us (preliminary) to trigger. There is no restriction on

the rise time, except for the sequencing defined above.

Table 15. Power-on characteristics

Symbol

Timing

Description

Min.

Max.

Unit

Parameter

VDDIO_x valid to

VDDCORE valid

The delay from

when the IO pad

voltages become

valid to core

μs

voltage valid

VDDCORE valid to The delay from

μs

De-assertion of

RESETN

when the VDD

core is valid to

when the RESETN

can be released

Mode pin valid

When the mode

pins becomes

valid. On power-

on, the mode pins

are reset to 00 and

are controlled via a

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

Symbol

Table 15. Power-on characteristics

Timing

Description

Min.

Max.

Unit

Parameter

POR circuit in the

always-on domain.

The timing is from

when the

VDD_AO1V8 is

valid to when the

mode pins are

reset to 00.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

VDD_AO_1V8

(Always on voltage to RTC)

VDD1V8

(Chip PMC power)

VDDIO_0

(Pad group 0 power)

VDDIO_1

(Pad group 1 power)

VDDIO_2

(Pad group2 power)

VDDIO_3

(Pad group3 power)

VDDIO_4

(Pad group4 power)

VDDA_BIAS

(ADCcomparator bias)

VREFP

(ADC Ref voltage)

VDDA_ADC1V8

(ADC/Comp power 1.8 volts)

VDDCORE

(Core Power needs DVFS

control)

RESETN

(External Chip reset)

XXXXXXXXX

PMIC_MODE0/1

(PMIC Mode pins (outputs))

Figure 4. Power-up ramp

1.2.2 Free-running oscillator FRO-192/96M specifications

Table 16. FRO-192M specifications

Symbol

Characteristic

Min.

Typ.

Max.

Unit

f_fro192m

FRO-192M frequency (nominal)

192

MHz

Δf_fro192mFrequency deviation

—

• 1T trim (Open loop)

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Thermal specifications

Table 16. FRO-192M specifications (continued)

Symbol

Characteristic

Min.

Typ.

Max.

Unit

t_startup

Start-up time

—

μs

jit_cyc

I_fro192m

V_min

Cycle to cycle jitter

Current consumption

Minimum voltage

—

0.8¹

105

—

111

—

μA

—

1. Vmin =0.8 V is derived from FRO192 MHz divided by 2/4/8.

NOTE

Any divided versions of the FRO that are not being used

anywhere should be turned off to save power.

Table 17. FRO-96M specifications

Symbol

f_fro96m

Characteristic

Min.

Typ.

Max.

Unit

FRO-96M frequency (nominal)

MHz

Δf_fro96m

Frequency deviation

• 1T trim (Open loop)

—

t_startup

Start-up time

—

120

—

μs

jit_cyc

I_fro96m

V_min

Cycle to cycle jitter

Current consumption

Minimum voltage

—

0.7¹

180

—

μA

—

1. Vmin =0.7 V is derived from FRO96 MHz divided by 2/4/8.

1.2.3 Crystal oscillator

T_amb= -20 °C to +70 °C; 1.71 V ≤ V_DD≤ 1.89 V.¹, ²

Table 18. Crystal oscillator characteristics

Symbol

Parameter

Min.

Typ.³

Max.

Unit

f_range

oscillator frequency

range

MHz

feedback resistor

high gain mode

only⁴

MΩ

ESR

Equivalent series

resistance

1. Parameters are valid over operating temperature range unless otherwise specified.

2. See XTAL oscillator

3. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

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Thermal specifications

4. CLKCTL0_SYSOSCCTL0[LP_ENABLE] = 1 sets High Gain Mode, which requires a 1 MΩ feedback resistor.

1.2.4 RTC oscillator

See RTC oscillator for connecting the RTC oscillator to an external clock source.

T_amb= -20 °C to +70 °C; 1.71 ≤ V_DD≤ 1.89

Table 19. RTC oscillator characteristics

Symbol

f₁

Parameter

Conditions

Min.

Typ.¹

32.768

Max.

Unit

kHz

kΩ

input frequency

ESR

Equivalent series

resistance

100K

, 2

t_{start_xtal}

Crystal oscillator

start-up time

250

t_{start_bypass}Bypass oscillator

start-up time

V_pp

Peak-to-Peak

amplitude of

oscillation

With oscillator

bypass mode

enabled

0.7

VDD_AO1V8

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

2. Proper PCB layout procedures must be followed to achieve specifications.

3. In bypass mode, using an input square wave only on RTCXIN with RTXOUT floating.

1.2.5 External Clock Input (CLKIN) pin

T_amb= -20 °C to +70 °C; 1.71 V to 1.89 V

Table 20. Dynamic characteristic: CLKIN

Symbol

Parameter

Conditions

Min.

Typ.¹

Max

Unit

F_i

input frequency

MHz

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages

1.2.6 Internal low-power oscillator (1 MHz)

The IRC is trimmed to 10% accuracy over the entire voltage and temperature range.

T_amb= -20 °C to +70 °C; 1.71 ≤ V_DD≤ 1.89 V

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Thermal specifications

Table 21. LPOSC characteristics

Symbol

f_{osc (RC)}

Parameter

Conditions

Min

Typ¹

Max

Unit

LPOSC clock

frequency

0.9

1.1

MHz

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

1.3 System modules

1.3.1 Reset timing parameters

The following figure shows the reset timing and Table 22 lists the timing parameters.

RESETN

(Input)

CC1

Figure 5. Reset timing diagram

Table 22. Reset timing parameters

Parameter

Min

Max

Unit

CC1

Duration of POR_B to

be qualified as valid

1.3.2 Serial Wire Debug (SWD) timing specifications

Table 23. SWD timing specifications

Symbol Description

Min.

Max.

Min.—

VLPR

mode

Max.—

VLPR

mode

Unit

SWD_CLK frequency of operation

—

MHz

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1000/J1

—

SWD_CLK rise and fall times

—

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i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

Thermal specifications

Table 23. SWD timing specifications (continued)

Symbol Description

Min.

Max.

Min.—

VLPR

mode

Max.—

VLPR

mode

Unit

SWD_DIO input data setup time to SWD_CLK

rise

—

J10

SWD_DIO input data hold time after SWD_CLK

rise

—

J11

J12

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

SWD_CLK (input)

Figure 6. Serial wire clock input timing

SWD_CLK

SWD_DIO

J10

Input data valid

J11

Output data valid

J12

J11

Output data valid

Figure 7. Serial wire data timing

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Thermal specifications

1.3.3 JTAG timing specifications

Table 24. JTAG timing specifications

Symbol Parameter

Min.

Max.

Min.—

VLPR

mode

Max.—

VLPR

mode

Unit

TCLK frequency of operation

• Boundary Scan

• JTAG

—

MHz

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

• JTAG

1000/J1

—

TCLK rise and fall times

Boundary scan input data setup time to TCLK

rise

—

Boundary scan input data hold time after TCLK

rise

—

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

10.5

2.5

—

J10

J11

J12

J13

J14

—

TCLK low to TDO high-Z

TRST assert time

100

TRST setup time (negation) to TCLK high

TCLK (input)

Figure 8. Test clock input timing

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i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

Thermal specifications

TCLK

Input data valid

Data inputs

Data outputs

Output data valid

Figure 9. Boundary scan (JTAG) timing

TCLK

TDI/TMS

TDO

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 10. Test Access Port timing

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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Thermal specifications

TCLK

TRST

J14

J13

Figure 11. TRST timing

1.3.4 Wake-up process

V_DD= 3.3 V;T_amb= 25 °C; using FRO as the system clock.

Table 25. Typical wake-up times from low power modes

Symbol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

t_wake

wake-up time from sleep

2, 3

150

μs

mode, 200

MHz

t_wake

wake-up time from deep-

sleep mode,

using

120

μs

RESETN.

from deep-

sleep mode,

using

PMIC_IRQ_N

t_wake

wake-up time from full deep

power-down

8.64

mode, using

RESETN

from full deep

power-down

mode, using

PMIC_IRQ_N

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

2. The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low

power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler.

3. FRO disbled, all peripherals off. PLL disabled.

4. Wake up from deep power-down causes the part to go through entire reset process. The wake-up time measured is the

time between when the Wake-Up pin is triggered to wake the device up and when a GPIO output pin is set in the reset

handler.

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External memory interface

1.4 External memory interface

1.4.1 FlexSPI Flash interface

Tamb = -20 °C to +70 °C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL =

5 pF balanced loading on all pins; Full Drive Mode on all pins, Input slew = 1 ns,

SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of

the rising or falling edge.

Table 26. Dynamic characteristics: FlexSPI flash interface1

Symbol

SDR mode

f_clk

Parameter

Conditions

Min.

Typ.

Max.

Unit

clock frequency Transmit

RX clock source = 0

—

200

MHz

RX clock source = 1

RX clock source = 3

116

200

—

t_DS

data set-up time RX clock source = 0

(internal dummy read

strobe and loopbacked

internally)

RX clock source = 1

(internal dummy read

strobe and loopbacked

from DQS pad)

—

source = 3 (external

DQS, Flash provides

read strobe)

—

0.6

—

t_DH

data hold time

RX clock source = 0

(internal dummy read

strobe and loopbacked

internally)

RX clock source = 1

(internal dummy read

strobe and loopbacked

from DQS pad)

—

source = 3 (external

DQS, Flash provides

read strobe)

—

t_V(Q)

data output valid

time

DDR Mode (with and without DQS)

f_clkclock frequency

Transmit

—

200

MHz

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External memory interface

Table 26. Dynamic characteristics: FlexSPI flash interface1 (continued)

Symbol

Parameter

Conditions

RX clock source = 0

RX clock source = 1

Min.

Typ.

Max.

Unit

MHz

—

RX clock source = 3, with —

external DQS.

200

t_DS

data set-up time RX clock source = 0

(internal dummy read

strobe and loopbacked

internally)

—

RX clock source = 1

(internal dummy read

strobe and loopbacked

from DQS pad)

source = 3 (external

DQS, Flash provides

read strobe)

—

0.6

—

t_DH

data hold time

RX clock source = 0

(internal dummy read

strobe and loopbacked

internally)

RX clock source = 1

(internal dummy read

strobe and loopbacked

from DQS pad)

—

source = 3 (external

DQS, Flash provides

read strobe)

—

t_V(Q)

data output valid

time

1. Based on simulation; not tested in production.

Following are the FlexSPI timing diagrams for SDR and DDR input and output timing

modes.

fclk

IO[0:7]

Internal Sample Clock

Figure 12. SDR mode (input timing, mode 0 and 1)

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i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

External memory interface

DQS

IO[0:7]

Internal Sample Clock

Figure 13. SDR mode (input timing, mode 3)

fclk

CLK

V(Q)max

IO[0:7]

V(Q)min

Figure 14. SDR mode (output timing, mode 0 and 1)

DQS

CLK

V(Q)max

IO[0:7]

V(Q)min

Figure 15. SDR mode (output timing, mode 3)

fclk

IO[0:7]

Internal Sample Clock

Figure 16. DDR mode (input timing, mode 0 and 1)

DQS

IO[0:7]

Internal sample clock

Figure 17. DDR mode (input timing, mode 3)

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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External memory interface

fclk

CLK

t_V(Q)max

V(Q)max

IO[0:7]

V(Q)min

Figure 18. DDR mode (output timing, mode 0 and 1)

DQS

TCLK

V(Q)max

IO[0:7]

V(Q)min

Figure 19. DDR mode (output timing, mode 3)

1.5 Display and graphics

1.5.1 LCDIF

T_amb= -20 °C to 70 °C; V_DD= 2.7 V to 3.6 V; C_L= 30 pF. Simulated values.

Table 27. LCDIF characteristics

Symbol

f_clk

Parameter

clock frequency

data output valid time

Conditions

on pin LCD_DCLK

on all LCD output pins

Min.

Typ.

Max.

Unit

MHz

t_v(Q)

0.3

4.5

1.5.2 MIPI DSI timing

The i.MX RT500 conforms to the MIPI D-PHY electrical specifications MIPI DSI

Version 1.01 and D-PHY specification Rev. 1.0 (and also DPI version 2.0, DBI version

2.0, DSC version 1.0a at protocol layer) for MIPI display port x2 lanes.

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External memory interface

1.5.3 Flexible IO controller (FlexIO)

Table 28. FlexIO timing specifications

Symbol

Description

Min

Typ.

Max.

Unit

Notes

t_ODS

Output delay skew between any

two FlexIO_Dx pins configured

as outputs that toggle on same

internal clock cycle

—

1.957

t_IDS

Input delay skew between any

two FlexIO_Dx pins configured

as inputs that are sampled on

the same internal clock cycle

—

1.403

1. Assumes pins muxed on same VDD_IO domain with same load

1.6 Analog characteristics

1.6.1 12-bit ADC characteristics

T_amb= -20 °C to +70 °C; 1.71 V ≤ V_DD≤ 3.6 V; V_SSA= VREFN = GND. ADC calibrated at T_amb= 25 °C.

Table 29. 12-bit ADC static characteristics

Symb

Parameter

Conditions

Notes

Min

Typ¹

Max

Unit

VADIN analog input voltage

f_clk(ADC)ADC clock frequency

See Figure 21

VREFN

VREFP

MHz

f_s

sampling frequency

Msamples/s

C_sampleSample cycles

3.5

131.5

C_comparFixed compare

17.5

cycles

C_conversConversion cycles

C_conversion= C_samples

C_compare

ion

CADIN Analog input

capacitance

², See Figure

4.5

RADIN Input resistance

See Figure 21

500

RAS

Analog source

resistance

kΩ

E_D

differential linearity

error

4, 5

4, 6

< 1

LSB

E_L(adj)integral non-linearity f_clk(ADC)= 22 MHz

< 1.1

Sample Time select

(STS bit in CMDH

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External memory interface

Table 29. 12-bit ADC static characteristics (continued)

Symb

Parameter

Conditions

Notes

Min

Typ¹

Max

Unit

E_O

offset error

4, 7

4, 8

< 1

0.3

LSB

V_err(FS)full-scale error

voltage

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

2. CADIN represents the external capacitance on the analog input channel for sampling speeds of 1.0 Msamples/s. No

parasitic capacitances included.

3. This resistance is external to the MCU. To achieve the best results, the analog source resistance must be kept as low

possible. The results in this data sheet were derived from a system that had less than 15 Ω analog source resistance.

See Figure 1

4. Based on characterization; not tested in production.

5. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 1.

6. The integral non-linearity (EL_(adj)) is the peak difference between the center of the steps of the actual and the ideal

transfer curve after appropriate adjustment of gain and offset errors. See Figure 1.

7. The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line

which fits the ideal curve. See Figure 1.

8. The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve

after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 1.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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External memory interface

offset

error

gain

error

4095

4094

4093

4092

4091

4090

(2)

code

out

(1)

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

(LSB

)

ideal

offset error

VREFP - VREFN

1 LSB =

4096

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Figure 20. 12-bit ADC characteristics

1.6.1.1 ADC input impedance

The following figure shows the ADC input impedance for this device.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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External memory interface

Figure 21. ADC input impedance

1.6.2 Temperature sensor

Table 30. Temperature sensor static and dynamic characteristics

(VDDA_BIAS = 3.3 V, All other supplies = 1.8 V)

Symbol

DT_sen

Parameter

Conditions

Notes

Min

Typ

Max

Unit

sensor

T_amb= -20 °C 1

2.77

°C

temperature to 70 °C

accuracy

E_L

linearity error Tamb = -20

°C to 70 °C

2.79

°C

1. Absolute temperature accuracy. Based on characterization. Not tested in production

Table 31. Temperature sensor Linear-Least-Square (LLS) fit parameters

(VDDA_BIAS = 3.3 V, All other supplies = 1.8 V)

Fit parameter

Conditions

Notes

Min

Typ

Max

Unit

LLS slope

T_amb= -20 °C to 1, 2

70 °C

-1.5738

mV/°C

LLS intercept at Tamb = -20 °C 1, 2

0° C to 70 °C

809.55

770.4

LLS intercept at Tamb = -20 °C 1, 2

25 °C to 70 °C

1. Based on characterization, Not tested in production.

2. Equation: Temp = 25 - ((Vtemp -Vtemp25)/m) Where: VTEMP is the voltage of the temperature sensor channel at the

ambient temperature VTEMP is the voltage of the temperature sensor channel at 25°C and VDD = 1.8 V m is the voltage

versus temperature slope in V/°C.

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External memory interface

Average Vo @1.8Vsupply

900

850

800

750

700

650

600

550

500

‐20

Temperature(C)

Fig 29. Average Vo @ 1.8V supply

Figure 22. Average Vo @ 1.8V supply

1.6.3 Comparator characteristics

T_amb= -20 C to +70 C; V_DD= 1.8 V to 3.6 V.

Table 32. Comparator characteristics

Symbol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

Static characteristics

Voffset

offset voltage V_IC= 0.1 V; V_DD

1.8 V

—

V_IC= 0.9 V; V_DD

1.8 V

—

V_IC= 1.7 V; V_DD

1.8 V

Dynamic characteristics

t_PD

propagation HIGH to LOW; V_DD

—

μs

delay

= 1.8 V; T_amb= 25

°C V_IC= 0.1 V; 100

mV overdrive input

V_IC= 0.1 V; rail-to-

rail input

—

915

525

600

—

V_IC= 0.9 V; 100 mV 2

overdrive input

V_IC= 0.9 V; rail-to-

rail input

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External memory interface

Table 32. Comparator characteristics (continued)

Symbol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

V_IC= 1.7 V; 100 mV 2

overdrive input

—

500

—

V_IC= 1.7 V; rail-to-

rail input

—

350

270

—

t_PD

propagation HIGH to LOW; V_DD2

delay

= 1.8 V; T_amb= 25

°C V_IC= 0.1 V; 100

mV overdrive input

V_IC= 0.1 V; rail-to-

rail input

—

310

340

210

150

125

5.8

—

μs

V_IC= 0.9 V; 100 mV 2

overdrive input

V_IC= 0.9 V; rail-to-

rail input

V_IC= 1.7 V; 100 mV 2

overdrive input

V_IC= 1.7 V; rail-to-

rail input

t_PD

propagation LOW to HIGH;

delay

VV_DD= 1.8 V; T_amb

= 25 °C, V_IC= 0.1

V; 100 mV

overdrive input

V_IC= 0.1 V; rail-to-

rail input

—

470

750

600

5.5

—

μs

V_IC= 0.9 V; 100 mV 2

overdrive input

V_IC= 0.9 V; rail-to-

rail input

V_IC= 1.7 V; 100 mV 2

overdrive input

V_IC= 1.7 V; rail-to-

rail input

1.25

105

t_PD

propagation LOW to HIGH;

delay

VV_DD= 1.8 V; T_amb

= 25 °C, V_IC= 0.1

V; 100 mV

overdrive input

V_IC= 0.1 V; rail-to-

rail input

—

115

110

120

110

—

V_IC= 0.9 V; 100 mV 2

overdrive input

V_IC= 0.9 V; rail-to-

rail input

V_IC= 1.7 V; 100 mV 2

overdrive input

Table continues on the next page...

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NXP Semiconductors

External memory interface

Table 32. Comparator characteristics (continued)

Symbol

Parameter

Conditions

Notes

Min.

Typ.¹

Max.

Unit

V_IC= 1.7 V; rail-to-

rail input

—

120

—

V_hys

hysteresis

voltage³

HYSTCRT[1:0] =

—

HYSTCRT[1:0] =

—

HYSTCRT[1:0] =

1. Characterized on typical samples, not tested in production

2. 100 mV overdrive corresponds to a square wave from 50 mV below the reference (VIC) to 50 mV above the reference.

3. Input hysteresis is relative to the reference input channel and is software programmable.

1.7 Communication interfaces

1.7.1 USART interface

Excluding delays introduced by external device and PCB, the maximum supported bit

rate for USART master synchronous mode is 20 Mbit/s, and the maximum supported

bit rate for USART slave synchronous mode is 20.0 Mbit/s.

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (HCLK), and capacitive loading.

T_amb= -20 °C to 70 °C; V_DD= 1.71 V to 1.89 V; C_L= 20 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting

= standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Table 33. USART interface characteristics1

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

USART master (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

data input set-

up time

0.087

0.03

data input hold

time

data output

valid time

14.058

16.412

USART slave (in synchronous mode)

t_su(D)

t_h(D)

data input set-

up time

0.087

data input hold

time

0.03

Table continues on the next page...

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External memory interface

Table 33. USART interface characteristics1 (continued)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

t_v(Q)

data output

valid time

3.684

1. Based on simulation; not tested in production

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

vQ)

v(Q)

START

BIT0

BIT1

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-015074

Figure 23. USART timing

1.7.2 I²C-bus

T_amb= -20 °C to +70 °C; 1.71 V ≤ V_DD≤ 1.89 V.¹

Table 34. I²C-bus pins1

Symbol

Parameter

Notes

Conditions

Standard-mode

Fast-mode

Min.

Max.

100

400

Unit

f_SCL

SCL clock

frequency

kHz

Fast-mode Plus

MHz

t_f

fall time

2, 3, 4, 5

Both SDA and

SCL signals

300

Standard-mode

Fast-mode

20x(VDD/3.6V)

300

Fast-mode Plus -

Standard-mode

Fast-mode

120

t_LOW

LOW period of

the SCL clock

4.7

1.3

0.5

μs

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

HIGH period of

the SCL clock

0.6

Table continues on the next page...

1. Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification

UM10204 for details.

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External memory interface

Table 34. I²C-bus pins1 (continued)

Symbol

Parameter

Notes

Conditions

Fast-mode Plus

Standard-mode

Fast-mode

Min.

0.26

Max.

Unit

μs

t_HD;DAT

data hold time

7, 2, 8

Fast-mode Plus

Standard-mode

Fast-mode

t_SU;DAT

data set-up time

9, 10

4.7

0.6

0.26

Fast-mode Plus

1. Guaranteed by design. Not tested in production.

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

3. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

4. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output

stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the

SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

5. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used,

designers should allow for this when considering bus timing.

6. The MSTTIME register allows programming of certain times for the clock (SCL) high and low times. Please see i.MX

RT500 Low-Power Crossover MCU Reference Manual for further details.

7. t_HD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the

acknowledge.

8. The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the

maximum of t_VD;DATor t_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the

LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it

releases the clock.

9. t_SU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission

and the acknowledge.

10. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement t_SU;DAT= 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

tr(max) + t_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line

is released. Also the acknowledge timing must meet this set-up time.

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

HD;DAT

VD;DAT

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

LOW

1 / f

SCL

Figure 24. I²C bus pins clock timing

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

External memory interface

1.7.3 I²S-bus interface

T_amb= -20 °C to 70 °C; V_DD= 1.71 V to 1.89 V; C_L= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Table 35. I²S-bus interface pins1, 2

Symbol

Parameter

Conditions

Notes

Min.

Typ.³

Max.

Unit

Common to master and slave

t_WH

pulse width

HIGH

on pins I2Sx_TX_SCK and I2Sx_RX_SCK⁴

(T_cyc/2) -1

(T_cyc/2) +1

t_WL

pulse width

LOW

on pins I2Sx_TX_SCK and I2Sx_RX_SCK⁴

(T_cyc/2) -1

Master

t_v(Q)

data output

valid time

on pin

I2Sx_TX_SD

6.798

17.505

on pin I2Sx_WS

16.055

t_su(D)

data input set- on pin

1.3

up time

I2Sx_RX_SD

t_h(D)

data input

hold time

on pin

I2Sx_RX_SD

2.9

Slave

t_v(Q)

data output

valid time

on pin

I2Sx_TX_SD

13.8

4.7

23.6

t_su(D)

data input set- on pin

up time

I2Sx_RX_SD

on pin

I2Sx_WS

0.9

t_h(D)

data input

hold time

on pin

I2Sx_RX_SD

on pin

I2Sx_WS

1. Based on simulation; not tested in production.

2. The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S

chapter in the i.MX RT500 Low-Power Crossover MCU Reference Manual (IMXRT500RM) to calculate clock and sample

rates.

3. Typical ratings are not guaranteed.

4. Based on simulation. Not tested in production.

5. Clock Divider register (DIV) = 0x0.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

External memory interface

cy(clk)

I2Sx_SCK

I2Sx_TX_SDA

v(Q)

I2Sx_RX_SDA

I2Sx_WS

h(D)

su(D)

v(Q)

Figure 25. I²S-bus timing (master)

cy(clk)

I2Sx_SCK

I2Sx_TX_SDA

v(Q)

I2Sx_RX_SDA

su(D)

h(D)

I2Sx_WS

h(D)

su(D)

Figure 26. I²S-bus timing (slave)

1.7.4 SPI interfaces (Flexcomm interfaces 0-8)

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (HCLK), and capacitive loading.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

External memory interface

Excluding delays introduced by external device and PCB, the maximum supported bit

rate for SPI master mode (transmit/receive) is 25 Mbit/s and the maximum supported

bit rate for SPI slave mode (transmit/receive) is 25 Mbit/s.

T_amb= -20 °C to 70 °C; 1.71 V ≤ V_DD≤ 1.89 V; C_L= 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.

Table 36. SPI interfaces1

Symbol

Parameter

Conditions

SPI master

Min.

Typ.

Max.

Unit

t_DS

t_DH

data set-up time

data hold time

5.0

t_v(Q)

data output valid time

13.0

SPI slave

t_DS

t_DH

data set-up time

data hold time

5.0

t_v(Q)

data output valid time

1. Based on simulation; not tested in production

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

Figure 27. SPI master timing

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

External memory interface

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

Figure 28. SPI slave timing

1.7.5 High-Speed SPI interface (Flexcomm interface 14)

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (HCLK), and capacitive loading.

Excluding delays introduced by external device and PCB, the maximum supported bit

rate for SPI master mode (transmit/receive) is 50 Mbit/s.

Excluding delays introduced by external device and PCB, the maximum supported bit

rate for SPI slave mode (receive) is 50 Mbit/s and for SPI slave mode (transmit) is 35

Mbit/s.

T_amb= -20 °C to 70 °C; 1.71 V ≤ V_DD≤ 1.89 V; C_L= 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

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External memory interface

Table 37. High-Speed SPI interfaces1

Symbol

Parameter

Conditions

SPI master

Min.

Typ.

Max.

Unit

t_DS

t_DH

data set-up time

data hold time

4.0

t_v(Q)

data output valid time

6.0

SPI slave

t_DS

t_DH

data set-up time

data hold time

3.0

t_v(Q)

data output valid time

10.0

1. Based on simulation; not tested in production

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

Figure 29. SPI master timing

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

External memory interface

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

Figure 30. SPI slave timing

1.7.6 SD/MMC and SDIO

T_amb= -20 °C to +70 °C, V_DD= 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode

on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the

rising or falling edge. Based on simulation, not tested in production.

Table 38. SD/MMC and SDIO characteristics (Default Speed (DS), High Speed (HS) SDR-12

and SDR-25)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

f_clk

clock frequency on pin SD_CLK;

data transfer

12.5

MHz

mode. DS/

SDR-12 (12.5

MB/s)

f_clk

clock frequency on pin SD_CLK;

data transfer

MHz

mode, HS/

SDR-25 (25

MB/s)

Table continues on the next page...

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External memory interface

Table 38. SD/MMC and SDIO characteristics (Default Speed (DS), High Speed (HS) SDR-12

and SDR-25) (continued)

Symbol

Parameter

data input set- on pins

up time SD_DATn as

Conditions

Min.

Typ.

Max.

Unit

t_su(D)

7.5

inputs

on pins

SD_CMD as

inputs

7.5

1.0

t_h(D)

data input hold on pins

time

SD_DATn as

inputs

on pins

SD_CMD as

inputs

t_v(Q)

data output

valid time

on pins

SD_DATn as

outputs

7.5

on pins

SD_CMD as

outputs

T_amb= -20 °C to +70 °C, V_DD= 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode on

all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising or

falling edge. Based on simulation, not tested in production.

Table 39. SD/MMC and SDIO characteristics ((SDR-50, SDR-104, HS-200 (MMC))

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

f_clk

clock frequency on pin SD_CLK;

data transfer

100

MHz

mode, SDR-50

(50 MB/s)

f_clk

clock frequency on pin SD_CLK;

data transfer

200

MHz

mode, SDR-104

(104 MB/s)

f_clk

clock frequency on pin SD_CLK;

data transfer

mode, HS-200

(MMC) (200

MB/s)

t_su(D)

data input set-

up time

on pins

SD_DATn as

inputs

7.5

on pins

SD_CMD as

inputs

Table continues on the next page...

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

External memory interface

Table 39. SD/MMC and SDIO characteristics ((SDR-50, SDR-104, HS-200 (MMC)) (continued)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

t_h(D)

data input hold

time

on pins

SD_DATn as

inputs

on pins

SD_CMD as

inputs

t_v(Q)

data output valid

time

on pins

SD_DATn as

outputs

7.5

on pins

SD_CMD as

outputs

T_amb= -20 °C to +70 °C, V_DD= 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode

on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the

rising or falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only.

Table 40. SD/MMC and SDIO characteristics ((DDR-50, HS DDR (MMC))

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

f_clk

clock frequency on pin SD_CLK;

data transfer

MHz

mode, DDR-50

(50 MB/s)

f_clk

clock frequency on pin SD_CLK;

data transfer

MHz

mode, HS-DDR

(104 MB/s)

t_su(D)

data input set-

up time

on pins

SD_DATn as

inputs

4.8

on pins

SD_CMD as

inputs

t_h(D)

data input hold

time

on pins

SD_DATn as

inputs

on pins

SD_CMD as

inputs

t_v(Q)

data output

valid time

on pins

SD_DATn as

outputs

5.0

on pins

SD_CMD as

outputs

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

External memory interface

T_amb= -20 °C to +70 °C, V_DD= 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode on

all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising or

falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only.

Table 41. SD/MMC and SDIO characteristics (HS-400(MMC))

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

f_clk

clock frequency on pin SD_CLK;

data transfer

200

MHz

mode, HS-400

(400 MB/s)

t_su(D)

t_h(D)

t_v(Q)

data input set-

up time

on pins

SD_DATn as

inputs

0.5

on pins

SD_CMD as

inputs

data input hold

time

on pins

SD_DATn as

inputs

on pins

SD_CMD as

inputs

data output valid

time

on pins

SD_DATn as

outputs

1.0

on pins

SD_CMD as

outputs

cy(clk)

SD_CLK

h(Q)

d(QV)

SD_CMD (O)

SD_DATn (O)

su(D)

h(D)

SD_CMD (I)

SD_DATn (I)

Figure 31. SD/MMC and SDIO timing

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

External memory interface

1.7.7 DMIC subsystem

T_amb= -20 °C to 70 °C; V_DD= 2.7 V to 3.6 V; C_L= 20 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Bypass bit = 0; Parameters sampled at the 50% level of the rising or falling edge.

Table 42. Dynamic characteristics1

Symbol

t_DS

Parameter

data set-up time

data hold time

Conditions

Min.

Typ.

Max.

Unit

t_DH

1. Based on simulated values.

CLOCK

DATA

Figure 32. DMIC timing diagram

1.7.8 USB interface characteristics

This section describes the USB1 port High Speed/Full Speed (HS/FS) transceiver. The

USB HS/FS meets the electrical compliance requirements defined in the Universal

Serial Bus Revision 2.0 Specification.

1.7.9 USB DCD electrical specifications

Table 43. USB DCD electrical specifications

Symbol

V_{DP_SRC}

Description

Min.

Typ.

Max.

Unit

USB_DP and USB_DM source voltages (up to 250

0.5

—

0.7

V_{DM_SRC}μA)

V_LGC

I_{DP_SRC}

I_{DM_SINK}

Threshold voltage for logic high

0.8

—

2.0

USB_DP source current

μA

USB_DM and USB_DP sink currents

100

150

I_{DP_SINK}

R_{DM_DWN}D- pulldown resistance for data pin contact detect

V_{DAT_REF}Data detect voltage

14.25

0.25

—

24.8

0.4

kΩ

0.33

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External memory interface

1.7.10 USB High Speed Transceiver and PHY specifications

This section describes the High Speed USB PHY parameters. The high speed PHY is

capable of full speed signaling as well.

The USB PHY meets the electrical compliance requirements defined in the Universal

Serial Bus Revision 2.0 Specification with the amendments below.

• USB ENGINEERING CHANGE NOTICE

• Title: 5V Short Circuit Withstand Requirement Change

• Applies to: Universal Serial Bus Specification, Revision 2.0

• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

• USB ENGINEERING CHANGE NOTICE

• Title: Pull-up/Pull-down resistors

• Applies to: Universal Serial Bus Specification, Revision 2.0

• USB ENGINEERING CHANGE NOTICE

• Title: Suspend Current Limit Changes

• Applies to: Universal Serial Bus Specification, Revision 2.0

• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

• Revision 2.0 plus errata and ecn June 4, 2010

• Battery Charging Specification (available from USB-IF)

• Revision 1.2, December 7, 2010

USB0_VBUS pin is a detector function which is 5v tolerant and complies with the

above specifications without needing any external voltage division components.

1.7.11 Improved Inter-Integrated Circuit Interface (MIPI-I3C)

specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the V_IHand/or

V_ILsignal points.

Table 44. MIPI-I3C specifications when communicating with legacy I²C devices

Symbol Characteristic

400 kHz/Fast mode

1 MHz/ Fast+ mode

Unit

Min.

Max.

0.4

—

Min.

Max.

f_SCL

SCL Clock Frequency

MHz

t_{SU_STA}Set-up time for a repeated START condition

600

260

—

Hold time t_HD; STA

(repeated)

—

Table continues on the next page...

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External memory interface

Table 44. MIPI-I3C specifications when communicating with legacy I²C devices (continued)

Symbol Characteristic

400 kHz/Fast mode

1 MHz/ Fast+ mode

Unit

Min.

Max.

Min.

Max.

START

condition

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

1300

600

100

—

500

260

—

t_{SU_DAT}Data set-up time

—

t_{HD_DAT}Data hold time for I₂C bus devices

—

t_f

Fall time of SDA and SCL signals

20*(Vdd/5.5

300

20*(Vdd/5.

5 v)

120

t_r

Rise time of SDA and SCL signals

600

1.3

300

—

260

0.5

120

—

µs

t_{SU_STO}Set-up time for STOP condition

t_BUF

Bus free time between STOP and START

condition

—

t_SP

Pulse width of spikes that must be suppressed

by the input filter

Table 45. MIPI-I3C open drain mode specifications

Symbol

Characteristic

Min.

200

—

Max.

—

Unit

Notes

t_{LOW_OD}LOW period of the SCL clock

t_{DIG_OD_L}t_{LOW_OD}+ t_{fDA_OD}(min)

t_HIGH

t_{fDA_OD}

t_{SU_OD}

t_CAS

HIGH period of the SCL clock

Fall time of SDA signal

—

t_CF

Data set-up time during open drain mode

—

Clock after START (S) Condition

• ENTAS0

38.4 n

1 μ

100 μ

2 m

50 m

—

• ENTAS1

• ENTAS2

• ENTAS3

t_CBP

Clock before STOP (P) condition

t_CAS(min)/2

t_{DIG_OD_L}

t_MMOverlapCurrent master to secondary master overlap time

during handoff

—

t_AVAL

t_IDLE

Bus available condition

—

μs

Bus idle condition

t_MMLock

Time internal where new master not driving SDA low

t_AVAL

1. C_b= total capacitance of the one bus line in pF.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

External memory interface

Table 46. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes

Symbol Characteristic

Min.

0.01

Typ.

12.5

—

Max.

Unit

MHz

Notes

f_SCL

t_LOW

t_{DIG_L}

SCL Clock Frequency

LOW period of the SCL clock

—

t_{HIGH_MIXED}HIGH period of the SCL clock for a mixed bus

—

t_{DIG_H_MIXE}

—

t_HIGH

t_{DIG_H}

t_SCO

t_CR

HIGH period of the SCL clock

—

Clock in to data out for a slave

SCL clock rise time

150 * 1 /

fSCL

(capped at

60)

t_CF

SCL clock fall time

—

150 * 1 /

fSCL

(capped at

60)

t_{HD_PP}

SDA signal data hold

• Master mode

• Slave mode

tCR+3 and

tCF+3

—

t_{SU_PP}

t_CASr

SDA signal setup

—

Clock after repeated START (Sr)

Clock before repeated START (Sr)

t_CAS(min)

t_CBSr

t_CAS

(min)/2

C_b

Capacitive load per bus line

—

1. When communicating with an I3C Device on a mixed Bus, the t_{DIG_H_MIXED}period must be constrained in order to make

sure that I²C devices do not interpret I3C signaling as valid I²C signaling.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

t_{HD; DAT}

t_HIGH

Figure 33. Timing definition for devices on the I²C bus

1.8 Timer modules

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Architectural overview

1.8.1 SCTimer/PWM output timing

T_amb= -20 °C to 70 °C; 1.71 V ≤ V_DD≤ 1.89 V C_L= 20 pF. Simulated skew (over process, voltage, and temperature) of

any two SCT fixed-pin output signals; sampled at the 50% level of the rising or falling edge; values guaranteed by design.

Table 47. SCTimer/PWM output dynamic characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

t_sk(o)

output skew

time

2.8

2 Architectural overview

The Arm Cortex-M33 includes two AHB-Lite buses: the code bus and the system bus.

The i.MX RT500 uses a multi-layer AHB matrix to connect the Arm Cortex-M33

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slave ports of the matrix to

be accessed simultaneously by different bus masters.

2.1 Detailed block diagram

The following figure shows the detailed block diagram for i. MX RT500

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Architectural overview

DSI

Host

Interface

MIPI

PHY

LCDIF

GPU

MIPI DSI Interface

HS USB Bus

ISP&Debug

Access Ports

ISP&Debug

Access Ports

HS USB

PHY

AXI Switch

General

Purpose

Smart

DMA

(PwrQuad

&Casper

SDIO

eMMC eMMC

SDIO

HASH

CRYPT

Purpose

S1-9

)

AXI : AHB

bridges

To Shared SRAM partitions 0 - 31

DMA

1-9

PwrQuad

rams

:AHB

AXI

2kB

bridge

Inst

Data

TCM Bus

I-ram

M33with

Tensilica

co-

To Shared SRAM partitions 0 - 27

ram

processors

FPU/MPU

Fusion

DSP

I-ram

ram

To Shared SRAM partitions 28 - 31

Pwr

System

Code

Quad

M6 M7

M10

M11

Boot Rom

192

cache ram

FlexSPI0

Cache

OTFAD

Controller

Flash Interface

To Shared SRAM partitions 0,1 (32 KB each)

To Shared SRAM partitions 2,3 (32 KB each)

To Shared SRAM partitions 4-7 (32 KB each)

P10

To Shared SRAM partitions 8-11 (64 KB each)

To Shared SRAM partitions 12-15 (128 KB each)

To Shared SRAM partitions 16-19 (256 KB each)

To Shared SRAM partitions 20-23 (256 KB each)

To Shared SRAM partitions 24-27 (256 KB each)

To Shared SRAM partitions 28-31 (256 KB each)

32KB

Smart DMA

RAM 32KB

P11

P12

cache ram

FlexSPI1

Flash I’face

Cache

Controller

P14

AIPS Lite

bridge

DMA

DMA0

GPIO

0-7

registers

Flexcoms 0-3

UARTs 0-3 - I2Cs 0-3

-SPIs 0-3 - I2Cs 0-3

registers

Timer

MU0

SEMA

P15

Flexcom16

-SPI15

Flexcom15

-I2C14

CRC

Engine

Audio Subsys

Flexcoms

Flexcom 14

-SPI14

Multilayer

AHB Matrix

(8-ch D -Mic

, etc)

UARTs 4-7

I2Cs 4-7

Decimator

SPIs 4-7 - I2Cs 4-7

P16

-Lite

AIPS

bridge

FlexSPI

SDIO0

registers

SDIO1

OTP

FlexSPI1

registers

ADC

registers

controller

OTFAD

registers

12-

16Kb OTP

Array

Temp

Sensor

Random

USB PHY

ACMP

registers

PMC

registers

Number Gen registers

P17

USB Ram

Interface

HS USB HS USB

SCTimer

PWM

Secure

Control

registers

SRAM

16KB

host

device

registers

P18

P13

Flexcoms8-13

-UARTs8-13

-SPIs8-13

CASPER

registers

AXI Switch

registers

PwrQuad

registers

HASH CRYPT

LCDIF

registers

Secure

GPIO0

slave interface

I2Cs8-13 - I2Ss8-13

CASPER

GPU

registers

rams

2KB

clock generation,

PLLs, power

clocks

AHB to

control, and

APB slave group0

(intended for M33 - only)

and

APB bridge

APB slave group1

other

system functions

controls

0,1, 2

WDT Osc

RSTCTLa, CLKCTLa, SYSCTLa

Windowed WDT1

FreqMeasure

I3C0,1

0,1,2

internal

power

voltage regulators

RBB/FBB

RSTCTLb, CLKCTLb, SYSCTLb

GPIO interrupt Control

Periph Input Mux Selects

Smart DMA Controller

5x32-bit Timers (T0 - 4)

PVT

22-23

I/O Configuration

Always-on Power Domain

PUF Ram

2KB

PUF

RTC Alarm Match

8-12

32kHz Osc

&Dividers

RTC Wake Counter

RTC Alarm Counter

WDT Osc

Windowed WDT0

MicroTick Timer

-Rate Timer

Multi

RTC Count

FlexIO Regs

RTC Subsec Counter

Cache Ctrl0 Regs

Cache Ctrl1 Regs

DSI Phy/Host Controller

Note:

- Orange shaded blocks support General Purpose DMA.

- Yellow shaded blocks include dedicated DMA Ctrl.

Figure 34. i.MX RT500 detailed block diagram

2.2 Shared system SRAM

The entire system TCM SRAM space (accessed in single cycle) of up to 5 MB is

divided into up to 32 separate partitions, which are accessible to both CPUs, both DMA

engines, and all other AHB bus masters. The Fusion CPU TCMI (Instruction) & TCMD

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Architectural overview

(Data) interfaces and the Graphics (GPU/LCD) subsystem each access the RAM via

separate, dedicated 64-bit interfaces. All other masters, including the Cortex-M33

processor and the DMA engines, access RAM via the main 32-bit AHB bus. All of

these accesses are single-cycle with the exception of the GPU/LCD. Hardware

interface modules arbitrate access to each RAM partition between the main AHB bus,

the graphics AHB bus and the Fusion Tightly-Coupled-Memory buses.

Under software control, each of the 32 individual SRAM partitions can be used

exclusively as code or as data, dedicated either CPU, or shared among the various

masters. Each partition can be independently placed in a low-power retention mode or

powered off entirely.

2.3 RT500 modules list

The i.MX RT500 contains a variety of digital and analog modules. The following

table describes briefly about these modules.

Table 48. i.MX RT500 modules list

Block Name

Block

Subsystem

Brief description

Mnemonic

Arm core modules

ARM Cortex M33 processor MCU

Core module

The Arm Cortex-M33 is a general

purpose, 32-bit microprocessor, which

offers high performance and very low

power consumption. The Arm Cortex-

M33 offers many new features, including

a Thumb-2 instruction set, low interrupt

latency, hardware multiply and divide,

interruptable/continuable multiple load

and store instructions, automatic state

save and restore for interrupts, tightly

integrated interrupt controller with wake-

up interrupt controller, and multiple core

buses capable of simultaneous

accesses. M33 includes ARM’s

TrustZone M for enhanced security as

well as a co-processor interface. This

interface is used on this device to provide

hardware acceleration for DSP functions

(Powerquad co-processor) and Security/

cryptography operations (CASPER co-

processor). A 3-stage pipeline is

employed so that all parts of the

processing and memory systems can

operate continuously. Typically, while

one instruction is being executed, its

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Architectural overview

Block Name

Table 48. i.MX RT500 modules list (continued)

Block

Subsystem

Brief description

Mnemonic

successor is being decoded, and a third

instruction is being fetched from memory.

Arm Cortex-M33 integrated FPU

Floating Point Unit (FPU)

Core modules

The FPU fully supports single-precision

add, subtract, multiply, divide, multiply

and accumulate, and square root

operations. It also provides conversions

between fixed-point and floating-point

data formats, and floating-point constant

instructions. The FPU provides floating-

point computation functionality that is

compliant with the ANSI/IEEE Std

754-2008, IEEE Standard for Binary

Floating-Point Arithmetic, referred to as

the IEEE 754 standard.

Memory Protection Unit

MPU

Core module

The Cortex-M33 includes a Memory

Protection Unit (MPU) which can be used

to improve the reliability of an embedded

system by protecting critical data within

the user application. The MPU allows

separating processing tasks by

disallowing access to each other's data,

disabling access to memory regions,

allowing memory regions to be defined

as read-only and detecting unexpected

memory accesses that could potentially

break the system. The MPU separates

the memory into distinct regions and

implements protection by preventing

disallowed accesses. The MPU supports

up to eight regions each of which can be

divided into eight subregions. Accesses

to memory locations that are not defined

in the MPU regions, or not permitted by

the region setting, will cause the Memory

Management Fault exception to take

place.

Nested Vectored Interrupt

Controller (NVIC) for Cortex-

M33

NVIC

Core modules

The NVIC is an integral part of the

Cortex-M33. The tight coupling to the

CPU allows for low interrupt latency and

efficient processing of late arriving

interrupts.

System Tick timer (SysTick) SysTick

The Arm Cortex-M33 includes a system

tick timer (SysTick) that is intended to

generate a dedicated SYSTICK

exception. The clock source for the

SysTick can be the FRO or the Cortex-

M33 core clock.

Memories

On-Chip static RAM

SRAM

Memories

The i.MX RT500 supports up to 5 MB

SRAM with separate bus master access

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

for higher throughput and individual

power control for low-power operation.

On-chip ROM

ROM

Memories

The 192 KB on-chip ROM contains the

boot loader and the following Application

Programming Interfaces (API):

• In-Application Programming (IAP)

and In-System Programming (ISP).

• ROM-based USB drivers (HID,

CDC, MSC). Supports flash

updates via USB.

• Supports booting from valid Octal/

Quad SPI, eMMC, USB, USART,

SPI, and I2C. • Legacy, Single, and

Dual image boot.

• OTP API for programming OTP

memory.

• Random Number Generator (RNG)

API.

One-Time Programmable

memory

OTP

FRO

Memories

The i.MX RT500 contains up to 16 kbits

one-time-programmable memory used

for part configuration, key storage (as an

alternative to PUF) and other uses.

Clock sources

System control

192 MHz Free Running

Oscillator (FRO)

The 192 MHz FRO oscillator provides a

high-frequency clock source that can be

used without the need for a high-power

PLL for many applications. This oscillator

is factory trimmed to 1% accuracy but

can optionally be tuned to 0.1%

accuracy using an accurate, known

reference clock such as the crystal

oscillator. The 192 MHz FRO, or a

divided version of it, may be used as the

main system clock and for many other

purposes.

1 MHz Low Power Oscillator LPO

System Control

The 1 MHz oscillator provides an ultra

low-power, low-frequency clock source

that can be used to clock a variety of

functions including the Watchdog Timer

(WWDT) and the OS/EVENT Timer. It

can also be used as the main system

clock for low-power operation. On Reset,

the device boots using this 1 MHz

oscillator.

The 1 MHz Low Power oscillator is

accurate to 5% over temperature.

Crystal Oscillator

System Control

The main crystal oscillator on the i.MX

RT500 can be used with crystal

frequencies from 4 MHz to 26 MHz. The

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Architectural overview

Block Name

Table 48. i.MX RT500 modules list (continued)

Block

Subsystem

Brief description

Mnemonic

crystal oscillator may be used to drive a

PLL to achieve higher clock rates.

32 KHz Crystal Oscillator

System Control

The 32KHz oscillator resides in the

"always-on" domain and is used to drive

the Real Time Clock. It is also available

for use for a variety of other purposes

including low-power UART operation or

as the main system clock for very low

frequency operation

System Control (PLLs)

System PLL (PLL0)

Audio PLL (PLL1)

PLL0

PLL1

System Control

The system PLL accepts an input clock

frequency in the range of 32.768 kHz to

25 MHz. The input frequency is multiplied

up to a high frequency with a Current

Controlled Oscillator (CCO). Generates

four independent outputs (PFD0-3).

System Control

The audio PLL accepts an input clock

frequency in the range of 1 MHz to 25

MHz. The input frequency is multiplied up

to a high frequency with a Current

Controlled Oscillator (CCO). The PLL can

be enabled or disabled by software.

I/O Muxing

General Purpose I/O (GPIO) GPIO

Pin Muxing

The i.MX RT500 provides up to six GPIO

ports with a total of up to 136 GPIO pins.

Device pins that are not connected to a

specific peripheral function are controlled

by the GPIO registers. Pins may be

dynamically configured as inputs or

outputs. Separate registers allow setting

or clearing any number of outputs

simultaneously. The current level of a

port pin can be read back no matter what

peripheral is selected for that pin. It can

optionally contribute to one of two GPIO

group interrupts, with selection of

polarity, level or edge detection.

Pin Interrupt and Pattern

Match (PINT)

I/O Mux

The pin interrupt block configures up to

eight pins from all digital pins for

providing eight external interrupts

connected to the NVIC. The pattern

match engine can optionally be used in

conjunction with software to create

complex state machines based on pin

inputs. Any digital pin, independent of the

function selected through the switch

matrix can be configured through the

SYSCON block as an input to the pin

interrupt or pattern match engine. The

registers that control the pin interrupt or

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

pattern match engine are located on the

I/O+ bus for fast single-cycle access.

Communication peripherals

High-speed USB Host/

Device interface (USB1)

USB1

Communication interfaces

The Universal Serial Bus (USB) is a 4-

wire bus that supports communication

between a host and one or more (up to

127) peripherals. The host controller

allocates the USB bandwidth to attached

devices through a token-based protocol.

The device controller enables 480 Mbit/s

data exchange with a USB host

controller. It consists of a register

interface, serial interface engine,

endpoint buffer memory. The bus

supports hot plugging and dynamic

configuration of the devices. All

transactions are initiated by the host

controller.

Flex SPI Controller

(FlexSPI)

FlexSPI

Communication interfaces

Two FlexSPI Interface modules,

supporting Octal and Quad SPI memory

devices are provided. The first FlexSPI

instance is primarily intended for code

execution from off-chip SPI flash

memory. The second instance is

primarily intended to access data from

RAMs like HyperRAM or pSRAM

(particularly for graphics). The second

instance is accessible by the DSP

processor as well as the M33. Target will

be for both interfaces to support up to

200 MHz DDR/SDR The FlexSPI

interfaces support HyperFlash,

HyperRAM and Xccela memory types,

among others. The first FlexSPI interface

(FlexSPI0) supports execute-in-place and

on-the-fly decryption using the latest

OTFAD module. It also provides a

mechanism to shift a designated range of

addresses to a different region of off-chip

memory to support dual-image boot. Both

FlexSPI Interfaces include a 32 KB cache

with an CACHE64 AHB-cache controller.

Additional logic is provided at the

CACHE64 interface to enable different

caching policies for different address

regions. These policies include:

• Write-back

• Write-through

• Non-cached

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

SD/eMMC interfaces

uSDHC

Communication interfaces

Two uSDHC SDIO/MMC card interfaces

are provided. One instance of this

interface (SDIO0) supports the eMMC

5.0 standard including HS400 DDR

mode. The other instance supports 100

MHz SDR, 50 MHz DDR.

Flexcomm Interface

FlexComm

Communication interfaces

Following are the features of FlexComm:

• USART with asynchronous

operation or synchronous master

or slave operation.

• SPI master or slave, with up to 4

slave selects.

• I2C, including separate master,

slave, and monitor functions.

• Two I2S functions using Flexcomm

Interface 6 and Flexcomm Interface

• Data for USART, SPI, and I2S

traffic uses the Flexcomm Interface

FIFO. The I2C function does not

use the FIFO.

I3C interface

I3C

Communication interface

Two I3C master/slave interfaces are

provided, both of which support DDR.

Counter/Timer modules

General-purpose 32-bit

timers/external event

counter

Counter/Timers

The i.MX RT500 includes five general-

purpose 32-bit timer/counters. The timer/

counter is designed to count cycles of the

system derived clock or an externally-

supplied clock. It can optionally generate

interrupts, generate timed DMA requests,

or perform other actions at specified

timer values, based on four match

registers. Each timer/counter also

includes two capture inputs to trap the

timer value when an input signal

transitions, optionally generating an

interrupt.

SCTimer/PWM

SCT/PWM

Counters/Timers

The SCTimer/PWM allows a wide variety

of timing, counting, output modulation,

and input capture operations. The inputs

and outputs of the SCTimer/PWM are

shared with the capture and match

inputs/outputs of the 32-bit general-

purpose counter/timers. The

SCTimer/PWM can be configured as two

16-bit counters or a unified 32-bit

counter. In the two-counter case, in

addition to the counter value the following

operational elements are independent for

each half:

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

• State variable

• Limit, halt, stop, and start

conditions.

• Values of Match/Capture registers,

plus reload or capture control

values.

In the two-counter case, the following

operational elements are global to the

SCTimer/PWM, but the last three can

use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

Windowed Watchdog Timer WWDT

(WWDT)

Timers

The purpose of the watchdog is to reset

the controller if software fails to

periodically service it within a

programmable time window. A separate

Watchdog Timer is provided for each of

the two CPUs.

Real Time Clock Timer

Multi-Rate Timer

RTC Timer

The RTC timer is a 32-bit timer which

counts down from a preset value to zero.

At zero, the preset value is reloaded and

the counter continues. The RTC timer

uses the 32.768 kHz clock input to create

a 1 Hz or 1 kHz clock.

MRT

The Multi-Rate Timer (MRT) provides a

repetitive interrupt timer with four

channels. Each channel can be

programmed with an independent time

interval, and each channel operates

independently from the other channels.

OS/Event Timer

An OS/EVENT Timer module provides a

common timebase between the two

CPUs for event synchronization and

timestamping. The OS/EVENT Timer is

comprised of a shared, free-running

counter readable by each CPU and

individual match and capture registers for

each CPU. The shared and local

counters in this module are implemented

using Gray code. This will enable them to

be read asynchronously by the

processing domains. The main counter in

the OS/EVENT Timer module begins

counting immediately following power-up

and continues counting through any

subsequent system resets (except those

caused by a new POR).

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

Micro-Tick Timer

MTR

Timers

A 32-bit MicroTick timer that runs from

the 1 MHz low-power oscillator. This

timer can wake up the device from

reduced power modes up to deep-sleep,

with extremely low power consumption.

The MicroTick timer has an added

timestamp feature in the form of 4

capture registers.

Graphics Peripherals

2D Graphics Processing

Unit (GPU)

GPU2D

Graphics

A 2D graphics engine is provided. The

GPU is used to generate graphics data

for display by the LCD Display Controller.

The GPU supports displays up to

640x480.

MIPI DSI Controller with on- MIPI-DSI

chip PHY

Graphics

LCD Display Controller, with on-chip MIPI

DSI Phy provides transfer rates up to

895.1 Mbps to support 1024x480

displays with 24-bit color at 60 frames

per second. A parallel DBI interface is

also provided (alternative to the serial

PHY).

Flexio

FlexIO

DMA

Graphics/Multimedia

The Flexio module under "Others"

category can be used to interface to an

LCD with a parallel interface.

Other Digital Peripherals

DMA Controller

Other

The DMA controller allows peripheral-to

memory, memory-to-peripheral, and

memory-to-memory transactions. Each

DMA stream provides unidirectional DMA

transfers for a single source and

destination. Two identical DMA

controllers are provided on i.MX RT500.

The user may elect to dedicate one of

these to the Cortex M-33 CPU and the

other for use by the DSP CPU and/or one

may be used as a secure DMA the other

non-secure.

DMIC Subsystem

DMIC

Other

DMIC subsystem includes:

• Pulse-Density Modulation (PDM)

data input for left and/or right

channels on 1 or 2 buses.

• Flexible decimation.

• 16 entry FIFO for each channel.

• DC blocking or unaltered DC bias

can be selected.

• Data can be transferred using DMA

from deep-sleep mode without

waking up the CPU, then

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Architectural overview

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

automatically returning to deep-

sleep mode.

• Data can be streamed directly to

I2S on Flexcomm Interface 7.

Smart DMA Engine

Flexible Input/Output

Smart DMA

Controller

Other

Smart DMA Controller with dedicated 32

KB code RAM

FlexIO

Others

The Flexible Input/Output (FlexIO)

module is capable of supporting a wide

range of protocols including, but not

limited to: UART, I2C, SPI, I2S, camera

interface, display interface, PWM

waveform generation, and so on

Cyclic Redundancy

Check(CRC) engine

CRC

Other

The Cyclic Redundancy Check (CRC)

generator with programmable polynomial

settings supports several CRC standards

commonly used. To save system power

and bus bandwidth, the CRC engine

supports DMA transfers.

Analog Peripherals

Analog

12-bit Analog to Digital

Converter

ADC

The ADC supports a resolution of 12-bit

and fast conversion rates of up to 1

Msamples/s. Sequences of analog-to-

digital conversions can be triggered by

multiple sources. Possible trigger

sources are the SCTimer/PWM, external

pins, and the Arm TXEV interrupt.

Temperature Sensor

Analog

The temperature sensor transducer uses

an intrinsic pn-junction diode reference

and outputs a CTAT voltage

(Complement To Absolute Temperature).

The output voltage varies inversely with

device temperature with an absolute

accuracy of better than 5 °C over the

full temperature range (-20 °C to +70 °C).

The temperature sensor is only

approximately linear with a slight

curvature. The output voltage is

measured over different ranges of

temperatures and fit with linear-least-

square lines. After power-up, the

temperature sensor output must be

allowed to settle to its stable value before

it can be used as an accurate ADC input.

For an accurate measurement of the

temperature sensor by the ADC, the ADC

must be configured in single-channel

burst mode. The last value of a nine-

conversion (or more) burst provides an

accurate result.

Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

Table 48. i.MX RT500 modules list (continued)

Block Name

Block

Subsystem

Brief description

Mnemonic

Analog Comparator

CMP

Analog

The Comparator (CMP) module provides

a circuit for comparing two analog input

voltages. The comparator circuit is

designed to operate across the full range

of the supply voltage (rail to rail

operation).

Security

Security Subsystem

Security

Comprises of:

• Trust Zone M

• AES256 Decryption Engine.

• SHA-1, SHA-2 HASH Engine.

• Physical Unclonable Function

(PUF) Key Generation

• CASPAR security Cortex-M33 co-

processor

• OTP memory

• Random number generator (RNG)

• On-the-Fly Decryption on FlexSPI

interface

On-The-Fly AES Decryption OTFAD

Security

The On-The-Fly AES Decryption

(OTFAD) module provides an advanced

hardware implementation that minimizes

any incremental cycles of latency

introduced by the decryption in the

overall external memory access time.

The OTFAD engine also includes

complete hardware support for a

standard AES key unwrap mechanism to

decrypt a key BLOB data instruction

containing the parameters needed for up

to 4 unique AES contexts.

True Random Number

Generator

TRNG

Security

The True Random Number Generator

(TRNG) module is used to generate high

quality, cryptographically secure, random

data. The TRNG module is capable of

generating its own entropy using an

integrated ring oscillator.

3 Application information

3.1 Current consumption vs. memory partitions

The following figure shows the current consumption vs memory partitions:

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

M33 active, running enhanced-while(1) code in different partitions.

Typical silicon, VDDCore=1.1V, Temperature=25℃, FBB, HCLK=192MHz (FRO).

All memories array/periphery ON (PDRUNCFG2/3) and only one partition clocked

(AHB_SRAM_ACCESS_DISABLE register).

Figure 35. Current consumption vs. memory partitions

3.2 Standard I/O pin configuration

The following figure shows the possible pin modes for standard I/O pins:

The default configuration for standard I/O pins is Z mode. The weak MOS devices

provide a drive capability equivalent to pull-up and pull-down resistors.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

from selected

pin function

FULLDRIVE

data out

output

driver

device

SLEWRATE

driver

configuration

logic

PUPDENA

PUPDSEL

ODENA

PU/PD/keeper

logic

PUPDENA

IBENA

PU/PD keeper

devices device

input

receiver

data in

IIENA

analog in

AMENA

Figure 36. Pin configuration

3.3 I/O power consumption

I/O pins are contributing to the overall dynamic and static power consumption of the

part. If pins are configured as digital inputs, a static current can flow depending on the

voltage level at the pin and the setting of the internal pull-up and pull-down resistors.

This current can be calculated using the parameters R_puand R_pdgiven in Table 6 for a

given input voltage V_I. For pins set to output, the current drive strength is given by

parameters I_OHand I_OLin Table 6, but for calculating the total static current, you also

need to consider any external loads connected to the pin.

I/O pins also contribute to the dynamic power consumption when the pins are switching

because the V_DDsupply provides the current to charge and discharge all internal and

external capacitive loads connected to the pin in addition to powering the I/O circuitry.

The contribution from the I/O switching current I_swcan be calculated as follows for any

given switching frequency f_swif the external capacitive load (C_ext) is known (see Table

6 for the internal I/O capacitance):

I_sw= V_DDx f_swx (C_io+ C_ext)

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

3.4 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances C_X1and

C_X2need to be connected externally on RTCXIN and RTCXOUT. See the following

figure.

RTxxx

RTCXIN

RTCXOUT

XTAL

Figure 37. RTC oscillator components

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper crystal,

the external load capacitor C_X1and C_X2values can also be generally determined by

the following expression:

C_X1= C_X2= 2C_L- C_Pad- 2C_STRAY

Where:

C_L- Crystal load capacitance

C_Pad- Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF, for each pad).

C_STRAY– stray capacitance between RTCXIN and RTCXOUT pins.

For example:

C_L= 9 pF

C_X1= C_X2= 2C_L- C_Pad- 2C_STRAY

C_X1= C_X2= 2*9 - 3 - 0 = 15 pF

Although C_STRAYcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors.

Therefore, it is recommended to fine tune the values of external load capacitors on

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

actual hardware board to get the accurate clock frequency. For fine tuning, output the

RTC Clock to the CLOCKOUT pin and optimize the values of external load capacitors

for minimum frequency deviation.

To use bypass mode on RTC, remove the crystal, drive an external clock to RTCIN pin,

and float the RTCOUT pin.

3.4.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone

crystal usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

3.5 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances C_Xand C_Y

need to be connected externally on XTALIN and XTALOUT. See the figure below.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

OSC Module

XTALIN

XTALOUT

Crystal

Figure 38. XTAL oscillator connection - Low-Power Mode

OOSSCC MMoodduule

XTALIN

XTALOUT

Crystal

Figure 39. XTAL oscillator connection - High Gain Mode

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper crystal,

the external load capacitor C_X1and C_X2values can also be generally determined by

the following expression:

C_x= C_y= 2C_L- C_Pad- 2C_STRAY

Where:

C_L- Crystal load capacitance

C_Pad- Pad capacitance of the XTALIN and XTALOUT pins (~3 pF, for each pad).

C_STRAY– stray capacitance between XTALIN and XTALOUT pins.

For example:

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

C_L= 9 pF

C_x= C_y= 2C_L- C_Pad- 2C_STRAY

C_x= C_y= 2*9 - 3 - 0 = 15 pF

Although C_STRAYcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors.

Therefore, it is recommended to fine tune the values of external load capacitors on

actual hardware board to get the accurate clock frequency. For fine tuning, measure the

clock on the XTALOUT pin and optimize the values of external load capacitors for

minimum frequency deviation.

To use bypass mode on system oscillator, set bit 1 to "1" in the system oscillator control

0 (CLKCTL0_SYSOSCCTL0), float the XTALIN pin, and drive XTALOUT with < 0.7

V to 1.8 V.

For oscillator high gain mode, a larger voltage swing is used at the crystal pin. This

gives a higher noise immunity within the oscillator and less edge to edge jitter of the

internal clock. When high gain mode is not required, power used by the crystal

oscillator can be reduced by using low power mode.

NOTE

High gain mode requires a 1 megaohm resistor (RF) to be

inserted.

3.5.1 XTAL Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors C_X, C_Y, and C_X3, in case of third overtone crystal

usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

3.5.2 Thermally compensated crystal oscillator (TCXO)

In the TXCO circuit, only the oscillator should be connected to the XTALIN pin while

the XTALOUT pin remains floating when driving the device with a TXCO. See the

following figure.

i.MX RT500

osc_clk

crystal

oscillator

XTALOUT

XTALIN

TCXO

Figure 40. Thermally compensated crystal oscillator

Symbol

Vmax

Parameter

Conditions

Min.

Typ.

Max.

Units

Maximum XTAL -

input voltage

VDD1V8

Vpp min

Min voltage for

XTALIN

500

800

VPP nom

Voltage where

Jitter in = jitter

out

CXTALIN

Fmax

XTALIN input

Impedance

Maximum input

frequency

MHz

3.6 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 41)

or bus-powered device (see Figure 42).

On the i.MX RT500, the USB_VBUS pin is 5 V tolerant pin regardless of whether

USB1_VDD3V3 or VDD pins are present or not.

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Application information

RTxxx

USB1_VDD3V3

1.5 kΩ

USB

USB_VBUS

D+

D-

USB-B

connector

USB_DP

USB_DM

Figure 41. USB interface on a self-powered device where USB_VBUS = 5 V

The internal pull-up (1.5 kΩ) can be enabled by setting the DCON bit in the

DEVCMDSTAT register to prevent the USB from timing out when there is a

significant delay between power-up and handling USB traffic. External circuitry is not

required.

RTxxx

USB1_VDD3V3

REGULATOR

(1)

USB_VBUS

USB

1.5 kΩ

(2)

USB_VBUS

USB_DP

VBUS

D+

USB-B

D-

connector

USB_DM

Figure 42. USB interface on a bus-powered device

In the figure above, two options exist for connecting VBUS to the USB_VBUS pin:

1. Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is

HIGH whenever the part is powered.

2. Connect the VBUS signal directly from the connector to the USB_VBUS pin. In

this case, 5 V are applied to the USB_VBUS pin while the regulator is ramping up

to to supply USB1_VDD3V3

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Abbreviations

4 Abbreviations

Table 49. Abbreviations

Acronym

Description

Advanced High-performance Bus

AHB

APB

Advanced Peripheral Bus

Application Programming Interface

Direct Memory Access

API

DMA

FRO oscillator

Internal Free-Running Oscillator, tuned to the factory

specified frequency

GPIO

FRO

LSB

General Purpose Input/Output

Free Running Oscillator

Least Significant Bit

MCU

PDM

PLL

MicroController Unit

Pulse Density Modulation

Phase-Locked Loop

SPI

Serial Peripheral Interface

Transmission Control Protocol/Internet Protocol

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

TCP/IP

TTL

USART

5 Pinouts

5.1 Signal multiplexing and pinouts

The table below shows the pin functions available on each pin, and for each package.

These functions are selectable using IOCON control registers.

Some functions, such as ADC or comparator inputs, are available only on specific

pins when digital functions are disabled on those pins. By default, the GPIO function

is selected except on pins PIO2_25 and PIO2_26, which are the serial wire debug

pins. This allows debug to operate through reset.

Most pins have all pull-ups, pull-downs, and inputs turned off at reset. This prevents

power loss through pins prior to software configuration. Due to special pin functions,

some pins have a different reset configuration: If the Boot ROM OTP is configured to

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Pinouts

use the ISP Select pins at boot, then these pins PIO1_15, PIO3_28, and PIO3_29 have

pull-ups enabled by ROM; otherwise these pull-ups are not enabled at boot. The SWD

pins PIO2_25 and PIO2_26 have the input buffers enabled at reset.

The state of pins PIO1_15, PIO3_28, and PIO3_29 at Reset determine the boot source

for the part (if configured in the Boot ROM OTP) or if the ISP handler is invoked.

The JTAG functions TRST, TCK, TMS, TDI, and TDO, are selected on pins PIO0_7 to

PIO0_11 by hardware when the part is in boundary scan mode.

5.2 i.MXRT500 Pinouts: 249 FOWLP package

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

PIO0_0

PIO0_1

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

I2S_BRID

GE_CLK_I

CTIMER0_

MAT0

GPIO_INT

_BMAT

SEC_PIO0

F14

G16

H16

H15

H14

PIO0_0

PIO0_1

PIO0_2

PIO0_3

PIO0_4

PIO0_0

PIO0_1

PIO0_2

PIO0_3

PIO0_4

FC0_SCK

FC0_TXD_

SCL_MIS

O_WS

I2S_BRID

GE_WS_I

CTIMER0_

MAT1

SEC_PIO0

FC0_RXD

I2S_BRID

GE_DATA

_IN

CTIMER0_

MAT2

SEC_PIO0

PIO0_2 _SDA_MO

SI_DATA

FC0_CTS_

SDA_SSE

CTIMER0_ FC1_SSEL

MAT3

SEC_PIO0

PIO0_3

PIO0_4

FC0_RTS_

SCL_SSE

CTIMER_I FC1_SSEL

CMP0_OU SEC_PIO0

NP0

PIO0_5 /

ADC0_0

FC0_SSEL SCT0_GPI SCT0_OU CTIMER_I

T0 NP1

SEC_PIO0

F16

F17

PIO0_5

PIO0_6

PIO0_5

PIO0_6

PIO0_6 /

ADC0_8

FC0_SSEL SCT0_GPI SCT0_OU CTIMER0_

SEC_PIO0

MAT0

I2S_BRID

GE_CLK_

OUT

PIO0_7 /

TRST

SCT0_GPI SCT0_OU CTIMER1_

SEC_PIO0

J15

H12

H17

K16

K15

PIO0_7

PIO0_8

PIO0_9

PIO0_10

PIO0_11

PIO0_7

PIO0_8

FC1_SCK

MAT0

FC1_TXD_

SCL_MIS

O_WS

I2S_BRID

GE_WS_O

PIO0_8 /

TCK

SCT0_GPI SCT0_OU CTIMER1_

T5 MAT1

SEC_PIO0

FC1_RXD

I2S_BRID

GE_DATA

_OUT

PIO0_9 /

TMS

SCT0_GPI SCT0_OU CTIMER1_

SEC_PIO0

PIO0_9 _SDA_MO

SI_DATA

MAT2

FC1_CTS_

PIO0_10 SDA_SSE

PIO0_10 /

TDI

SCT0_GPI SCT0_OU CTIMER1_ FC0_SSEL

T7 MAT3

SEC_PIO0

_10

FC1_RTS_

PIO0_11 SCL_SSE

PIO0_11 /

TDO

SCT0_GPI SCT0_OU CTIMER_I FC0_SSEL

T8 NP2

SEC_PIO0

_11

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

PIO0_12 /

ADC0_1

FC1_SSEL SCT0_GPI SCT0_OU CTIMER_I

T2 NP3

SEC_PIO0

_12

E14

F15

PIO0_12

PIO0_13

PIO0_12

PIO0_13

PIO0_13 /

ADC0_9

FC1_SSEL SCT0_GPI SCT0_OU CTIMER0_

T3 MAT1

SEC_PIO0

_13

I2S_BRID

GE_CLK_I

SCT0_GPI SCT0_OU CTIMER2_

SEC_PIO0

_14

B12

B15

A16

B17

B16

PIO0_14

PIO0_15

PIO0_16

PIO0_17

PIO0_18

PIO0_14

PIO0_15

PIO0_16

PIO0_17

PIO0_18

PIO0_14 FC2_SCK

MAT0

FC2_TXD_

PIO0_15 SCL_MIS

O_WS

I2S_BRID

GE_WS_I

SCT0_GPI SCT0_OU CTIMER2_

T1 MAT1

SEC_PIO0

_15

FC2_RXD

PIO0_16 _SDA_MO

SI_DATA

I2S_BRID

GE_DATA

_IN

SCT0_GPI SCT0_OU CTIMER2_

T2 MAT2

SEC_PIO0

_16

FC2_CTS_

PIO0_17 SDA_SSE

SCT0_GPI SCT0_OU CTIMER2_ FC5_SSEL

T3 MAT3

SEC_PIO0

_17

FC2_RTS_

PIO0_18 SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC5_SSEL

T6 NP4

SEC_PIO0

_18

PIO0_19 /

ADC0_2

FC2_SSEL SCT0_GPI SCT0_OU CTIMER_I UTICK_CA

T4 NP5 P0

SEC_PIO0

_19

F13

A14

PIO0_19

PIO0_21

PIO0_19

SCT0_GPI SCT0_OU CTIMER3_ CTIMER_I TRACECL

SEC_PIO0

_21

PIO0_21

PIO0_21 FC3_SCK

MAT0

NP11

FC3_TXD_

PIO0_22 SCL_MIS

O_WS

SCT0_GPI SCT0_OU CTIMER3_ CTIMER_I TRACEDA

T6 MAT1 NP7 TA[0]

SEC_PIO0

_22

B14

C13

D13

PIO0_22

PIO0_23

PIO0_24

FC3_RXD

PIO0_23 _SDA_MO

SI_DATA

SCT0_GPI SCT0_OU CTIMER3_ CTIMER0_ TRACEDA

T8 MAT2 MAT3 TA[1]

SEC_PIO0

_23

PIO0_23

PIO0_24

FC3_CTS_

PIO0_24 SDA_SSE

SCT0_GPI SCT0_OU CTIMER3_ FC2_SSEL TRACEDA

T9 MAT3 TA[2]

SEC_PIO0

_24

CLKOUT

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC3_RTS_

PIO0_25 SCL_SSE

FREQME_ CTIMER_I FC2_SSEL TRACEDA

SEC_PIO0

_25

C12

A12

B11

D14

D12

PIO0_25

PIO0_28

PIO0_29

PIO0_30

PIO0_31

PIO0_25

PIO0_28

PIO0_29

PIO0_30

PIO0_31

CLKIN

GPIO_CLK

NP6

TA[3]

I2S_BRID

GE_CLK_

OUT

CTIMER4_

MAT0

SEC_PIO0

_28

PIO0_28 FC4_SCK

FC4_TXD_

PIO0_29 SCL_MIS

O_WS

I2S_BRID

GE_WS_O

CTIMER4_

MAT1

SEC_PIO0

_29

FC4_RXD

PIO0_30 _SDA_MO

SI_DATA

I2S_BRID

GE_DATA

_OUT

CTIMER4_

MAT2

SEC_PIO0

_30

FC4_CTS_

PIO0_31 SDA_SSE

SCT0_GPI SCT0_OU CTIMER4_ FC3_SSEL

T6 MAT3

SEC_PIO0

_31

FC4_RTS_

SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC3_SSEL

A10

PIO1_0

PIO1_3

PIO1_4

PIO1_0

PIO1_3

PIO1_4

PIO1_0

PIO1_3

PIO1_4

NP8

HS_SPI1_

SCK

FC5_SCK

FC5_TXD_

SCL_MIS

O_WS

HS_SPI1_

MISO

FC5_RXD

PIO1_5 _SDA_MO

SI_DATA

HS_SPI1_

MOSI

PIO1_5

PIO1_6

PIO1_5

PIO1_6

FC5_CTS_

SDA_SSE

SCT0_GPI SCT0_OU

FC4_SSEL HS_SPI1_

SSELN0

PIO1_6

FC5_RTS_

SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC4_SSEL HS_SPI1_

T5 NP9 SSELN1

PIO1_7

FREQME_ CTIMER_I

GPIO_CLK NP10

PIO1_10

MCLK

CLKOUT

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

HS_SPI0_

SCK

CTIMER2_

MAT0

K13

K14

K17

L16

M16

T17

U16

T15

T14

R13

R12

N12

R14

P14

P13

U14

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_15

PIO1_18

PIO1_19

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_24

PIO1_25

PIO1_26

PIO1_27

PIO1_28

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_15

PIO1_18

PIO1_19

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_24

PIO1_25

PIO1_26

PIO1_27

PIO1_28

HS_SPI0_

MISO

CTIMER2_

MAT1

HS_SPI0_

MOSI

CTIMER2_

MAT2

HS_SPI0_

SSELN0

CTIMER2_

MAT3

PIO1_15 /

ISP0

HS_SPI0_

SSELN1

CTIMER3_

MAT0

FLEXSPI0 SCT0_GPI

_SCLK

CTIMER3_

MAT3

PIO1_18

PIO1_19

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_24

PIO1_25

PIO1_26

PIO1_27

PIO1_28

FLEXSPI0 SCT0_OU

_SS0_N T0

CTIMER4_

MAT0

CLKOUT

FLEXSPI0 SCT0_GPI

_DATA0

CTIMER4_

MAT1

FLEXSPI0 SCT0_OU

_DATA1 T1

CTIMER4_

MAT2

FLEXSPI0 SCT0_GPI

_DATA2

CTIMER4_

MAT3

FLEXSPI0 SCT0_OU

_DATA3 T2

CTIMER_I

NP8

FLEXSPI0 SCT0_GPI

_DATA4

FLEXSPI0 SCT0_OU

_DATA5 T3

FLEXSPI0 SCT0_GPI

_DATA6

FLEXSPI0 SCT0_OU

_DATA7 T4

FLEXSPI0 SCT0_GPI

_DQS

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FLEXSPI0 SCT0_OU UTICK_CA CTIMER_I FLEXSPI0

U12

PIO1_29

PIO1_30

PIO1_31

PIO2_0

PIO2_1

PIO2_2

PIO2_3

PIO2_4

PIO2_5

PIO1_29

PIO1_30

PIO1_31

PIO2_0

PIO2_1

PIO2_2

PIO2_3

PIO2_4

PIO2_5

PIO1_29

_SS1_N

NP13

_SCLK_N

SCT0_GPI

PIO1_30 SD0_CLK

PIO1_31 SD0_CMD

SCT0_GPI

SmartDMA

_PIO0

PIO2_0

PIO2_1

PIO2_2

PIO2_3

PIO2_4

PIO2_5

SD0_D[0]

SD0_D[1]

SD0_D[2]

SD0_D[3]

SCT0_GPI

SmartDMA

_PIO1

SCT0_OU

SmartDMA

_PIO2

SCT0_OU

SmartDMA

_PIO3

SD0_WR_ SCT0_OU

SmartDMA

_PIO4

SD0_DS

PRT

SCT0_OU

SmartDMA

_PIO5

SD0_D[4]

FC8_SCK

FC8_TXD_

SCL_MIS

O_WS

SCT0_GPI

CTIMER1_

MAT0

SmartDMA

_PIO6

PIO2_6

PIO2_7

PIO2_8

PIO2_6

PIO2_7

PIO2_8

PIO2_6

PIO2_7

PIO2_8

SD0_D[5]

SD0_D[6]

SD0_D[7]

FC8_RXD

_SDA_MO

SI_DATA

SCT0_GPI

CTIMER1_

MAT1

SmartDMA

_PIO7

FC8_CTS_

SDA_SSE

SCT0_OU

CTIMER1_

MAT2

SmartDMA

_PIO8

FC8_CTS_

SDA_SSE

SD0_CAR SCT0_OU

D_DET_N T5

CTIMER1_

MAT3

SmartDMA

_PIO9

PIO2_9

SD0_RES SCT0_GPI

ET_N

CTIMER2_ FC8_SSEL

MAT0

SmartDMA

_PIO10

PIO2_10

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

SD0_VOL SCT0_GPI

CTIMER2_ FC8_SSEL

SmartDMA

_PIO11

E15

D17

PIO2_11

PIO2_14

PIO2_15

PIO2_24

PIO2_25

PIO2_26

PIO2_11

PIO2_14

PIO2_15

PIO2_24

PIO2_25

PIO2_26

MAT1

PIO2_14 /

CMP0_A

SCT0_OU

CTIMER_I

NP1

32KHZ_CL

KOUT

SmartDMA

_PIO14

PIO2_15 /

CMP0_D

SCT0_OU

SmartDMA

_PIO15

CLKIN

GPIO_INT

_BMAT

SmartDMA

_PIO24

PIO2_24

PIO2_25

PIO2_26

SWO

SmartDMA

_PIO25

SWCLK

SmartDMA

_PIO26

SWDIO

USB1_OV

PIO2_27 ERCURRE

NTN

SmartDMA

_PIO27

PIO2_27

USB1_PO

PIO2_28

SmartDMA

_PIO28

B10

D10

C14

PIO2_28

PIO2_29

PIO2_30

PIO2_28

PIO2_29

PIO2_30

PIO2_31

RTPWRN

SCT0_OU

SmartDMA

_PIO029

PIO2_29 I3C0_SCL

PIO2_30 I3C0_SDA

PIO2_31 I3C0_PUR

CLKOUT

CLKIN

SWO

SCT0_OU

CMP0_OU

SmartDMA

_PIO30

PIO2_31 /

CMP0_B

SCT0_OU UTICK_CA CTIMER_I

T7 P3 NP15

SmartDMA

_PIO31

USB1_VB USB1_VB

US US

USB1_VD USB1_VD

D3V3 D3V3

USB1_DM USB1_DM

USB1_DP USB1_DP

PMIC_MO PMIC_MO

DE1

PMIC_MO PMIC_MO

DE0 DE0

DE1

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

PMIC_I2C PMIC_I2C

_SDA

PMIC_I2C PMIC_I2C

_SCL _SCL

PMIC_IRQ PMIC_IRQ

PMIC_LD

O_ENABL

LDO_ENA

BLE

XTALIN

XTALOUT XTALOUT

RTCXIN RTCXIN

RTCXOUT RTCXOUT

RESETN RESETN

F12

G12

VREFP

VREFN

VREFP

VREFN

FC0_TXD_

SCL_MIS I3C1_SCL

O_WS

PDM_CLK PDM_DAT

23 A23

D16

C16

PIO3_1

PIO3_2

PIO3_1

PIO3_2

PIO3_1

PIO3_2

FC0_RXD

_SDA_MO I3C1_SDA

SI_DATA

PDM_CLK PDM_DAT

45 A45

FC0_CTS_

SDA_SSE I3C1_PUR

PDM_CLK PDM_DAT

CMP0_OU

D15

PIO3_3

PIO3_8

PIO3_9

PIO3_3

PIO3_8

PIO3_9

PIO3_3

PIO3_8

LCD_D23

A67

CTIMER0_

MAT0

FC10_SC

SD1_CLK LCD_D9

FC10_TXD

_SCL_MIS

CTIMER0_

MAT1

PIO3_9 SD1_CMD LCD_D10

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC10_RX

D_SDA_M

OSI

CTIMER0_

MAT2

C10

PIO3_10

PIO3_11

PIO3_10

PIO3_11

PIO3_12

PIO3_10 SD1_D[0] LCD_D11

PIO3_11 SD1_D[1] LCD_D12

PIO3_12 SD1_D[2] LCD_D13

FC10_CTS

_SDA_SS

ELN0

CTIMER0_

MAT3

FC10_RTS

_SCL_SS

ELN1

CTIMER_I

NP0

PIO3_12

PIO3_13

CTIMER_I

NP1

FC10_SSE

LN2

PIO3_13

PIO3_14

PIO3_15

PIO3_13 SD1_D[3] LCD_D14

SD1_WR_

PIO3_14 /

CMP0_E

CTIMER3_

MAT0

FC10_SSE

LN3

PIO3_14

LCD_D15

SD1_DS

PRT

CTIMER3_

MAT1

E10

PIO3_15

PIO3_15 SD1_D[4] LCD_D16

PIO3_16 SD1_D[5] LCD_D17

FC5_SCK

FC5_TXD_

SCL_MIS

O_WS

CTIMER3_

MAT2

PIO3_16

PIO3_17

PIO3_18

FC5_RXD

_SDA_MO

SI_DATA

CTIMER3_

MAT3

PIO3_17

PIO3_18

PIO3_17 SD1_D[6] LCD_D18

FC5_CTS_

SDA_SSE

CTIMER4_

MAT0

PIO3_18 SD1_D[7] LCD_D19

SD1_CAR

CTIMER4_

MAT1

PIO3_19

PIO3_20

PIO3_19

PIO3_20

PIO3_19

PIO3_20

PIO3_21

LCD_D20

LCD_D21

LCD_D22

MCLK

D_DET_N

SD1_RES

ET_N

CTIMER4_

MAT2

SD1_VOL

CTIMER4_

MAT3

GPIO_INT

_BMAT

PIO3_21

PIO3_25

PIO3_21

PIO3_25

R16

PIO3_25 FC6_SCK

FC6_TXD_

PIO3_26 SCL_MIS

O_WS

T16

PIO3_26

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC6_RXD

N14

N13

PIO3_27

PIO3_28

PIO3_27 _SDA_MO

SI_DATA

FC6_CTS_

PIO3_28 SDA_SSE

PIO3_28 /

ISP1

FC6_RTS_

PIO3_29 SCL_SSE

PIO3_29 /

ISP2

M13

N15

M15

PIO3_29

PIO4_0

PIO4_1

FREQME_

GPIO_CLK

PIO4_0

PIO4_1

PIO4_0

FC7_SCK

CLKOUT

CLKIN

FC7_TXD_

SCL_MIS

O_WS

PIO4_1

FC7_RXD

M17

M14

P17

P16

P15

PIO4_2

PIO4_3

PIO4_4

PIO4_5

PIO4_6

PIO4_2

PIO4_3

PIO4_4

PIO4_5

PIO4_6

PIO4_2 _SDA_MO

SI_DATA

FC7_CTS_

PIO4_3

PIO4_4

PIO4_5

PIO4_6

SDA_SSE

FC7_RTS_

SCL_SSE

FC1_SCK

FC1_TXD_

SCL_MIS

O_WS

FC7_SSEL

FC1_RXD

_SDA_MO

SI_DATA

FC7_SSEL

MIPI_DSI_ MIPI_DSI_

CLKP CLKP

MIPI_DSI_ MIPI_DSI_

CLKN CLKN

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

MIPI_DSI_ MIPI_DSI_

D0P

MIPI_DSI_ MIPI_DSI_

D0N D0N

MIPI_DSI_ MIPI_DSI_

D1P D1P

MIPI_DSI_ MIPI_DSI_

D1N D1N

MIPI_DSI_ MIPI_DSI_

VDD11 VD11

MIPI_DSI_ MIPI_DSI_

VDD18 VDD18

MIPI_DSI_ MIPI_DSI_

VDDA_CA VDDA_CA

MIPI_DSI_ MIPI_DSI_

VSS

FLEXSPI1

_SCLK

PIO4_11

PIO4_11 FC2_SCK

SD1_CLK

SD1_CMD

FC2_TXD_

PIO4_12 SCL_MIS

O_WS

FLEXSPI1

_DATA0

PIO4_12

PIO4_13

PIO4_14

PIO4_12

PIO4_13

PIO4_14

FC2_RXD

PIO4_13 _SDA_MO

SI_DATA

FLEXSPI1

_DATA1

SD1_D[0]

SD1_D[1]

FC2_CTS_

PIO4_14 SDA_SSE

FLEXSPI1

_DATA2

FC2_RTS_

PIO4_15 SCL_SSE

FLEXSPI1

_DATA3

PIO4_15

PIO4_16

PIO4_15

PIO4_16

SD1_D[2]

SD1_D[3]

FC2_SSEL FLEXSPI1

_DQS

PIO4_16

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC2_SSEL FLEXSPI1 FLEXSPI1 SD1_WR_

E13

PIO4_17

PIO4_18

PIO4_20

PIO4_17

PIO4_18

_SS1_N _SCLK_N

PRT

PIO4_18 /

ADC0_6

FLEXSPI1

_SS0_N

SD1_D[4]

FC11_SC

FLEXIO_D

PIO4_20

PIO4_20 DBI_CSX

PIO4_21 DBI_DCX

SD1_D[6]

SD1_D[7]

FC11_TXD

_SCL_MIS

FLEXIO_D

P10

U10

PIO4_21

PIO4_22

PIO4_23

PIO4_24

FC11_RX

D_SDA_M

OSI

SD1_CAR

D_DET_N

FLEXIO_D

PIO4_22

PIO4_23

PIO4_24

PIO4_22

FC11_CTS

_SDA_SS

ELN0

DBI_RWD LCD_ENA

SD1_RES

ET_N

TRACECL FLEXIO_D

PIO4_23

BLE

FC11_RTS

_SCL_SS

ELN1

LCD_DTC

SD1_VOL

TRACEDA FLEXIO_D

TA[0]

T10

PIO4_24 DBI_WRX

LCD_HSY

FC11_SSE TRACEDA FLEXIO_D

LN2 TA[1]

T11

T12

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

DBI_E

LCD_VSY

FC11_SSE TRACEDA FLEXIO_D

LN3

TA[2]

TRACEDA FLEXIO_D

LCD_D0

LCD_D1

LCD_D2

DBI_D0

DBI_D1

DBI_D2

TA[3]

FLEXIO_D

FC12_TXD

_SCL_MIS

FLEXIO_D

PIO4_30

LCD_D3

DBI_D3

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

PIO4_31

PIO5_0

PIO5_1

PIO5_2

PIO5_3

Func 1

LCD_D4

LCD_D5

LCD_D6

LCD_D7

Func 2

DBI_D4

DBI_D5

DBI_D6

DBI_D7

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC12_RX

D_SDA_M

OSI

FLEXIO_D

N10

P12

PIO4_31

PIO5_0

PIO5_1

PIO5_2

PIO5_3

PIO4_31

PIO5_0

PIO5_1

PIO5_2

PIO5_3

FC12_CTS

_SDA_SS

ELN0

FLEXIO_D

FC12_RTS

_SCL_SS

ELN1

FLEXIO_D

LOW_FRE

Q_CLKOU

FC12_SSE

LN2

FLEXIO_D

LOW_FRE

Q_CLKOU

T_N

FC12_SSE

LN3

FLEXIO_D

R10

LCD_D8

LCD_D9

DBI_D8

DBI_D9

PDM_CLK

PIO5_4

PIO5_8

PIO5_4

PIO5_8

PIO5_4

PIO5_8

PDM_DAT

A01

LCD_D13 DBI_D13

FC4_CTS_

SDA_SSE

FLEXSPI1

_DATA4

PIO5_15

PIO5_16

PIO5_15

PIO5_16

PIO5_15 LCD_D20

PIO5_16 LCD_D21

FC4_RTS_

SCL_SSE

FLEXSPI1

_DATA5

FLEXSPI1

_DATA6

FC4_SSEL

PIO5_17

PIO5_18

PIO5_17

PIO5_18

PIO5_17 LCD_D22

PIO5_18 LCD_D23

FLEXSPI1

_DATA7

FC4_SSEL

J12,

J13,K12, VDDIO_0

M10,M12

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

E9,

F10,F11, VDDIO_1

F9,J5 J6

N6, P7

M8 N9

F6, F7

VDDIO_2

VDDIO_3

VDDIO_4

G9,

H10,H8,

H9,J10,

J11,J9,

K10,K8,

K9, L9

VDDCORE

VDD_AO1

D4, B2

H13

VDDA_AD

C1V8

VDDA_BIA

E12

D11, D7

VSSA

A1, A17,

C3, C7,

C11, C15,

E7, E11,

G3, G4,

G5, G7,

G8, G10,

G11, G13,

G14, G15,

H11, K7,

K11, L3,

L4, L5, L6,

L7, L8,

VSS

L10, L11,

L12, L13,

L14, L15,

Table continues on the next page...

Part Num

(249FOW Pin Name DEFAULT

LP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

M7, M11,

N7, N11,

P11, R3,

R7, R11,

R15, U1,

U17

G6, M6,

H7, J7,

VDD1V8

J14, H6,

VDD1V8_1

Pinouts

5.3 i.MX RT500 Pinouts: 141 CSP package

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

PIO0_0

PIO0_1

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

I2S_BRID

GE_CLK_I

CTIMER0_

MAT0

GPIO_INT

_BMAT

PIO0_0

PIO0_1

PIO0_0

PIO0_1

FC0_SCK

FC0_TXD_

SCL_MIS

O_WS

I2S_BRID

GE_WS_I

CTIMER0_

MAT1

FC1_CTS_

PIO0_10 /

TDI

SCT0_GPI SCT0_OU CTIMER1_ FC0_SSEL

PIO0_10

PIO0_11

PIO0_10 SDA_SSE

MAT3

FC1_RTS_

PIO0_11 SCL_SSE

PIO0_11 /

TDO

SCT0_GPI SCT0_OU CTIMER_I FC0_SSEL

NP2

PIO0_12 /

ADC0_1

FC1_SSEL SCT0_GPI SCT0_OU CTIMER_I

T2 NP3

PIO0_12

PIO0_13

PIO0_12

PIO0_13

PIO0_13 /

ADC0_9

FC1_SSEL SCT0_GPI SCT0_OU CTIMER0_

T3 MAT1

I2S_BRID

GE_CLK_I

SCT0_GPI SCT0_OU CTIMER2_

PIO0_14

PIO0_15

PIO0_16

PIO0_17

PIO0_18

PIO0_14

PIO0_15

PIO0_16

PIO0_17

PIO0_14 FC2_SCK

MAT0

FC2_TXD_

PIO0_15 SCL_MIS

O_WS

I2S_BRID

GE_WS_I

SCT0_GPI SCT0_OU CTIMER2_

T1 MAT1

FC2_RXD

PIO0_16 _SDA_MO

SI_DATA

I2S_BRID

GE_DATA

_IN

SCT0_GPI SCT0_OU CTIMER2_

T2 MAT2

FC2_CTS_

PIO0_17 SDA_SSE

SCT0_GPI SCT0_OU CTIMER2_ FC5_SSEL

T3 MAT3

FC2_RTS_

PIO0_18 SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC5_SSEL

T6 NP4

PIO0_18

PIO0_19

PIO0_19 /

ADC0_2

FC2_SSEL SCT0_GPI SCT0_OU CTIMER_I UTICK_CA

T4 NP5 P0

PIO0_19

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC0_RXD

PIO0_2 _SDA_MO

SI_DATA

I2S_BRID

GE_DATA

_IN

CTIMER0_

MAT2

PIO0_2

PIO0_21

PIO0_22

PIO0_2

PIO0_21

PIO0_22

SCT0_GPI SCT0_OU CTIMER3_ CTIMER_I TRACECL

PIO0_21 FC3_SCK

MAT0

NP11

FC3_TXD_

PIO0_22 SCL_MIS

O_WS

SCT0_GPI SCT0_OU CTIMER3_ CTIMER_I TRACEDA

T6 MAT1 NP7 TA[0]

FC3_RXD

PIO0_23 _SDA_MO

SI_DATA

SCT0_GPI SCT0_OU CTIMER3_ CTIMER0_ TRACEDA

T8 MAT2 MAT3 TA[1]

PIO0_23

PIO0_24

PIO0_25

PIO0_28

PIO0_29

PIO0_3

PIO0_23

PIO0_24

PIO0_25

PIO0_28

PIO0_29

PIO0_3

FC3_CTS_

PIO0_24 SDA_SSE

SCT0_GPI SCT0_OU CTIMER3_ FC2_SSEL TRACEDA

T9 MAT3 TA[2]

CLKOUT

CLKIN

FC3_RTS_

PIO0_25 SCL_SSE

FREQME_ CTIMER_I FC2_SSEL TRACEDA

GPIO_CLK

NP6

TA[3]

I2S_BRID

GE_CLK_

OUT

CTIMER4_

MAT0

PIO0_28 FC4_SCK

FC4_TXD_

PIO0_29 SCL_MIS

O_WS

I2S_BRID

GE_WS_O

CTIMER4_

MAT1

FC0_CTS_

CTIMER0_ FC1_SSEL

PIO0_3

SDA_SSE

MAT3

FC4_RXD

PIO0_30 _SDA_MO

SI_DATA

I2S_BRID

GE_DATA

_OUT

CTIMER4_

MAT2

PIO0_30

PIO0_31

PIO0_30

PIO0_31

FC4_CTS_

PIO0_31 SDA_SSE

SCT0_GPI SCT0_OU CTIMER4_ FC3_SSEL

T6 MAT3

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FC0_RTS_

SCL_SSE

CTIMER_I FC1_SSEL

CMP0_OU

PIO0_4

NP0

PIO0_5 /

ADC0_0

FC0_SSEL SCT0_GPI SCT0_OU CTIMER_I

T0 NP1

PIO0_5

PIO0_6

PIO0_5

PIO0_6

PIO0_6 /

ADC0_8

FC0_SSEL SCT0_GPI SCT0_OU CTIMER0_

MAT0

I2S_BRID

GE_CLK_

OUT

PIO0_7 /

TRST

SCT0_GPI SCT0_OU CTIMER1_

PIO0_7

PIO0_8

PIO0_9

PIO1_0

PIO0_7

PIO0_8

FC1_SCK

MAT0

FC1_TXD_

SCL_MIS

O_WS

I2S_BRID

GE_WS_O

PIO0_8 /

TCK

SCT0_GPI SCT0_OU CTIMER1_

T5 MAT1

FC1_RXD

I2S_BRID

GE_DATA

_OUT

PIO0_9 /

TMS

SCT0_GPI SCT0_OU CTIMER1_

PIO0_9 _SDA_MO

SI_DATA

MAT2

FC4_RTS_

SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC3_SSEL

PIO1_0

NP8

HS_SPI0_

SCK

CTIMER2_

MAT0

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_15

PIO1_18

PIO1_19

PIO1_11

PIO1_12

PIO1_13

PIO1_14

PIO1_15

PIO1_18

PIO1_19

HS_SPI0_

MISO

CTIMER2_

MAT1

HS_SPI0_

MOSI

CTIMER2_

MAT2

HS_SPI0_

SSELN0

CTIMER2_

MAT3

PIO1_15 /

ISP0

HS_SPI0_

SSELN1

CTIMER3_

MAT0

FLEXSPI0 SCT0_GPI

_SCLK

CTIMER3_

MAT3

PIO1_18

PIO1_19

FLEXSPI0 SCT0_OU

_SS0_N T0

CTIMER4_

MAT0

CLKOUT

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

FLEXSPI0 SCT0_GPI

CTIMER4_

MAT1

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_28

PIO1_3

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_28

PIO1_3

PIO1_20

PIO1_21

PIO1_22

PIO1_23

PIO1_28

PIO1_3

_DATA0

FLEXSPI0 SCT0_OU

_DATA1 T1

CTIMER4_

MAT2

FLEXSPI0 SCT0_GPI

_DATA2

CTIMER4_

MAT3

FLEXSPI0 SCT0_OU

_DATA3 T2

CTIMER_I

NP8

FLEXSPI0 SCT0_GPI

_DQS

HS_SPI1_

SCK

F11

FC5_SCK

FC5_TXD_

SCL_MIS

O_WS

HS_SPI1_

MISO

F12

E12

PIO1_4

PIO1_5

PIO1_6

PIO1_4

PIO1_5

PIO1_6

PIO1_7

PIO1_4

FC5_RXD

PIO1_5 _SDA_MO

SI_DATA

HS_SPI1_

MOSI

FC5_CTS_

SDA_SSE

SCT0_GPI SCT0_OU

FC4_SSEL HS_SPI1_

SSELN0

PIO1_6

PIO1_7

PIO1_9

FC5_RTS_

SCL_SSE

SCT0_GPI SCT0_OU CTIMER_I FC4_SSEL HS_SPI1_

PIO1_7

NP9

SSELN1

PIO1_9 /

ADC0_12 / PIO1_9

CMP1_B

FC5_SSEL SCT0_GPI UTICK_CA CTIMER1_

HS_SPI1_

SSELN3

MAT3

PIO2_14 /

PIO2_14

CMP0_A

SCT0_OU

CTIMER_I

NP1

32KHZ_CL

KOUT

SmartDMA

_PIO14

PIO2_14

PIO2_15

PIO2_24

PIO2_15 /

PIO2_15

CMP0_D

SCT0_OU

SmartDMA

_PIO15

CLKIN

GPIO_INT

_BMAT

SmartDMA

_PIO24

PIO2_24

SWO

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

SmartDMA

_PIO25

F10

E11

PIO2_25

PIO2_26

PIO2_25

PIO2_26

PIO2_25

PIO2_26

SWCLK

SmartDMA

_PIO26

SWDIO

USB1_OV

PIO2_27 ERCURRE

NTN

SmartDMA

_PIO27

E10

PIO2_27

SCT0_OU

SmartDMA

_PIO29

PIO2_29

PIO2_30

PIO2_29

PIO2_30

PIO2_31

PIO2_29 I3C0_SCL

PIO2_30 I3C0_SDA

PIO2_31 I3C0_PUR

CLKOUT

CLKIN

SWO

SCT0_OU

CMP0_OU

SmartDMA

_PIO30

PIO2_31 /

CMP0_B

SCT0_OU UTICK_CA CTIMER_I

SmartDMA

_PIO31

NP15

FC6_CTS_

PIO3_28 SDA_SSE

PIO3_28 /

ISP1

PIO3_28

FC6_RTS_

PIO3_29 SCL_SSE

PIO3_29 /

ISP2

PIO3_29

PIO4_20

PIO4_21

FC11_SC

FLEXIO_D

PIO4_20

PIO4_21

PIO4_20 DBI_CSX

SD1_D[6]

SD1_D[7]

FC11_TXD

_SCL_MIS

FLEXIO_D

PIO4_21 DBI_DCX

FC11_RX

D_SDA_M

OSI

SD1_CAR

D_DET_N

FLEXIO_D

PIO4_22

PIO4_23

PIO4_24

PIO4_22

PIO4_23

PIO4_24

PIO4_22

FC11_CTS

_SDA_SS

ELN0

DBI_RWD LCD_ENA

SD1_RES

ET_N

TRACECL FLEXIO_D

PIO4_23

BLE

FC11_RTS

_SCL_SS

ELN1

LCD_DTC

SD1_VOL

TRACEDA FLEXIO_D

TA[0]

PIO4_24 DBI_WRX

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

LCD_HSY

FC11_SSE TRACEDA FLEXIO_D

LN2 TA[1]

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

PIO4_25

PIO4_26

PIO4_27

PIO4_28

PIO4_29

DBI_E

LCD_VSY

FC11_SSE TRACEDA FLEXIO_D

LN3

TA[2]

TRACEDA FLEXIO_D

LCD_D0

LCD_D1

LCD_D2

DBI_D0

DBI_D1

DBI_D2

TA[3]

FLEXIO_D

B10

FLEXIO_D

FC12_TXD

_SCL_MIS

FLEXIO_D

PIO4_30

LCD_D3

DBI_D3

FC12_RX

D_SDA_M

OSI

FLEXIO_D

PIO4_31

PIO5_4

PIO4_31

PIO5_4

PIO4_31

PIO5_4

LCD_D4

LCD_D9

DBI_D4

DBI_D9

PDM_CLK

PDM_DAT

A01

C11

PIO5_8

LCD_D13 DBI_D13

MCLK

PIO6_27

MIPI_DSI_ MIPI_DSI_

CLKN CLKN

J12

MIPI_DSI_ MIPI_DSI_

CLKP CLKP

H11

MIPI_DSI_ MIPI_DSI_

D0N D0N

MIPI_DSI_ MIPI_DSI_

D0P

MIPI_DSI_

VDD11

H12

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

MIPI_DSI_

VDD18

G10

MIPI_DSI_

K12

VDDA_CA

MIPI_DSI_

VSS

J11

PMIC_IRQ PMIC_IRQ

PMIC_MO PMIC_MO

DE0 DE0

PMIC_MO PMIC_MO

DE1 DE1

RESETN RESETN

RTCXIN RTCXIN

K10

L11

J10

K11

B11

B12

RTCXOUT RTCXOUT

USB1_DM USB1_DM

USB1_DP USB1_DP

USB1_VD USB1_VD

D10

D3V3

VREFN/

VSSA

VREFN

VREFP/

VDDA_AD

C1V8/

VDDA_BIA

VREFP

XTALIN

XTALOUT XTALOUT

A3, B1,

B6, E1, F2, VDDIO_0

Table continues on the next page...

Part Num

(141WLC Pin Name DEFAULT

SP)

Func 0

Func 1

Func 2

Func 3

Func 4

Func 5

Func 6

Func 7

Func 8

Func 15

D11, G6,

VDDIO_1

H5, L6, M5

VDDIO_2

VDDIO_3

VDDIO_4

A10, B2,

C1, C3,

C10, C12,

E6, F6,

G7, G12,

VDDCORE

VDD1V8

A11, L12,

M11, F5,

VDD_AO1

L10

M10

VDD1V8_1

VSSA

A1, A2,

A12, B3,

F7, F8,

G8, G11,

H1, H7,

G9, H10,

M1, M9,

M12

VSS

Pinouts

5.4 249-pin FOWLP and 141-pin WLCSP ballmaps

The following figure shows the 249 FOWLP ballmap for this device.

PIO3_12

PIO3_18

PIO3_19

PIO3_20

VDD1V8

VDDIO_4

VDD1V8

VDDIO_1

PMIC_I2C_SDA

VSS

PIO3_8

VSS

RTCXIN

XTALOUT

XTALIN

PIO1_0

PIO0_28

PIO0_14

PIO0_25

PIO0_31

VDDA_BIAS

VREFP

PIO0_21

PIO0_22

PIO2_31

PIO0_30

PIO0_12

PIO0_0

VSS

PIO0_16

PIO0_18

PIO3_2

PIO3_1

VSS

MIPI_DSI_D0P

VDD_AO1V8

MIPI_DSI_D0N

MIPI_DSI_CLKP

RTCXOUT

VSS

PIO3_13

VSS

PIO3_9

PIO2_29

PIO3_11

PIO2_30

PIO3_15

VDDIO_1

VSS

PIO0_29

VSS

PIO0_15

VSS

PIO0_17

RESETN

VDD_AO1V8

PMIC_MODE1

MIPI_DSI_VSS

VSS

LDO_ENABLE

PMIC_IRQ_N

PIO3_21

PIO3_10

PIO3_16

PIO3_14

PIO0_23

PIO0_24

PIO4_18

PIO0_19

VSS

MIPI_DSI_CLKN

PMIC_MODE0

MIPI_DSI_D1P

MIPI_DSI_D1N

VSS

VSSA

VSS

PIO3_17

VSSA

VSS

PIO3_3

PIO2_14

PIO0_13

VSS

PIO2_15

PIO0_6

PIO0_9

PIO1_13

PIO4_2

PIO4_4

VDD1V8_1

MIPI_DSI_VDDA18

VSS

VDDIO_1

VDDCORE

PIO5_1

MIPI_DSI_VDDA_CA

PIO4_14

PIO4_17

PIO4_13

PIO4_11

VDDIO_4

VSS

VDDIO_1

VSS

PIO0_5

PIO0_1

PIO0_2

VSS

PIO5_15

VDDIO_1

USB1_VDD3V3

VSS

VREFN

PIO4_12

PIO4_16

PIO5_17

PIO4_15

VSS

PIO5_16

PIO5_18

PMIC_I2C_SCL

VSS

VDD1V8

VSS

VDDCORE

MIPI_DSI_VDD11

VDDCORE

VSS

VDDCORE

VSS

PIO0_8

VDDA_ADC1V8

VDDIO_0

PIO1_11

VSS

PIO0_4

VDD1V8

PIO1_12

VSS

PIO0_3

PIO0_7

PIO0_11

VSS

VDDCORE

VSS

VDDIO_0

VSS

PIO1_4

PIO1_3

PIO1_5

PIO2_25

PIO0_10

PIO1_14

PIO1_15

VSS

PIO1_7

PIO2_27

PIO2_24

PIO5_8

PIO2_26

PIO1_6

PIO1_10

PIO2_10

PIO2_5

VDD1V8

VDDIO_2

PIO2_4

VSS

VDDIO_3

PIO4_30

VDDIO_0

PIO4_31

PIO4_21

PIO5_3

VSS

VDDIO_0

PIO1_24

PIO5_0

PIO3_29

PIO3_28

PIO1_27

PIO1_22

PIO4_3

PIO3_27

PIO1_26

PIO1_25

PIO1_21

PIO1_28

PIO4_1

PIO4_0

PIO4_6

VSS

VDDIO_3

PIO4_27

VSS

PIO2_28

PIO5_4

PIO2_11

PIO2_7

VDDIO_2

VSS

PIO4_29

VSS

PIO4_5

PIO3_25

PIO3_26

PIO1_19

VSS

PIO2_6

PIO1_30

PIO1_31

PIO2_8

PIO4_20

PIO5_2

VSS

PIO1_23

PIO4_26

PIO1_29

USB1_DM

VSS

USB1_VBUS

USB1_DP

PIO2_9

PIO2_1

PIO2_2

PIO4_23

PIO4_24

PIO4_22

PIO4_25

PIO1_20

PIO1_18

VSS

PIO2_0

PIO2_3

PIO4_28

Figure 43. i.MX RT500 249-pin FOWLP ballmap

The following figure shows the 141-pin WLCSP ballmap for this device.

PIO0_16

PIO0_30

VSSA

VDDCORE

VDD1V8

XTALOUT

VSSA

VSS

PIO0_17

PIO1_9

PIO2_14

PIO0_13

PIO0_2

PIO0_3

VDDIO_0

PIO1_12

PIO1_13

PIO1_14

VDDCORE

VSS

PIO0_21

PIO0_24

PIO0_15

PIO0_18

PIO0_19

VDDIO_0

PIO0_4

VDDIO_1

PIO0_23

PIO2_31

PIO0_22

VDDIO_1

PIO0_12

VDD1V8

VDDIO_3

PIO1_22

PIO1_21

PIO1_20

PIO1_18

PIO0_28

VDDIO_1

PIO0_14

PIO0_31

PIO0_25

VDDIO_1

VDDCORE

PIO4_26

PIO1_23

VDDIO_0

PIO1_28

PIO2_29

PIO1_0

PIO2_30

PIO0_29

VSS

VDD1V8_1

VDD_AO1V8

PMIC_MODE0

RTCXIN

VDD1V8

RESETN

VSS

PIO2_15

PIO0_6

PIO0_0

VSS

XTALOUT

PMIC_IRQ

PMIC_MODE1

MIPI_DSI_D0N

VSS

VDD1V8

MIPI_DSI_VDDA_CA

RTCXOUT

MIPI_DSI_VSS

MIPI_DSI_CLKP

VSS

VDDA_ADC1V8

PIO0_5

MIPI_DSI_CLKN

MIPI_DSI_VDD11

VDDCORE

MIPI_DSI_D0P

VSS

PIO0_8

PIO0_10

VDDIO_0

PIO1_15

VDDCORE

VDDIO_0

VSS

PIO0_1

VDDCORE

VSS

MIPI_DSI_VDD18

PIO2_25

PIO0_9

VSS

PIO1_7

PIO1_3

PIO1_4

PIO0_11

PIO1_11

VDDCORE

VSS

PIO0_7

PIO4_23

PIO4_25

PIO4_24

PIO4_21

PIO2_24

PIO4_29

PIO4_27

PIO4_20

PIO4_22

PIO1_6

PIO2_27

PIO2_26

PIO1_5

PIO1_19

PIO6_27

PIO3_29

PIO3_28

PIO5_4

USB1_VDD3V3

VDDCORE

PIO4_28

VDDIO_1

PIO5_8

PIO4_30

PIO4_31

VDDCORE

USB0_DP

VSS

USB0_DM

VDD1V8

VDDIO_0

VDDCORE

Figure 44. i.MX RT500 141-pin CSP ballmap

106

NXP Semiconductors

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

Pinouts

5.5 Termination of unused pins

The following table shows how to terminate pins that are not used in the application.

In many cases, unused pins should be connected externally or configured correctly by

software to minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with

their internal pull-up disabled. To configure a GPIO pin as output and drive it LOW,

select the GPIO function in the IOCON register, select output in the GPIO DIR

the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 50. Termination of unused pins

Default state¹

Recommended termination of

unused pins

All PIOn pins

Most are Z, a few are PU

Can be left unconnected if configured

by software as an output with pull-up

disabled and driven LOW.

PMIC_I2C_SCL/SDA

PMIC_IRQ_N

Leave unconnected

Tie to VDD_AO1V8 if not used in the

system.

PMIC_MODEn

RESETN

Leave unconnected.

Tie high if not used in the system.

Tie to ground.

RTCXIN

RTCXOUT

USB1_DM/DP

Leave unconnected.

Can be left unconnected. If the USB

interface is not used, these pins can be

left unconnected except in deep power-

down mode where they must be

externally pulled low. When the USB

PHY is disabled, the pins are floating.

USB1_VBUS

VDD1V8

Leave unconnected.

VDD_1V8_1

Tie to 1.8V power during active. Can

be powered off during deep sleep

mode to reduce current consumption

by approximately 22 uA.

USB1_VDD3V3

VDD_AO1V8

Leave unconnected.

Tie to 1.8V power.

VDDA_ADC1V8

Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

107

NXP Semiconductors

Power supply for pins

Table 50. Termination of unused pins (continued)

Default state¹

Recommended termination of

unused pins

VDDA_BIAS

VREFN

Tie to 1.8V power.

Tie to VSS.

VREFP

Tie to VDDA_ADC1V8 analog supply

10 kΩ resistor to ground

Leave unconnected

Tie to VSS

MIPI_DSI_VDD11

MIPI_DSI_VDD18

MIPI_DSI_VDDA_CAP

MIPI_DSI_VSS

VSSA

Tie to VSS.

XTALIN

Tie to ground.

XTALOUT

Leave unconnected.

1. Z = Input, pull-up, and pull-down disabled; PU = Pull-Up enabled; F = Floating, High-Z

5.6 Pin states in different power modes

Table 51. Pin states in different power modes

Active

Sleep

Deep-sleep

Deep power-down

Floating

All PIOn pins

As configured in IOCON¹. Default is Z (input, pull-up, and pull-down

disabled), except for a few pins where the pull-up and input are enabled.

1. Default and programmed pin states are retained in sleep and deep-sleep.

5.7 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

249-pin FOWLP

Then use this document number

98ASA01357D

141-pin WLCSP

98ASA01653D

6 Power supply for pins

108

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

Power supply for pins

The following table shows the GPIOs belonging to the specific VDDIO groups and

VDD_AO1V8 domain.

VDDIO_0, 1, 2, and 4 supply pins can ONLY be powered from 1.71V to 1.98V. The

VDDIO_3 supply pin can be powered between 1.71V to 3.6V.

Table 52. Power supply for pins

GPIO pins

PIO0_0 to PIO0_13 (Fail Safe Pads)

PIO1_11 to PIO1_15 (Fail Safe Pads)

PIO1_18 to PIO1_29 (High Speed Pads)

PIO2_14 to PIO2_15 (Fail Safe Pads)

PIO3_25 to PIO3_29 (Fail Safe Pads)

PIO4_0 to PIO4_6 (Fail Safe Pads)

VDDIO_0

VDDIO_1

PIO0_14 to PIO0_19 (Fail Safe Pads)

PIO0_21 to PIO0_25 (Fail Safe Pads)

PIO0_28 to PIO0_31 (Fail Safe Pads)

PIO1_0 (Fail Safe Pads)

PIO1_2 to PIO1_7 (Fail Safe Pads)

PIO1_10 (Fail Safe Pad)

PIO2_24 to PIO2_31 (High Speed Pads)

PIO3_1 to PIO3_3 (Fail Safe Pads)

PIO4_11 to PIO4_17 (High Speed Pads)

PIO4_18 (Fail Safe Pad)

PIO5_15 to PIO5_18 (High Speed)

PMIC_I2C_SCL

PMIC_I2C_SDA

VDDIO_2

PIO1_30 to PIO1_31 (High Speed Pads)

PIO2_0 to PIO2_8 (High Speed Pads)

PIO2_9 to PIO2_11 (Fail Safe Pads)

PIO4_20 to PIO4_31 (Fail Safe Pads)

PIO5_0 to PIO5_4, PIO5_8 (Fail Safe Pads)

PIO3_8 to PIO3_18 (High Speed Pads)

PIO3_19 to PIO3_21 (Fail Safe Pads)

RESETN

VDDIO_3

VDDIO_4

VDD_AO1V8

LDO_ENABLE

PMIC_IRQ_N

PMIC_MODE0 and PMIC_MODE1

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

109

NXP Semiconductors

Revision history

7 Revision history

Table 53. Revision history

Rev. No.

Date

Substantial changes

02/2021

Initial public release

110

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021

NXP Semiconductors

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automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting

from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard

warranty and NXP Semiconductors’ product specifications.

Applications — Applications that are described herein for any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use

without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors

products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product

Table continues on the next page...

design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit

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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of

IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation

of the device at these or any other conditions above those given in the Recommended operating conditions section (if

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Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V

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950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.

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NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7,

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NXP B.V. 2021.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 02/2021

Document identifier: IMXRT500EC

NXP Semiconductors

Data Sheet Addendum

Document Number: IMXRT500ECAD

Rev. 0, 04/2021

Addendum to Rev. 0 of the i.MX

RT500 Low-Power Crossover

Processor Data Sheet

This addendum identifies changes to Rev. 0 of the i.MX RT500 Low-Power Crossover Processor Data

Sheet. The changes described in this addendum have not been implemented in the specified pages.

1 Update the table “General operating conditions”

Location: Section 1.1.6, Table 5, Page 14

Add the following row to Table 5, “General operating conditions”

Symbol

Parameter Conditions

Min.

Typ.

Max.

Unit

f_{otp_clk}

OTP clock For OTP

frequency programmin

g only

120

MHz

(fclk/OTP_CLK_DIV[DIV])

Update the section “Termination of unused pins”

2 Update the section “Termination of unused pins”

Location: Section 5,5, Page 107

Replace the paragraph text within the section “Termination of unused pins” with the text below.

The following table shows how to terminate pins on functions that are not used in the application. In many

cases, unused pins should be connected externally or configured correctly by software to minimize the

overall power consumption of the part.

By default, unused pins with GPIO functions are tri-stated with the input buffer disabled and can remain

floating.

All power pins in the domains listed below must be connected to the recommended voltage.

3 Update the table “Termination of unused pins”

Location: Section 5.5, Table 50, Page 107

Replace Table 50 “Termination of unused pins” with the following table.

Function

Pin Name

Default Recommended termination of unused pins

state¹

GPIO

All PIOn pins

Leave unconnected.

PMIC Control

Control

PMIC_I2C_SCL/SDA

PMIC_IRQ_N

PMIC_MODEn

LDO_ENABLE

RESETN

Leave unconnected.

I, Z

10 kΩ resistor to VDD_AO1V8.

Leave unconnected.

10 kΩ resistor to ground.

100 kΩ resistor to VDD_AO1V8.

Control

Addendum to i.MX RT500 Low-Power Crossover Processor Data Sheet, Rev. 0

NXP Semiconductors

Update the table “Termination of unused pins”

Oscillator

USB1

RTCXIN

Connect to ground.

RTCXOUT

Leave unconnected.

Connect to ground.

XTALIN

XTALOUT

Leave unconnected.

10 kΩ resistor to ground.

Leave unconnected.

Connect to ground.

USB1_DM/DP

USB1_VBUS

USB1_VDD3V3

MIPI_DSI_VDD11

MIPI_DSI_VDD18

MIPI_DSI_VDDA_CAP

MIPI_DSI_VSS

MIPI_DSI_D0N/D0P

MIPI_DSI_D1N/D1P

MIPI_DSI_CLKP

MIPI_DSI_CLKN

VREFP

USB1

MIPI_DSI

Analog

Leave unconnected.

Connect to VDDA_ADC1V8.

Connect to ground.

Analog

VREFN

Power

VDDCORE

Connect to 1.0V power.

Connect to 1.8V power.

Power

VDD1V8

Power

VDD_1V8_1

Connect to 1.8V power during active. Can be powered off

during deep sleep mode to reduce current consumption by

approximately 22 uA.

Power

VDD_AO1V8

VDDIO_n

VDDA_ADC1V8

VDDA_BIAS

VSSA

Connect to 1.8V power.

Connect to ground.

VSS

Connect to ground.

Z = high impedance; I = Input; O = Output

Addendum to i.MX RT500 Low-Power Crossover Processor Data Sheet, Rev. 0

NXP Semiconductors

Update the table “Power supply for pins”

4 Update the table “Power supply for pins”

Location: Section 6, Table 52, Page 109

Add the following rows to Table 52 “Power supply for pins”.

GPIO pins

VDDIO_0

PIO6_27 (Fail Safe Pad)

VDDIO_1 PIO5_4 and PIO5_8 (Fail Safe Pads)

Replace the following rows in Table 52 “Power supply for pins”, with the ones shown in the table.

VDDIO_1: PIO1_2 to PIO1_7 (Fail Safe Pads)

VDDIO_1: PIO1_10 (Fail Safe Pads)

VDDIO_3: PIO5_0 to PIO5_4, PIO5_8 (Fail Safe Pads)

GPIO pins

VDDIO_1 PIO1_3 to PIO1_7 (Fail Safe Pads)

PIO1_9 to PIO1_10 (Fail Safe Pads)

VDDIO_3

PIO5_0 to PIO5_3 (Fail Safe Pads)