PMV117EN [NXP]
uTrenchMOS enhanced logic level FET; uTrenchMOS增强逻辑电平FET
| 型号： | PMV117EN |
| 厂家： | 
NXP |
| 描述： | uTrenchMOS enhanced logic level FET |
| 文件： | 总12页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PMV117EN
µTrenchMOS™ enhanced logic level FET
Rev. 02 — 7 April 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Very fast switching
■ Subminiature surface-mounted
package
1.3 Applications
■ Battery management
■ High-speed switch
■ Low power DC-to-DC converter
1.4 Quick reference data
■ VDS ≤ 30 V
■ ID ≤ 2.5 A
■ RDSon ≤ 117 mΩ (VGS = 10 V)
■ Ptot ≤ 0.83 W
2. Pinning information
Table 1:
Pinning
Pin
1
Description
gate (G)
Simplified outline
Symbol
D
S
3
2
source (S)
drain (D)
3
G
1
2
mbb076
SOT23
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PMV117EN
TO-236AB plastic surface mounted package; 3 leads
SOT23
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
-
±20
2.5
V
Tsp = 25 °C; VGS = 10 V; Figure 2 and 3
Tsp = 100 °C; VGS = 10 V; Figure 2
Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tsp = 25 °C; Figure 1
-
A
-
1.6
A
IDM
Ptot
Tstg
Tj
peak drain current
-
10
A
total power dissipation
storage temperature
junction temperature
-
0.83
+150
+150
W
°C
°C
−65
−65
Source-drain diode
IS
source (diode forward) current (DC) Tsp = 25 °C
-
-
0.8
3.3
A
A
ISM
peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
2 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
03aa17
03aa25
120
120
Ider
(%)
Pder
(%)
80
40
0
80
40
0
0
50
100
150
200
0
50
100
150
200
Tsp ( C)
Tsp ( C)
°
°
V
GS ≥ 10 V
Ptot
Pder
=
× 100 %
------------------------
ID
P
°
tot(25 C)
Ider
=
× 100 %
--------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature
Fig 2. Normalized continuous drain current as a
function of solder point temperature
03ak56
2
10
I
D
(A)
Limit R
= V / I
DS D
DSon
10
t
= 10 µs
p
100 µs
1 ms
1
10 ms
DC
100 ms
−1
10
−2
10
−1
2
10
1
10
10
V
(V)
DS
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
3 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
100 K/W
Rth(j-sp) thermal resistance from junction to solder point
Figure 4
-
-
03ak55
3
10
Z
th(j-sp)
(K/W)
2
10
δ = 0.5
0.2
0.1
t
p
P
δ =
0.05
0.02
10
T
single pulse
t
t
p
T
1
10
−4
−3
−2
−1
10
10
10
1
10
t
(s)
p
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
4 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 10 µA; VGS = 0 V
Tj = 25 °C
30
27
37
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1.5
1.1
-
2
-
-
V
V
V
Tj = 150 °C
-
Tj = −55 °C
-
2.7
IDSS
VDS = 24 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.01 0.5
µA
µA
nA
Tj = 150 °C
-
10
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 10 V; ID = 500 mA; Figure 6 and 8
Tj = 25 °C
10
100
RDSon
drain-source on-state resistance
-
-
-
74
117
mΩ
VGS = 4.5 V; ID = 500 mA; Figure 6 and 8
Tj = 25 °C
117
188
190
300
mΩ
mΩ
Tj = 150 °C
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 0.5 A; VDD = 15 V; VGS = 10 V;
Figure 11
-
-
-
-
-
-
-
-
-
-
4.6
0.6
1.35
147
65
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
VGS = 0 V; VDS = 10 V; f = 1 MHz;
Figure 13
41
VDD = 15 V; RL = 15 Ω; VGS = 10 V
4
7.5
18
td(off)
tf
turn-off delay time
fall time
13
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 0.83 A; VGS = 0 V; Figure 12
-
-
0.7
69
1.2
-
V
reverse recovery time IS = 1 A; dIS/dt = −100 A/µs; VGS = 0 V;
ns
VDS = 25 V
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
5 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
03ak57
3.4
03ak58
3
400
10
6 4.5 3.8 3.6
V
(V) = 3
3.2
T = 25 ˚C
j
GS
R
DSon
3.4
I
D
(mΩ)
(A)
3.2
300
2
3
3.6
3.8
200
100
0
2.8
4.5
6
1
0
2.6
10
V
(V) = 2.4
GS
0
0.2
0.4
0.6
0.8
1
0
1
2
3
I
(A)
V
DS
(V)
D
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
03ak59
03ad57
2
3
V
> I × R
D DSon
DS
a
I
D
(A)
1.5
2
1
0.5
0
1
0
T = 150 ˚C
j
25 ˚C
−60
0
60
120
180
0
1
2
3
4
T (°C)
j
V
(V)
GS
Tj = 25 °C and 150 °C; VDS > ID × RDSon
RDSon
a =
------------------------------
RDSon(25
°
C)
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
6 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
03ak63
03ak64
−1
2.5
10
I
V
D
GS(th)
(A)
(V)
typ
−2
2
10
10
10
10
10
min
min
typ
−3
1.5
−4
−5
−6
1
0.5
0
−60
0
60
120
180
0
0.8
1.6
2.4
3.2
T (°C)
j
V
GS
(V)
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
03ak62
10
V
GS
I = 0.5 A
D
(V)
T = 25 °C
j
8
V
= 15 V
DD
6
4
2
0
0
2
4
6
Q
(nC)
G
ID = 0.5 A; VDD = 15 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
7 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
03ak61
03ak60
3
3
10
V
= 0 V
GS
I
S
(A)
C
(pF)
2
C
iss
2
10
C
C
oss
1
0
rss
T = 150 ˚C
25 ˚C
j
10
10
−1
2
0
0.3
0.6
0.9
1.2
1
10
10
V
(V)
V
(V)
SD
DS
Tj = 25 °C and 150 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
8 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
7. Package outline
Plastic surface mounted package; 3 leads
SOT23
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
e
1
b
p
w M
B
L
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
b
c
D
E
e
e
H
L
Q
v
w
A
p
p
1
E
max.
1.1
0.9
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
mm
0.1
1.9
0.95
0.2
0.1
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
JEITA
99-09-13
04-11-04
SOT23
TO-236AB
Fig 14. Package outline SOT23
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
9 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
8. Revision history
Table 6:
Revision history
Document ID
PMV117EN_2
Modifications:
Release date
Data sheet status Change notice Doc. number
Supersedes
20050407
Product data sheet
-
9397 750 14709 PMV117EN-01
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Table 5 “Characteristics”; correction to VGS(th) data
• Table 2 “Ordering information”: added
PMV117EN-01
20030226
Product data
-
9397 750 11095
-
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
10 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
9. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
11 of 12
PMV117EN
Philips Semiconductors
µTrenchMOS™ enhanced logic level FET
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information . . . . . . . . . . . . . . . . . . . . 11
3
4
5
6
7
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 7 April 2005
Document number: 9397 750 14709
Published in The Netherlands
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