PMWD15UN_技术文档

PMWD15UN

Dual N-channel µTrenchMOS™ ultra low level FET

Rev. 04 — 5 April 2005

Product data sheet

1. Product proﬁle

1.1 General description

Dual common drain N-channel enhancement mode Field-Effect Transistor (FET) in a

plastic package using TrenchMOS™ technology.

1.2 Features

■ Surface mounting package

■ Very low threshold voltage

■ Low proﬁle

■ Fast switching

1.3 Applications

■ Portable appliances

■ Battery management

■ PCMCIA cards

■ Load switching

1.4 Quick reference data

■ V_DS≤ 20 V

■ P_tot≤ 4.2 W

■ I_D≤ 11.6 A

■ R_DSon≤ 18.5 mΩ

2. Pinning information

Table 1:

1, 8

2, 3

4

Pinning

Description

drain (D)

Simpliﬁed outline

Symbol

8

5

D

source1 (S1)

gate1 (G1)

gate2 (G2)

source2 (S2)

5

6, 7

G1

S1

G2

S2

mbl600

1

4

SOT530-1 (TSSOP8)

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

3. Ordering information

Table 2:

Ordering information

Type number

Package

Name

Description

plastic thin shrink small outline package; 8 leads; body width 4.4 mm

Version

PMWD15UN

TSSOP8

SOT530-1

4. Limiting values

Table 3:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DS

V_DGR

V_GS

I_D

drain-source voltage (DC)

25 °C ≤ T_j≤ 150 °C

-

20

drain-gate voltage (DC)

gate-source voltage

drain current (DC)

25 °C ≤ T_j≤ 150 °C; R_GS= 20 kΩ

-

20

V

-

±12

11.6

7.3

V

[1]

T_sp= 25 °C; V_GS= 4.5 V; Figure 2 and 3

T_sp= 100 °C; V_GS= 4.5 V; Figure 2

T_sp= 25 °C; pulsed; t_p≤ 10 µs; Figure 3

T_sp= 25 °C; Figure 1

-

A

-

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

46.4

4.2

A

total power dissipation

storage temperature

junction temperature

-

W

°C

−55

+150

Source-drain diode

[1]

I_S

source (diode forward) current (DC) T_sp= 25 °C

-

3.5

14

A

I_SM

peak source (diode forward) current T_sp= 25 °C; pulsed; t_p≤ 10 µs

[1] Single device conducting.

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

2 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

03aa17

03aa25

120

I_der

P_der

(%)

80

40

0

80

40

0

50

100

150

200

0

50

100

150

200

T_sp( C)

°

V

_GS≥ 4.5 V

P_tot

P_der

=

× 100 %

------------------------

I_D

P

°

tot(25 C)

I_der

=

× 100 %

--------------------

I

°

D(25 C)

Fig 1. Normalized total power dissipation as a

function of solder point temperature

Fig 2. Normalized continuous drain current as a

function of solder point temperature

003aaa250

10²

I_D

Limit R_DSon= V_DS/ I_D

t_p= 100 µs

(A)

1 ms

10

10 ms

100 ms

1 s

DC

1

10^-1

10^-2

10^-1

1

10

10²

V_DS(V)

T_sp= 25 °C; I_DMis single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

3 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

5. Thermal characteristics

Table 4:

Thermal characteristics

Symbol Parameter

Conditions

Min

Typ

-

Max Unit

R_th(j-sp)thermal resistance from junction to solder point

Figure 4

-

30

-

K/W

R_th(j-a)

thermal resistance from junction to ambient

mounted on a printed-circuit

board; minimum footprint;

vertical in still air

100

003aaa251

10²

Z_th(j-sp)

(K/W)

δ = 0.5

10

0.2

0.1

0.05

t_p

δ =

0.02

P

1

T

single pulse

t

t_p

T

10^-1

10^-4

10^-3

10^-2

10^-1

1

10

10²

t_p(s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

4 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

6. Characteristics

Table 5:

Characteristics

T_j= 25 °C unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max Unit

Static characteristics

V_(BR)DSSdrain-source breakdown voltage

I_D= 250 µA; V_GS= 0 V

T_j= 25 °C

20

18

-

V

T_j= −55 °C

V_GS(th)

I_DSS

gate-source threshold voltage

drain-source leakage current

I_D= 1 mA; V_DS= V_GS; Figure 9 and 10

V_DS= 20 V; V_GS= 0 V

T_j= 25 °C

0.45 0.7

-

1

µA

nA

T_j= 150 °C

100

I_GSS

gate-source leakage current

V_GS= ±10 V; V_DS= 0 V

V_GS= 4.5 V; I_D= 5 A; Figure 7and 8

T_j= 25 °C

R_DSon

drain-source on-state resistance

-

15.3 18.5 mΩ

T_j= 150 °C

26

20

17

31

mΩ

V_GS= 1.8 V; I_D= 4.5 A; Figure 7 and 8

V_GS= 2.5 V; I_D= 5 A; Figure 7 and 8

28.5 mΩ

20.5 mΩ

Dynamic characteristics

Q_g(tot)

Q_gs

Q_gd

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

gate-source charge

gate-drain (Miller) charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

I_D= 4 A; V_DS= 16 V; V_GS= 4.5 V;

Figure 13

-

22.2

2.1

-

nC

pF

ns

6.2

V_GS= 0 V; V_DS= 16 V; f = 1 MHz;

Figure 11

1450

280

190

14.7

22.4

57

V_DS= 10 V; R_L= 10 Ω; V_GS= 4.5 V;

R_G= 6 Ω

t_d(off)

t_f

turn-off delay time

fall time

33

Source-drain diode

V_SD

t_rr

source-drain (diode forward) voltage I_S= 5 A; V_GS= 0 V; Figure 12

-

0.67 1.2

V

reverse recovery time

recovered charge

I_S= 5 A; dI_S/dt = −100 A/µs; V_GS= 0 V;

V_R= 20 V

45

-

ns

nC

Q_r

12.3

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

5 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

003aaa252

003aaa253

12

1.8 1.5

4.5

I_D

V_DS> I_Dx R_DSon

(A)

V_GS(V) = 1.35

8

4

0

8

4

0

T_j= 150 °C

1.3

25 °C

1.2

1.1

0

0.2

0.4

0.6

0.8

1

0

0.5

1

1.5

2

V

_GS(V)

V

_DS(V)

T_j= 25 °C

T_j= 25 °C and 150 °C; V_DS> I_D× R_DSon

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

03aa27

003aaa254

2

100

1.2

1.3

1.1

R_DSon

a

(mΩ)

1.5

75

1

0.5

0

50

25

0

V_GS(V) = 1.8

4.5

2.5

8

-60

0

60

120

180

0

4

12

I_D(A)

T ( C)

°

j

T_j= 25 °C

R_DSon

a =

------------------------------

R_DSon(25

°

C)

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

6 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

03aj64

03aj65

−3

10

1.2

V_GS(th)

(V)

I

D

(A)

max

typ

0.9

0.6

0.3

0

−4

−5

−6

10

min

typ

max

min

10

0

0.2

0.4

0.6

0.8

1

(V)

-60

0

60

120

180

T_j(°C)

V

GS

I_D= 1 mA; V_DS= V_GS

T_j= 25 °C; V_DS= 5 V

Fig 9. Gate-source threshold voltage as a function of

junction temperature

Fig 10. Sub-threshold drain current as a function of

gate-source voltage

003aaa256

003aaa255

10⁴

12

I_S

C

(pF)

(A)

C_iss

10³

8

150 °C

C_oss

T_j= 25 °C

C_rss

10²

4

10

0

10^-1

1

10

10²

0

0.2

0.4

0.6

0.8

1

V_DS(V)

V

_SD(V)

V_GS= 0 V; f = 1 MHz

T_j= 25 °C and 150 °C; V_GS= 0 V

Fig 11. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

values

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

7 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

003aaa257

5

4

3

2

1

0

V_GS

(V)

0

5

10

15

20

25

Q

_G(nC)

I_D= 4 A; V_DD= 16 V

Fig 13. Gate-source voltage as a function of gate charge; typical values

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

8 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

7. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm

SOT530-1

E

A

D

X

c

y

H

E

v

M

A

Z

8

5

A

2

(A )

A

3

A

1

pin 1 index

θ

L

p

L

detail X

1

4

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

UNIT

v

w

y

Z

θ

1

2

3

p

E

p

max.

0.15

0.05

0.95

0.85

0.30

0.19

0.20

0.13

3.1

2.9

4.5

4.3

6.5

6.3

0.7

0.5

0.70

0.35

8°

0°

mm

1.1

0.65

0.25

0.94

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-24

03-02-18

SOT530-1

MO-153

Fig 14. Package outline SOT530-1 (TSSOP8)

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

9 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

8. Revision history

Table 6:

Revision history

Document ID

PMWD15UN_4

Modiﬁcations:

Release date

Data sheet status

Change notice Doc. number

Supersedes

20050405

Product data sheet

-

9397 750 14713 PMWD15UN-03

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors.

• I_Dand P_totdata revised in Section 1.4 “Quick reference data”.

• I_D, I_DM, P_tot, I_Sand I_SMdata revised in Table 3 “Limiting values”.

• Figure 3 revised in Section 4 “Limiting values”.

• R_th(j-sp)data revised in Table 4 “Thermal characteristics”.

• Figure 4 revised in Section 5 “Thermal characteristics”.

PMWD15UN-03

PMWD15UN-02

PMWD15UN-01

20040220

20030807

20030204

Product data

-

9397 750 12677 PMWD15UN-02

9397 750 11777 PMWD15UN-01

9397 750 10829

-

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

10 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

9. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

12. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

13. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14713

Product data sheet

Rev. 04 — 5 April 2005

11 of 12

PMWD15UN

Philips Semiconductors

Dual N-channel µTrenchMOS™ ultra low level FET

14. Contents

1

Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Contact information . . . . . . . . . . . . . . . . . . . . 11

3

4

5

6

7

8

9

10

11

12

13

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 5 April 2005

Document number: 9397 750 14713

Published in The Netherlands


型号：	PMWD15UN
厂家：	NXP
描述：	Dual N-channel mTrenchMOS?? ultra low level FET 双N沟道mTrenchMOS ？超低水平FET
文件：	总12页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PMWD15UN [NXP]

相关型号：

PMWD16UN

PMWD18UN

PMWD19UN

PMWD20XN

PMWD20XN,118

PMWD22XN

PMWD26UN

PMWD26UN,518

PMWD30UN

PMWD30UN,518

PMX

PMX-1JJFREQ2