PN7360AUEV/C300Y [NXP]
RISC Microcontroller;
| 型号： | PN7360AUEV/C300Y |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 |
| 文件： | 总108页 (文件大小：1024K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PN7462 family
NFC Cortex-M0 microcontroller
Rev. 4.1 — 28 June 2018
406341
Product data sheet
COMPANY PUBLIC
1 General description
The PN7462 family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers
offering high performance and low power consumption. It has a simple instruction set and
memory addressing along with a reduced code size compared to existing architectures.
PN7462 family offers an all in one solution, with features such as NFC, supporting all
NFC Forum modes, microcontroller, optional contact smart card reader, and software in a
single chip. It operates at CPU frequencies of up to 20 MHz.
Table 1.ꢀComparison of the PN7462 family members
PN7462AUHN PN7462AUEV PN7412AUHN PN7362AUHN PN7362AUEV PN7360AUHN PN7360AUEV
Contact
smart card
reader
Class A, B, C No
Class A, B, C No
No
No
No
ISO/IEC 7816 Yes
Yes
Yes
No
No
No
No
UART
Contactless Yes
interface
Yes
No
Yes
Yes
Yes
80 kB
Yes
80 kB
Available
Flash
160 kB
160 kB
160 kB
160 kB
160 kB
memory
SRAM data
memory
12 kB
12 kB
12 kB
12 kB
12 kB
12 kB
12 kB
General
purposes I/O
12 up-to 21
HVQFN64
14 up-to 21
VFBGA64
12 up-to 21
HVQFN64
14 up-to 21
HVQFN64
14 up-to 21
VFBGA64
14 up-to 21
HVQFN64
14 up-to 21
VFBGA64
Package
type
Having the differences listed in the table above, all products within the PN7462 family
are equipped with 12 kB of SRAM data memory and 4 kB EEPROM. All products within
the family also include one host interface with either high-speed mode I2C-bus, SPI, USB
or high-speed UART, and two master interfaces, SPI and Fast-mode Plus I2C-bus. Four
general-purpose counter/timers, a random number generator, one CRC coprocessor and
up to 21 general-purpose I/O pins.
The PN7462 family NFC microcontroller offers a one chip solution to build contactless, or
contact and contactless applications. It is equipped with a highly integrated high-power
output NFC-IC for contactless communication at 13.56 MHz enabling EMV-compliance
on RF level, without additional external active components.
By integrating a contact ISO/IEC 7816 interface on a single chip, the PN7462AUHN
provides a solution for dual interface smart card readers. Whereas the PN7412AUHN
offers a solution for a contact reader only. The PN7462AUHN and PN7412AUHN contact
interfaces offer a high level of security for the card by performing current limiting, short-
NXP Semiconductors
PN7462 family
NFC Cortex-M0 microcontroller
circuit detection, ESD protection as well as supply supervision. On PN7462AUHN,
PN7412AUHN and PN7462AUEV, an additional UART output is also implemented to
address applications where more than one contact card slot is needed. It enables an
easy connection to multiple smart card slot interfaces like TDA8026.
PN7462AUHN and PN7412AUHN provide thermal and short-circuit protection on all card
contacts. It also provides automatic activation and deactivation sequences initiated by
software or hardware.
PN7462_FAM
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2 Features and benefits
2.1 Integrated contact interface frontend
This chapter applies to the products with contact interface only.
• Class A, B, and C cards can work on 1.8 V, 3 V, and 5 V supply
• Specific ISO UART, variable baud rate through frequency or division ratio
programming, error management at character level for T = 0, and extra guard time
register
• DC-to-DC converter for class A support starting at 3 V, and class B support starting at
2.7 V
• Thermal and short-circuit protection on contact cards
• Automatic activation and deactivation sequence, initiated by software or by hardware in
case of short-circuit, card removal, overheating, and VDD or VDD drop-out
• Enhanced ESD protection (> 12 kV)
• ISO/IEC 7816 compliant
• Compliance with EMV contact protocol specification
• Clock generation up to 13.56 MHz
• Synchronous card support
• Possibility to extend the number of contact interfaces, with the addition of slot
extenders such as TDA8026
2.2 Integrated ISO/IEC 7816-3&4 UART interface
This chapter applies to the products with Integrated ISO/IEC 7816 UART interface
only.
The PN7462 family offers the possibility to extend the number of contact interfaces
available. It uses an I/O auxiliary interface to connect a slot extension (TDA8035 - 1 slot,
TDA8020 - 2 slots, and TDA8026 - 5 slots).
• Class A (5 V), class B (3 V), and class C (1.8 V) smart card supply
• Protection of smart card
• Three protected half-duplex bidirectional buffered I/O lines (C4, C7, and C8)
• Compliant with ISO/IEC 7816 and EMVCo standards
2.3 Integrated contactless interface frontend
This chapter applies to the products with integrated contactless interface only.
• High RF output power frontend IC for transfer speed up to 848 kbit/s
• NFC IP1 and NFC IP2 support
• Full NFC Forum tag support (type 1, type 2, type 3, type 4A, type 4B and type 5)
• P2P active and passive, target, and initiator
• Card emulation ISO14443 type A
• ISO/IEC 14443 type A and type B
• MIFARE products using Crypto 1
• ISO/IEC 15693, and ISO/IEC 18000-3 mode 3
• Low-power card detection
PN7462_FAM
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Product data sheet
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NXP Semiconductors
PN7462 family
NFC Cortex-M0 microcontroller
• Dynamic Power Control (DPC)
• Adaptive Wave Control (AWC)
• Adaptive Range Control (ARC)
• Compliance with EMV contactless protocol specification
2.4 Cortex-M0 microcontroller
• Processor core
– ARM Cortex: 32-bit M0 processor
– Built-in Nested Vectored Interrupt Controller (NVIC)
– Non-maskable interrupt
– 24-bit system tick timer
– Running frequency of up to 20 MHz
– Clock management to enable low power consumption
• Memory
– Flash: 160 kB / 80 kB
– SRAM: 12 kB
– EEPROM: 4 kB
– 40 kB boot ROM included, including USB mass storage primary boot loader for code
download
• Debug option
– Serial Wire Debug (SWD) interface
• Peripherals
– Host interface:
– USB 2.0 full speed with USB 3.0 hub connection capability
– HSUART for serial communication, supporting standards speeds from 9600 bauds to
115200 bauds, and faster speed up to 1.288 Mbit/s
– SPI with half-duplex and full duplex capability with speeds up to 7 Mbit/s
– I2C supporting standard mode, fast mode, and high-speed mode with multiple
address supports
– Master interface:
– SPI with half-duplex capability from 1 Mbit/s to 6.78 Mbit/s
– I2C supporting standard mode, fast mode, fast mode plus, and clock stretching
• Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors
• GPIO1 to GPIO12 can be used as edge and level sensitive interrupt sources
• Power
– Two reduced power modes: standby mode and hard power-down mode
– Supports suspend mode for USB host interface
– Processor wake-up from hard power-down mode, standby mode, suspend mode via
host interface, GPIOs, RF field detection
– Integrated PMU to adjust internal regulators automatically, to minimize the power
consumption during all possible power modes
– Power-on reset
– RF supply: external, or using an integrated LDO (TX LDO, configurable with 3 V, 3.3
V, 3.6 V, 4.5 V, and 4.75 V)
– Pad voltage supply: external 3.3 V or 1.8 V, or using an integrated LDO (3.3 V
supply)
• Timers
PN7462_FAM
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NXP Semiconductors
PN7462 family
NFC Cortex-M0 microcontroller
– Four general-purpose timers
– Programmable Watchdog Timer (WDT)
• CRC coprocessor
• Random number generator
• Clocks
– Crystal oscillator at 27.12 MHz
– Dedicated PLL at 48 MHz for the USB
– Integrated HFO 20 MHz and LFO 365 kHz
• General
– HVQFN64 package
– VFBGA64 package
– Temperature range: -40 °C to +85 °C
PN7462_FAM
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Product data sheet
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NXP Semiconductors
PN7462 family
NFC Cortex-M0 microcontroller
3 Applications
• Physical access control
• Gaming
• USB NFC reader, including dual interface smart card readers
• Home banking, payment readers EMVCo compliant
• High integration devices
• NFC applications
PN7462_FAM
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Product data sheet
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PN7462 family
NFC Cortex-M0 microcontroller
4 Quick reference data
Table 2.ꢀQuick reference data
Operating range: -40 °C to +85 °C unless specified; contact interface: VDDP(VBUSP) = VDDP(VBUS); contactless interface:
internal LDO not used
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDP(VBUS)
power supply voltage
on pin VBUS
card emulation, passive target
(PLM)
2.3
-
5.5
V
all RF modes; class B and class 2.7
C contact interface support
-
-
5.5
5.5
V
V
all RF modes; class A, class B
and class C contact interface
support
3
VDD(PVDD)
PVDD supply voltage
1.8 V
3.3 V
1.65
1.8
3.3
12
1.95
3.6
18
V
3
-
V
IDDP(VBUS)
power supply current on in hard power-down mode; T
μA
pin VBUS
= 25 °C; VDDP(VBUS) = 5.5 V;
RST_N = 0
stand by mode; T = 25 °C;
VDDP(VBUS) = 3.3 V; external
PVDD LDO used
-
-
-
-
18
55
120
-
-
μA
μA
µA
mA
stand by mode; T = 25 °C;
VDDP(VBUS) = 5.5 V; internal
PVDD LDO used
-
suspend mode, USB interface;
VDDP(VBUS) = 5.5 V; external
PVDD supply; T = 25 °C
250
250
IDD(TVDD)
TVDD supply current
on pin TVDD_IN; maximum
supported current by the
contactless interface
Pmax
Tamb
maximum power
dissipation
-
-
-
1050
+85
mW
°C
ambient temperature
JEDEC PCB
-40
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5 Ordering information
The table below lists the ordering information of the PN7462 family.
Table 3.ꢀOrdering information
Type number
Package
Name
Description
Version
PN7462AUHN
PN7462AUEV
PN7412AUHN
PN7362AUHN
PN7362AUEV
PN7360AUHN
PN7360AUEV
HVQFN64
160 kB memory; contact interface; ISO/IEC 7816-3&4
UART interface;
SOT804-4
SOT1307-2
SOT804-4
SOT804-4
SOT1307-2
SOT804-4
SOT1307-2
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
VFBGA64
HVQFN64
HVQFN64
VFBGA64
HVQFN64
VFBGA64
160 kB memory; no contact interface; ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
160 kB memory; contact interface; ISO/IEC 7816-3&4
UART interface; no contactless interface
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
160 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
160 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
80 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
80 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
PN7462_FAM
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Product data sheet
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PN7462 family
NFC Cortex-M0 microcontroller
6 Block diagram
6.1 Block diagram PN7462 HVQFN64
ARM-CORTEX M0
SRAM
12 kB
EEPROM
4 kB
ROM
40 kB
SWD
FLASH
160 kB
CODE PATCH
slave
system
bus
slave
slave
AHB LITE
master slave
master
master
POWER, CLOCK
AND RESET
USB
GPIO
XTAL
CLOCK GENERATORS
HFO
LFO
I2C
SPI
USB PLL
PMU
HSU
MAIN LDO
TX LDO
PVDD LDO
VCC LDO
DC-DC
HOST INTERFACES
SC LDO
CLIF
TEMPERATURE SENSOR
SPI MASTER
TIMERS
TIME 0, 1, 2, 3
WATCHDOG
I2C MASTER
CTIF
ISO7816 UART
RNG
CRC
I/O AUX
aaa-021334
Figure 1.ꢀBlock diagram
PN7462_FAM
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PN7462 family
NFC Cortex-M0 microcontroller
6.2 Block diagram PN7462 VFBGA64
ARM-CORTEX M0
SRAM
12 kB
EEPROM
4 kB
ROM
40 kB
SWD
FLASH
160 kB
CODE PATCH
slave
system
bus
slave
slave
AHB LITE
master slave
master
master
POWER, CLOCK
AND RESET
USB
GPIO
XTAL
CLOCK GENERATORS
HFO
LFO
I2C
SPI
USB PLL
PMU
HSU
MAIN LDO
TX LDO
PVDD LDO
VCC LDO
DC-DC
HOST INTERFACES
SC LDO
CLIF
TEMPERATURE SENSOR
SPI MASTER
TIMERS
TIME 0, 1, 2, 3
WATCHDOG
I2C MASTER
ISO7816 UART
RNG
CRC
I/O AUX
aaa-029225
Figure 2.ꢀBlock diagram
PN7462_FAM
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NFC Cortex-M0 microcontroller
6.3 Block diagram PN7412 HVQFN64
ARM-CORTEX M0
SRAM
12 kB
EEPROM
4 kB
ROM
40 kB
SWD
FLASH
160 kB
CODE PATCH
slave
system
bus
slave
slave
AHB LITE
master slave
master
POWER, CLOCK
AND RESET
USB
GPIO
XTAL
CLOCK GENERATORS
HFO
LFO
I2C
SPI
USB PLL
PMU
HSU
MAIN LDO
TX LDO
PVDD LDO
VCC LDO
DC-DC
HOST INTERFACES
SC LDO
TEMPERATURE SENSOR
SPI MASTER
TIMERS
TIME 0, 1, 2, 3
WATCHDOG
I2C MASTER
CTIF
ISO7816 UART
RNG
CRC
I/O AUX
aaa-030118
Figure 3.ꢀBlock diagram
PN7462_FAM
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NFC Cortex-M0 microcontroller
6.4 Block diagram PN736X
ARM-CORTEX M0
SRAM
12 kB
EEPROM
4 kB
ROM
40 kB
SWD
FLASH
160 / 80 kB
CODE PATCH
slave
system
bus
slave
slave
AHB LITE
master slave
master
master
POWER, CLOCK
AND RESET
USB
GPIO
XTAL
CLOCK GENERATORS
HFO
LFO
I2C
SPI
USB PLL
PMU
HSU
HOST INTERFACES
MAIN LDO
TX LDO
PVDD LDO
CLIF
TEMPERATURE SENSOR
SPI MASTER
TIMERS
TIME 0, 1, 2, 3
WATCHDOG
I2C MASTER
RNG
CRC
aaa-025625
Figure 4.ꢀBlock diagram
PN7462_FAM
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NFC Cortex-M0 microcontroller
7 Pinning information
7.1 Pinning HVQFN64
terminal 1
index area
terminal 1
index area
l2CM_SDA
GPIO14
GPIO15
GPIO16
n.c.
1
2
3
4
5
6
7
8
9
48 VBUSP
47 n.c.
l2CM_SDA
CLK_AUX
IO_AUX
INT_AUX
PRES
1
2
3
4
5
6
7
8
9
48 VBUSP
47 SCVDD
46 SAM
46 n.c.
45 GNDP
44 PVDD_OUT
43 VBUS
42 RST_N
41 XTAL2
40 XTAL1
39 VDD
45 GNDP
44 PVDD_OUT
43 VBUS
ATX_A
ATX_B
ATX_C
ATX_D
ATX_A
ATX_B
42 RST_N
ATX_C
41 XTAL2
PN7462AU
PN736XAU
ATX_D
40 XTAL1
PVDD_IN 10
DVDD 11
PVDD_IN 10
DVDD 11
39 VDD
38 VUP_TX
37 TVDD_OUT
36 ANT2
38 VUP_TX
37 TVDD_OUT
DWL_REQ 12
IRQ 13
DWL_REQ 12
IRQ 13
GND
GND
36 ANT2
35 ANT1
34 TVDD_IN
33 TX1
SWDCLK 14
SWDIO 15
GPIO1 16
35 ANT1
SWDCLK 14
SWDIO 15
GPIO1 16
34 TVDD_IN
33 TX1
aaa-025629
aaa-021124
Transparent top view
Transparent top view
Figure 5.ꢀPin configuration PN736X
Figure 6.ꢀPin configuration PN7462
terminal 1
index area
l2CM_SDA
CLK_AUX
IO_AUX
INT_AUX
PRES
1
2
3
4
5
6
7
8
9
48 VBUSP
47 SCVDD
46 SAM
45 GNDP
44 PVDD_OUT
43 VBUS
42 RST_N
41 XTAL2
40 XTAL1
39 VDD
ATX_A
ATX_B
ATX_C
PN7412AU
ATX_D
PVDD_IN 10
DVDD 11
38 VUP_TX
37 TVDD_OUT
36 n.c.
DWL_REQ 12
IRQ 13
GND
SWDCLK 14
SWDIO 15
GPIO1 16
35 n.c.
34 n.c.
33 n.c.
aaa-030468
Transparent top view
Figure 7.ꢀPin configuration PN7412
Important note: the inner leads below the package are internally connected to the PIN.
Special care needs to be taken during the design so that no conductive part is present
under these PINs, which could cause short cuts.
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7.2 Pin description HVQFN64
Table 4.ꢀPin description
Pin Symbol Description PN736X
PN736X
Symbol Description PN7462
PN7462
Symbol Description PN7412
PN7412
1
2
3
4
I2CM_S I2C-bus serial data I/O
DA master/GPIO13
I2CM_S I2C-bus serial data I/O
I2CM_S I2C-bus serial data I/O
DA
master/GPIO13
DA
master/GPIO13
CLK_A GPIO14
UX
CLK_A auxiliary card contact clock/ CLK_A auxiliary card contact clock/
UX GPIO14 UX GPIO14
IO_AUX GPIO15
IO_AUX auxiliary card contact I/O/
GPIO15
IO_AUX auxiliary card contact I/O/
GPIO15
INT_AU GPIO16
X
INT_AU auxiliary card contact
INT_AU auxiliary card contact
X
interrupt/GPIO16
X
interrupt/GPIO16
5
6
n.c.
not connected
PRES
card presence
PRES
card presence
ATX_A SPI slave select input
(NSS_S)/I2C-bus serial
clock input (SCL_S)/
HSUART RX
ATX_A SPI slave select input
(NSS_S)/I2C-bus serial
clock input (SCL_S)/
HSUART RX
ATX_A SPI slave select input
(NSS_S)/I2C-bus serial
clock input (SCL_S)/
HSUART RX
7
8
9
ATX_B SPI slave data input
(MOSI_S)/I2C-bus serial
data I/O (SDA_S)/HSUART
TX
ATX_B SPI slave data input
(MOSI_S)/I2C-bus serial
data I/O (SDA_S)/HSUART
TX
ATX_B SPI slave data input
(MOSI_S)/I2C-bus serial
data I/O (SDA_S)/HSUART
TX
ATX_C USB D+/SPI slave data
output (MISO_S)/I2C-bus
address bit0 input/HSUART
RTS
ATX_C USB D+/SPI slave data
output (MISO_S)/I2C-bus
address bit0 input/HSUART
RTS
ATX_C USB D+/SPI slave data
output (MISO_S)/I2C-bus
address bit0 input/HSUART
RTS
ATX_D USB D-/SPI clock input
(SCK_S)/I2C-bus address
bit1 input/HSUART CTS
ATX_D USB D-/SPI clock input
(SCK_S)/I2C-bus address
bit1 input/HSUART CTS
ATX_D USB D-/SPI clock input
(SCK_S)/I2C-bus address
bit1 input/HSUART CTS
10 PVDD_ pad supply voltage input
IN
PVDD_ pad supply voltage input
IN
PVDD_ pad supply voltage input
IN
11 DVDD
digital core logic supply
voltage input
DVDD
digital core logic supply
voltage input
DVDD
digital core logic supply
voltage input
12 DWL_R entering in download mode DWL_R entering in download mode DWL_R entering in download mode
EQ
EQ
EQ
13 IRQ
interrupt request output
IRQ
interrupt request output
IRQ
interrupt request output
14 SWDC SW serial debug line clock SWDC SW serial debug line clock SWDC SW serial debug line clock
LK LK LK
15 SWDIO SW serial debug line input/ SWDIO SW serial debug line input/ SWDIO SW serial debug line input/
output
output
output
16 GPIO1 general-purpose I/O/SPI
master select2 output
GPIO1 general-purpose I/O/SPI
master select2 output
GPIO1 general-purpose I/O/SPI
master select2 output
17 GPIO2 general-purpose I/O
18 GPIO3 general-purpose I/O
19 GPIO4 general-purpose I/O
20 GPIO5 general-purpose I/O
GPIO2 general-purpose I/O
GPIO3 general-purpose I/O
GPIO4 general-purpose I/O
GPIO5 general-purpose I/O
GPIO2 general-purpose I/O
GPIO3 general-purpose I/O
GPIO4 general-purpose I/O
GPIO5 general-purpose I/O
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Pin Symbol Description PN736X
PN736X
Symbol Description PN7462
PN7462
Symbol Description PN7412
PN7412
21 GPIO6 general-purpose I/O
22 GPIO7 general-purpose I/O
23 GPIO8 general-purpose I/O
24 GPIO9 general-purpose I/O
25 GPIO10 general-purpose I/O
26 GPIO11 general-purpose I/O
27 GPIO12 general-purpose I/O
GPIO6 general-purpose I/O
GPIO7 general-purpose I/O
GPIO8 general-purpose I/O
GPIO9 general-purpose I/O
GPIO10 general-purpose I/O
GPIO11 general-purpose I/O
GPIO12 general-purpose I/O
GPIO6 general-purpose I/O
GPIO7 general-purpose I/O
GPIO8 general-purpose I/O
GPIO9 general-purpose I/O
GPIO10 general-purpose I/O
GPIO11 general-purpose I/O
GPIO12 general-purpose I/O
28 RXN
29 RXP
30 VMID
receiver input
RXN
RXP
VMID
receiver input
n.c.
n.c.
n.c.
See UM10858 for
connection details
receiver input
receiver input
See UM10858 for
connection details
receiver reference voltage
input
receiver reference voltage
input
See UM10858 for
connection details
31 TX2
antenna driver output
TX2
antenna driver output
n.c.
keep unconnected
32 TVSS
ground for antenna power
supply
TVSS
ground for antenna power
supply
TVSS
ground for antenna power
supply
33 TX1
antenna driver output
TX1
antenna driver output
n.c.
n.c.
keep unconnected
Connect to GND
34 TVDD_ antenna driver supply
TVDD_ antenna driver supply
IN
voltage input
IN
voltage input
35 ANT1
antenna connection for
load modulation in card
emulation and P2P passive
target modes
ANT1
antenna connection for
load modulation in card
emulation and P2P passive
target modes
n.c.
See UM10858 for
connection details
36 ANT2
antenna connection for
load modulation in card
emulation and P2P passive
target modes
ANT2
antenna connection for
load modulation in card
emulation and P2P passive
target modes
n.c.
See UM10858 for
connection details
37 TVDD_ antenna driver supply,
OUT output of TX_LDO
TVDD_ antenna driver supply,
OUT output of TX_LDO
TVDD_ antenna driver supply,
OUT output of TX_LDO
38 VUP_T supply of the contactless
VUP_T supply of the contactless
VUP_T supply of the contactless
X
TX_LDO
X
TX_LDO
X
TX_LDO
39 VDD
1.8 V regulator output for
digital blocks
VDD
1.8 V regulator output for
digital blocks
VDD
1.8 V regulator output for
digital blocks
40 XTAL1 27.12 MHz clock input for
crystal
XTAL1 27.12 MHz clock input for
crystal
XTAL1 27.12 MHz clock input for
crystal
41 XTAL2 27.12 MHz clock input for
crystal
XTAL2 27.12 MHz clock input for
crystal
XTAL2 27.12 MHz clock input for
crystal
42 RST_N reset pin
RST_N reset pin
RST_N reset pin
43 VBUS
main supply voltage input of VBUS
microcontroller
main supply voltage input of VBUS
microcontroller
main supply voltage input of
microcontroller
44 PVDD_ output of PVDD_LDO for
OUT pad voltage supply
PVDD_ output of PVDD_LDO for
PVDD_ output of PVDD_LDO for
OUT
pad voltage supply
OUT
pad voltage supply
45 GNDP Ground
GNDP Ground
GNDP Ground
PN7462_FAM
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Pin Symbol Description PN736X
PN736X
Symbol Description PN7462
PN7462
Symbol Description PN7412
PN7412
46 n.c.
not connected
SAM
DC-to-DC converter
connection
SAM
DC-to-DC converter
connection
47 n.c.
not connected
SCVDD input LDO for DC-to-DC
converter
SCVDD input LDO for DC-to-DC
converter
48 VBUSP Connected to VBUS
VBUSP main supply for the contact VBUSP main supply for the contact
interface
interface
49 n.c.
50 n.c.
not connected
not connected
SAP
VUP
DC-to-DC converter
connection
SAP
VUP
DC-to-DC converter
connection
reserved; connected to
GND through a decoupling
capacitance
reserved; connected to
GND through a decoupling
capacitance
51 n.c.
not connected
VCC
card supply output of
contact interface
VCC
card supply output of
contact interface
52 n.c.
53 n.c.
not connected
not connected
RST
CLK
reset pin of contact interface RST
reset pin of contact interface
clock pin of contact
interface
CLK
clock pin of contact
interface
54 GNDC connected to the ground
GNDC connected to the ground
GNDC connected to the ground
55 n.c.
56 n.c.
57 n.c.
not connected
not connected
not connected
AUX1
AUX2
IO
C4 card I/O pin of contact
interface
AUX1
AUX2
IO
C4 card I/O pin of contact
interface
C8 card I/O pin of contact
interface
C8 card I/O pin of contact
interface
card I/O
card I/O
58 USB_V used for USB VBUS
BUS detection
USB_V used for USB VBUS
BUS detection
USB_V used for USB VBUS
BUS detection
59 PVDD_ pad supply voltage input for PVDD_ pad supply voltage input for PVDD_ pad supply voltage input for
M_IN master interfaces M_IN master interfaces M_IN master interfaces
60 SPIM_S SPI master select 1 output/ SPIM_S SPI master select 1 output/ SPIM_S SPI master select 1 output/
SN GPIO17 SN GPIO17 SN GPIO17
61 SPI_SC SPI master clock output/ SPI_SC SPI master clock output/ SPI_SC SPI master clock output/
LK GPIO18 LK GPIO18 LK GPIO18
62 SPIM_ SPI master data output/ SPIM_ SPI master data output/ SPIM_ SPI master data output/
MOSI GPIO19 MOSI GPIO19 MOSI GPIO19
63 SPIM_ SPI master data input/ SPIM_ SPI master data input/ SPIM_ SPI master data input/
MISO GPIO20 MISO GPIO20 MISO GPIO20
64 I2CM_S I2C-bus serial clock output I2CM_S I2C-bus serial clock output I2CM_S I2C-bus serial clock output
CL
master/GPIO21
CL
master/GPIO21
CL
master/GPIO21
Die GND
pad
Ground
GND
Ground
GND
Ground
PN7462_FAM
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7.3 Pinning VFBGA64
H
G
F
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
aaa-027834
Figure 8.ꢀPin configuration VFBGA64
7.4 Pin description VFBGA64
Table 5.ꢀPin description
Pin
Symbol
PN736X
Description PN736X
Symbol
PN7462
Description PN7462
A1
A2
A3
I2CM_SDA
I2C-bus serial data I/O master/GPIO13
I2CM_SDA
I2C-bus serial data I/O master/GPIO13
SPIM_MISO SPI master data input/GPIO20
SPIM_MISO SPI master data input/GPIO20
PVDD_M_IN pad supply voltage input for master
interfaces
PVDD_M_IN pad supply voltage input for master
interfaces
A4
A5
VBUSP
VBUS
Connected to VBUS
VBUSP
VBUS
Connected to VBUS
main supply voltage input of
microcontroller
main supply voltage input of
microcontroller
A6
A7
PVSS
Pad ground
PVSS
Pad ground
PVDD_OUT output of PVDD_LDO for pad voltage
supply
PVDD_OUT output of PVDD_LDO for pad voltage
supply
A8
B1
B2
XTAL2
27.12 MHz clock input for crystal
GPIO16
SPI slave select input (NSS_S)/I2C-bus
serial clock input (SCL_S)/HSUART RX
XTAL2
27.12 MHz clock input for crystal
INT_AUX
ATX_A
INT_AUX
ATX_A
auxiliary card contact interrupt/GPIO16
SPI slave select input (NSS_S)/I2C-bus
serial clock input (SCL_S)/HSUART RX
B3
B4
B5
B6
B7
B8
C1
C2
SPIM_MOSI SPI master data output/GPIO19
SPIM_SSN SPI master select 1 output/GPIO17
USB_VBUS used for USB VBUS detection
SPIM_MOSI SPI master data output/GPIO19
SPIM_SSN SPI master select 1 output/GPIO17
USB_VBUS used for USB VBUS detection
PVSS
Pad ground
PVSS
Pad ground
PVSS
Pad ground
PVSS
Pad ground
XTAL1
CLK_AUX
ATX_B
27.12 MHz clock input for crystal
GPIO14
SPI slave data input (MOSI_S)/I2C-bus
serial data I/O (SDA_S)/HSUART TX
XTAL1
CLK_AUX
ATX_B
27.12 MHz clock input for crystal
auxiliary card contact clock/GPIO14
SPI slave data input (MOSI_S)/I2C-bus
serial data I/O (SDA_S)/HSUART TX
PN7462_FAM
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Pin
Symbol
PN736X
Description PN736X
Symbol
PN7462
Description PN7462
C3
I2CM_SCL
I2C-bus serial clock output master/
GPIO21
I2CM_SCL
I2C-bus serial clock output master/
GPIO21
C4
C5
C6
C7
C8
D1
D2
SPI_SCLK
DVSS
SPI master clock output/GPIO18
Digital ground
SPI_SCLK
DVSS
SPI master clock output/GPIO18
Digital ground
PVSS
Pad ground
PVSS
Pad ground
RST_N
VDD
reset pin
RST_N
VDD
reset pin
1.8 V regulator output for digital blocks
pad supply voltage input
1.8 V regulator output for digital blocks
pad supply voltage input
PVDD_IN
ATX_C
PVDD_IN
ATX_C
USB D+/SPI slave data output
(MISO_S)/I2C-bus address bit0 input/
HSUART RTS
USB D+/SPI slave data output
(MISO_S)/I2C-bus address bit0 input/
HSUART RTS
D3
D4
D5
D6
D7
D8
E1
E2
IRQ
interrupt request output
GPIO15
IRQ
interrupt request output
auxiliary card contact I/O/GPIO15
Digital ground
IO_AUX
DVSS
PVSS
PVSS
VUP_TX
DVDD
ATX_D
IO_AUX
DVSS
PVSS
PVSS
VUP_TX
DVDD
Digital ground
Pad ground
Pad ground
Pad ground
Pad ground
supply of the contactless TX_LDO
digital core logic supply voltage input
USB D-/SPI clock input (SCK_S)/I2C-bus ATX_D
address bit1 input/HSUART CTS
supply of the contactless TX_LDO
digital core logic supply voltage input
USB D-/SPI clock input (SCK_S)/I2C-bus
address bit1 input/HSUART CTS
E3
GPIO1
general-purpose I/O/SPI master select2 GPIO1
output
general-purpose I/O/SPI master select2
output
E4
E5
E6
E7
GPIO5
DVSS
AVSS
ANT2
general-purpose I/O
Digital ground
GPIO5
DVSS
AVSS
general-purpose I/O
Digital ground
Analog ground
Analog ground
antenna connection for load modulation ANT2
in card emulation and P2P passive target
modes
antenna connection for load modulation
in card emulation and P2P passive target
modes
E8
F1
F2
F3
F4
F5
F6
F7
TVDD_OUT antenna driver supply, output of TX_LDO TVDD_OUT antenna driver supply, output of TX_LDO
DWL_REQ
SWDIO
GPIO6
GPIO9
GPIO12
AVSS
entering in download mode
SW serial debug line input/output
general-purpose I/O
DWL_REQ
SWDIO
GPIO6
entering in download mode
SW serial debug line input/output
general-purpose I/O
general-purpose I/O
GPIO9
general-purpose I/O
general-purpose I/O
GPIO12
AVSS
general-purpose I/O
Analog ground
Analog ground
ANT1
antenna connection for load modulation ANT1
in card emulation and P2P passive target
modes
antenna connection for load modulation
in card emulation and P2P passive target
modes
F8
TVDD_IN
antenna driver supply voltage input
TVDD_IN
antenna driver supply voltage input
PN7462_FAM
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Pin
Symbol
PN736X
Description PN736X
Symbol
PN7462
Description PN7462
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
SWDCLK
GPIO4
GPIO7
GPIO8
GPIO10
GPIO11
AVSS
TX1
SW serial debug line clock
general-purpose I/O
general-purpose I/O
general-purpose I/O
general-purpose I/O
general-purpose I/O
Analog ground
SWDCLK
GPIO4
GPIO7
GPIO8
GPIO10
GPIO11
AVSS
TX1
SW serial debug line clock
general-purpose I/O
general-purpose I/O
general-purpose I/O
general-purpose I/O
general-purpose I/O
Analog ground
antenna driver output
general-purpose I/O
general-purpose I/O
receiver reference voltage input
receiver input
antenna driver output
general-purpose I/O
general-purpose I/O
receiver reference voltage input
receiver input
GPIO3
GPIO2
VMID
GPIO3
GPIO2
VMID
RXN
RXN
RXP
receiver input
RXP
receiver input
TVSS
TX2
Antenna driver ground
antenna driver output
Antenna driver ground
TVSS
TX2
Antenna driver ground
antenna driver output
Antenna driver ground
TVSS
TVSS
PN7462_FAM
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8 Functional description
8.1 ARM Cortex-M0 microcontroller
The PN7462 family is an ARM Cortex-M0-based 32-bit microcontroller, optimized for low-
cost designs, high energy efficiency, and simple instruction set.
The CPU operates on an internal clock, which can be configured to provide frequencies
such as 20 MHz, 10 MHz, and 5 MHz.
The peripheral complement of the PN7462 family includes a 160 kB flash memory, a 12
kB SRAM, and a 4 kB EEPROM. It also includes one configurable host interface (Fast-
mode Plus and high-speed I2C, SPI, HSUART, and USB), two master interfaces (Fast-
mode Plus I2C, SPI), 4 timers, 12 general-purpose I/O pins, one ISO/IEC 7816 contact
card interface (PN7462AUHN only), one ISO/IEC 7816-3&4 UART (PN7462AUHN and
PN7462AUEV only) and one 13.56 MHz contactless interface.
8.2 Memories
8.2.1 On-chip flash programming memory
The PN7462 family contains160 / 80 kB on-chip flash program memory depending on
the version. The flash can be programmed using In-System Programming (ISP) or In-
Application Programming (IAP) via the on-chip boot loader software.
The flash memory is divided into two instances of 80 kB each, with each sector
consisting of individual pages of 64 bytes.
8.2.1.1 Memory mapping
The flash memory mapping is described in Figure 9.
0x0021 6FFF
0x0022 AFFF
0x0022 A7FF
2
RESERVED
KBytes
user
application
80
KBytes
FLASH
user
158
application
KBytes
0x0020 3000
0x0020 3000
PN7360
PN7362 / PN7462
aaa-025626
Figure 9.ꢀFlash memory mapping
PN7462_FAM
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8.2.2 EEPROM
The PN7462 family embeds 4 kB of on-chip byte-erasable and byte-programmable
EEPROM data memory.
The EEPROM can be programmed using In-System Programming (ISP).
8.2.2.1 Memory mapping
0x201FFF
3.5
KBytes
user space
0x201200
512
Bytes
RESERVED
0x201000
aaa-021125
Figure 10.ꢀEEPROM memory mapping
8.2.3 SRAM
The PN7462 family contains a total of 12 kB on-chip static RAM memory.
8.2.3.1 Memory mapping
The SRAM memory mapping is shown in Figure 11.
PN7462_FAM
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RAM_Sys_End = 0x00102FFF
RAM_Sys_Start = 0x00102F00
256
Bytes
RAM_SYSTEM
RESERVED
12000
Bytes
RAM USER RW
RAM_User_Start = 0x00100020
RAM_User_RO_Start = 0x100000
32
Bytes
RESERVED
aaa-021126
Figure 11.ꢀSRAM memory mapping
8.2.4 ROM
The PN7462 family contains 40 kB of on-chip ROM memory. The on-chip ROM contains
boot loader, USB mass storage primary download, and the following Application
Programming Interfaces (APIs):
• In-Application Programming (IAP) support for flash
• Lifecycle management of debug interface, code write protection of flash memory and
USB mass storage primary download
• USB descriptor configuration
• Configuration of timeout and source of pad supply
8.2.5 Memory map
The PN7462 family incorporates several distinct memory regions. Figure 12 shows the
memory map, from the user program perspective, following reset.
The APB peripheral area is 512 kB in size, and is divided to allow up to 32 peripherals.
Only peripherals from 0 to 15 are accessible. Each peripheral allocates 16 kB, which
simplifies the address decoding for the peripherals. APB memory map is described in
Figure 13 and Figure 14.
PN7462_FAM
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4 GB
0xFFFF FFFF
4 GB
0xFFFF FFFF
RESERVED
RESERVED
PRIVATE PERIPHERAL BUS
RESERVED
0xE0FF FFFF
0xE000 0000
0xE0FF FFFF
PRIVATE PERIPHERAL BUS
0xE000 0000
RESERVED
0x4007 FFFF
0x4000 0000
0x4007 FFFF
APB PERIPHERAL
APB PERIPHERAL
RESERVED
0x4000 0000
1 GB
1 GB
RESERVED
0x0022 AFFF
0x0020 3000
0x0022 AFFF
160 kB FLASH
80 kB FLASH
0x0020 3000
RESERVED
RESERVED
0x0020 1FFF
0x0020 1000
0x0020 1FFF
4 kB EEPROM
4 kB EEPROM
0x0020 1000
EEPROM REG
RESERVED
EEPROM REG
0x0020 0000
0x0020 0000
2 MB
2 MB
RESERVED
0x0010 2FFF
0x0010 0000
0x0010 2FFF
12 kB SRAM
12 kB SRAM
RESERVED
0x0010 0000
1 MB
0 MB
1 MB
0 MB
RESERVED
0x0000 9FFF
0x0000 0000
0x0000 9FFF
40 kB ROM
40 kB ROM
0x0000 0000
PN7360
PN7362 / PN7462
aaa-025628
Figure 12.ꢀPN7462 family memory map
PN7462_FAM
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APB ID
APB IF name
Connected IP
0x4004 8000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
aaa-021127
Reserved
Reserved
Reserved
16 to 31
15
14
13
12
11
10
9
SPIMASTER_APB
I2CMASTER_APB
SPI Master IF
I2C Master IF
Reserved
USB_APB
PCR_APB
HostIF (USB) IP
PowerClockResetModule IP
HostIF (I2C/SPI/HSU/BufMgt) IP
Timer IP
8
HOST_APB
TIMERS_APB
RNG_APB
7
6
RNG IP
Reserved
5
CLOCKGEN_APB
CRC_APB
Clock Gen module
CRC IP
4
3
2
PMU_APB
PMU modules
Contactless IP
1
0
CL_APB
Reserved
Figure 13.ꢀAPB memory map PN736X
APB ID
APB IF name
Connected IP
0x4004 8000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
aaa-028697
Reserved
Reserved
Reserved
16 to 31
15
14
13
12
11
10
9
SPIMASTER_APB
I2CMASTER_APB
SPI Master IF
I2C Master IF
Reserved
USB_APB
PCR_APB
HostIF (USB) IP
PowerClockResetModule IP
HostIF (I2C/SPI/HSU/BufMgt) IP
Timer IP
8
HOST_APB
TIMERS_APB
RNG_APB
7
6
RNG IP
5
CTUART_APB
CLOCKGEN_APB
CRC_APB
Contact UART IP
Clock Gen module
CRC IP
4
3
2
PMU_APB
PMU modules
1
0
CL_APB
Contactless IP
Reserved
Figure 14.ꢀAPB memory map PN7462
PN7462_FAM
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APB ID
APB IF name
Connected IP
0x4004 8000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
aaa-030119
Reserved
Reserved
Reserved
16 to 31
15
14
13
12
11
10
9
SPIMASTER_APB
I2CMASTER_APB
SPI Master IF
I2C Master IF
Reserved
USB_APB
PCR_APB
HostIF (USB) IP
PowerClockResetModule IP
HostIF (I2C/SPI/HSU/BufMgt) IP
Timer IP
8
HOST_APB
TIMERS_APB
RNG_APB
7
6
RNG IP
5
CTUART_APB
CLOCKGEN_APB
CRC_APB
Contact UART IP
Clock Gen module
CRC IP
4
3
2
PMU_APB
PMU modules
1
0
Reserved
Reserved
Figure 15.ꢀAPB memory map PN7412
8.3 Nested Vectored Interrupt Controller (NVIC)
Cortex-M0 includes a Nested Vectored Interrupt Controller (NVIC). The tight coupling to
the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
8.3.1 NVIC features
• System exceptions and peripheral interrupts control
• Support 32 vectored interrupts
• Four interrupt priority levels with hardware priority level masking
• One Non-Maskable Interrupt (NMI) connected to the watchdog interrupt
• Software interrupt generation
8.3.2 Interrupt sources
The following table lists the interrupt sources available in the PN7462 family
microcontroller.
Table 6.ꢀInterrupt sources
EIRQ# Source
Description
0
1
2
3
4
5
6
timer 0/1/2/3 general-purpose timer 0/1/2/3 interrupt
-
reserved
CLIF
contactless interface module interrupt
EECTRL
EEPROM controller
-
reserved
-
reserved
host IF
TX or RX buffer from I2C, SPI, HSU, or USB module
PN7462_FAM
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EIRQ# Source
Description
7
8
9
contact IF
ISO7816 contact module interrupt
reserved
-
PMU
power management unit (temperature sensor, over current, overload,
and VBUS level)
10
11
12
SPI master
I2C master
PCR
TX or RX buffer from SPI master module
TX or RX buffer from I2C master module
high temperature from temperature sensor 0 and 1; interrupt to CPU
from PCR to indicate wake-up from suspend mode; out of standby; out
of suspend; event on GPIOs configured as inputs
13
14
PCR
PCR
interrupt common GPIO1 to GPIO12
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO1
15
16
17
18
19
20
21
22
23
24
25
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO2
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO3
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO4
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO5
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO6
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO7
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO8
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO9
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO10
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO11
interrupt (rise/fall/both-edge/level-high/level-low interrupt as
programmed) GPIO12
26
-
reserved
27
-
reserved
28
-
reserved
29
-
reserved
30
-
reserved
31
-
reserved
NMI[1]
WDT
watchdog interrupt is connected to the non-maskable interrupt pin
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[1] The NMI is not available on an external pin.
8.4 GPIOs
The PN7462 family has up to 21 general-purpose I/O (GPIO) with configurable pull-up
and pull-down resistors, up to 9 of those GPIOs are multiplexed with SPI master, I2C-bus
master and AUX pins (if available).
Pins can be dynamically configured as inputs or outputs. GPIO read/write are made by
the FW using dedicated registers that allow reading, setting, or clearing inputs. The value
of the output register can be read back, as well as the current state of the input pins.
8.4.1 GPIO features
• Dynamic configuration as input or output
• 3.3 V and 1.8 V signaling
• Programmable weak pull-up and weak pull-down
• Independent interrupts for GPIO1 to GPIO12
• Interrupts: edge or level sensitive
• GPIO1 to GPIO12 can be programmed as wake-up sources
• Programmable spike filter (3 ns)
• Programmable slew rate (3 ns and 10 ns)
• Hysteresis receiver with disable option
8.4.2 GPIO configuration
The GPIO configuration is done through the PCR module (power, clock, and reset).
8.4.3 GPIO interrupts
GPIO1 to GPIO12 can be programmed to generate an interrupt on a level, a rising or
falling edge or both.
8.5 CRC engine 16/32 bits
The PN7462 family has a configurable 16/32-bit parallel CRC co-processor.
The 16-bit CRC is compliant to X.25 (CRC-CCITT, ISO/IEC 13239) standard with a
generator polynome of:
The 32-bit CRC is compliant to the ethernet/AAL5 (IEEE 802.3) standard with a
generator polynome of:
CRC calculation is performed in parallel, meaning that one CRC calculation is performed
in one clock cycle. The standard CRC 32 polynome is compliant with FIPS140-2.
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Note: No final XOR calculation is performed.
Following are the CRC engine features:
• Configurable CRC preset value
• Selectable LSB or MSB first
• CRC 32 calculation based on 32-bit, 16-bit, and 8-bit words
• CRC16 calculation based on 32-bit, 16-bit, and 8-bit words
• Supports bit order reverse
8.6 Random Number Generator (RNG)
The PN7462 family integrates a random number generator. It consists of an analog True
Random Number Generator (TRNG), and a digital Pseudo Random Number Generator
(PRNG). The TRNG is used for loading a new seed in the PRNG.
The random number generator features:
• 8-bit random number
• Compliant with FIPS 140-2
• Compliant with BSI AIS20 and SP800-22
8.7 Master interfaces
8.7.1 I2C master interface
The PN7462 family contains one I2C master and one I2C slave controller. This chapter
describes the master interface. For more information on the I2C slave controller, refer to
Section 8.8.2.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial Data Line (SDA). Each device has a unique address. The device can
operate either as a receive-only device (such as LCD driver) or a transmitter with the
capability to both receive and send information (such as memory).
8.7.1.1 I2C features
The I2C master interface supports the following features:
• Standard I2C-compliant bus interface with open-drain pins
• Standard-mode, fast mode, and fast mode plus (up to 1 Mbit/s).
• Support I2C master mode only.
• Programmable clocks allowing versatile rate control.
• Clock stretching
• 7-bit and 10-bit I2C slave addressing
• LDM/STM instruction support
• Maximum data frame size up to 1024 bytes
8.7.2 SPI interface
The PN7462 family contains one SPI master controller and one SPI slave controller.
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The SPI master controller transmits the data from the system RAM to the SPI external
slaves. Similarly, it receives data from the SPI external slaves and stores them into the
system RAM. It can compute a CRC for received frames and automatically compute and
append CRC for outgoing frames (optional feature).
8.7.2.1 SPI features
The SPI master interface provides the following features:
• SPI master interface: synchronous, half-duplex
• Supports Motorola SPI frame formats only (SPI block guide V04.0114 (Freescale)
specification)
• Maximum SPI data rate of 6.78 Mbit/s
• Multiple data rates such as 1, 1.51, 2.09, 2.47, 3.01, 4.52, 5.42 and 6.78 Mbit/s
• Up to two slaves select with selectable polarity
• Programmable clock polarity and phase
• Supports 8-bit transfers only
• Maximum frame size: 511 data bytes payload + 1 CRC byte
• Optional 1 byte CRC calculation on all data of TX and RX buffer
• AHB master interface for data transfer
8.8 Host interfaces
The PN7462 family embeds four different interfaces for host connection: USB, HSUART,
I2C, and SPI.
The four interfaces share the buffer manager and the pins; see Table 7.
Table 7.ꢀPin description for host interface
Name
SPI
I2C
USB
-
HSU
ATX_A
ATX_B
ATX_C
ATX_D
NSS_S
MOSI_S
MISO_S
SCK_S
SCL_S
SDA_S
I2C_ADR0
I2C_ADR1
HSU_RX
HSU_TX
-
DP
DM
HSU_RTS_N
HSU_CTS_N
The interface selection is done by configuring the Power Clock Reset (PCR) registers.
Note: The host interface pins should not be kept floating.
8.8.1 High-speed UART
The PN7462 family has a high-speed UART which can operate in slave mode only.
Following are the HSUART features:
• Standard bit-rates are 9600, 19200, 38400, 57600, 115200, and up to 1.288 Mbit/s
• Supports full duplex communication
• Supports only one operational mode: start bit, 8 data bits (LSB), and stop bits
• The number of "stop bits" programmable for RX and TX is 1 stop bit or 2 stop bits
• Configurable length of EOF (1-bit to 122-bits)
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Table 8.ꢀHSUART baudrates
Bit rate (kBd)
9.6
19.2
38.4
57.6
115.2
230.4
460.8
921.6
1288 K
8.8.2 I2C host interface controller
The PN7462 family contains one I2C master and one I2C slave controller. This section
describes the slave interface used for host communication. For more information on the
I2C master controller, refer to Section 8.7.1.
The I2C-bus is bidirectional and uses only two wires: a Serial Clock Line (SCL) and a
Serial Data Line (SDA). I2C standard mode (100 kbit/s), fast mode (400 kbit/s and up to 1
Mbit/s), and high-speed mode (3.4 Mbit/s) are supported.
8.8.2.1 I2C host interface features
The PN7462 family I2C slave interface supports the following features:
• Support slave I2C bus
• Standard mode, fast mode (extended to 1 Mbit/s support), and high-speed modes
• Supports 7-bit addressing mode only
• Selection of the I2C address done by two pins
– It supports multiple addresses
– The upper bits of the I2C slave address are hard-coded. The value corresponds to
the NXP identifier for I2C blocks. The value is 0101ꢀ0XXb.
• General call (software reset only)
• Software reset (in standard mode and fast mode only)
Table 9.ꢀI2C interface addressing
I2C_ADR1 I2C_ADR0 I2C address (R/W = 0, write)
I2C address (R/W = 0, read)
0
0
1
1
0
1
0
1
0 × 28
0 × 29
0 × 2A
0 × 2B
0 × 28
0 × 29
0 × 2A
0 × 2B
8.8.3 SPI host/Slave interface
The PN7462 family host interface can be used as SPI slave interface.
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The SPI slave controller operates on a four wire SSI: Master In Slave Out (MISO), Master
Out Slave In (MOSI), Serial Clock (SCK), and Not Slave Select (NSS). The SPI slave
select polarity is fixed to positive polarity.
8.8.3.1 SPI host interface features
The SPI host/slave interface has the following features:
• SPI speeds up to 7 Mbit/s
• Slave operation only
• 8-bit data format only
• Programmable clock polarity and phase
• SPI slave select polarity selection fixed to positive polarity
• Half-duplex in HDLL mode
• Full-duplex in native mode
If no data is available, the MISO line is kept idle by making all the bits high (0xFF).
Toggling the NSS line indicates a new frame.
Note: Programmable echo-back operation is not supported.
Table 10.ꢀSPI configuration
connection
CPHA switch: Clock phase: Defines the sampling edge of MOSI data
• CPHA = 1: Data are sampled on MOSI on the even clock edges of SCK, after NSS goes low
• CPHA = 0: Data are sampled on MOSI on the odd clock edges of SCK, after NSS goes low
CPOL switch: Clock polarity
• IFSEL1 = 0: The clock is idle low, and the first valid edge of SCK is a rising one
• IFSEL1 = 0: The clock is idle high, and the first valid edge of SCK is a falling one
8.8.4 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between
a host and up to 127 peripherals. The host controller allocates the USB bandwidth to
attached devices through a token-based protocol. The bus supports hot-plugging and
dynamic configuration of devices. The host controller initiates all transactions. The
PN7462 family USB interface consists of a full-speed device controller with on-chip PHY
(physical layer) for device functions.
8.8.4.1 Full speed USB device controller
The PN7462 family embeds a USB device peripheral, compliant with USB 2.0
specification, full speed. It is interoperable with USB 3.0 host devices.
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer.
The status of a completed USB transfer or error condition is indicated via status registers.
If enabled, an interrupt is generated.
Following are the USB interface features:
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• Fully compliant with USB 2.0 specification (full speed)
• Dedicated USB PLL available
• Supports 14 physical (7 logical) endpoints including one control endpoint
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types
• Single or double buffering allowed
• Support wake-up from suspend mode on USB activity and remote wake-up
• Soft-connect supported
8.9 Contact interface
Note: This following chapter applies to PN7462AUHN, PN7412AUHN and PN7462AUEV
only. PN7462AUHN and PN7412AUHN embed a contact interface and I/O auxiliary
interface. PN7462AUEV embeds the I/O auxiliary interface only.
The PN7462 and PN7412 integrate an ISO/IEC 7816 interface to enable the
communication with a contact smart card. It does not require addition of an external
contact frontend for reading payment cards, SAM for secure applications, etc. It offers a
high level of security for the card by performing current limitation, short-circuit detection,
ESD protection as well as supply supervision.
PN7462 and PN7412 also offer the possibility to extend the number of contact interfaces
available. They use an I/O auxiliary interface to connect a slot extension (TDA8035 - 1
slot, TDA8020 - 2 slots, and TDA8026 - 5 slots).
• Class A (5 V), class B (3 V), and class C (1.8 V) smart card supply
• Protection of smart card
• Three protected half-duplex bidirectional buffered I/O lines (C4, C7, and C8)
• Compliant with ISO/IEC 7816 and EMVCo 4.3 standards
8.9.1 Contact interface features and benefits
• Protection of the smart card
– Thermal and current limitation in the event of short-circuit (pins I/O, VCC
)
– VCC regulation: 5 V, 3 V, and 1.8 V
– Automatic deactivation initiated by hardware in the event of a short-circuit, card take-
off, overheating, falling of PN7462 supply
– Enhanced card-side ElectroStatic Discharge (ESD) protection of greater than 8 kV
• Support of class A, class B, and class C contact smart cards
• DC-to-DC converter for VCC generation to enable support of class A and class B cards
with low input voltages
• Built-in debouncing on card presence contact
• Compliant with ISO/IEC 7816 and EMVCo 4.3 standards
• Card clock generation up to 13.56 MHz using external crystal oscillator (27.12 MHz);
provides synchronous frequency changes of fXTAL / 2, fXTAL / 3, fXTAL / 4, fXTAL / 5, fXTAL
/ 6, fXTAL / 8, and fXTAL / 16
• Specific ISO/IEC UART with APB access for automatic convention processing, variable
baud rate through frequency or division ratio programming, error management at
character level for T = 0 and extra guard time register
– FIFO 1 character to 32 characters in both reception and transmission mode
– Parity error counter in reception mode and transmission mode with automatic
retransmission
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– Cards clock stop (at HIGH or LOW level)
– Automatic activation and deactivation sequence through a sequencer
– Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO/IEC
7816 and EMV
– Versatile 24-bit timeout counter for Answer To Reset (ATR) and waiting times
processing
– Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT); 22 ETU in
T = 1 and 16 ETU in T = 0
– Supports synchronous cards
8.9.2 Voltage supervisor
The PN7462 integrates a voltage monitor to ensure that sufficient voltage is available for
the contact interface; see Section 8.15.4 and Section 9.1.3.
In order to provide the right voltage needed for the various ISO/IEC 7816 contact card
classes (A, B, or C), the following voltages are needed:
• VDDP(VBUSP) > 2.7 V for support of class B and class C contact cards
• VDDP(VBUSP) > 3 V for support of class A contact cards
• Remark: To support class A cards, DC-to-DC converter is used in doubler mode. To
support class B cards with VDDP(VBUSP) < 3.9 V, DC-to-DC converter is used in doubler
mode. To support class B cards with VDDP(VBUSP) > 3.9 V, DC-to-DC converter is used
in follower mode.
Figure 16 shows the classes that are supported, depending on VDDP(VBUSP)
.
class A
cards
class B
cards
class C
cards
V
DDP(VBUSP)
3.9 V
DC-to-DC converter
needed in doubler mode
DC-to-DC converter
needed in follower mode
V
DDP(VBUSP)
threshold value
card deactivation to be
performed when
3.0 V
2.7 V
V
is going
DDP(VBUSP)
below the threshold value
aaa-021128
Figure 16.ꢀVDDP(VBUS), supported contact cards classes, and card deactivation
When the VDDP(VBUSP) is going below the threshold value, in the one of the conditions
indicated below, a card deactivation is performed:
• Class A card activated, and VDDP(VBUSP) going below 3 V
• Class B card activated, and VDDP(VBUSP) going below 3.9 V (DC-to-DC converter in
follower mode)
• Class B card activated, and VDDP(VBUSP) going below 2.7 V (DC-to-DC converter in
doubler mode)
• Class C card activated, and VDDP(VBUSP) going below 2.7 V
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The VBUSP voltage monitor can be configured so that an automatic "card deactivation"
sequence is performed automatically when VDDP(VBUSP) is going below the threshold
value.
8.9.3 Clock circuitry
The card clock is generated from the crystal oscillator, connected on the pin XTAL1 and
XTAL2.
The card frequency is configured through the contact interface registers. The following
value can be chosen: fXTAL / 2, fXTAL / 3, fXTAL / 4, fXTAL / 5, fXTAL / 6, fXTAL / 8, and fXTAL
16.
/
It is possible to put the card clock to a logical level 0 or 1 (clock stop feature).
The duty cycle on the pin CLK is between 45 % and 55 %, for all the available clock
dividers.
8.9.4 I/O circuitry
The three data lines I/O, AUX1, and AUX2 are identical.
I/O is referenced to VCC. To enter in the idle state, the I/O line is pulled HIGH via a 10 kΩ
resistor (I/O to VCC).
The active pull-up feature ensures fast LOW to HIGH transitions. At the end of the active
pull-up pulse, the output voltage depends on the internal pull-up resistor and the load
current.
The maximum frequency on these lines is 1.5 MHz.
8.9.5 VCC regulator
VCC regulator delivers up to 60 mA for class A cards (0 V to 5 V). It also delivers up to
55 mA for class B cards (0 V to 3 V) and up to 35 mA for class C cards (from 0 V to 1.8
V).
The VCC has an internal overload detection at approximately 110 mA for class A and B,
and 90 mA for class C.
This detection is internally filtered, allowing the card to draw spurious current pulses as
defined in EMVCo specification, without causing a deactivation. The average current
value must remain below the maximum.
8.9.6 Activation sequence
The presence of a contact card is indicated to PN7462 through PRESN signal. If all
supply conditions are met, the PN7462 may start an activation sequence. Figure 17
shows the activation sequence.
The sequencer clock is based on the crystal oscillator: fseq = fXTAL /10. When the contact
interface is active, the period for activation phases is: T = 64/fseq = 23.6 μs.
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T / 2
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Start
VUP
VCC
IO
CLK
RST
t
t
t
t
t
4
t
5
aaa-021129
0
1
2
3
Figure 17.ꢀContact interface - activation sequence
Once the activation sequence is triggered, the following sequence takes place:
• Contact LDOs and DC-to-DC converter (when relevant) starts at t1
• VCC starts rising from 0 to the required voltage (5 V, 3 V, and 1.8 V) at t2
• IO rises to VCC at t3
• CLK starts at t4
• RST pin is enabled at t5
8.9.7 Deactivation sequence
When triggered by the PN7462, the deactivation following sequence takes place:
• Card reset (pin RST) status goes LOW
• Clock (CLK) stopped at LOW level
• Pin IO falls to 0 V
• VCC falls to 0 V
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T / 2
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Start
RST
CLK
IO
VCC
DC-to-DC converter/
LDOs
aaa-021130
t
t
t
t
t
4
0
1
2
3
Figure 18.ꢀDeactivation sequence for contact interface
The deactivation sequence is performed in the following cases:
• Removal of card; generated automatically by the PN7462
• Overcurrent detection on pin VCC; generated automatically by the PN7462
• Overcurrent detection on pin IO; generated automatically by the PN7462
• Detection for overheating; generated automatically by the PN7462
• Pin VBUSP going below relevant voltage threshold (optional); part of the pin VBUSP
monitor
• Reset request through software
8.9.8 I/O auxiliary - connecting TDA slot extender
To address applications where multiple ISO/IEC 7816 interfaces are needed, the PN7462
integrates the possibility to connect contact slot extenders like TDA8026, TDA8020, or
TDA8035.
The following pins are available:
• INT_AUX
• CLK_AUX
• IO_AUX
For more details about the connection, refer to the slot extender documentation.
8.10 Contactless interface - 13.56 MHz
This chapter applies to the products with contactless interface only.
The PN7462 family embeds a high power 13.56 MHz RF frontend. The RF interface
implements the RF functionality like antenna driving, the receiver circuitry, and all the
low-level functionalities. It helps to realize an NFC forum or an EMVCo compliant reader.
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The PN7462 family allows different voltages for the RF drivers. For information related to
the RF interface supply, refer Section 8.15.
The PN7462 family uses an external oscillator, at 27.12 MHz. It is a clock source for
generating RF field and its internal operation.
Key features of the RF interface are:
• ISO/IEC 14443 type A & B compliant
• MIFARE functionality, including MIFARE Classic encryption in read/write mode
• ISO/IEC 15693 compliant
• NFC Forum - NFCIP-1 & NFCIP-2 compliant
– P2P, active and passive mode
– reading of NFC forum tag types 1, 2, 3, 4, and 5
• FeliCa
• ISO/IEC 18000-3 mode 3
• EMVCo contactless 2.6
– RF level can be achieved without the need of booster circuitry (for some antenna
topologies the EMV RF-level compliance might physically not be achievable)
• Card mode - enabling the emulation of an ISO/IEC 14443 type A card
– Supports Passive Load Modulation (PLM) and Active Load Modulation (ALM)
• Low Power Card Detection (LPCD)
• Adjustable RX-voltage level
A minimum voltage of 2.3 V helps to use card emulation, and P2P passive target
functionality in passive load modulation.
A voltage above 2.7 V enables all contactless functionalities.
8.10.1 RF functionality
8.10.1.1 Communication mode for ISO/IEC 14443 type A and for MIFARE Classic
The physical level of the communication is shown in Figure 19.
(1)
ISO/IEC 14443 A
ISO/IEC 14443 A CARD
READER
(2)
001aam268
1. Reader to Card: 100 % ASK; modified miller coded; transfer speed 106 kbit/s to 848 kbit/s
2. Card to Reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 19.ꢀRead/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE
Classic
The physical parameters are described in Table 11
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Table 11.ꢀCommunication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
reader to card (send
reader side
100 % ASK
100 % ASK
100 % ASK
100 % ASK
data from the PN7462 modulation
family to a card)
bit encoding
modified miller
encoding
modified miller
encoding
modified miller
encoding
modified miller
encoding
fc = 13.56 MHz
bit rate (kbit/s)
fc / 128
fc / 64
fc / 32
fc / 16
card to reader (PN7462 card side
sub carrier load
modulation
sub carrier load
modulation
sub carrier load
modulation
sub carrier load
modulation
family receives data
from a card)
modulation
subcarrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
bit encoding
Manchester
encoding
BPSK
BPSK
BPSK
Figure 20 shows the data coding and framing according to ISO/IEC 14443 A.
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
odd
odd
parity
parity
parity
start bit is 1
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
even
parity
8-bit data
8-bit data
8-bit data
odd
odd
parity
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the frame
001aak585
Figure 20.ꢀData coding and framing according to ISO/IEC 14443 A card response
The internal CRC coprocessor calculates the CRC value based on the selected protocol.
In card mode for higher baudrates, the parity is automatically inverted as end of
communication indicator.
8.10.1.2 ISO/IEC14443 B functionality
The physical level of the communication is shown in Figure 21
(1)
ISO/IEC 14443 B
ISO/IEC 14443 B CARD
READER
(2)
001aal997
1. Reader to Card: NRZ; transfer speed 106 kbit/s to 848 kbit/s
2. Card to reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s
Figure 21.ꢀISO/IEC 14443 B read/write mode communication diagram
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The physical parameters are described in Table 12
Table 12.ꢀCommunication overview for ISO/IEC 14443 B reader/writer
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
reader to card (send
reader side
10 % ASK
10 % ASK
10 % ASK
10 % ASK
data from the PN7462 modulation
family to a card)
bit encoding
NRZ
NRZ
64/fc
NRZ
32/fc
NRZ
16/fc
fc = 13.56 MHz
bit rate [kbit/s]
128/fc
card to reader (PN7462 card side
sub carrier load
modulation
sub carrier load
modulation
sub carrier load
modulation
sub carrier load
modulation
family receives data
from a card)
modulation
sub carrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
bit encoding
BPSK
BPSK
BPSK
BPSK
8.10.1.3 FeliCa functionality
The FeliCa mode is a general reader/writer to card communication scheme, according to
the FeliCa specification. The communication on a physical level is shown in Figure 22.
1. PCD to PICC 8-30 % ASK
Manchester Coded,
baudrate 212 to 424 kbaud
FeliCa CARD
(PICC)
FeliCa READER
(PCD)
2. PICC to PCD, > Load modulation
Manchester Coded,
baudrate 212 to 424 kbaud
001aam271
Figure 22.ꢀFeliCa read/write communication diagram
The physical parameters are described in Table 13.
Table 13.ꢀCommunication overview for FeliCa reader/writer
Communication direction
Signal type
Transfer speed FeliCa
FeliCa higher transfer
speeds
212 kbit/s
424 kbit/s
reader to card (send data
from the PN7462 family to a
card)
reader side modulation
bit encoding
8 % to 30 % ASK
Manchester encoding
fc / 64
8 % to 30 % ASK
Manchester encoding
fc / 32
bit rate
fc = 13.56 MHz
card to reader (PN7462
family receives data from a
card)
card side modulation
bit encoding
load modulation
Manchester encoding
load modulation
Manchester encoding
Note: The PN7462 family does not manage FeliCa security aspects.
PN7462 family supports FeliCa multiple reception cycles.
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PayLoad
32 byte
XXX
Status
RFU
[15:13]
RFU
RFU [31:24]
RFU [23:16]
Len [4:0]
[7:5]
4 byte
aaa-021253
Figure 23.ꢀMultiple reception cycles - data format
8.10.1.4 ISO/IEC 15693 functionality
The physical level of the communication is shown in Figure 24.
(1)
ISO / IEC 15693
READER
ISO / IEC 15693
CARD
(2)
aaa-021138
1. Reader to Card: 1/256 and 1/4 encoding
2. Card to Reader: Manchester coding
Figure 24.ꢀISO/IEC 15693 read/write mode communication diagram
The physical parameters are described in Table 14.
Table 14.ꢀCommunication overview for ISO/IEC 15693 reader to label
Communication direction
Signal type
Transfer speed
fc / 8192 kbit/s
fc / 512 kbit/s
reader to label (send data
from the PN7462 family to a
card)
reader side modulation
10 % to 30 % ASK or
100 % ASK
10 % to 30 % ASK or 90 % to
100 % ASK
bit encoding
bit length
1/256
1/4
4.833 μs
302.08 μs
Table 15.ꢀCommunication overview for ISO/IEC 15693 label to reader
Communication
direction
Signal type
Transfer speed
6.62 kbit/s
13.24 kbit/s[1]
26.48 kbit/s
52.96 kbit/s
label to reader
card side
not supported
not supported
single (dual)
single sub carrier
(PN7462 family
receives data from a
card) fc = 13.56 MHz
modulation
sub carrier load
modulation ASK
load modulation ASK
bit length (μs)
bit encoding
-
-
-
-
-
-
37.76
18.88
Manchester coding
fc / 32
Manchester coding
fc / 32
subcarrier
frequency (MHz)
[1] Fast inventory (page) read command only (ICODE proprietary command).
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pulse
modulated
carrier
~9.44 µs
~18.88 µs
0 1 2 3 4
.
.
.
2
2
5
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2 2 2 2
5 5 5 5
2 3 4 5
~4,833 ms
001aam272
Figure 25.ꢀData coding according to ISO/IEC 15693 standard mode reader to label
8.10.1.5 ISO/IEC18000-3 mode 3 functionality
The ISO/IEC 18000-3 mode 3 is not described in this document. For a detailed
explanation of the protocol, refer to the ISO/IEC 18000-3 standard.
PN7462 family supports the following features:
• TARI = 9.44 μs or 18.88 μs
• Downlink: Four subcarrier pulse Manchester and two subcarrier pulse Manchester
• Subcarrier: 423 kHz (fc / 32) with DR = 0 kHz and 847 kHz (fc / 16) with DR = 1
8.10.1.6 NFCIP-1 modes
The NFCIP-1 communication differentiates between an active and a passive
communication mode.
• In active communication mode, both initiator and target use their own RF field to
transmit data
• In passive communication mode, the target answers to an initiator command in a load
modulation scheme. The initiator is active in terms of generating the RF field
• The initiator generates RF field at 13.56 MHz and starts the NFCIP-1 communication
• In passive communication mode, the target responds to initiator command in load
modulation scheme. In active communication mode, it uses a self-generated and self-
modulated RF field.
PN7462 family supports NFCIP-1 standard. It supports active and passive
communication mode at transfer speeds of 106 kbit/s, 212 kbit/s, and 424 kbit/s, as
defined in the NFCIP-1 standard.
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Initial command
host
host
NFC INITIATOR
NFC TARGET
1. initiator starts communication at
selected transfer speed
powered to
powered for
generate RF field
digital processing
response
host
host
NFC INITIATOR
NFC TARGET
2. target answers at
the same transfer speed
powered for digital
processing
powered to
generate RF field
001aan216
Figure 26.ꢀActive communication mode
Table 16.ꢀCommunication overview for active communication mode
Communication
direction
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
initiator to target
target to initiator
according to ISO/IEC 14443
A 100 % ASK, modified miller
coded
according to
FeliCa, 8-30 %
ASK Manchester
coded
according to
FeliCa, 8-30 %
ASK Manchester
coded
Note: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.
1. initiator starts communication
at selected transfer speed
host
host
NFC INITIATOR
NFC TARGET
2. targets answers using
load modulated data
at the same transfer speed
powered to
powered for
generate RF field
digital processing
001aan217
Figure 27.ꢀPassive communication mode
Table 17.ꢀCommunication overview for passive communication mode
Communication
direction
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
initiator to target
according to ISO/IEC
14443 A 100 % ASK,
modified miller coded
according to
FeliCa, 8-30 % ASK
Manchester coded
according to
FeliCa, 8-30 % ASK
Manchester coded
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Communication
direction
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
target to initiator
according to ISO/IEC
14443 A @106 kB
according to FeliCa, > according to FeliCa, >
12 % ASK Manchester 12 % ASK Manchester
modified miller coded
coded
coded
The NFCIP-1 protocol is managed in the PN7462 family customer application firmware.
Note: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.
ISO/IEC14443 A card operation mode
PN7462 family can be addressed as a ISO/IEC 14443 A card. It means that it can
generate an answer in a load modulation scheme according to the ISO/IEC 14443 A
interface description.
Note: PN7462 family components do not support a complete card protocol. The NFC
controller customer application firmware handles it.
The following table describes the physical layer of a ISO/IEC14443 A card mode:
Table 18.ꢀISO/IEC14443 A card operation mode
Communication direction
ISO/IEC 14443 A (transfer speed: 106 kbit per second)
reader/writer to PN7462 family
modulation on reader side
bit coding
100 % ASK
modified miller
128/fc
bit length
PN7462 family to reader/writer
modulation on PN7462
family side
sub carrier load modulation
subcarrier frequency
bit coding
fc / 16
Manchester coding
NFCIP-1 framing and coding
The NFCIP-1 framing and coding in active and passive communication mode is defined
in the NFCIP-1 standard.
PN7462 family supports the following data rates:
Table 19.ꢀFraming and coding overview
Transfer speed
106 kbit/s
Framing and coding
according to the ISO/IEC 14443 A/MIFARE scheme
according to the FeliCa scheme
according to the FeliCa scheme
212 kbit/s
424 kbit/s
NFCIP-1 protocol support
The NFCIP-1 protocol is not elaborated in this document. The PN7462 family component
does not implement any of the high-level protocol functions. These high-level protocol
functions are implemented in the microcontroller. For detailed explanation of the protocol,
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refer to the NFCIP-1 standard. However, the datalink layer is according to the following
policy:
• Speed shall not be changed while there is continuous data exchange in a transaction.
• Transaction includes initialization, anticollision methods, and data exchange (in a
continuous way means no interruption by another transaction).
In order not to disturb current infrastructure based on 13.56 MHz, the following general
rules to start NFCIP-1 communication are defined:
1. By default, NFCIP-1 device is in target mode. It means that its RF field is switched off.
2. The RF level detector is active.
3. Only if the application requires, the NFCIP-1 device switches to initiator mode.
4. An initiator shall only switch on its RF field if the RF level detector does not detect
external RF field during a time of TIDT
.
5. The initiator performs initialization according to the selected mode.
8.10.2 Contactless interface
8.10.2.1 Transmitter (TX)
The transmitter is able to drive an antenna circuit connected to outputs TX1 and TX2
with a 13.56 MHz carrier signal. The signal delivered on pins TX1 and pin TX2 is a 13.56
MHz carrier, modulated by an envelope signal for energy and data transmission. It can
be used to drive an antenna directly, using a few passive components for matching and
filtering. For a differential antenna configuration, either TX1 or TX2 can be configured to
put out an inverted clock.
100 % modulation and several levels of amplitude modulation on the carrier can be
performed to support 13.56 MHz carrier-based RF-reader/writer protocols. The standards
ISO/IEC14443 A and B, FeliCa, and ISO/IEC18092 define the protocols.
The PN7462 family embeds an overshoot and undershoot protection. It is used to
configure additional signals on the transmitter output, for controlling the signal shape at
the antenna output.
TVDD
envelope
hs_gate
M2
clk_highside
clk_lowside
TX1
TVDD
ls_gate<14:0>
M1<
PRE-DRIVERS
aaa-021254
Figure 28.ꢀPN7462 family output driver
8.10.2.2 Receiver (RX)
In reader mode, the response of the PICC device is coupled from the PCB antenna to
the differential input RXP/RXN. The reader mode receiver extracts this signal by first
removing the carrier in passive mixers (direct conversion for I and Q). It then filters
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and amplifies the baseband signal before converting to digital values. The conversion
to digital values is done with two separate ADCs, for I and Q channels. Both I and Q
channels have a differential structure, which improves the signal quality.
The I/Q mixer mixes the differential input RF-signal down to the baseband. The mixer has
a bandwidth of 2 MHz.
The down-mixed differential RX input signals are passed to the BBA and a band-pass
filter. For considering all the protocols (type A/B, FeliCa), the high-pass cut-off frequency
of BBA is configured between 45 kHz and 250 kHz. The configuration is done in four
different steps. The low-pass cut-off frequency is greater than 2 MHz.
The output of band-pass filter is further amplified with a gain factor which is configurable
between 30 dB and 60 dB. The baseband amplifier (BBA)/ADC I-channel and Q-channel
can be enabled separately. It is required for ADC-based card mode functionality as only
the I-channel is used in this case.
BBA
RXP
DATA
I-CLK
AGC
MIX
CLK
VMID
Q-CLK
BBA
DATA
RXN
aaa-021388
Figure 29.ꢀReceiver block diagram
VMID
A resistive divider between AVDD and GND generates VMID. The resistive divider is
connected to the VMID pin. An external blocking capacitor of typical value 100 nF is
connected.
Automatic Gain Control (AGC)
The contactless interface AGC is used to control the amplitude of 13.56 MHz sine-wave
input signal received. The signal is received at the antenna connected between the pins
RXP and RXN. A comparator is used to compare the peak value of the input signal with a
reference voltage.
A voltage divider circuit is used to generate the reference voltage. An external resistor
(typically 3.3 kΩ) is connected to the RX input, which forms a voltage divider with an on-
chip variable resistor. The voltage divider circuit so formed has a 10-bit resolution.
Note: The comparator monitors the RXP signal only.
By varying the on-chip resistor, the amplitude of the input signal can be modified. The
value of on-chip resistor is increased or decreased, depending on the output of the
sampled comparator. The on-chip resistor value is adjusted until the peak of the input
signal matches the reference voltage. Thus, the AGC circuit automatically controls the
amplitude of the RX input.
The internal amplitude controlling resistor in the AGC has a default value of 10 KΩ. It
means that, when the resistor control bits in AGC_VALUE_REG <9:0> are all 0, the
resistance is 10 KΩ. As the control bits are increased, resistors are switched in parallel to
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the 10 KΩ resistor. It lowers the resultant resistance value to 5 kΩ (AGC_VALUE_REG
<9:0>, all bits set to 1).
Mode detector
The mode detector is a functional block of the PN7462 family which senses for an RF
field generated by another device. The mode detector facilitates to distinguish between
type Aꢁand FeliCa target mode. The host responds depending on the recognized
protocol generated by an initiator peer device.
Note: The PN7462 family emulates type A cards and peer-to-peer active target modes
according to ISO / IEC18092.
8.10.3 Low-Power Card Detection (LPCD)
The low-power card detection is an energy saving feature of the PN7462 family. It
detects the presence of a card without starting a communication. Communication
requires more energy to power the card and takes time, increasing the energy
consumption.
It is based on antenna detuning detection. When a card comes close to the reader, it
affects the antenna tuning, which is detected by PN7462 family.
The sensitivity can be varied for adjusting to various environment and applications
constraints.
Remark: Reader antenna detuning may have multiple sources such as cards and metal
near the antenna. Hence it is important to adjust the sensitivity with care to optimize the
detection and power consumption. As the generated field is limited, distance for card
detection might be reduced compared to normal reader operation. Performances depend
on the antenna and the sensitivity used.
8.10.4 Active Load Modulation (ALM)
When PN7462 family is used in card emulation mode or P2P passive target mode, it
modulates the field emitted by the external reader or NFC passive initiator.
(1)
PN7462 family
CARD TYPE A EMULATION
(2)
OR
P2P PASSIVE TARGET
aaa-021139
1. Type A reader or NFC passive initiator generate the RF and sends commands
2. PN7462 family modulates the field of reader for sending its answer
Figure 30.ꢀCommunication in card emulation of NFC passive target
To modulate the field, PN7462 family offers two possibilities:
• Passive Load Modulation (PLM): The PN7462 family modifies the antenna
characteristics, which are detected by the reader through antenna coupling.
• Active Load Modulation (ALM): The PN7462 family generates a small field, in phase
opposition with the field emitted by the reader. This modulation is detected by the
reader reception stage.
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The modulation type to use depends on the external reader and the antenna of PN7462
family and the application.
8.10.5 Dynamic Power Control (DPC)
The PN7462 family supports the Dynamic Power Control (DPC) feature.
A lookup table is used to configure the output voltage and to control the transmitter
current. In addition to the control of the transmitter current, wave shaping settings can be
controlled as well, depending on the selected protocol and the measured antenna load.
8.10.5.1 RF output control
The DPC controls the RF output current and output voltage depending on the loading
condition of the antenna.
8.10.5.2 Adaptive Waveform Control (AWC)
The DPC includes the Adaptive Waveform Control (AWC) feature.
Depending on the level of detected detuning on the antenna, RF wave shaping related
register settings can be automatically updated, according to the selected protocol. A
lookup table is used to configure the modulation index, the rise time and the fall time.
8.11 Timers
The PN7462 family includes two 12-bit general-purpose timers (on LFO clock domain)
with match capabilities. It also includes two 32-bit general-purpose timers (on HFO clock
domain) and a Watchdog Timer (WDT).
The timers and WDT can be configured through software via a 32-bit APB slave
interface.
Table 20.ꢀTimer characteristics
Name
Clock
source
Frequency Counter
length
Resolution Maximum
delay
Chaining
Timer 0
Timer 1
Timer 2
Timer 3
Watchdog
LFO/2
LFO/2
HFO
182.5 kHz
182.5 kHz
20 MHz
12 bit
12 bit
32 bit
32 bit
10 bit
300 μs
300 μs
50 ns
1.2 s
1.2 s
214 s
214 s
22 s
No
Yes
No
No
No
HFO
20 MHz
50 ns
LFO/128
2.85 kHz
21.5 ms
8.11.1 Features of timer 0 and timer 1
• 12-bit counters
• One match register per timer, no capture registers and capture trigger pins are needed
• One common output line gathering the four timers (Timer 0, Timer 1, Timer 2, and
Timer 3)
• Interrupts
• Timer 0 and timer 1 can be concatenated (multiplied)
• Timer 0 and timer 1 have two count modes: single-shot or free-running
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• Timer 0 and timer 1 timeout interrupts can be individually masked
• Timer 0 and timer 1 clock source is LFO clock (LFO/2 = 182.5 kHz)
Remark: The timers are dedicated for RF communication.
8.11.2 Features of timer 2 and timer 3
• 32-bit counters
• 1 match register per timer, no capture registers and capture trigger pins are needed
• 1 common output line gathering four timers (Timer 0, Timer 1, Timer 2, and Timer 3)
• Interrupts
• Timer 2 and timer 3 have two count modes: single-shot and free-running
• Timer 2 and timer 3 timeout interrupts can be individually masked
• Timer 2 and timer 3 clock source is the system clock
8.12 System tick timer
The PN7462 family microcontroller includes a system tick timer (SYSTICK) that
generates a dedicated SYSTICK exception at a fixed time interval (10 ms).
8.13 Watchdog timer
If the microcontroller enters an erroneous state, the watchdog timer resets the
microcontroller. When the watchdog timer is enabled, if the user program fails to
"feed" (reload) the watchdog timer within a predetermined time, it generates a system
reset.
The watchdog timer can be enabled through software. If there is a watchdog timeout
leading to a system reset, the timer is disabled automatically.
• 10-bit counter
• Based on a 2.85 kHz clock
• Triggers an interrupt when a predefined counter value is reached
• Connected to the ARM subsystem NMI (non-maskable interrupt)
• If the watchdog timer is not periodically loaded, it resets PN7462 family
8.14 Clocks
The PN7462 family clocks are based on the following clock sources:
• 27.12 MHz external quartz
• 27.12 MHz crystal oscillator
• Internal oscillator: 20 MHz High Frequency Oscillator (HFO)
• Internal oscillator: 365 kHz Low Frequency Oscillator (LFO)
• Internal PLL at 48 MHz for the USB interface
Figure 31 indicates the clocks used by each IP.
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clif_pll_in_sel
dk_input_buffer
PLL I/P
BUFFER
XTAL1
00
01
10
11
clk_xtal
tie `'0''
tie `'0''
pll_bypass
pll_clkout
pll_clkin
CLIF PLL
10
00
pll_clkout2
CLIF_DIG
pll_clkout2
pll_clkin
PLL_INPUT_BUFFER_BYPASS
XTAL_SEL_EXTERNAL_CLOCK
11
01
CLIF_PLL_REF_CLK_SELECT[1:0]
clk_pll_27m12
CLIF_ANA
PCR
XTAL2
clk_xtal
XTAL
clk_pll_27m12
usb_pll_clkin
1
0
clk_ip_27m12
CLIF_PLL_CLOCK_SELECT[1:0]
usb_pll_in_sel
tie `'0''
PCR_CLK_CFG2.EXT_CLK_SEL
11
tie `'0''
clk_xtal
10 usb_pll_clkin
clk_usb_48 MHz
USB PLL
00
01
00
tie `'0''
clk_input_buffer
10
01
11
usb_pll_clkout_div2
/2
tie `'0''
USB_PLL_REF_CLK_SELECT[1:0]
USB_PLL_CLKOUT_SELECT[1:0]
usb_pll_clkout
aaa-021248
Figure 31.ꢀClocks and IP overview
8.14.1 Quartz oscillator (27.12 MHz)
The 27.12 MHz quartz oscillator is used as a reference for all operations where the
stability of the clock frequency is important for reliability. It includes contactless interface,
SPI and I2C master interfaces, USB PLL for the USB interface, and HSUART.
Regular and low-power crystals can be used. Figure 32 shows the circuit for generating
stable clock frequency. The quartz and trimming capacitors are off-chip.
PN7462 family
XTAL1
crystal
XTAL2
27.12 MHz
C
C
aaa-021140
Figure 32.ꢀCrystal oscillator connection
Table 21 describes the levels of accuracy and stability required on the crystal.
Table 21.ꢀCrystal requirements
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fxtal
crystal frequency
ISO/IEC and FCC
compliancy
-
27.12
-
MHz
[1]
Δfxtal
ESR
crystal frequency accuracy
equivalent series resistance
-50
-
-
+50
100
ppm
Ω
50
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Symbol
Parameter
Conditions
Min
Typ
10
-
Max
-
Unit
pF
CL
load capacitance
drive power
-
-
Pdrive
100
μW
[1] This requirement is according to FCC regulations requirements. The frequency should be +/- 14 kHz to meet ISO/IEC
14443 and ISO/IEC 18092.
8.14.2 USB PLL
The PN7462 family integrates a dedicated PLL to generate a low-noise 48 MHz clock, by
using the 27.12 MHz from the external crystal. The 48 MHz clock generated is used as
the USB main clock.
Following are the USB PLL features:
• Low-skew, peak-to-peak cycle-to-cycle jitter, 48 MHz output clock
• Low power in active mode, low power-down current
• On-chip loop filter, external RC components not needed
8.14.3 High Frequency Oscillator (HFO)
The PN7462 family has an internal low-power High Frequency Oscillator (HFO) that
generates a 20 MHz clock. The HFO is used to generate the system clock. The system
clock default value is 20 MHz, and it can be configured to 10 MHz and 5 MHz for
reducing power consumption.
8.14.4 Low Frequency Oscillator (LFO)
The PN7462 family has an internal low-power Low Frequency Oscillator (LFO) that
generates a 365 kHz clock. The LFO is used by EEPROM, POR sequencer, contactless
interface, timers, and watchdog.
8.14.5 Clock configuration and clock gating
In order to reduce the overall power consumption, the PN7462 family facilitates
adjustment of system clock. It integrates clock gating mechanisms.
The system clock can be configured to the following values: 20 MHz, 10 MHz, and 5
MHz.
The clock of the following blocks can be activated or deactivated, depending on the
peripherals used:
• Contactless interface
• Contact interface
• Host interfaces
• I2C master interface
• SPI master interface
• CRC engine
• Timers
• Random generator
• System clock
• EEPROM
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• Flash memory
8.15 Power management
8.15.1 Power supply sources
The PN7462 family is powered using the following supply inputs:
• VBUS: main supply voltage for internal analog modules, digital logic, and memories
• VBUSP: supply voltage for the contact interface
• TVDD_IN: supply for the contactless interface
• PVDD_IN: pad voltage reference and supply of the host interface (HSU, USB, I2C, and
SPI) and the GPIOs
• PVDD_M_IN: pad voltage reference and supply for the master interface (SPI and I2C)
• DVDD: supply for the internal digital blocks
8.15.2 PN7462 Power Management Unit (PMU)
The integrated Power Management Unit (PMU) provides supply for internal analog
modules, internal digital logic and memories, pads. It also provides supply voltages for
the contactless and contact interface.
It automatically adjusts internal regulators to minimize power consumption during all
possible power states.
The power management unit embeds a mechanism to prevent the IC from overheat,
overconsumption, or overloading the DC-to-DC converter:
• TXLDO 5 V monitoring
• VCC current limiter
• DC-to-DC converter current overload
• SCVDD current overload
• Temperature sensor
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VUP
SC_LDO
VCC_LDO
VBUSP
VCC
DC-to-DC
converter
DVDD
Digital logic and memories
internal analog blocks
mandatory
VDD
MILDO
VBUS
PVDD_LDO
PVDD_OUT
optional
PVDD_IN
pad supply
PVDD_M_IN
master interface pads
TX_LDO
VUP_TX
TVDD_OUT
TVDD_IN
RF transmitter
aaa-021141
Figure 33.ꢀPN7462 LDOs and power pins overview
PN7462 embeds five Low Drop-Out regulators (LDO) for ensuring the stability of power
supply, while the application is running.
• MLDO (main LDO): It provides 1.8 V supply for internal analog, digital and memory
modules
• TXLDO: This LDO can be used to supply the RF transmitter
• PVDD_LDO: PVDD_LDO provides 3.3 V that can be used for all pads supply
• SCLDO: This LDO provides a 2.4 V output to be used for contact card supply. The
main aim is to be able to address class B operation when the voltage available is
below 3.9 V. It is achieved by providing a stable input voltage to the internal DC-to-DC
converter.
• VCC_LDO: the VCC_LDO provides the supply for the contact smart card
Some are used while some are optional, like the TX_LDO which is proposed for the RF
interface. It is up to the application designer to decide whether LDOs should be used.
8.15.2.1 Main LDO
The Main LDO (MLDO) provides a 1.8 V supply for all internal, digital and memory
modules. It takes input from VBUS. MLDO includes a current limiter that avoids damage
to the output transistors.
Output supply is available on VDD pin which must be connected externally to the DVDD
pin.
Following are the main LDO features:
• Main Low-Drop-Out (MLDO) voltage regulator powered by VBUS (external supply)
• Current limiter to avoid damaging the output transistors
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8.15.2.2 PVDD_LDO
The PVDD_LDO provides 3.3 V supply, that can be used for all digital pads. It may also
be used to provide 3.3 V power to external components, avoiding an external LDO. It is
supplied by VBUS, and requires a minimum voltage of 4 V to be functional. It delivers a
maximum of 30 mA.
The output pin for PVDD_LDO is PVDD_OUT.
PVDD_LDO is used to provide the necessary supply to PVDD_IN and PVDD_M_IN (pad
supply for master interfaces).
When an external supply is used, PVDD_OUT must be connected to the ground. When
the LDO output is connected to the ground, the chip switches off the PVDD_LDO.
The PVDD_LDO has a low-power mode, which is used automatically when the chip is in
standby mode or suspend mode. It facilitates supply to HOST pads and GPIOS, and to
detect wake-up signals coming from these interfaces.
Following are the PVDD_LDO features:
• Low-Drop-Out voltage regulator powered by VDDP(VBUS) (external supply)
• Supports soft-start mode to limit inrush current during the initial charge of the external
capacitance when the LDO is powered up
• Current limiter to avoid damaging the output transistors
Note: When PVDD_LDO is used, there must not be any load current drawn from
PVDD_LDO during the soft start of the PVDD_LDO.
8.15.2.3 Contact interface - SCLDO LDO
The SCLDO provides a regulated voltage to the DC-to-DC converter, to enable class B
operation when VDDP(VBUS) is in between 2.7 V to 3.9 V.
Following are the contact interface features:
• Current limiter for short circuit protection
• Supports soft-start mode to limit the inrush current during the initial charge of the
external capacitance when the LDO is powered up
8.15.2.4 Contact interface DC-to-DC converter
The PN7462 includes a DC-to-DC converter that supports class A and class B cards,
when the input voltage VDDP(VBUSP) is not sufficient.
The DC-to-DC converter is a capacitance voltage doubler. It takes power from the
SCLDO. The DC-to-DC converter can be bypassed. Its output (VUP) is regulated
between 3.3 V to 5.5 V.
The DC-to-DC converter can work in the following modes:
• Follower mode: This mode is used when VDDP(VBUSP) is high enough to provide the
desired power to the VCC LDO
• Doubler mode: This mode is used when VDDP(VBUSP) is not high enough to supply the
requested VCC output
The doubler mode is used in the following conditions:
• Class A cards support
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• Class B cards support, when VDDP(VBUSP) is less than 3.9 V
For class C cards, the DC-to-DC converter is always in a follower mode.
An external capacitor (470 nF) should be connected between SAM and SAP pins, to
ensure the functioning of the DC-to-DC converter.
Table 22.ꢀSCLDO and DC-to-DC converter modes
Supported card VDDP(VBUSP)
SCLCO mode
DC-to-DC converter
mode
Class A
Class B
Class B
Class C
> 3 V
follower mode
doubler mode
doubler mode
follower mode
follower mode
2.7 V < VDDP(VBUSP) < 3.9 V LDO mode
> 3.9 V
> 2.7 V
follower mode
follower mode
8.15.2.5 VCC LDO
The VCC LDO supplies contact interface supply VCC
.
Following are the VCC LDO features:
• Low drop-out voltage regulator
• Current limiter for chip and card protection
• Automatic deactivation in case of overload
8.15.2.6 TXLDO
The PN7462 family consists of an internal transmitter supply LDO. The TXLDO can be
used to maintain a constant output voltage for the RF interface.
The TXLDO is designed to protect the chip from voltage ripple introduced by the power
supply on the pin VUP_TX. It is powered through the pin VUP_TX.
The programmable output voltages are: 3.0 V, 3.3 V, 3.6 V, 4.5 V, and 4.75 V.
For a given output voltage, VUP_TX shall always be higher than 0.3 V. In other words,
to supply a 3 V output, the minimum voltage to be applied on VUP_TX is 3.3 V. If the
voltage is not sufficient, then the voltage at the pin TVDD_OUT follows the voltage at the
pin VUP_TX, lowered of 0.3 V.
When it is not used, TVDD_OUT shall be connected to TVDD_IN, and TX_LDO shall be
turned off.
Following are the TXLDO features:
• Low-Drop-Out (TXLDO) voltage regulator
• Current load up to 180 mA
• Supports soft-start mode to limit inrush current during the initial charge of the external
capacitance
• Current limiter to avoid damaging the output transistors
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8.15.3 PN736X Power Management Unit (PMU)
The integrated Power Management Unit (PMU) provides supply for internal analog
modules, internal digital logic and memories, pads. It also provides supply voltages for
the contactless interface.
It automatically adjusts internal regulators to minimize power consumption during all
possible power states.
The power management unit embeds a mechanism to prevent the IC from overheat,
overconsumption, or overloading the DC-to-DC converter:
• TXLDO 5 V monitoring
• Temperature sensor
DVDD
Digital logic and memories
internal analog blocks
mandatory
MILDO
VBUS
VDD
PVDD_LDO
PVDD_OUT
PVDD_IN
optional
pad supply
PVDD_M_IN
master interface pads
TX_LDO
VUP_TX
TVDD_OUT
TVDD_IN
RF transmitter
aaa-025627
Figure 34.ꢀPN736X LDOs and power pins overview
PN736X embeds three Low Drop-Out regulators (LDO) for ensuring the stability of power
supply, while the application is running.
• MLDO (main LDO): It provides 1.8 V supply for internal analog, digital and memory
modules
• TXLDO: This LDO can be used to supply the RF transmitter
• PVDD_LDO: PVDD_LDO provides 3.3 V that can be used for all pads supply
Some are used while some are optional, like the TX_LDO which is proposed for the RF
interface. It is up to the application designer to decide whether LDOs should be used.
8.15.3.1 Main LDO
The Main LDO (MLDO) provides a 1.8 V supply for all internal, digital and memory
modules. It takes input from VBUS. MLDO includes a current limiter that avoids damage
to the output transistors.
Output supply is available on VDD pin which must be connected externally to the DVDD
pin.
Following are the main LDO features:
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• Main Low-Drop-Out (MLDO) voltage regulator powered by VBUS (external supply)
• Current limiter to avoid damaging the output transistors
8.15.3.2 PVDD_LDO
The PVDD_LDO provides 3.3 V supply, that can be used for all digital pads. It may also
be used to provide 3.3 V power to external components, avoiding an external LDO. It is
supplied by VBUS, and requires a minimum voltage of 4 V to be functional. It delivers a
maximum of 30 mA.
The output pin for PVDD_LDO is PVDD_OUT.
PVDD_LDO is used to provide the necessary supply to PVDD_IN and PVDD_M_IN (pad
supply for master interfaces).
When an external supply is used, PVDD_OUT must be connected to the ground. When
the LDO output is connected to the ground, the chip switches off the PVDD_LDO.
The PVDD_LDO has a low-power mode, which is used automatically when the chip is in
standby mode or suspend mode. It facilitates supply to HOST pads and GPIOS, and to
detect wake-up signals coming from these interfaces.
Following are the PVDD_LDO features:
• Low-Drop-Out voltage regulator powered by VDDP(VBUS) (external supply)
• Supports soft-start mode to limit inrush current during the initial charge of the external
capacitance when the LDO is powered up
• Current limiter to avoid damaging the output transistors
Note: When PVDD_LDO is used, there must not be any load current drawn from
PVDD_LDO during the soft start of the PVDD_LDO.
8.15.3.3 TXLDO
The PN7462 family consists of an internal transmitter supply LDO. The TXLDO can be
used to maintain a constant output voltage for the RF interface.
The TXLDO is designed to protect the chip from voltage ripple introduced by the power
supply on the pin VUP_TX. It is powered through the pin VUP_TX.
The programmable output voltages are: 3.0 V, 3.3 V, 3.6 V, 4.5 V, and 4.75 V.
For a given output voltage, VUP_TX shall always be higher than 0.3 V. In other words,
to supply a 3 V output, the minimum voltage to be applied on VUP_TX is 3.3 V. If the
voltage is not sufficient, then the voltage at the pin TVDD_OUT follows the voltage at the
pin VUP_TX, lowered of 0.3 V.
When it is not used, TVDD_OUT shall be connected to TVDD_IN, and TX_LDO shall be
turned off.
Following are the TXLDO features:
• Low-Drop-Out (TXLDO) voltage regulator
• Current load up to 180 mA
• Supports soft-start mode to limit inrush current during the initial charge of the external
capacitance
• Current limiter to avoid damaging the output transistors
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8.15.4 Power modes
The PN7462 family offers four different power modes, that enable the user to optimize its
energy consumption. They are:
• Hard power-down mode
• Standby mode
• USB suspend mode
• Active mode
8.15.4.1 Active mode
In active mode, all functionalities are available and all IPs can be accessed. It is possible
to configure the various clocks (IP clock, system clock) using register settings so that
chip consumption is reduced. If IPs are not used, they can be disabled.
8.15.4.2 Standby mode
In standby mode, only a reduced part of the digital and the analog is active. It reduces
the chip power consumption. The possible wake-up sources are still powered.
The LFO clock is used to lower the energy needs.
Active part in standby mode: Main LDO is active, in a low-power mode, plus all
configured wake-up sources.
Depending on the application requirements, it is possible to configure PVDD_LDO in
active mode, low-power mode or shut down mode when PN7462 family is going to
standby mode. PVDD_LDO is active in a low-power mode by default.
Entering in standby mode: The application code triggers standby mode. Before
entering in standby mode, the PN7462 manages the deactivation of the contact card.
The PN7462 family has two internal temperature sensors. If these sensors detect an
overheat, the chip is put into standby mode by the application firmware. It leaves the
standby mode when both temperature sensors indicate that the temperature has come
below the configured limit.
Limitations: Standby mode is not possible in the following cases:
• A host communication is in progress.
• A wake-up condition is fulfilled. For example, external RF field presence is a wake-up
source, and a field is detected.
• The RF field detector is a possible wake-up source, and the RF field detector is
disabled.
• PVDD is not present.
8.15.4.3 Suspend mode
In suspend mode, clock sources are stopped except LFO. It reduces the chip power
consumption.
Entering in suspend mode: An interrupt indicates to the application firmware when no
activity has been detected on the USB port for more that 3 ms. The application code
triggers the suspend mode.
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Before entering in suspend mode, the PN7462 manages automatically, the deactivation
of the contact card.
Limitations: Suspend mode is prevented in the following cases:
• A host communication is in progress.
• A wake-up condition is fulfilled. For example, external RF field presence is a wake-up
source, and a field is detected.
• The RF field detector is a possible wake-up source, and the RF field detector is
disabled.
• No voltage at pin PVDD.
8.15.4.4 Wake-up from standby mode and suspend mode
PN7462 family can be woken-up from standby mode, and suspend mode, using the
following means:
• Host Interface: SPI, HSUART, I2C, and USB if already selected before standby mode
(SPI, HSUART, and I2C) or suspend mode (USB).
• RF field detection (presence of a reader or an NFC device in reader mode or P2P
initiator)
• GPIO
• Contact card insertion, contact card removal (PN7462AUHN only)
• Interrupt generated on the auxiliary UART interface, through the interrupt pin
(PN7462AUHN and PN7462AUEV only)
• Wake-up counter, for example to timely check for the presence of any contact or
contactless card
• Current overconsumption on the PVDD_OUT, voltage above 5 V on TVDD_IN
• Temperature sensor: When the chip goes in to standby mode because of over-heating,
and when the temperature goes below the sensor configured value, it wakes-up
automatically. Each temperature sensor can be configured separately.
It is possible to configure the sources as enabled or disabled.
8.15.4.5 Hard Power-Down (HPD) mode
The Hard Power-Down (HPD) reduces the chip power consumption, by powering down
most of its blocks. All clocks and LDOs are turned off, except the main LDO which is set
in low-power mode.
Entering in HPD mode: If the RST_N pin is set to low, the NFC controller enters in to
Hard Power Down (HPD) mode. It also enters in to HPD mode if the VDDP(VBUS) goes
below the critical voltage necessary for the chip to work (2.3 V) and the auto HPD feature
is enabled.
Exiting the HPD mode: The NFC controller leaves the HPD mode, when both RST_N
pin is set to high level and the VDDP(VBUS) voltage is above 2.3 V.
8.15.5 Voltage monitoring
The voltage monitoring mode detects whether the voltage is within the operational
conditions to enable a proper operation of the RF interface or the contact interface. The
following power supplies are monitored: VBUS (two voltage monitors), VBUS_P (one
voltage monitor).
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Section 9.1.2 discusses about the minimum voltages necessary for contactless interface
operation and Section 9.1.3 for the contact interface operation.
Table 23.ꢀThreshold configuration for voltage monitor
Voltage monitor
VBUSMON1
VBUSMON2
VBUSP
Threshold 1
2.3 V
Threshold 2
2.7 V
Threshold 3
n.a.[1]
n.a.[1]
2.7 V
4.0 V
2.7 V
3.0 V
3.9 V
[1] n.a. means not applicable.
8.15.5.1 VBUS monitor
The PN7462 family includes up to two levels (2.3 V or 2.7 V) for monitoring the voltage
on the VBUS pin. If this voltage falls below one of the selected levels, the BOD asserts
an interrupt signal to the PCR. This signal may be enabled for interrupt in the interrupt
enable register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor
the signal by reading a dedicated status register. Two threshold levels (2.3 V or 2.7 V)
can be selected to cause a forced Hard Power-Down (HPD) of chip.
8.15.5.2 VBUSP monitor
The PN7462 family includes three levels (2.7 V, 3.0 V, and 3.9 V) for monitoring the
voltage on the VBUSP pin.
In addition to the above, the following applies to products with contact interface: When
the voltage falls below the selected threshold value, and CT automatic deactivation
is enabled in the PCR system register, hardware automatically de-activates the CT
interface. An interrupt signal is also asserted to the PCR. This signal can be enabled for
interrupt in the interrupt enable register in the PCR, to cause a CPU interrupt. Software
must check VBUSP monitor levels by reading dedicated status registers before starting
card activation sequence.
8.15.5.3 PVDD LDO supply monitor
The PN7462 family includes up to two levels (VBUSMON2: 2.7 V or 4.0 V) for monitoring
the voltage on the PVDD LDO input supply. If supply voltage is 4.0 V or above, PVDD
LDO can be enabled. The software has to check whether the voltage is sufficient before
enabling the LDO.
8.15.6 Temperature sensor
The PN7462 family power management unit provides temperature sensors, associated
to the TX_LDO and the contact interface DC-to-DC converter. It detects problems that
would result in high power consumption and heating, which could damage the chip and
the user device.
Triggering levels are configurable. Following temperatures can be chosen: 135 °C, 130
°C, 125 °C, and 120 °C. By default, the temperature sensor is set to 120 °C.
When one of the temperature sensors detects an increase in temperature above the
configured level, an interrupt is generated. The application can then decide to go
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into standby or suspend mode. The PN registers indicate which temperature sensor
generated the interrupt.
When the temperature goes below the configured threshold temperature, the NFC
controller wakes up automatically.
8.16 System control
8.16.1 Reset
PN7462 family has six possible sources for reset. The list of sources is described in
Table 21.
Table 24.ꢀReset sources
Source
Description
software - PCR
software - ARM
I2C interface
watchdog
soft reset from the PCR peripheral
software reset form the ARM processor
I2C Standard 3.0 defines a method to reset the chip via an I2C command[1]
reset the chip if the watchdog threshold is not periodically reloaded
power-on reset sequence; if the voltage is above 2.3 V, reset the chip
VBUS voltage
[1] This feature can be disabled.
The watchdog reset, I2C reset and soft resets from PCR and ARM processor resets the
chip except the PCR and the ARM debug interface. The Power-On Reset (POR) resets
the complete chip including the PCR and ARM debug interface.
Upon reset, the processor executes the first instruction at address 0, which is initially the
reset vector mapped from the boot block. At that point, all the processor and peripheral
registers are initialized to predetermined values.
8.16.2 Brown-Out Detection (BOD)
The PN7462 family includes up to two levels for monitoring the voltage on the VBUS pin.
If this voltage falls below one of the selected voltages (2.3 V or 2.7 V), the BOD asserts
an interrupt signal to the PCR. This signal can be enabled for interrupt in the interrupt
enable register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor
the signal by reading a dedicated status register. Two threshold levels (2.3 V and 2.7 V)
can be selected to cause a forced Hard Power-Down (HPD) of the chip.
8.16.3 APB interface and AHB-Lite
All APB peripherals are connected to one APB bus.
The AHB-Lite connects the AHB masters. The AHB masters include the CPU bus of the
ARM Cortex-M0, host interface, contactless interface, SPI interface to the flash memory.
It also includes EEPROM memory, SRAM, ROM, and AHB to APB bridge.
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8.16.4 External interrupts
PN7462 family enables the use of 12 GPIOs as edge or level sensitive inputs (GPIO1 to
GPIO12).
8.17 SWD debug interface
The Cortex-M0 processor-based devices use serial wire ARM CoreSightTM Debug
technology. The PN7462 family is configured to support four break points and two watch
points.
The SWD interface can be disabled for having code (or data) read/write access
protection. A dedicated SWD disable bit is available in the protected area of the
EEPROM memory. Once the SWD interface is disabled, it is not possible to enable it
anymore.
8.17.1 SWD interface features
• Run control of the processor allowing to start and stop programs
• Single step one source or assembler line
• Set breakpoints while the processor is running
• Read/write memory contents and peripheral registers on-the-fly
• "printf" like debug messages through the SWD interface
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9 Application design-in information
9.1 Power supply connection
The following table indicates the power sources for all the PN7462 family power inputs.
Table 25.ꢀPower supply connection
Power inputs Power sources
Comment
VBUS
external source
chosen according to the expected performances
(contact interface and Class A/B/C support, RF
power when TX_LDO is used, global power
consumption)
VBUSP
external source; connected to
VBUS
VBUSP is connected to VBUS, with the addition
of a decoupling capacitor
TVDD_IN
PVDD_IN
external supply or using the
TX_LDO
external supply can be used (up to 5.5 V) to
increase RF power
external supply or using
PVDD_LDO
PVDD_LDO can be used, when VDDP(VBUS) > 4
V. It makes a regulated 3.3 V supply available
to GPIO and host interface pads, without the
addition of an external LDO
for 1.8 V, external supply is used
PVDD_M_IN external supply or using
PVDD_LDO
PVDD_LDO can be used, when VDDP(VBUS) > 4
V. It makes a regulated 3.3 V supply available
to GPIO and host interface pads, without the
addition of an external LDO
external supply is used for 1.8 V
DVDD
connected to the VDD output
VDD provides 1.8 V stabilized supply, out of the
MAIN_LDO
1. When external supply and PVDD_OUT are not used, PVDD_OUT must be connected
to the ground, with a ground resistance of less than 10 Ω.
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9.1.1 Powering up the microcontroller
(1)
VBUS
V
,
DDP(VBUS)
GND
VBUSP
I
DDP(VBUS)
TVSS
GNDC
GNDP
PN7462 family
VDD
DVDD
(2)
(3)
VBUS
VBUS
V
I
,
V
,
DDP(VBUS)
DDP(VBUS)
DDP(VBUS)
I
DDP(VBUS)
VBUSP
VBUSP
PVDD_OUT
PVDD_OUT
PN7462 family
PN7462 family
PVDD_IN
PVDD_IN
external supply
PVDD_M_IN
PVDD_M_IN
aaa-025630
1. Powering up the microcontroller and the digital blocks (DVDD).
2. Two possibilities for powering the pad interfaces (PVDD_IN and PVDD_M_IN (3)).
Remark: The capacitance must be chosen so that the capacitance value is correct at 5 V
Figure 35.ꢀPowering up the microcontroller
The schematics in Figure 35 describe the power supply of the chip (VDDP(VBUS)),
including the digital blocks supply (DVDD). It indicates two possibilities to supply the
pads, using the internal LDO, or using an external supply. The internal LDO requires that
VDDP(VBUS) > 4 V. It avoids the requirement of a separate LDO when VDDP(VBUS) has a
sufficient voltage.
Power supply is available to pads through PVDD_IN (host interface). Similarly, power
supply is available to master interface pads through PVDD_M_IN. When PVVD _LDO is
used, maximum total current available from PVDD_OUT for the pads supply is 30 mA.
When an external source is used for PVDD_IN and PVDD_M_IN, PVDD_OUT must be
connected to the ground, with a ground resistance of less than 10 Ω.
9.1.2 Powering up the contactless interface
Powering of contactless interface is done though TVDD_IN. Internal LDO (TXLDO) or
external supply can be used.
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(1)
(2)
VBUS
VBUS
PN7462 family
supply
PN7462 family
supply
TX2
TX2
TX1
antenna
supply
antenna
supply
VUP_TX
VUP_TX
TX1
PN7462 family
PN7462 family
TVDD_OUT
TVDD_IN
TVDD_OUT
TVDD_IN
TVSS
TVSS
aaa-021143
The capacitance value must be chosen so that the capacitance value is correct at 5 V.
1. Using TXLDO
2. Without using TXLDO
Figure 36.ꢀPowering up the contactless interface using a single power supply
(1)
(2)
VBUS
VBUS
PN7462 family
supply
PN7462 family
supply
TX2
TX1
TX2
TX1
antenna
supply
antenna
supply
PN7462 family
RF transmitter
supply
VUP_TX
VUP_TX
PN7462 family
PN7462 family
TVDD_OUT
TVDD_IN
TVDD_OUT
TVDD_IN
PN7462 family
RF transmitter
supply
TVSS
TVSS
aaa-021144
The capacitance value must be chosen so that the capacitance value is correct at 5 V.
1. Using TXLDO.
2. Without using TXLDO.
Figure 37.ꢀPowering up the contactless interface using an external RF transmitter supply
Note: The TVDD_OUT pin must not be left floating. It should be at the same voltage as
the TVDD_IN pin.
The power design must be designed properly to be able to deliver a clean power supply
voltage.
In any case (external TVDD or internal TX_LDO internal supply), TVDD_IN supply must
be stable before turning on the RF field. The capacitor shall be 6.8 μF or higher (up to 10
μF)
Every noise level on top of the supply voltage can disturb the RF communication
performance of the PN7462 family. Therefore, special attention must be paid to the
filtering circuit.
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When powering up the device through the USB interface, TVDD capacitor value
shall be chosen so that the maximum capacitance on VBUS remains as per the USB
specification.
9.1.3 Powering up the contact interface
SAM
SCVDD
SAP
VUP
GDNP
VBUSP
PN7462
VCC
VBUS
GNDC
V
I
,
DDP(VBUS)
DDP(VBUS)
aaa-021145
1. The capacitances values must be chosen so that the capacitance values are correct at 5.6 V.
Figure 38.ꢀPowering up the contact interface
Contact interface is powered through VBUSP. VBUSP must be connected to VBUS, as
per the schematic in Figure 38.
In order to provide the right voltage needed for the various ISO/IEC 7816 contact card
classes (A, B, or C), the following voltages are needed:
• VDDP(VBUSP) > 2.7 V: Support of class B and class C contact cards
• VDDP(VBUSP) > 3 V: Support of class A contact cards
Remark: To support class A cards, DC-to-DC converter is used. To support class B
cards with VDDP(VBUSP) < 3.9 V, DC-to-DC converter is used.
Figure 39 indicates the method to connect the pins related to contact interfaces, when no
contact interface is used.
SAM
SCVDD
GDNP
n.c.
n.c.
SAP
VUP
n.c.
n.c.
PN7462
VBUSP
VBUS
VCC
n.c.
GNDC
V
I
,
DDP(VBUS)
DDP(VBUS)
connections when CT interface
is not used
aaa-021146
Figure 39.ꢀContact interface power supply connection when contact interface is not used
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9.2 Connecting the USB interface
(1)
Cp = 10 nF
USB
connector
Rs = 1 kΩ
USB_VBUS
USB_DP
USB_DM
PN7462 family
aaa-021147
1. Cp is optional.
Figure 40.ꢀUSB interface on a bus-powered device
When the USB interface is not used, the USB_VBUS pin shall be connected to the
ground.
9.3 Connecting the contact interface
The following diagrams indicate the method to connect the contact interface, when the
contact interface is used, and when it is not used.
PRES
AUX1
CLK
RST
C1 C2 C3 C4
PRES
(1)
C = 100 nF
PN7462
V
PVDD_IN
GNDC
C5 C6 C7 C8
(2)
C = 470 nF
R = 0 Ω
VCC
IO
AUX2
aaa-021148
1. To place close to C1 (VCC) pin of the card connector, with good connection to the ground.
2. Place close to VCC pin, with good connection to GNDC.
Figure 41.ꢀConnecting the contact interface
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PRES
AUX1
CLK
n.c.
n.c.
n.c.
n.c.
RST
PN7462
GNDC
VCC
IO
n.c.
n.c.
n.c.
AUX2
connections when CT interface
is not used
aaa-021149
Figure 42.ꢀConnection of contact interface when not used
9.4 Connecting the RF interface
Cant
ANT1
C3=1 nF
RX1
R
C1
L
TX1
antenna
antenna
C0
C0
C2
C2
TVSS
TX2
PN7462 family
L
C1
R
C3=1 nF
RX2
Cant
ANT2
VMID
C=100 nF
aaa-021150
Figure 43.ꢀRF interface - example of connection to an antenna
9.5 Unconnected I/Os
When not used, the following pins need to be "not connected":
• I2C Master interface: I2CM_SDA, I2CM_SCL
• SPI Master interface: SPIM_SSN, SPIM_SCLK, SPIM_MOSI, SPIM_MISO
• AUX interface: INT_AUX, IO_AUX, CLK_AUX (PN7462 only)
Pads have to be configured in GPIO mode, pad input and output driver need to be
disabled.
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10 Limiting values
Table 26.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VESD
electrostatic discharge voltage
Human Body Model (HBM)
[1]
[1]
on card pins IO, RST, VCC,
AUX1, CLK, AUX2, PRESN
-12
-2
+12
+2
kV
kV
on all pins except contact
interface pins
Charged Device Model (CDM)
on all pins
[1]
-1
-55
-
+1
kV
Tstg
storage temperature
non-operating
+150
+125
1050
°C
Tj(max)
Ptot
maximum junction temperature
total power dissipation
°C
reader mode; VDDP(VBUS) = 5.5 V
-
mW
[1] EIA/JESD22-A114-D.
Table 27.ꢀLimiting values for GPIO1 to GPIO12
Symbol
Parameter
Conditions
Min
Max
Unit
Vi
input voltage
-0.3
4.2
V
Table 28.ꢀLimiting values for I2C master pins (i2cm_sda, i2cm_scl)
Symbol
Parameter
Conditions
Min
Max
Unit
Vi
input voltage
-0.3
4.2
V
Table 29.ꢀLimiting values for SPI master pins ( spim_nss, spim_miso, spim_mosi and spi_clk)
Symbol
Parameter
Conditions
Min
Max
Unit
Vi
input voltage
-0.3
4.2
V
Table 30.ꢀLimiting values for host interfaces atx_a, atx_b, atx_c, atx_d in all configurations (USB, HSUART, SPI and
I2C)
Symbol
Parameter
Conditions
Min
Max
Unit
Vi
input voltage
-0.3
4.2
V
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Table 31.ꢀLimiting values for crystal oscillator
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
high-level input voltage
XTAL1, XTAL2
0
2.2
V
Table 32.ꢀLimiting values for power supply
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Min
-0.3
-0.3
Max
6
Unit
V
[1]
[1]
VDDP(VBUS) power supply voltage on pin VBUS
VDDP(VBUSP) power supply voltage on pin VBUSP
6
V
pin supply voltage for host interface and GPIOs (on pin PVDD_IN)
[1]
[1]
VDD(PVDD)
PVDD supply voltage
on pin PVDD_IN; power supply
for host interfaces and GPIOs
-0.3
-0.3
4.2
4.2
V
V
pin supply voltage for master interfaces (on pin PVDD_M_IN)
VDD(PVDD)
PVDD supply voltage
on pin PVDD_M_IN; power
supply for master interfaces
RF interface LDO (pin VUP_TX)
VI(LDO) LDO input voltage
RF transmitter (pin TVDD_IN)
VDD(TVDD) TVDD supply voltage
[1]
[1]
for RF interface LDO
-0.3
-0.3
6
6
V
V
for RF interface transmitter
[1] Maximum/minimum voltage above the maximum operating range and below ground that can be applied for a short time (< 10 ms) to a device without
leading to irrecoverable failure. Failure includes the loss of reliability and shorter life time of the device.
Table 33.ꢀLimiting values for contact interface
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
high-level input voltage
on card pins IO, RST, AUX1,
AUX2, CLK
-0.3
5.75
V
Table 34.ꢀProtection and limitations for contact interface
Symbol
IOlim
Parameter
Conditions
Min
5
Typ
Max Unit
output current limit on IO, C4, C8
shutdown current
class A, B, C
8
15
mA
mA
mA
mA
mA
Isd
on pin VCC = 5 V
70
75
75
60
85
90
90
70
110
110
110
90
on pin VCC = 3 V (doubler mode)
on pin VCC = 3 V (follower mode)
on pin VCC = 1.8 V
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Table 35.ꢀLimiting values for RF interface
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Vi
input voltage
on pins RXN and RXP
0
2.2
V
1. Maximum/minimum voltage above the maximum operating range and below
ground that can be applied for a short time (< 10 ms) to a device without leading to
irrecoverable failure. Failure includes the loss of reliability and shorter life time of the
device.
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11 Recommended operating conditions
Table 36.ꢀOperating conditions
Symbol
Tamb
Parameter
Conditions
Min
-40
2.3
Typ
25
-
Max Unit
ambient temperature
JDEC PCB - 0.5
85
°C
V
VDDP(VBUS)
power supply voltage on pin VBUS external PVDD supply, card
5.5
emulation and passive target
(PLM)
external PVDD supply, reader
mode, NFC initiator and passive/
active target mode (ALM and
PLM)
2.7
4
-
-
5.5
5.5
V
V
internal PVDD_LDO supply,
reader mode, NFC initiator and
passive/active target mode (ALM
and PLM)
VDDP(VBUSP) power supply voltage on pin VBUSP class B and class C contact card
2.7
3
-
-
5.5
5.5
V
V
class A, class B, and class C
contact card
host interface and GPIOs pin power supply (pin PVDD_IN)
VDD(PVDD)
PVDD supply voltage
for digital pins
1.8 V pin supply
3.3 V pin supply
1.65 1.8
3.3
1.95
3.6
V
V
3
SPI master and I2C master interfaces pin power supply (on pin PVDD_M_IN)
VDD(PVDD)
PVDD supply voltage
for master pins
1.8 V pin supply
3.3 V pin supply
1.65 1.8
1.95
3.6
V
V
3
3.3
RF interface LDO (pin VUP_TX)
VI(LDO) LDO input voltage
TX_LDO supply for powering up
RF interface
3
5
5.5
V
RF interface transmitter
IDD(TVDD)
TVDD supply current
on pin TVDD_IN
-
-
250
mA
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12 Thermal characteristics
Table 37.ꢀThermal characteristics
Symbol
Parameter
Conditions
Typical VFBGA64
package
Typical HVQFN64
package
Unit
Rth(j-a)
thermal resistance in free air with exposed pad
53.4
40.0
°K/W
from junction to
ambient
soldered on a four-layer JEDEC
PCB
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13 Characteristics
13.1 Static characteristics
Table 38.ꢀStatic characteristics for RST_N input pin
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
VIH
Parameter
Conditions
Min
1.1
0
Typ
Max
Unit
V
high-level input voltage
low-level input voltage
-
VDDP(VBUS)
VIL
-
0.4
V
IIH
high-level input current Vi = VDDP(VBUS)
low-level input current Vi = 0 V
input capacitance
-
-
1
-
μA
μA
pF
IIL
-1
-
-
Cin
5
-
Table 39.ꢀStatic characteristics for IRQ output pin
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
high-level output
voltage
IOH < 3 mA
VPVDD_IN
0.4
-
-
VPVDD_IN
V
VOL
low-level output
voltage
IOL < 3 mA
0
-
0.4
V
CL
load capacitance
extra pull down
-
-
-
20
pF
Rpull-down
extra pull-down is
activated in HDP
0.45
0.8
MΩ
Table 40.ꢀStatic characteristics for DWL_REQ
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
high-level input voltage VVPVDD_IN= 1.8 V
0.65 ×
-
-
V
VPVDD_IN
VIL
high-level input voltage VVPVDD_IN= 1.8 V
-
-
0.35 ×
V
VPVDD_IN
VIH
VIL
IIH
high-level input voltage VVPVDD_IN = 3.3 V
high-level input voltage VVPVDD_IN = 3.3 V
high-level input current VI = PVDD_IN
low-level input current VI = 0 V
load capacitance
2
-
-
-
V
-
0.8
V
-
-
1
-
μA
μA
pF
IIL
-1
-
-
CL
5
-
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13.1.1 GPIO static characteristics
Table 41.ꢀStatic characteristics for GPIO1 to GPIO21
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
high-level output
voltage
IOH < 3 mA
VPVDD_IN
0.4
-
-
VPVDD_IN
V
VOL
VIH
low-level output
voltage
IOH < 3 mA
0
-
0.4
V
high-level input voltage VPVDD_IN = 3.3 V
VPVDD_IN = 1.8 V
2
-
-
-
-
V
V
0.65 ×
VPVDD_IN
VIL
low-level input voltage VPVDD_IN = 3.3 V
VPVDD_IN = 1.8 V
-
-
-
-
0.8
V
V
0.35 ×
VPVDD_IN
Vhys
IOZ
hysteresis voltage
VPVDD_IN = 1.8 V and
VPVDD_IN = 3.3 V
0.1 ×
VPVDD_IN
-
-
-
V
OFF-state output
current
VO = 0 V; VO =
-
1000
nA
VPVDD_IN; on-chip pull-
up/pull-down resistors
disabled
Rpd
Rpu
IOSH
pull-down resistance
pull-up resistance
VPVDD_IN = 3.3 V
VPVDD_IN = 1.8 V
VPVDD_IN = 3.3 V
VPVDD_IN = 1.8 V
65
65
65
65
-
90
90
90
90
-
120
120
120
120
58
kΩ
kΩ
kΩ
kΩ
mA
short circuit current
output high
Drive high; cell
connected to ground;
VPVDD_IN = 3.3 V
Drive low; cell
connected to
-
-
30
mA
PVDD_IN; VPVDD_IN
1.8 V
=
IOSL
short circuit current
output low
VOH = VPVDD_IN = 3.3
V
-
-
-
-
54
37
mA
mA
VOH = VPVDD_IN = 1.8
V
IIL
low-level input current VI = 0 V
-1
-
-
-
-
-
µA
µA
mA
IIH
IOH
high-level input current VI = VPVDD_IN
1
3
high-level output
current
VOH = VPVDD_IN
-
IOL
low-level output
current
VOL = 0 V
-
-
3
mA
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13.1.2 Static characteristics for I2C master
Table 42.ꢀStatic characteristics for I2CM_SDA, I2CM_SCL - S
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
high-level output
voltage
IOH < 3 mA
0.7 ×
VPVDD_M_IN
-
VPVDD_M_IN
V
VOL
low-level output
voltage
IOL < 3 mA
0
-
0.4
V
CL
load capacitance
-
-
-
10
-
pF
V
VIH
High-level input
voltage
0.7 ×
VPVDD_M_IN
VIL
low-level input voltage
-
-
0.3 ×
V
VPVDD_M_IN
IIH
IIL
high-level input current VI = VPVDD_M_IN
low-level input current VI = 0 V
input capacitance
-
-
1
-
μA
μA
pF
-1
-
-
Cin
5
-
13.1.3 Static characteristics for SPI master
Table 43.ꢀStatic characteristics for SPIM_MOSI
Symbol
VOH
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level output voltage IOH < 3 mA
VPVDD_M_IN - 0.4
-
-
-
VPVDD_M_IN
VOL
low-level output voltage
load Capacitance
IOL< 3 mA
0
-
0.4
20
V
CL
pF
Table 44.ꢀStatic characteristics for SPIM_NSS
Symbol
VOH
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level output voltage IOH < 3 mA
VPVDD_M_IN - 0.4
-
-
-
VPVDD_M_IN
VOL
low-level output voltage
load Capacitance
IOL < 3 mA
0
-
0.4
20
V
CL
pF
Table 45.ꢀStatic characteristics for SPIM_MISO
Symbol
VIH
VIL
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level input voltage
low-level input voltage
high-level input voltage
low-level input voltage
high-level input current
low-level input current
input capacitance
VPVDD_M_IN = 1.8 V
VPVDD_M_IN = 1.8 V
VPVDD_M_IN = 3.3 V
VPVDD_M_IN = 3.3 V
Vi = VPVDD_M_IN
Vi = 0 V
0.65 × VPVDD_M_IN
-
-
-
-
-
-
5
-
-
0.35 × VPVDD_M_IN
V
VIH
VIL
2
-
-
V
0.8
V
IIH
-
1
-
µA
µA
pF
IIL
-1
-
Cin
-
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PN7462 family
NFC Cortex-M0 microcontroller
Table 46.ꢀStatic characteristics for SPI_SCLK
Symbol
VOH
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level output voltage IOH < 3 mA
VPVDD_M_IN - 0.4
-
-
-
VPVDD_M_IN
VOL
low-level output voltage
load capacitance
IOL < 3 mA
0
-
0.4
20
V
CL
pF
13.1.4 Static characteristics for host interface
Table 47.ꢀStatic characteristics for ATX_ used as SPI_NSS, ATX_ used as I2CADR0, ATX_ used as SPI_SCK, ATX_
used as SPI_MOSI
Symbol
VIH
VIL
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level input voltage
low-level input voltage
high-level input voltage
low-level input voltage
high-level input current
low-level input current
input capacitance
VPVDD_IN = 1.8 V
VPVDD_IN = 1.8 V
VPVDD_IN = 3.3 V
VPVDD_IN = 3.3 V
Vi = VPVDD_IN
Vi = 0 V
0.65 × VPVDD_M_IN
-
-
-
-
-
-
5
-
-
0.35 × VPVDD_M_IN
V
VIH
VIL
2
-
-
V
0.8
V
IIH
-
1
-
µA
µA
pF
IIL
-1
-
Cin
-
Table 48.ꢀStatic characteristics of ATX_ used as I2CSDA, ATX_ used as I2CSCL
Symbol
VOH
VOL
CL
Parameter
Conditions
Min
Typ
Max
Unit
V
high-level output voltage IOH < 3 mA
0.7 × VPVDD_IN
-
-
-
-
-
-
-
5
VPVDD_IN
low-level output voltage
load capacitance
IOL < 3 mA
0
0.4
V
-
10
pF
V
VIH
high-level input voltage
low-level input voltage
high-level input current
low-level input current
Input capacitance
0.7 × VPVDD_IN
-
VIL
-
0.3 × VPVDD_IN
V
IIH
Vi = VPVDD_IN
Vi = 0 V
-
1
-
μA
μA
pF
IIL
-1
-
Cin
-
Table 49.ꢀStatic characteristics of ATX_ used as SPIMISO
Symbol
VOH
Parameter
Conditions
Min
Typ
Max
VPVDD_IN
0.4
Unit
V
high-level output voltage IOH < 3 mA
low-level output voltage IOL < 3 mA
load capacitance
VPVDD_IN - 0.4
-
-
-
VOL
0
-
V
CL
20
pF
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Table 50.ꢀUSB characteristics
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
-10
4
Typ
Max
10
Unit
μA
V
IOZ
OFF-state output current 0 V < Vi < 3.3 V
-
-
VDDP(VBUS) power supply voltage on
pin VBUS
5.5
VDI
differential input
sensitivity voltage
(D+) - (D-)
0.2
0.8
0.8
-
-
-
-
V
V
V
VCM
differential common
mode voltage range
includes VDI range
2.5
2
Vth(rs)se
single-ended receiver
switching threshold
voltage
VOL
low-level output voltage for low-speed or full-
-
-
-
0.3
V
V
speed; RL of 1.5 kΩ to
3.6 V
VOH
high-level output voltage driven; for low- speed
or full-speed;
2.8
VPVDD_IN
RL of 15 kΩ to GND
Ctrans
ZDRV
transceiver capacitance pin to GND
-
15
-
-
pF
Ω
driver output impedance with 33 Ω series
28
44
for driver which is not
high-speed capable
resistor; steady state
drive
VCRS
output signal crossover
voltage
1.3
-
2
V
Table 51.ꢀStatic characteristics of HSU_TX and HSU RTS pin
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
VOH
Parameter
Conditions
Min
Typ
Max
VPVDD_IN
0.4
Unit
V
high-level output voltage IOH < 3 mA
low-level output voltage IOL < 3 mA
load capacitance
VPVDD_IN - 0.4
-
-
-
VOL
0
-
V
CL
20
pF
Table 52.ꢀStatic characteristics of HSU_RX, HSU_CTS
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
VIH
Parameter
high-level input voltage VPVDD_M_IN = 1.8 V
low-level input voltage VPVDD_M_IN = 1.8 V
high-level input voltage VPVDD_M_IN = 3.3 V
Conditions
Min
Typ
Max
Unit
V
0.65 × VPVDD_IN
-
-
-
-
-
-
-
VIL
-
0.35 × VPVDD_IN
V
VIH
2
-
-
V
VIL
low-level input voltage
high-level input current
low-level input current
VPVDD_M_IN = 3.3 V
0.8
1
V
IIH
-
μA
μA
IIL
-1
-
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CL
load capacitance
-
5
-
pF
13.1.5 Clock static characteristics
Table 53.ꢀStatic characteristics of XTAL pin (XTAL1, XTAL2)
Tamb = -40 °C to +85°C
Symbol
Parameter[1]
Conditions
Min
Typ[2] Max
Unit
Input clock characteristics on XTAL1 when using PLL
Vi(p-p)
peak-to-peak input
voltage
0.2
-
1.65
V
XTAL pin characteristics XTAL PLL input
IIH
high-level input current
low-level input current
input voltage
Vi = VDD
Vi = 0 V
-
-
1
μA
μA
V
IIL
-1
-
-
Vi
-
-
VDD
VAL
Cin
input voltage amplitude
input capacitance
200
-
-
-
-
mV
pF
all power modes
2
Pin characteristics for 27.12 MHz crystal oscillator
Cin
Cin
input capacitance
input capacitance
pin XTAL1
pin XTAL2
-
-
2
2
-
-
pF
pF
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.
13.1.6 Static characteristics - power supply
Table 54.ꢀStatic characteristics for power supply
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDDP(VBUSP)
power supply current
on pin VBUSP
external supply current for
contact interface, in operating
mode
-
-
200
mA
pin supply: PVDD_LDO
VO(LDO)
LDO output voltage
VDDP(VBUS) >= 4.0 V, IPVDDOUT
<= 30 mA
3
-
3.3
-
3.6
30
V
IDD(PVDD_OUT) maximum supply
current
for pin PVDD_OUT
mA
pin supply for host interface and GPIOs (on pin PVDD_IN)
IDD(PVDD) PVDD supply current
pin supply for master interfaces (on pin PVDD_M_IN)
IDD(PVDD) PVDD supply current
contactless interface: TX_LDO (pins VUP_TX, TVDD_OUT)
-
-
-
-
25
25
5.5
mA
mA
V
-
VI(LDO)
LDO input voltage
3
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IL(LDO)(max)
maximum LDO load
current
-
-
180
mA
VO(LDO)
LDO output voltage
DC output voltage (target: 3.0 V)
5.5 V > VI(LDO) > 3.3 V
2.8
-
3
3.25
-
V
DC output voltage (target: 3.0 V)
3.3 V > VI(LDO) > 2.7 V
VI(LDO)
0.3
-
-
-
V
DC output voltage (target: 3.3 V)
5.5 V > VI(LDO) > 3.6 V
3.1
-
3.3
3.55
-
V
DC output voltage (target: 3.3 V)
3.6 V > VI(LDO) > 2.7 V
VI(LDO)
0.3
V
DC output voltage (target: 3.6 V)
5.5 V > VI(LDO) > 3.9 V
3.4
-
3.6
3.95
-
V
DC output voltage (target: 3.6 V)
3.9 V > VI(LDO) > 2.7 V
VI(LDO)
0.3
V
DC output voltage (target: 4.5 V)
5.5 V > VI(LDO) > 5.0 V
4.3
4.55
-
4.5
4.75
-
4.9
5.2
180
V
DC output voltage (target: 4.7 V)
5.5 V > VI(LDO) > 5.0 V
V
IO(LDO)
LDO output current
VI(LDO) = 5.5 V
mA
Contactless interface: RF transmitter (on pin TVDD_IN)
IDD(TVDD)
TVDD supply current
maximum current supported by
the RF transmitter
-
-
250
mA
nF
Contact Interface: smart card power supply (pin VCC)
Cdec decoupling capacitance connected on pin VCC (220 nF
396
570
1000
+ 220 nF 10 %)
VCC
supply voltage
class A; ICC < 60 mA
class B; ICC < 50 mA
class C; ICC < 30 mA
4.75
2.85
1.71
4.6
5
5.25
3.15
1.89
5.4
V
V
V
V
3
1.8
-
class A; current pulses of 40 nA
with ICC < 200 mA, tw < 400 ns
class B; current pulses of 40 nA
with ICC < 200 mA, tw < 400 ns
2.76
1.66
-
-
-
-
3.24
1.94
350
V
class C; current pulses of 12 nA
with ICC < 200 mA, tw < 400 ns
V
Vripple(p-p)
SR
peak-to-peak ripple
voltage
from 20 kHz to 200 MHz
mV
slew rate on pin VCC
5 V, class A cards
3 V, class B cards
1.8 V, class C cards
class A
0.02
-
-
-
-
-
0.025
0.015
0.009
60
V/μs
V/μs
V/μs
mA
0.012
0.0072
ICC
supply current
-
-
class B
55
mA
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Symbol
Parameter
Conditions
Min
Typ
Max
35
Unit
mA
mA
class C
-
-
-
-
Pin VCC shorted to ground
110
Contact interface: DC-to-DC converter
VSAP SAP (DC-to-DC
VDDP(VBUSP) = 5 V, VCC = 5 V;
-
-
-
-
-
-
-
-
9
V
V
V
V
V
V
V
converter) - high-level ICC < 60 mA DC
output voltage
VDDP(VBUSP) = 5 V, VCC = 3 V;
ICC < 55 mA DC
-
5
VDDP(VBUSP) = 5 V, VCC = 1.8 V;
ICC < 35 mA DC
-
5
VDDP(VBUSP) = 3.3 V, VCC = 5 V;
ICC < 60 mA DC
-
9
VDDP(VBUSP) = 3.3 V, VCC = 3 V;
ICC < 55 mA DC
-
9
VDDP(VBUSP) = 3.3 V, VCC = 1.8
V; ICC < 35 mA DC
-
3.3
5.9
VUP
VUP - high-level output Class A; VDDP(VBUSP) = 3 V to 5
5.35
voltage
V, ICC < 60 mA
Class B; ICC < 55 mA
3.53
2.4
-
-
5.5
5.5
V
V
Class C, VDDP(VBUSP) = 2.7 V to
5.5 V, ICC < 35 mA DC
CSAPSAM
DC-to-DC converter
capacitance
connected between SAP and
SAM with VDDP(VBUSP) = 3 V
300
1.5
470
2.7
600
4.7
nF
µF
CVUP
DC-to-DC converter
capacitance
connected on pin VUP
Voltage detector for the DC-to-DC converter
Vdet
detection voltage
on pin VBUSP for doubler
selection, follower/doubler for
class B card
3.775
3.9
4.2
V
Table 55.ꢀStatic characteristics for voltage monitors
Tamb = -40 °C to +85 °C
Symbol
Parameter
Conditions
VBUS monitor
set to 2.3 V
set to 2.7 V
set to 4.0 V
VBUS monitor
set to 2.3 V
set to 2.7 V
set to 4.0 V
Min
Typ
Max
Unit
V(th)HL
negative-going
threshold voltage
2.15
2.6
2.3
2.45
2.95
3.9
V
V
V
2.75
3.8
3.6
Vhys
hysteresis voltage
100
100
40
150
150
80
200
200
100
mV
mV
mV
PN7462_FAM
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PN7462 family
NFC Cortex-M0 microcontroller
Symbol
Parameter
Conditions
VBUSP monitor
set to 2.7 V
set to 3.0 V
set to 3.9 V
VBUSP monitor
set to 2.7 V
set to 3.0 V
set to 3.9 V
Min
Typ
Max
Unit
V(th)HL
negative-going
threshold voltage
2.45
2.68
3.7
2.56
2.825
3.9
2.65
2.95
4.1
V
V
V
Vhys
hysteresis voltage
12
14
20
25
30
35
35
40
55
mV
mV
mV
13.1.7 Static characteristics for power modes
Table 56.ꢀStatic characteristics for power modes
Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDDP(VBUS) power supply current on
pin VBUS
active mode; VDDP(VBUS) = 5.5 V,
external PVDD, external TVDD, all
IP clocks disabled
-
6.5
-
mA
code
while(1){}
executed from flash;
active mode; VDDP(VBUS) = 5.5 V,
external PVDD, external TVDD, all
IP clocks enabled
-
8.5
-
mA
code
while(1){}
executed from flash;
suspend mode; VDDP(VBUS) = 5.5 V,
external PVDD, T = 25 °C
-
-
120
360
250
440
μA
µA
VBUS = 5.5 V, T = 25 °C, internal
PVDD LDO, including D+ and D-
pull-up
standby mode; VDDP(VBUS) = 3.3 V;
external PVDD supply; Tamb = 25 °C
-
-
-
18
55
12
-
μA
μA
μA
standby mode; VDDP(VBUS) = 5.5 V;
Vinternal PVDD supply; Tamb = 25 °C
-
hard power down; VDDP(VBUS)
=
18
5.5 V; RST_N = 0 V; Tamb = 25 °C
13.1.8 Static characteristics for contact interface
Table 57.ꢀStatic characteristics for contact interface
Tamb = -40 °C to +80 °C
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Data lines (pins IO, AUX1, AUX2)
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Symbol
Parameter
Conditions
Min
0
Typ
Max
Unit
V
Vo
output voltage on pin IO
inactive mode, no load
inactive mode, II/O = 1 mA
pin IO Configured as output
-
-
-
0.1
0
0.3
V
VOL
low-level output voltage
0
0.15 × VCC
V
IOL = 1 mA (class A,B), 500 μA
(class C)
pin IO configure as output, IOL < 15
mA
0
-
-
0.4
V
V
VOH
high-level output voltage pin IO configure as output, IOH
<
0.9 × VCC
VCC
-200 µA, VCC = 5 V, 3 V and 1.8 V;
active pull-up
pin IO configure as output, IOH < -20
μA; VCC = 1.8 V
0.8 × VCC
0
-
-
VCC
0.4
V
V
pin IO configure as output, IOH < 15
mA
VIL
VIH
Vhys
IIL
low-level input voltage
high-level input voltage
hysteresis voltage
pin IO configure as input
0
-
0.2 × VCC
VCC
V
0.6 × VCC
-
V
on pin IO
20
-
75
-
120
mV
μA
μA
kΩ
low-level input current
on pin IO; VIL = 0 V
750
ILH
high-level leakage current on pin IO; VIH = VCC
-
-
10
Rpu
pull-up resistance
connected to VCC
7
10
13
Reset output to the card
Vo
output voltage
inactive mode; no load
inactive mode; Io = 1 mA
0
0
0
-
-
-
0.1
0.3
0.3
V
V
V
VOL
low-level output voltage
IOL = 200 µA, VCC = 5 V and VCC
3 V
=
IOL = 200 µA, VCC = 1.8 V
0
-
-
0.1 × VCC
VCC
V
V
VOH
high-level output voltage IOH = -200 μA
0.9 × VCC
Clock output to the card
Vo
output voltage
inactive mode; no load
inactive mode; Io = 1 mA
IOL = 200 μA
0
0
0
-
-
-
0.1
V
V
V
0.3
VOL
low-level output voltage
minimum
(0.1 × VCC
0.3)
;
VOH
high-level output voltage IOH = -200 μA
0.9 × VCC
-0.3
-
VCC
V
Card presence input
VIL
low-level input voltage
-
-
-
0.3 ×
VPVDD_IN
V
V
V
VIH
Vhys
high-level input voltage
hysteresis voltage
0.7 ×
VPVDD_IN
VPVDD_IN
0.3
+
0.03 ×
-
VPVDD_IN
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Symbol
ILL
Parameter
Conditions
Min
Typ
Max
1
Unit
μA
low-level leakage current VIL = 0
-
-
-
-
ILH
high-level leakage current VIH = VPVDD_IN
5
μA
13.1.9 Static characteristics RF interface
Table 58.ꢀStatic characteristics for RF interface
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pins ANT1 and ANT2
Z
impedance
between ANT1 and ANT2;
low impedance
-
10
17
Ω
pins RXN and RXP
Vi(dyn)
Cin
dynamic input voltage
on pins RXN and RXP
on pins RXN and RXP
-
-
VDD - 0.05
V
input pin capacitance
impedance
-
12
-
-
pF
kΩ
Z
between pins RX to VMID;
reader, card emulation and
P2P modes
0
15
Vdet
detection voltage
card emulation and target
modes; configuration for 19
mV threshold
-
-
30
mV(p-p)
pins TX1 and TX2
VOH
VOL
ROL
high-level output voltage pins TX1 and TX2; TVDD_IN
3.1 V and IOH = 30 mA
=
=
VTVDD_IN
- 150
-
-
-
-
-
-
mV
mV
Ω
low-level output voltage pins TX1 and TX2; TVDD_IN
3.1; ITX = 30 mA
-
-
-
-
200
80
10
10
low-level output
resistance
VTX = VTVDD - 100 mV;
CWGsN = 01h
VTX = VTVDD - 100 mV;
CWGsN = 0Fh
Ω
ROH
high-level output
resistance
VTX = VTVDD - 100 mV
Ω
13.2 Dynamic characteristics
Table 59.ꢀDynamic characteristics for IRQ output pin
Data are given for Tamb = -40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
high speed; CL = 12 pF;
VPVDD_IN = 3.3 V
1
-
3.5
ns
high speed; CL = 12 pF;
VPVDD_IN = 1.8 V
1
3
-
-
3.5
10
ns
ns
tf
fall time
slow speed; CL = 12 pF;
VPVDD_IN = 3.3 V
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NFC Cortex-M0 microcontroller
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
slow speed; CL = 12 pF;
VPVDD_IN = 1.8 V
2
-
10
ns
tr
rise time
high speed: CL = 12 pF;
VPVDD_IN = 3.3 V
1
1
3
2
-
-
-
-
3.5
3.5
10
ns
ns
ns
ns
high speed: CL = 12 pF;
VPVDD_IN = 1.8 V
tr
rise time
slow speed: CL = 12 pF;
VPVDD_IN = 3.3 V
slow speed: CL = 12 pF;
VPVDD_IN = 1.8 V
10
13.2.1 Flash memory dynamic characteristics
Table 60.ꢀDynamic characteristics for flash memory
Symbol
tprog
Parameter
Conditions
Min
Typ
-
Max
Unit
programming time
endurance
1 page (64 bytes); slow clock
-
2.5
ms
NEndu
tret
200
-
500
20
-
-
kcycles
years
retention time
13.2.2 EEPROM dynamic characteristics
Table 61.ꢀDynamic characteristics for EEPROM
Symbol
tprog
Parameter
Conditions
Min
Typ
2.8
500
20
Max
Unit
programming time
endurance
1 page (64 bytes)
-
-
-
-
ms
NEndu
tret
300
-
kcycles
years
retention time
13.2.3 GPIO dynamic characteristics
80 %
80 %
50 %
20 %
50 %
20 %
gnde
t
t
r
f
aaa-021151
Figure 44.ꢀOutput timing measurement condition for GPIO
Table 62.ꢀDynamic characteristics for GPIO1 to GPIO21
Tamb = -40 °C to +85 °C
Symbol
Parameter
Conditions
Min
Max
Unit
tr
rise time
CL = 12 pF; PVDD = 1.8 V; slow
speed
2.0
10.0
ns
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Symbol
Parameter
Conditions
Min
1.0
3.0
Max
3.5
Unit
ns
CL = 12 pF; PVDD = 1.8 V; fast speed
CL = 12 pF; PVDD = 3.3 V; slow
speed
10.0
ns
CL = 12 pF; PVDD = 3.3 V; fast speed
1.0
2.0
3.5
ns
ns
tf
fall time
CL = 12 pF; PVDD = 1.8 V; slow
speed
10.0
CL = 12 pF; PVDD = 1.8 V; fast speed
1.0
3.0
3.5
ns
ns
CL = 12 pF; PVDD = 3.3 V; slow
speed
10.0
CL = 12 pF; PVDD = 3.3 V; fast speed
1.0
3.5
ns
13.2.4 Dynamic characteristics for I2C master
t
t
DA
t
DA
HD;DAT
SDA
SCL
t
t
t
HIGH
SU;STA
HD;STA
t
SU;DAT
t
LOW
aaa-021152
²
Figure 45.ꢀI C-bus pins clock timing
Table 63.ꢀTiming specification for fast mode plus I2C
Tamb = -40 °C to +85 °C
Symbol
fSCL
Parameter
Conditions
Min
0
Max
Unit
MHz
ns
SCL clock frequency
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
1
-
tSU;STA
set-up time for a
(repeated) START
condition
260
tHD;STA
tLOW
hold time (repeated)
START condition
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
260
500
260
-
-
-
ns
ns
ns
low period of the SCL
clock
tHIGH
high period of the SCL
clock
tSU;DAT
tHD;DAT
tr(SDA)
tf(SDA)
data set-up time
data hold time
SDA rise time
SDA fall time
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
50
0
-
-
ns
ns
ns
ns
-
120
120
-
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Symbol
Parameter
Conditions
Min
Max
Unit
Vhys
hysteresis of Schmitt
trigger inputs
fast mode plus; Cb < 100 pF
0.1 ×
VPVDD_M_IN
-
V
Table 64.ꢀTiming specification for fast mode I2C
Tamb = -40 °C to +85 °C
Symbol
fSCL
Parameter
Conditions
Min
0
Max
Unit
kHz
ns
SCL clock frequency
fast mode; Cb < 400 pF
400
-
tSU;STA
set-up time for a (repeated) START fast mode; Cb < 400 pF
condition
600
tHD;STA
hold time (repeated) START
condition
fast mode; Cb < 400 pF
600
-
ns
tLOW
low period of the SCL clock
high period of the SCL clock
data set-up time
fast mode; Cb < 400 pF
fast mode; Cb < 400 pF
fast mode; Cb < 400 pF
fast mode; Cb < 400 pF
fast mode plus; Cb < 100 pF
fast mode plus; Cb < 100 pF
1.3
600
100
0
-
μs
ns
ns
ns
ns
ns
V
tHIGH
-
tSU;DAT
tHD;DAT
tr(SDA)
tf(SDA)
Vhys
-
data hold time
900
250
250
-
SDA rise time
30
SDA fall time
30
hysteresis of Schmitt trigger inputs fast mode; Cb < 400 pF
0.1 ×
VPVDD_IN
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13.2.5 Dynamic characteristics for SPI
T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
MISO
DATA VALID
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Figure 46.ꢀSPI master timing
Table 65.ꢀDynamic characteristics and Timing specification for SPI master interface
Symbol
fSCK
tDS
Parameter
Conditions
Min
0
Max
6.78
-
Unit
MHz
ns
SCK frequency
data set-up time
data hold time
controlled by the host
25
25
-
tDH
-
ns
tv(Q)
data output valid time
data output hold time
25
25
ns
th(Q)
-
ns
Dynamic characteristics for SPI_SCLK, SPIM_NSS, SPIM_MOSI
tf
tr
tf
fall time
rise time
fall time
rise time
CL = 12 pF; high speed; VPVDD_IN = 3.3 V
1
3
3.5
10
ns
ns
CL = 12 pF; slow speed; VPVDD_IN = 3.3
V
CL = 12 pF; high speed; VPVDD_IN = 3.3 V
1
3
3.5
10
ns
ns
CL = 12 pF; slow speed; VPVDD_IN = 3.3
V
CL = 12 pF; high speed; VPVDD_IN = 1.8 V
1
2
3.5
10
ns
ns
CL = 12 pF; slow speed; VPVDD_IN = 1.8
V
tr
CL = 12 pF; high speed; VPVDD_IN = 1.8 V
1
3.5
ns
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Symbol
Parameter
Conditions
Min
Max
Unit
CL = 12 pF; slow speed; VPVDD_IN = 1.8
V
2
10
ns
13.2.6 Dynamic characteristics of host interface
t
t
DA
t
DA
HD;DAT
SDA
SCL
t
t
t
HIGH
SU;STA
HD;STA
t
SU;DAT
t
LOW
aaa-021153
Figure 47.ꢀI2C-bus pins clock timing
Table 66.ꢀTiming specification for I2C high speed
Tamb = -40 °C to +85 °C
Symbol
fscl
Parameter
Conditions
high speed; Cb < 100 pF
Min
Max
3.4
-
Unit
MHz
ns
clock frequency
0
tSU;STA
set-up time for a (repeated) high speed; Cb < 100 pF
START condition
160
tHD;STA
hold time (repeated) START high speed; Cb < 100 pF
condition
160
-
ns
tLOW
low period of the SCL clock high speed; Cb < 100 pF
high period of the SCL clock high speed; Cb < 100 pF
160
60
10
0
-
ns
ns
ns
μs
ns
ns
V
tHIGH
-
tSU;DAT
tHD;DAT
tr(SDA)
tf(SDA)
Vhys
data set-up time
data hold time
SDA rise time
SDA fall time
high speed; Cb < 100 pF
high speed; Cb < 100 pF
high speed; Cb < 100 pF
high speed; Cb < 100 pF
-
-
10
10
80
80
-
hysteresis of Schmitt trigger high speed; Cb < 100 pF
inputs
0.1 ×
VPVDD_IN
Table 67.ꢀDynamic characteristics for the I2C slave interface: ATX_B used as I2C_SDA, ATX_A used as I2C_SCL
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
CL = 100 pF, Rpull-up = 2 K,
standard and fast mode
30
-
250
ns
CL = 100 pF, Rpull-up = 1 K, high
speed
10
-
80
ns
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
CL = 100 pF, Rpull-up = 2 K,
standard and fast mode
30
-
250
ns
CL = 100 pF, Rpull-up = 1 K, high
speed
10
-
100
ns
T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DS
DH
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
v(Q)
DATA VALID
002aae830
Figure 48.ꢀSPI slave timings
Table 68.ꢀDynamic characteristics for SPI slave interface
Symbol
fSCK
tDS
Parameter
Conditions
Min
0
Max
7
Unit
MHz
ns
SCK frequency
data set-up time
data hold time
controlled by the host
25
25
-
-
tDH
-
ns
tv(Q)
data output valid time
data output hold time
25
25
ns
th(Q)
-
ns
Table 69.ꢀDynamic characteristics for SPI slave interface: ATX_C as SPI_MISO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ns
tf
fall time
CL = 12 pF; high speed;
VPVDD_IN = 3.3 V
1
-
3.5
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CL = 12 pF; slow speed;
VPVDD_IN = 3.3 V
3
-
10
ns
tr
rise time
CL = 12 pF; high speed;
VPVDD_IN = 3.3 V
1
3
1
2
1
2
-
-
-
-
-
-
3.5
10
ns
ns
ns
ns
ns
ns
CL = 12 pF; slow speed;
VPVDD_IN = 3.3 V
tf
fall time
rise time
CL = 12 pF; high speed;
VPVDD_IN = 1.8 V
3.5
10
CL = 12 pF; slow speed;
VPVDD_IN = 1.8 V
tr
CL = 12 pF; high speed;
VPVDD_IN = 1.8 V
3.5
10
CL = 12 pF; slow speed;
VPVDD_IN = 1.8 V
Table 70.ꢀDynamic characteristics for HSUART ATX_ as HSU_TX, ATX_ as HSU_RTS
Symbol
Parameter
Conditions[1]
Min
1
Typ
Max
3.5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tf
fall time
high speed; VPVDD_IN = 3.3 V
slow speed; VPVDD_IN = 3.3 V
high speed; VPVDD_IN = 3.3 V
slow speed; VPVDD_IN = 3.3 V
high speed; VPVDD_IN = 1.8 V
slow speed; VPVDD_IN = 1.8 V
high speed; VPVDD_IN = 1.8 V
slow speed; VPVDD_IN = 1.8 V
-
-
-
-
-
-
-
-
3
tr
tf
tr
rise time
fall time
rise time
1
3.5
10
3
1
3.5
10
2
1
3.5
10
2
[1] CL=12 pF maximum.
Table 71.ꢀDynamic characteristics for USB interface
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VBUS
Symbol
Parameter
rise time
fall time
Conditions
10 % to 90 %
10 % to 90 %
tr / tf
Min
Typ
Max
20
Unit
ns
tr
4
4
-
-
-
-
tf
20
ns
tFRFM
differential rise and fall time
matching
109
%
VCRS
output signal crossover voltage
source SE0 interval of EOP
1.3
160
-2
-
-
-
2
V
tFEOPT
tFDEOP
T = 25 °C; see Figure 49
175
+5
ns
ns
source jitter for differential transition T = 25 °C; see Figure 49
to SE0 transition
tJR1
receiver jitter to next transition
T = 25 °C
-18.5
-
+18.5 ns
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Symbol
tJR2
Parameter
Conditions
Min
-9
Typ
Max
+9
-
Unit
ns
receiver jitter for paired transitions
receiver SE0 interval of EOP
10 % to 90 %; T = 25 °C
-
-
tFEOPR
must accept as EOP; see
Figure 49
82
ns
T
PERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: t
FEOPT
differential data to
SE0/EOP skew
n × T
+ t
PERIOD
FDEOP
receiver EOP width: t
, t
EOPR1 EOPR2
002aab561
Figure 49.ꢀUSB interface differential data-to-EOP transition skew and EOP width
13.2.7 Clock dynamic characteristics
Table 72.ꢀDynamic characteristics for internal oscillators
Tamb = -40 °C to +85 °C
Symbol
low frequency oscillator
Parameter[1]
Conditions
Min
300
18
Typ[2] Max
Unit
kHz
fosc(int)
internal oscillator frequency
VDDP(VBUS) = 3.3 V
365
20
400
22
high frequency oscillator
fosc(int)
internal oscillator frequency
VDDP(VBUS) = 3.3 V
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.
Table 73.ꢀDynamic characteristics for PLL
Tamb = -40 °C to +85°C
Symbol
Parameter[1]
Conditions
Min
Typ[2] Max
50
Unit
Δf
frequency deviation
deviation added to
CLK_XTAL1 frequency on RF
frequency generated using
PLL
-50
-
ppm
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.
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13.2.8 Dynamic characteristics for power supply
Table 74.ꢀDynamic characteristics for power supply
Symbol
DC-to-DC internal oscillator
fosc(int) internal oscillator frequency
Parameter
Conditions
Min
Typ
Max
Unit
DC-to-DC converter
-
3.39
-
MHz
13.2.9 Dynamic characteristics for boot and reset
Table 75.ꢀDynamic characteristics for boot and reset
Symbol
twL(RST_N) RST_N Low pulse width time
tboot boot time
Parameter
Conditions
Min
10
-
Typ
Max
-
Unit
μs
-
-
external PVDD supply; supply
is stable at reset
320
µs
internal PVDD_LDO supply;
supply is stable at reset
-
-
2.2
ms
13.2.10 Dynamics characteristics for power mode
Table 76.ꢀPower modes - wake-up timings
Symbol
Parameter
Conditions
Min
Typ
Max
500
150
Unit
μs
[1]
[1]
twake
wake-up time
standby mode
suspend mode
-
-
-
-
μs
[1] Wake-up timings are measured from the wake-up event to the point in which the user application code reads the first instruction.
13.2.11 Dynamic characteristics for contact interface
Table 77.ꢀDynamic characteristics for contact interface
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Data lines (pins IO, AUX1, AUX2)
fdata
tr(i)
data rate
on data lines
-
-
-
-
1.5
1.2
Mbps
μs
input rise time
from VIL maximum to VIH
minimum
tf(i)
input fall time
from VIL maximum to VIH
minimum
-
-
-
-
-
1.2
0.1
0.1
-
μs
μs
μs
ns
tr(o)
tf(o)
tw(pu)
output rise time
output fall time
pull-up pulse width
CL < = 80 pF; 10 % to 90 %
from 0 to VCC
-
CL < = 80 pF; 10 % to 90 %
from 0 to VCC
-
295
Reset output to the card
tr
tf
rise time
fall time
CL = 100 pF
CL = 100 pF
-
-
-
-
0.1
0.1
μs
μs
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock output to the card (CLK)
[1]
[1]
[1]
[1]
tr
rise time
CL = 30 pF; fCLK = 10 MHz
CL = 30 pF; fCLK = 5 MHz
CL = 30 pF; fCLK = 10 MHz
CL = 30 pF; fCLK = 5 MHz
operational
-
-
-
-
-
-
-
-
8
ns
ns
ns
ns
tr
rise time
-
16
8
tf
fall time
-
tf
fall time
-
16
fCLK
δ
frequency on pin CLK
duty cycle
slew rate
0
13.56 MHz
[1]
CL = 30 pF
45
0.2
55
-
%
SR
rise and fall; CL = 30 pF; VCC
+5 V
=
=
=
V/ns
rise and fall; CL = 30 pF; VCC
+3 V
0.12
-
-
-
-
V/ns
V/ns
rise and fall; CL = 30 pF; VCC
+1.8 V
0.072
PRESN
tdeb
debounce time
on pin PRESN
-
6
-
ms
Timings
tact
activation time
see figure below; T = 25 °C
see figure below; T = 25 °C
11
60
-
22
ms
μs
tdeact
deactivation time
100
250
[1] The transition time and duty factor definitions are shown in Figure below.
t
t
r
f
V
OH
90%
90%
(V
+ V ) /2
OL
OH
10%
10%
V
OL
t
t
2
1
fce666
Figure 50.ꢀDefinition of output and input transition times
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14 Marking
14.1 Marking HVQFN64
Table 78.ꢀMarking codes
Type number
PN7462AUHN
PN7362AUHN
PN7360AUHN
PN7412AUHN
Common
Line
Marking code
PN7462AU-00
PN7362AU-00
PN7360AU-00
PN7412AU-00
Line A
Line B
Line C
Diffusion Batch ID, Assembly Sequence ID
Characters: Diffusion and assembly location, date code,
product version (indicated by mask version), product life cycle
status. This line includes the following elements at 8 positions:
1. Diffusion center code: Z
2. Assembly center code: S
3. RHF-2006 indicator: D "Dark Green"
4. Year code (Y) 1
5. Year code (Y) 2
6. Week code (W) 1
7. Week code (W) 2
8. HW version
Line D
Line E
Empty
Empty
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14.1.1 Package marking drawing
Terminal 1 index area
A
B
C
D
E
0
5
aaa-021255
Figure 51.ꢀMarking in HVQFN64
14.2 Marking VFBGA64
Table 79.ꢀMarking codes
Type number
Line
Marking code
PN7462AUEV
Line A
7462x
x: means version number
PN7362AUEV
PN7360AUEV
Common
7362x
x: means version number
7360x
x: means version number
Line B
Line C
DBID+ASID
Diffusion batch, 2 digits + Assembly batch, 2digits
ZSDyywwX
Manufacturing code including:
• Diffusion center code, 1 digit (Z for SSMC)
• Assembly center code, 1 digit (S for ATKH)
• RoHS compliancy indicator, 1 digit (D: Dark Green; fully
compliant RoHS and no halogen and antimony)
• Manufacturing year and week, digits:
– YY: production year
– WW: production week code
• Product life cycle status code, 1 digit:
– X: means not qualified product
– nothing means released product
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14.2.1 Package marking drawing
terminal 1
index area
A : 5
B : 5
C : 8
M497
0
5
aaa-028642
Figure 52.ꢀMarking in VFBGA64
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15 Package outline HVQFN64
HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;
64 terminals; body 9 x 9 x 0.85 mm
SOT804-4
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
e
v
C
C
A B
1/2 e
b
L
y
1
y
w
C
L
1
17
32
16
33
E
t
e
E
s
E
e
2
h
1/2 e
1
48
X
terminal 1
index area
64
49
L
D
D
D
t
s
h
2
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
A
A
b
c
D
D
h
D
s
D
t
E
E
E
E
e
e
e
2
L
L
1
L
2
v
w
y
y
1
1
h
s
t
1
max 1.00 0.05 0.30
mm nom 0.85 0.02 0.21 0.2 9.0 5.10 0.14 0.45 9.0 5.10 0.14 0.45 0.5 7.5 7.5 0.4 0.25 0.25 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 8.9 4.95 0.09 0.40 8.9 4.95 0.09 0.40 0.3
9.1 5.25 0.19 0.50 9.1 5.25 0.19 0.50
0.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot804-4_po
Issue date
References
Outline
version
European
projection
IEC
- - -
JEDEC
- - -
JEITA
- - -
10-05-26
10-05-27
SOT804-4
Figure 53.ꢀPackage outline HVQFN64
PN7462_FAM
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Footprint information for reflow soldering of HVQFN64 package
SOT804-4
Hx
Gx
D
P
0.105
0.125
C
Ø 0.3 drilled vias (41x)
SPx
SPy
Hy Gy
SPy tot
SLy By Ay
0.065
0.065
SPx tot
0.065
SLx
Bx
0.065
X
0.29
Ax
0.24
Recommended stencil thickness: 0.1 mm
detail X
0.85 0.9
solder land
solder land plus solder paste
solder resist opening
occupied area
solder paste deposit
Dimensions in mm
Ax
P
Ay
Bx
By
SLx
SLy
SPx
0.70
SPy SPx tot SPy tot
0.70 3.50 3.50
C
D
Gx
Gy
Hx
Hy
0.50 10.00
8.20
8.20
5.10
5.10
0.90
0.29
9.25
9.25 10.25 10.25
10.00
15-12-15
15-12-22
sot804-4_fr
Issue date
Figure 54.ꢀFootprint information for reflow soldering of HVQFN64
PN7462_FAM
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16 Package outline VFBGA64
Figure 55.ꢀPackage outline VFBGA64
PN7462_FAM
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17 Packing information
17.1 Packing information HVQFN64
Moisture Sensitivity Level (MSL) evaluation has been performed according to JEDEC
J-STD-020C. MSL for this package is level 3 which means 260 °C Pb-free convection
reflow maximum temperature peak.
Dry packing is required with following floor conditions: 168 hours out of bag floor life at
maximum ambient temperature 30 °C/60 % RH.
For information on packing, refer to the PIP relating to this product at http://
www.nxp.com.
17.2 Packing information VFBGA64
Moisture Sensitivity Level (MSL) evaluation has been performed according to JEDEC
J-STD-020C. MSL for this package is level 3 which means 260 °C Pb-free convection
reflow maximum temperature peak.
Dry packing is required with following floor conditions: 168 hours out of bag floor life at
maximum ambient temperature 30 °C/60 % RH.
For information on packing, refer to the PIP relating to this product at http://
www.nxp.com.
PN7462_FAM
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18 Abbreviations
Table 80.ꢀAbbreviations
Acronym
ADC
ALM
ASK
Description
Analog to Digital Convertor
Active Load Modulation
Amplitude Shift Keying
Binary Phase Shift Keying
Contactless Interface
Cyclic Redundancy Check
Dynamic Power Control
BPSK
CLIF
CRC
DPC
EEPROM
GPIO
I2C
Electrically Erasable Programmable Read-Only Memory
General-Purpose Input Output
Inter-Interchanged Circuit
Integrated Circuit
IC
IAP
In-Application Programming
In-System Programming
Low DropOut
ISP
LDO
LPCD
MSL
NFC
NRZ
NVIC
P2P
Low-Power Card Detection
Moisture Sensitivity Level
Near Field Communication
Non-Return to Zero
Nested Vectored Interrupt Controller
Peer-to-Peer
PLL
Phase-Locked Loop
PLM
SPI
Passive Load Modulation
Serial Peripheral Interface
Serial Wire Debug
SWD
UART
USB
Universal Asynchronous Receiver Transmitter
Universal Serial Bus
PN7462_FAM
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19 Revision history
Table 81.ꢀRevision history
Document ID
Release date
20180628
Data sheet status
Change notice
Supersedes
PN7462_FAM v. 4.1
Product data sheet
-
PN7462_FAM v. 4.0
and PN7462_FAM incl
PN7412 v.3.0
Modifications:
• New type PN7412AUHN added
• Combined data sheets PN7462_FAM and PN7462_FAM incl PN7412
PN7462_FAM v. 4.0
Modifications:
20180201 Product data sheet
-
PN7462 v. 3.2 and
PN736X v. 3.3
• Combined data sheets PN736X and PN7462.
• Added description about VFBGA64 package versions.
PN736X v. 3.3
Modifications:
20170907 Product data sheet
-
PN736X v.3.2
• Removed chapter 8.9 "I/O auxiliary - ISO/IEC 7816 UART" which is not available on the
product.
• Updated Pin description, removed pin fuinctionality INT_AUX , CLK_AUX and IO_AUX
• Updated Section 9.5 "Unconnected I/O's", removed description of AUX interface INT_AUX,
IO_AUX, CLK_AUX which is not available on the product
PN736X v. 3.2
Modifications:
20161213
Product data sheet
-
-
-
PN746X_736X v.3.1
• Product name title and Descriptive title updated
• Editorial changes
PN746X_736X v.3.1
Modifications:
20160405
Product data sheet
PN746X_736X v.3.0
• Descriptive title updated
• Section 1 "General description": updated
PN746X_736X v.3.0
20160330
Product data sheet
-
PN7462_FAM
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20 Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
20.2 Definitions
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
Draft — The document is a draft version only. The content is still under
to result in personal injury, death or severe property or environmental
internal review and subject to formal approval, which may result in
damage. NXP Semiconductors and its suppliers accept no liability for
modifications or additions. NXP Semiconductors does not give any
inclusion and/or use of NXP Semiconductors products in such equipment or
representations or warranties as to the accuracy or completeness of
applications and therefore such inclusion and/or use is at the customer’s own
information included herein and shall have no liability for the consequences
risk.
of use of such information.
Applications — Applications that are described herein for any of these
Short data sheet — A short data sheet is an extract from a full data sheet
products are for illustrative purposes only. NXP Semiconductors makes
with the same product type number(s) and title. A short data sheet is
no representation or warranty that such applications will be suitable
intended for quick reference only and should not be relied upon to contain
for the specified use without further testing or modification. Customers
detailed and full information. For detailed and full information see the
are responsible for the design and operation of their applications and
relevant full data sheet, which is available on request via the local NXP
products using NXP Semiconductors products, and NXP Semiconductors
Semiconductors sales office. In case of any inconsistency or conflict with the
accepts no liability for any assistance with applications or customer product
short data sheet, the full data sheet shall prevail.
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
Product specification — The information and data provided in a Product
and products planned, as well as for the planned application and use of
data sheet shall define the specification of the product as agreed between
customer’s third party customer(s). Customers should provide appropriate
NXP Semiconductors and its customer, unless NXP Semiconductors and
design and operating safeguards to minimize the risks associated with
customer have explicitly agreed otherwise in writing. In no event however,
their applications and products. NXP Semiconductors does not accept any
shall an agreement be valid in which the NXP Semiconductors product
liability related to any default, damage, costs or problem which is based
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed
customer’s third party customer(s). NXP does not accept any liability in this
respect.
to be accurate and reliable. However, NXP Semiconductors does not
Limiting values — Stress above one or more limiting values (as defined in
give any representations or warranties, expressed or implied, as to the
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
accuracy or completeness of such information and shall have no liability
damage to the device. Limiting values are stress ratings only and (proper)
for the consequences of use of such information. NXP Semiconductors
operation of the device at these or any other conditions above those
takes no responsibility for the content in this document if provided by an
given in the Recommended operating conditions section (if present) or the
information source outside of NXP Semiconductors. In no event shall NXP
Characteristics sections of this document is not warranted. Constant or
Semiconductors be liable for any indirect, incidental, punitive, special or
repeated exposure to limiting values will permanently and irreversibly affect
consequential damages (including - without limitation - lost profits, lost
the quality and reliability of the device.
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
legal theory. Notwithstanding any damages that customer might incur for
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
agreement shall apply. NXP Semiconductors hereby expressly objects to
Semiconductors.
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
notice. This document supersedes and replaces all information supplied prior
the grant, conveyance or implication of any license under any copyrights,
to the publication hereof.
patents or other industrial or intellectual property rights.
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20.4 Licenses
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC
14443 Type B software enabled and is
licensed under Innovatron’s Contactless
Card patents license for ISO/IEC 14443 B.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
The license includes the right to use the IC
in systems and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the
Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/
IEC 21481 does not convey an implied license under any patent right
infringed by implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Comparison of the PN7462 family members .....1
Tab. 42. Static characteristics for I2CM_SDA,
I2CM_SCL - S .................................................75
Tab. 43. Static characteristics for SPIM_MOSI ............. 75
Tab. 44. Static characteristics for SPIM_NSS ............... 75
Tab. 45. Static characteristics for SPIM_MISO ............. 75
Tab. 46. Static characteristics for SPI_SCLK ................ 76
Tab. 47. Static characteristics for ATX_ used as
SPI_NSS, ATX_ used as I2CADR0, ATX_
used as SPI_SCK, ATX_ used as SPI_MOSI .. 76
Tab. 48. Static characteristics of ATX_ used as
I2CSDA, ATX_ used as I2CSCL .....................76
Tab. 49. Static characteristics of ATX_ used as
SPIMISO ..........................................................76
Tab. 50. USB characteristics .........................................77
Tab. 51. Static characteristics of HSU_TX and HSU
RTS pin ........................................................... 77
Quick reference data .........................................7
Ordering information ..........................................8
Pin description .................................................14
Pin description .................................................17
Interrupt sources ............................................. 25
Pin description for host interface .....................29
HSUART baudrates .........................................30
I2C interface addressing ................................. 30
Tab. 10. SPI configuration .............................................31
Tab. 11. Communication overview for ISO/IEC 14443
type A and read/write mode for MIFARE
Classic .............................................................38
Tab. 12. Communication overview for ISO/IEC 14443
B reader/writer .................................................39
Tab. 13. Communication overview for FeliCa reader/
writer ................................................................39
Tab. 14. Communication overview for ISO/IEC 15693
reader to label .................................................40
Tab. 15. Communication overview for ISO/IEC 15693
label to reader .................................................40
Tab. 52. Static
characteristics
of
HSU_RX,
HSU_CTS ........................................................77
Tab. 53. Static characteristics of XTAL pin (XTAL1,
XTAL2) ............................................................ 78
Tab. 54. Static characteristics for power supply ............ 78
Tab. 55. Static characteristics for voltage monitors ....... 80
Tab. 56. Static characteristics for power modes ............81
Tab. 57. Static characteristics for contact interface ....... 81
Tab. 58. Static characteristics for RF interface ..............83
Tab. 59. Dynamic characteristics for IRQ output pin ..... 83
Tab. 60. Dynamic characteristics for flash memory .......84
Tab. 61. Dynamic characteristics for EEPROM .............84
Tab. 62. Dynamic characteristics for GPIO1 to
GPIO21 ............................................................84
Tab. 63. Timing specification for fast mode plus I2C .....85
Tab. 64. Timing specification for fast mode I2C ............ 86
Tab. 65. Dynamic characteristics and Timing
specification for SPI master interface ..............87
Tab. 66. Timing specification for I2C high speed ...........88
Tab. 67. Dynamic characteristics for the I2C slave
interface: ATX_B used as I2C_SDA, ATX_A
Tab. 16. Communication
overview
for
active
communication mode ...................................... 42
Tab. 17. Communication overview for passive
communication mode ...................................... 42
Tab. 18. ISO/IEC14443 A card operation mode ............43
Tab. 19. Framing and coding overview ......................... 43
Tab. 20. Timer characteristics ....................................... 47
Tab. 21. Crystal requirements ....................................... 49
Tab. 22. SCLDO and DC-to-DC converter modes .........54
Tab. 23. Threshold configuration for voltage monitor .... 59
Tab. 24. Reset sources ................................................. 60
Tab. 25. Power supply connection ................................ 62
Tab. 26. Limiting values ................................................ 68
Tab. 27. Limiting values for GPIO1 to GPIO12 ............. 68
Tab. 28. Limiting values for I2C master pins
(i2cm_sda, i2cm_scl) .......................................68
Tab. 29. Limiting values for SPI master pins
( spim_nss, spim_miso, spim_mosi and
used as I2C_SCL ............................................88
Tab. 68. Dynamic characteristics for SPI slave
interface ...........................................................89
spi_clk) ............................................................ 68
Tab. 30. Limiting values for host interfaces atx_a,
atx_b, atx_c, atx_d in all configurations
Tab. 69. Dynamic characteristics for SPI slave
interface: ATX_C as SPI_MISO ...................... 89
(USB, HSUART, SPI and I2C) ........................ 68
Tab. 70. Dynamic characteristics for HSUART ATX_
as HSU_TX, ATX_ as HSU_RTS ....................90
Tab. 71. Dynamic characteristics for USB interface ...... 90
Tab. 31. Limiting values for crystal oscillator .................69
Tab. 32. Limiting values for power supply .....................69
Tab. 33. Limiting values for contact interface ................69
Tab. 34. Protection and limitations for contact
interface ...........................................................69
Tab. 35. Limiting values for RF interface .......................70
Tab. 36. Operating conditions ....................................... 71
Tab. 37. Thermal characteristics ................................... 72
Tab. 38. Static characteristics for RST_N input pin ....... 73
Tab. 39. Static characteristics for IRQ output pin .......... 73
Tab. 40. Static characteristics for DWL_REQ ................73
Tab. 41. Static characteristics for GPIO1 to GPIO21 .....74
Tab. 72. Dynamic
characteristics
for
internal
oscillators .........................................................91
Tab. 73. Dynamic characteristics for PLL ......................91
Tab. 74. Dynamic characteristics for power supply ....... 92
Tab. 75. Dynamic characteristics for boot and reset ......92
Tab. 76. Power modes - wake-up timings .....................92
Tab. 77. Dynamic characteristics for contact interface ...92
Tab. 78. Marking codes .................................................94
Tab. 79. Marking codes .................................................95
Tab. 80. Abbreviations .................................................101
Tab. 81. Revision history .............................................102
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Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Block diagram ................................................... 9
Fig. 30. Communication in card emulation of NFC
passive target ..................................................46
Block diagram ................................................. 10
Block diagram ................................................. 11
Block diagram ................................................. 12
Pin configuration PN736X ...............................13
Pin configuration PN7462 ............................... 13
Pin configuration PN7412 ............................... 13
Pin configuration VFBGA64 ............................ 17
Flash memory mapping ...................................20
Fig. 31. Clocks and IP overview ...................................49
Fig. 32. Crystal oscillator connection ............................49
Fig. 33. PN7462 LDOs and power pins overview .........52
Fig. 34. PN736X LDOs and power pins overview ........ 55
Fig. 35. Powering up the microcontroller ......................63
Fig. 36. Powering up the contactless interface using
a single power supply ..................................... 64
Fig. 10. EEPROM memory mapping ............................21
Fig. 11. SRAM memory mapping .................................22
Fig. 12. PN7462 family memory map ...........................23
Fig. 13. APB memory map PN736X .............................24
Fig. 14. APB memory map PN7462 .............................24
Fig. 15. APB memory map PN7412 .............................25
Fig. 16. VDDP(VBUS), supported contact cards
classes, and card deactivation ........................33
Fig. 17. Contact interface - activation sequence .......... 35
Fig. 18. Deactivation sequence for contact interface ....36
Fig. 19. Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ....... 37
Fig. 37. Powering up the contactless interface using
an external RF transmitter supply ................... 64
Fig. 38. Powering up the contact interface ...................65
Fig. 39. Contact interface power supply connection
when contact interface is not used ..................65
Fig. 40. USB interface on a bus-powered device ......... 66
Fig. 41. Connecting the contact interface .....................66
Fig. 42. Connection of contact interface when not
used .................................................................67
Fig. 43. RF interface - example of connection to an
antenna ............................................................67
Fig. 44. Output timing measurement condition for
GPIO ................................................................84
Fig. 20. Data coding and framing according to ISO/
IEC 14443 A card response ............................38
Fig. 45. I²C-bus pins clock timing .................................85
Fig. 46. SPI master timing ............................................87
Fig. 47. I2C-bus pins clock timing ................................88
Fig. 48. SPI slave timings ............................................ 89
Fig. 49. USB interface differential data-to-EOP
transition skew and EOP width ....................... 91
Fig. 21. ISO/IEC 14443
B
read/write mode
communication diagram .................................. 38
Fig. 22. FeliCa read/write communication diagram ...... 39
Fig. 23. Multiple reception cycles - data format ............40
Fig. 24. ISO/IEC
15693
read/write
mode
communication diagram .................................. 40
Fig. 25. Data coding according to ISO/IEC 15693
standard mode reader to label ........................ 41
Fig. 26. Active communication mode ........................... 42
Fig. 27. Passive communication mode .........................42
Fig. 28. PN7462 family output driver ............................44
Fig. 29. Receiver block diagram ...................................45
Fig. 50. Definition of output and input transition times ...93
Fig. 51. Marking in HVQFN64 ......................................95
Fig. 52. Marking in VFBGA64 ...................................... 96
Fig. 53. Package outline HVQFN64 ............................. 97
Fig. 54. Footprint information for reflow soldering of
HVQFN64 ........................................................98
Fig. 55. Package outline VFBGA64 ............................. 99
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Contents
1
2
2.1
2.2
General description ............................................ 1
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.10
Clock circuitry .................................................. 34
I/O circuitry ...................................................... 34
VCC regulator ..................................................34
Activation sequence .........................................34
Deactivation sequence .................................... 35
I/O auxiliary - connecting TDA slot extender ....36
Contactless interface - 13.56 MHz ...................36
RF functionality ................................................37
Features and benefits .........................................3
Integrated contact interface frontend ................. 3
Integrated ISO/IEC 7816-3&4 UART
interface ............................................................. 3
Integrated contactless interface frontend ...........3
Cortex-M0 microcontroller ................................. 4
Applications .........................................................6
Quick reference data .......................................... 7
Ordering information .......................................... 8
Block diagram ..................................................... 9
Block diagram PN7462 HVQFN64 .................... 9
Block diagram PN7462 VFBGA64 ...................10
Block diagram PN7412 HVQFN64 .................. 11
Block diagram PN736X ................................... 12
Pinning information .......................................... 13
Pinning HVQFN64 ........................................... 13
Pin description HVQFN64 ............................... 14
Pinning VFBGA64 ............................................17
Pin description VFBGA64 ................................17
Functional description ......................................20
ARM Cortex-M0 microcontroller ...................... 20
Memories ......................................................... 20
On-chip flash programming memory ............... 20
Memory mapping .............................................20
EEPROM ......................................................... 21
Memory mapping .............................................21
SRAM ...............................................................21
Memory mapping .............................................21
ROM .................................................................22
Memory map ....................................................22
Nested Vectored Interrupt Controller (NVIC) ....25
NVIC features ..................................................25
Interrupt sources ..............................................25
GPIOs .............................................................. 27
GPIO features ..................................................27
GPIO configuration .......................................... 27
GPIO interrupts ................................................27
CRC engine 16/32 bits .................................... 27
Random Number Generator (RNG) .................28
Master interfaces ............................................. 28
I2C master interface ........................................ 28
I2C features .....................................................28
SPI interface ....................................................28
SPI features .....................................................29
Host interfaces .................................................29
High-speed UART ............................................29
I2C host interface controller .............................30
I2C host interface features .............................. 30
SPI host/Slave interface .................................. 30
SPI host interface features .............................. 31
USB interface .................................................. 31
Full speed USB device controller .................... 31
Contact interface ............................................. 32
Contact interface features and benefits ........... 32
Voltage supervisor ...........................................33
2.3
2.4
3
4
5
6
6.1
6.2
6.3
6.4
7
7.1
7.2
7.3
7.4
8
8.10.1
8.10.1.1 Communication mode for ISO/IEC 14443
type A and for MIFARE Classic .......................37
8.10.1.2 ISO/IEC14443 B functionality .......................... 38
8.10.1.3 FeliCa functionality .......................................... 39
8.10.1.4 ISO/IEC 15693 functionality .............................40
8.10.1.5 ISO/IEC18000-3 mode 3 functionality ..............41
8.10.1.6 NFCIP-1 modes ...............................................41
8.10.2
Contactless interface ....................................... 44
8.10.2.1 Transmitter (TX) .............................................. 44
8.10.2.2 Receiver (RX) ..................................................44
8.10.3
8.10.4
8.10.5
8.10.5.1 RF output control .............................................47
8.10.5.2 Adaptive Waveform Control (AWC) ................. 47
8.11
8.11.1
8.11.2
8.12
8.13
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.14.5
8.15
Low-Power Card Detection (LPCD) .................46
Active Load Modulation (ALM) ........................ 46
Dynamic Power Control (DPC) ........................47
8.1
8.2
8.2.1
8.2.1.1
8.2.2
8.2.2.1
8.2.3
8.2.3.1
8.2.4
8.2.5
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.5
Timers ..............................................................47
Features of timer 0 and timer 1 ....................... 47
Features of timer 2 and timer 3 ....................... 48
System tick timer .............................................48
Watchdog timer ............................................... 48
Clocks .............................................................. 48
Quartz oscillator (27.12 MHz) ..........................49
USB PLL ..........................................................50
High Frequency Oscillator (HFO) .................... 50
Low Frequency Oscillator (LFO) ......................50
Clock configuration and clock gating ............... 50
Power management .........................................51
Power supply sources ..................................... 51
PN7462 Power Management Unit (PMU) ........ 51
8.15.1
8.15.2
8.15.2.1 Main LDO ........................................................ 52
8.15.2.2 PVDD_LDO ......................................................53
8.15.2.3 Contact interface - SCLDO LDO ..................... 53
8.15.2.4 Contact interface DC-to-DC converter .............53
8.15.2.5 VCC LDO .........................................................54
8.15.2.6 TXLDO .............................................................54
8.6
8.7
8.7.1
8.7.1.1
8.7.2
8.7.2.1
8.8
8.8.1
8.8.2
8.8.2.1
8.8.3
8.8.3.1
8.8.4
8.8.4.1
8.9
8.15.3
PN736X Power Management Unit (PMU) ........55
8.15.3.1 Main LDO ........................................................ 55
8.15.3.2 PVDD_LDO ......................................................56
8.15.3.3 TXLDO .............................................................56
8.15.4
Power modes ...................................................57
8.15.4.1 Active mode .....................................................57
8.15.4.2 Standby mode ................................................. 57
8.15.4.3 Suspend mode ................................................ 57
8.15.4.4 Wake-up from standby mode and suspend
mode ................................................................58
8.15.4.5 Hard Power-Down (HPD) mode ...................... 58
8.15.5
8.15.5.1 VBUS monitor ..................................................59
8.9.1
8.9.2
Voltage monitoring ...........................................58
PN7462_FAM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.1 — 28 June 2018
406341
107 / 108
NXP Semiconductors
PN7462 family
NFC Cortex-M0 microcontroller
8.15.5.2 VBUSP monitor ............................................... 59
8.15.5.3 PVDD LDO supply monitor ..............................59
19
20
Revision history .............................................. 102
Legal information ............................................103
8.15.6
8.16
Temperature sensor ........................................ 59
System control .................................................60
Reset ................................................................60
Brown-Out Detection (BOD) ............................ 60
APB interface and AHB-Lite ............................ 60
External interrupts ............................................61
SWD debug interface ...................................... 61
SWD interface features ................................... 61
Application design-in information ...................62
Power supply connection .................................62
Powering up the microcontroller ...................... 63
Powering up the contactless interface ............. 63
Powering up the contact interface ................... 65
Connecting the USB interface ......................... 66
Connecting the contact interface ..................... 66
Connecting the RF interface ............................67
Unconnected I/Os ............................................67
Limiting values ..................................................68
Recommended operating conditions .............. 71
Thermal characteristics ....................................72
Characteristics .................................................. 73
Static characteristics ........................................73
GPIO static characteristics .............................. 74
Static characteristics for I2C master ................75
Static characteristics for SPI master ................75
Static characteristics for host interface ............ 76
Clock static characteristics .............................. 78
Static characteristics - power supply ............... 78
Static characteristics for power modes ............ 81
Static characteristics for contact interface ........81
Static characteristics RF interface ................... 83
Dynamic characteristics ...................................83
Flash memory dynamic characteristics ............84
EEPROM dynamic characteristics ...................84
GPIO dynamic characteristics ......................... 84
Dynamic characteristics for I2C master ........... 85
Dynamic characteristics for SPI .......................87
Dynamic characteristics of host interface ........ 88
Clock dynamic characteristics ......................... 91
Dynamic characteristics for power supply ........92
Dynamic characteristics for boot and reset ......92
8.16.1
8.16.2
8.16.3
8.16.4
8.17
8.17.1
9
9.1
9.1.1
9.1.2
9.1.3
9.2
9.3
9.4
9.5
10
11
12
13
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.2.9
13.2.10 Dynamics characteristics for power mode ....... 92
13.2.11 Dynamic characteristics for contact interface ... 92
14
Marking ...............................................................94
Marking HVQFN64 .......................................... 94
Package marking drawing ............................... 95
Marking VFBGA64 ...........................................95
Package marking drawing ............................... 96
Package outline HVQFN64 ............................... 97
Package outline VFBGA64 ............................... 99
Packing information ........................................100
Packing information HVQFN64 ......................100
Packing information VFBGA64 ...................... 100
Abbreviations .................................................. 101
14.1
14.1.1
14.2
14.2.1
15
16
17
17.1
17.2
18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 June 2018
Document identifier: PN7462_FAM
Document number: 406341
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