PNX8526 [NXP]
Programmable source decoder with integrated peripherals; 可编程信源解码器,集成外设型号: | PNX8526 |
厂家: | NXP |
描述: | Programmable source decoder with integrated peripherals |
文件: | 总59页 (文件大小:2875K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PNX8526
Programmable source decoder with integrated peripherals
Rev. 01 – 6 October 2003
Preliminary data
1. General description
The PNX8526 is a highly integrated media processor for use in Advanced Set Top
Boxes (ASTB) and Digital Television (DTV) systems. The PNX8526 is targeted at the
mid to high-end ASTB/DTV systems, decoding “all format” HD and SD MPEG2
source material with Standard Definition (SD), or double line-rate SD display
capabilities. Although the PNX8526 can process high level input formats, its display
capabilities are primarily targeted at NTSC, PAL and SECAM televisions. It is also
intended for lower cost DTVs, those not considered high definition. Progressive
output is also available for double line-rate television displays, or for high resolution
graphic content to be displayed on a computer monitor. The PNX8526 is designed in
a high performance 0.12-micron process.
The PNX8526 performs source decode functions, including - conditional access,
MPEG2 transport stream de-mux, MPEG2 video decode, audio decode and
processing, graphics generation, video processing, and image composition and
display. A 32-bit 200 MHz VLIW processor, referred to as the TriMedia™ 3200 CPU
core (TM32 CPU), carries out the majority of media processing operations performed
by the PNX8526. Fixed function hardware will perform some operations that are not
handled by the TM32 CPU. Additionally, the PNX8526 supports a number of
peripheral interfaces such as I2C, USB, IDE and UART. Other interfaces such as
IEEE-1284 and Ethernet may be supported via Super I/O devices that reside on a
PCI expansion bus. The expansion bus also provides for glueless interface to 8-bit
wide slave devices, such as Flash/ROM, DOCSIS modem, UARTs, etc.
An embedded MIPS processor (PR3940) running at 150 MHz is intended to run the
OS. (There is no direct support for an external processor; however, a CPU of any type
may be connected to the PNX8526 via the PCI interface.) This implies a complete
CPU subsystem consisting of the CPU itself, local memory, and an interface to PCI.
The MIPS processor is primarily responsible for control functions and
graphics-intensive operating systems, while the TM32 CPU is responsible for running
all real-time media processing functions. All resources supported within the PNX8526
are accessible by both the MIPS processor and the TM32 CPU. The software
documentation of the PNX8526 provides more details on the interaction between the
MIPS and the TM32 CPU.
The PNX8526 is intended to be used with a small companion IC, the PNX8510. This
analog companion chip provides the majority of analog video and audio support for
the output of the PNX8526. The PNX8510 companion is capable of simultaneously
driving two video channels (6 DACs) and two stereo audio channels (4 DACs).
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
2. Features
■ 200 MHz, 5 instruction/clock cycle 32-bit VLIW processing core (TM32 CPU)
■ 150 MHz, MIPS PR3940 processing core
■ External CPU support via PCI
■ Support for multiple digital video (D1) input streams
■ Support for multiple MPEG2 or DIRECTV transport streams (parallel format)
■ On-chip conditional access for DVB, DES, MULTI2, CAM, DIRECTV
■ On-chip copy protection support for OpenCable™ and ATSC (NRSS-B)
■ Simultaneous decode of two SD streams (MPEG2) or one HD MPEG Stream
(AFD style HD-SD decode)
■ Simultaneous decode of two AC-3 or equivalent audio streams
■ High performance 2D rendering and DMA capability
■ Dual image composition/screen refresh engines: four layer primary output, two
layer secondary output
■ Multiple channel output to support watch/record and multi-room modes
■ Embedded 1394 link layer with 5C copy protection
■ Soft modem support via SSI interface
■ 16, 32, and 64 MB Unified Memory Architecture implemented with high speed
SDRAM (166 MHz)
■ System expansion capability via industry standard PCI bus
■ Core peripherals (I2C, UART, USB, etc.) on the chip, other peripherals supported
via third-party SuperIO chip
3. Applications
■ Advanced Set Top Box (ASTB)
■ Digital Television (DTV)
4. Ordering information
Table 1:
Ordering Information
Type number Package Description
Name
Version
PNX8526EH HBGA456 Plastic thermal enhanced ball grid array package; 456 balls; body 35 x 35 x 1.8
mm; heatsink
SOT610-1
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
2 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
5. Block diagram
166 MHz, 64-bit wide SDRAM
1394
PHY
1394
MMI
TS_OUT*
DV_OUT1
656
DV1 656*
VIP1
AICP1
AICP2
656/HD/VGA
OUTPUT
MODE
656
TS
TS & 656
ROUTER
DV_OUT2
656
DV2 656/TS
DV3 656/TS
VIP2
MSP1-2
MSP3
2
■
I S audio*
AO1-3
SPDO
TS
spdif audio
2
■
I S audio*
AI1-3
TSDMA
MBS
spdif audio
SPDI
UART1-2*
UART3/Sync Serial i/f*
Gen. Purpose I/O
USB host i/f (2 port)
Smartcard1-2
VMPG
12
misc. I/O
DE (2D)
2
I S (2x)
27 MHz
xtal
BOOT, RESET, CLOCK
TM-DBG
DMA
JTAG
TM32 MEDIA PROCESSOR
5 issue, 200 MHz
32 kB I$
PR3940 MIPS CPU
150 MHz
EJTAG
debug
16 kB I$
8 kB D$
R4K MMU
16 kB 2-port D$
128 32-bit regs
PCI
33 MHz, 32-bit PCI 2.2
(includes NAND/nor flash, IDE drive & 68k peripheral capability)
MCE540
I/O marked * can also function as general purpose serial I/O pins
Due to pin sharing either AI3 or AO3 can be active, not both
Fig 1. PNX8526 - block diagram
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
3 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
6. Pinning information
MDB852
handbook, halfpage
AF
AD
AB
Y
AE
AC
AA
W
U
V
PNX8526EH
T
R
P
N
M
K
L
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
ball A1
2
4
6
8
index area
Fig 2. Pin configuration
6.1 Pinning
In the tables that follow the PNX8526 signals have been sorted by functional group.
For quick reference, Table 2 identifies each functional group and gives table location.
Table 2:
Signal groups
Group Name
Functional
Group
Table/Page Number
PCI
Peripheral Controller Interface
Miscellaneous System Interface
Main Memory Interface
General Purpose Input/Output
Serial Communication
Universal Serial Bus
Table 3 on page 5
Table 4 on page 7
Table 5 on page 7
Table 6 on page 9
Table 7 on page 10
Table 8 on page 10
Table 9 on page 11
Table 10 on page 11
Table 11 on page 11
Table 12 on page 13
Table 13 on page 14
Table 14 on page 14
MISC
MMI
GPIO
COM
USB
1394
I2C-bus
AVIF
DVB
IEEE 1394 Port
Serial Communications Port
Audio and Video Interface
Digital Video Bus
PLL
Phase Lock Loop
PWR
Analog Power and Ground / Digital Power and
Ground Connections
TEST
Test Contacts
Table 15 on page 17
Table 16 on page 18
All pins
Pin Descriptions in alpha/numeric order
6.2 Pin description
All pad inputs and I/O have built-in pull-ups (~80 kΩ) and Schmitt trigger input
thresholds. (See Table 19 for maximum ratings).
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
4 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
The following pins do not have pull-ups:
XTALI, PCIx, analog pins, I2C, Main Memory Interface, USB_DPx and USB_DMx.
The following pins do not have Schmitt trigger inputs:
XTALI, analog pins, USB_DPx and USB_DMx.
Table 3:
Peripheral Controller Interface (PCI)
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
AD[16]
AD[15]
AD[14]
AD[13]
AD[12]
AD[11]
AD[10]
AD[09]
AD[08]
AD[07]
AD[06]
AD[05]
AD[04]
AD[03]
AD[02]
AD[01]
AD[00]
C/BE[3]
C/BE[2]
AB1
AB2
AB3
AB4
AC1
AC2
AC3
AD2
AE3
AF4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Address or Data Bit 31
Multiplexed Address or Data Bit 30
Multiplexed Address or Data Bit 29
Multiplexed Address or Data Bit 28
Multiplexed Address or Data Bit 27
Multiplexed Address or Data Bit 26
Multiplexed Address or Data Bit 25
Multiplexed Address or Data Bit 24
Multiplexed Address or Data Bit 23
Multiplexed Address or Data Bit 22
Multiplexed Address or Data Bit 21
Multiplexed Address or Data Bit 20
Multiplexed Address or Data Bit 19
Multiplexed Address or Data Bit 18
Multiplexed Address or Data Bit 17
Multiplexed Address or Data Bit 16
Multiplexed Address or Data Bit 15
Multiplexed Address or Data Bit 14
Multiplexed Address or Data Bit 13
Multiplexed Address or Data Bit 12
Multiplexed Address or Data Bit 11
Multiplexed Address or Data Bit 10
Multiplexed Address or Data Bit 9
Multiplexed Address or Data Bit 8
Multiplexed Address or Data Bit 7
Multiplexed Address or Data Bit 6
Multiplexed Address or Data Bit 5
Multiplexed Address or Data Bit 4
Multiplexed Address or Data Bit 3
Multiplexed Address or Data Bit 2
Multiplexed Address or Data Bit 1
Multiplexed Address or Data Bit 0
Multiplexed Command or Byte Enable 3
Multiplexed Command or Byte Enable 2
AE4
AD4
AE5
AD5
AC5
AC6
AD8
AC8
AF9
AE9
AD9
AC9
AF10
AE10
AC10
AF11
AE11
AD11
AC11
AE12
AD12
AC12
AD1
AF5
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
5 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 3:
Peripheral Controller Interface (PCI)…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
C/BE[1]
C/BE[0]
CLK
AE8
AD10
AA1
AF7
I/O
I/O
I
Multiplexed Command or Byte Enable 1
Multiplexed Command or Byte Enable 0
PCI Bus Clock
DEVSEL
I/O
Device Select is asserted when a target address is decoded and remains
asserted to indicate that a target device is selected.
FRAME
GNT
AF6
Y3
I/O
I/O
Frame is asserted to indicate start of bus transaction and remains
asserted until final data phase begins.
Arbitration Grant is asserted to indicate access to the bus has been
granted. This pin is an input when an external arbiter is used and an
output when using the internal arbiter.
GNT_A
GNT_B
Y4
I/O
I/O
Auxiliary Arbitration Grant_A is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is
configured.
#
#
AA4
Auxiliary Arbitration Grant_B is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is
configured.
IDSEL
INTA
AF3
V4
I/O
I/O
Initialization Device Select provides chip select during configuration read
and write transactions.
Interrupt A is asserted to request an interrupt. This pin may be configured
as an input if the internal PIC is used, or as an output if the external
interrupt controller is used. Polarity in active low.
IRDY
PAR
AE6
AF8
I/O
I/O
Initiator Ready is asserted during writes to indicate valid data on
AD[31:0]. Also asserted during reads to indicate the target is prepared to
accept data. Wait states are inserted until IRDY and TRDY are both
asserted.
Parity supports even parity across the PCI Address/Data Bus AD[31:0])
and Command/ Byte Enable Bus (C/BE[3:0]). The Bus Master drives PAR
for address and write data phases. The Target drives PAR for the read
data phases.
PERR
REQ
AD7
Y2
I/O
I/O
I/O
I/O
Parity Error indicates data parity errors during all PCI transactions except
Special Cycle.
Arbitration Request on PCI Bus. Request is an output when using an
external arbiter and an input when using an internal arbiter.
REQ_A
REQ_B
AA2
AA3
Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal
arbiter is configured.
#
#
Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal
arbiter is configured.
RESET_IN
SERR
W3
I
PCI Bus Global Reset
System Error
AC7
AE7
I/O
I/O
STOP
Stop is asserted to indicate a request from the target for the master to
stop the current transmission.
TRDY
AD6
I/O
Target Ready is asserted during reads to indicate valid data on AD[31:0].
It is asserted during writes to indicate the target is prepared to accept
data. Wait states are inserted until IRDY and TRDY are both asserted.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
6 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 4:
Misc. System Interface (MISC)
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
XIO_A25
AE13
AF13
AF12
AC13
AD13
Y1
I/O
I/O
I/O
I/O
I/O
O
XIO Address Bit 25
#
#
#
#
#
#
XIO_ACK
XIO Acknowledge (EEPROM)
External I/O Select2
External I/O Select1
External I/O Select0
System Reset Output
XIO_SEL[2]
XIO_SEL[1]
XIO_SEL[0]
SYS_RSTN_OUT
Table 5:
Main Memory Interface (MMI)
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
MA[11]
MA[10]
MA[9]
C22
B21
A21
C21
A20
C20
D18
D19
C19
D20
B20
D21
M25
M24
M23
L26
L25
L24
L23
K26
K24
K23
J26
O
Memory Address Bit 11
Memory Address Bit 10
Memory Address Bit 9
Memory Address Bit 8
Memory Address Bit 7
Memory Address Bit 6
Memory Address Bit 5
Memory Address Bit 4
Memory Address Bit 3
Memory Address Bit 2
Memory Address Bit 1
Memory Address Bit 0
Memory Data Bit 63
Memory Data Bit 62
Memory Data Bit 61
Memory Data Bit 60
Memory Data Bit 59
Memory Data Bit 58
Memory Data Bit 57
Memory Data Bit 56
Memory Data Bit 55
Memory Data Bit 54
Memory Data Bit 53
Memory Data Bit 52
Memory Data Bit 51
Memory Data Bit 50
Memory Data Bit 49
Memory Data Bit 48
Memory Data Bit 47
O
O
MA[8]
O
MA[7]
O
MA[6]
O
MA[5]
O
MA[4]
O
MA[3]
O
MA[2]
O
MA[1]
O
MA[0]
O
MD[63]
MD[62]
MD[61]
MD[60]
MD[59]
MD[58]
MD[57]
MD[56]
MD[55]
MD[54]
MD[53]
MD[52]
MD[51]
MD[50]
MD[49]
MD[48]
MD[47]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J25
J24
J23
H26
H25
H23
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
7 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 5:
Main Memory Interface (MMI)…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
MD[46]
MD[45]
MD[44]
MD[43]
MD[42]
MD[41]
MD[40]
MD[39]
MD[38]
MD[37]
MD[36]
MD[35]
MD[34]
MD[33]
MD[32]
MD[31]
MD[30]
MD[29]
MD[28]
MD[27]
MD[26]
MD[25]
MD[24]
MD[23]
MD[22]
MD[21]
MD[20]
MD[19]
MD[18]
MD[17]
MD[16]
MD[15]
MD[14]
MD[13]
MD[12]
MD[11]
MD[10]
MD[09]
MD[08]
G26
G25
G24
G23
F26
F25
F24
F23
E25
E24
D25
D26
E23
D24
C25
A18
B18
C18
A19
B17
C17
D17
A16
B16
C16
D16
A15
B15
C15
D15
C14
A14
D14
A13
B13
C13
D13
A12
B12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Memory Data Bit 46
Memory Data Bit 45
Memory Data Bit 44
Memory Data Bit 43
Memory Data Bit 42
Memory Data Bit 41
Memory Data Bit 40
Memory Data Bit 39
Memory Data Bit 38
Memory Data Bit 37
Memory Data Bit 36
Memory Data Bit 35
Memory Data Bit 34
Memory Data Bit 33
Memory Data Bit 32
Memory Data Bit 31
Memory Data Bit 30
Memory Data Bit 29
Memory Data Bit 28
Memory Data Bit 27
Memory Data Bit 26
Memory Data Bit 25
Memory Data Bit 24
Memory Data Bit 23
Memory Data Bit 22
Memory Data Bit 21
Memory Data Bit 20
Memory Data Bit 19
Memory Data Bit 18
Memory Data Bit 17
Memory Data Bit 16
Memory Data Bit 15
Memory Data Bit 14
Memory Data Bit 13
Memory Data Bit 12
Memory Data Bit 11
Memory Data Bit 10
Memory Data Bit 09
Memory Data Bit 08
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
8 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 5:
Main Memory Interface (MMI)…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
MD[07]
MD[06]
MD[05]
MD[04]
MD[03]
MD[02]
MD[01]
MD[00]
MDQM[7]
MDQM[6]
MDQM[5]
MDQM[4]
MDQM[3]
MDQM[2]
MDQM[1]
MDQM[0]
MBA[1]
MBA[0]
MCKE
C12
A11
B11
D11
A10
C11
B10
C10
K25
H24
E26
A24
A17
B14
D12
A9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Memory Data Bit 07
Memory Data Bit 06
Memory Data Bit 05
Memory Data Bit 04
Memory Data Bit 03
Memory Data Bit 02
Memory Data Bit 01
Memory Data Bit 00
SDRAM Control Bit 7
SDRAM Control Bit 6
SDRAM Control Bit 5
SDRAM Control Bit 4
SDRAM Control Bit 3
SDRAM Control Bit 2
SDRAM Control Bit 1
SDRAM Control Bit 0
SDRAM Bank Select
SDRAM Bank Select
Memory Clock Enable
Memory Clock
O
O
O
O
O
O
O
D22
B22
C23
C26
B19
A22
B23
A23
B24
O
O
O
MCLK[1]
MCLK[0]
MCS
O
O
Memory Clock
O
Memory Chip Select
EDODRAM Row Address Strobe
Memory Column Address Select
Memory Write Enable
MRAS
O
MCAS
O
MWE
O
Table 6:
General Purpose Input/Output (GPIO)
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
GPIO[11]
GPIO[10]
GPIO[9]
GPIO[8]
GPIO[7]
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
N26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose Input/Output Bit 11
General Purpose Input/Output Bit 10
General Purpose Input/Output Bit 9
General Purpose Input/Output Bit 8
General Purpose Input/Output Bit 7
General Purpose Input/Output Bit 6
General Purpose Input/Output Bit 5
General Purpose Input/Output Bit 4
General Purpose Input/Output Bit 3
#
#
#
#
#
#
#
#
#
N24
N23
M26
AE14
AF14
AD14
AC14
C5
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
9 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 6:
General Purpose Input/Output (GPIO)…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
GPIO[2]
GPIO[1]
GPIO[0]
B4
D5
C4
I/O
I/O
I/O
General Purpose Input/Output Bit 2
General Purpose Input/Output Bit 1
General Purpose Input/Output Bit 0
#
#
#
Table 7:
Serial Communication (COM)
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
UA1_TX
U24
U25
T23
U26
T24
T25
T26
R23
R24
R25
R26
P23
P24
P26
P25
N25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
UART1 Transmit
#
#
#
#
#
#
UA1_RX
UART1 Receive
UA2_TX
UART2 Transmit
UA2_RX
UART2 Receive
UA2_RTSN
UA2_CTSN
SC1_DA
UART2 Request To Send
UART2 Clear To Send
Smart Card1 Data
SC1_CMD
SC1_RST
SC1_OFFN
SC1_SCCK
SC2_DA
Smart Card1 Command
Smart Card1 Reset
O
I
Smart Card1 Off
O
Smart Card1 Bit Clock
Smart Card2 Data
I/O
O
SC2_CMD
SC2_RST
SC2_OFFN
SC2_SCCK
Smart Card2 Command
Smart Card2 Reset
O
I
Smart Card2 Off
O
Smart Card2 Bit Clock
Synchronous Serial Interface Clock Input
Synchronous Serial Interface Frame Sync
Synchronous Serial Interface Receive
Synchronous Serial Interface Transmit
SSI_SCLK_CTSN V1
I/O
I/O
I/O
I/O
#
#
#
#
SSI_FS_RTSN
SSI_RXD
V2
U4
V3
SSI_TXD
Table 8:
Universal Serial Bus (USB)
Symbol
Pin
A5
B6
C6
D7
W1
Type
I/O
I/O
I/O
I/O
O
Description
USB_DP[1]
USB_DP[0]
USB_DM[0]
USB_DM[1]
USB_PWR
Data Plus Bit 1
Data Plus Bit 0
Data Minus Bit 0
Data Minus Bit 1
USB port power On/Off
0 = Power on
1 = Power off
USB_OVRCUR
W2
I
Indicates over current being drawn by a USB device
0 = Over current detected
1 = No over current
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
10 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 9:
IEEE 1394 port
Symbol
Pin
B9
D10
C9
A8
B8
D9
C8
A7
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
PHY_D[7]
PHY_D[6]
PHY_D[5]
PHY_D[4]
PHY_D[3]
PHY_D[2]
PHY_D[1]
PHY_D[0]
PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets.
PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets.
PHY Control Bit 1. Indicates the mode for data on the Din port.
PHY Control Bit 0. Indicates the mode for data on the Din port.
PHY_CTL[1]
PHY_CTL[0]
PHY_LREQ
B7
C7
B5
Used by the link to make bus requests and to access PHY registers. This is a serial
bus. A train of pulses is sent on this signal.
PHY_ISO_N
A6
I
Signals which type of isolation mode is used at the PHY-Link interface.
0 = This is 1394-1995 Annex J type isolation. Enables differentiator circuitry.
1 = Direct connection or single capacitor isolation mode. This will disable the
differentiator circuitry.
CLK_L1394
D8
I
System clock. 49.152 MHz input
Table 10: Serial communication port (I2C)
Symbol
Pin
D6
A4
H1
K4
Type
I/O
Description
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
Serial Communications Port (I2C-bus) Clock
Serial Communications Port (I2C-bus) Data
Serial Communications Port (I2C-bus) Clock
Serial Communications Port (I2C-bus) Data
I/O
I/O
I/O
Table 11: Audio and video interface
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type Description
Alternate
Function
DV_OUT1[9]
DV_OUT1[8]
DV_OUT1[7]
DV_OUT1[6]
DV_OUT1[5]
DV_OUT1[4]
DV_OUT1[3]
DV_OUT1[2]
DV_OUT1[1]
DV_OUT1[0]
DV_OUT2[9]
DV_OUT2[8]
DV_OUT2[7]
M2
M1
N4
N3
N1
N2
P2
P1
P4
P3
R2
R4
R3
O
O
O
O
O
O
O
O
O
O
O
O
O
Digital Video Output1, Bit 9 for primary display channel from AICP
Digital Video Output1, Bit 8 for primary display channel from AICP
Digital Video Output1, Bit 7 for primary display channel from AICP
Digital Video Output1, Bit 6 for primary display channel from AICP
Digital Video Output1, Bit 5 for primary display channel from AICP
Digital Video Output1, Bit 4 for primary display channel from AICP
Digital Video Output1, Bit 3 for primary display channel from AICP
Digital Video Output1, Bit 2 for primary display channel from AICP
Digital Video Output1, Bit 1 for primary display channel from AICP
Digital Video Output1, Bit 0 for primary display channel from AICP
Digital Video Output2, Bit 9 for secondary display channel from AICP
Digital Video Output2, Bit 8 for secondary display channel from AICP
Digital Video Output2, Bit 7 for secondary display channel from AICP
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
11 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 11: Audio and video interface…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type Description
Alternate
Function
DV_OUT2[6]
DV_OUT2[5]
DV_OUT2[4]
DV_OUT2[3]
DV_OUT2[2]
DV_OUT2[1]
DV_OUT2[0]
DV_CLK1
T1
T2
T3
U1
T4
U2
U3
M3
R1
L1
O
O
O
O
O
O
O
O
O
O
I/O
O
Digital Video Output2, Bit 6 for secondary display channel from AICP
Digital Video Output2, Bit 5 for secondary display channel from AICP
Digital Video Output2, Bit 4 for secondary display channel from AICP
Digital Video Output2, Bit 3 for secondary display channel from AICP
Digital Video Output2, Bit 2 for secondary display channel from AICP
Digital Video Output2, Bit 1 for secondary display channel from AICP
Digital Video Output2, Bit 0 for secondary display channel from AICP
Digital Video Clock1 for primary display channel from AICP
Digital Video Clock2 for secondary display channel from AICP
Horizontal Sync for primary display
Vertical Sync for primary display
Blanking for primary display
DV_CLK2
HSYNC
VSYNC
L2
BLANK
M4
I2S_IN1_OSCLK
I2S_IN1_SCK
I2S_IN1_WS
I2S_IN1_SD
I2S_IN2_OSCLK
I2S_IN2_SCK
I2S_IN2_WS
I2S_IN2_SD
I2S_IO_OSCLK
I2S_IO_SCK
I2S_IO_WS
AD20 O
AC19 I/O
AF21 I/O
AE21 I
Audio IN1OverSample Clock
Audio IN1 Serial Clock
Audio IN1 Word Select
Audio IN1 Data
AD21 O
AC20 I/O
AF22 I/O
AE22 I
Audio IN2 OverSample Clock
Audio IN2 Serial Clock
Audio IN2 Word Select
Audio IN2 Data
AF15 I/O
AE15 I/O
AC15 I/O
AD15 I/O
AF16 I/O
AE16 I/O
AD16 I/O
Audio IN/OUT OverSample Clock
Audio IN/OUT Serial Clock
#
#
#
#
#
#
#
Audio IN/OUT Word Select
I2S_IO_SD[3]
I2S_IO_SD[2]
I2S_IO_SD[1]
I2S_IO_SD[0[
I2S_OUT1_OSCLK
I2S_OUT1_SCK
I2S_OUT1_WS
I2S_OUT1_SD
I2S_OUT2_OSCLK
I2S_OUT2_SCK
I2S_OUT2_WS
I2S_OUT2_SD
SPDIF_IN
Audio IN/OUT Data Bit 3
Audio IN/OUT Data Bit 2
Audio IN/OUT Data Bit 1
Audio IN/OUT Data Bit 0
K3
J1
J3
J2
K2
L3
K1
L4
O
Audio OUT1 OverSample Clock
Audio OUT1 Serial Clock
I/O
I/O
O
Audio OUT1 Word Select
Audio OUT1 Data
O
Audio OUT2OverSample Clock
#
#
#
#
I/O
I/O
O
Audio OUT2 Serial Clock
Audio OUT2 Word Select
Audio OUT2 Data
AF17 I
Multi-ch/SPDIF Input
SPDIF_OUT
AC16 O
Multi-ch/SPDIF Output
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
12 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 12: Digital video bus
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
DV1_DATA[9]
DV1_DATA[8]
DV1_DATA[7]
DV1_DATA[6]
DV1_DATA[5]
DV1_DATA[4]
DV1_DATA[3]
DV1_DATA[2]
DV1_DATA[1]
DV1_DATA[0]
DV1_VALID
DV1_CLK
AE17
AD17
AF18
AC17
AE18
AD18
AF19
AE19
AC18
AD19
AF20
AE20
AF23
AC21
AD22
AE23
AC22
AD23
AE24
AF24
AD24
AD26
AD25
AC24
W23
I/O
ITU-656 VIP Data Bit 9 (Most Significant Bit)
ITU-656 VIP Data Bit 8
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
I/O
I/O
ITU-656 VIP Data Bit 7
I/O
ITU-656 VIP Data Bit 6
I/O
ITU-656 VIP Data Bit 5
I/O
ITU-656 VIP Data Bit 4
I/O
ITU-656 VIP Data Bit 3
I/O
ITU-656 VIP Data Bit 2
I/O
ITU-656 VIP Data Bit 1
I/O
ITU-656 VIP Data Bit 0 (Least Significant Bit)
ITU-656 VIP Data Valid
I/O
I/O
ITU-656 VIP Data Clock
DV2_DATA[7]
DV2_DATA[6]
DV2_DATA[5]
DV2_DATA[4]
DV2_DATA[3]
DV2_DATA[2]
DV2_DATA[1]
DV2_DATA[0]
DV2_SOP
I
Digital Video Transport Stream2 Data Bit 7
Digital Video Transport Stream2 Data Bit 6
Digital Video Transport Stream2 Data Bit 5
Digital Video Transport Stream2 Data Bit 4
Digital Video Transport Stream2 Data Bit 3
Digital Video Transport Stream2 Data Bit 2
Digital Video Transport Stream2 Data Bit 1
Digital Video Transport Stream2 Data Bit 0
Digital Video Transport Stream2 Start of Packet
Digital Video Transport Stream2 Error
Digital Video Transport Stream2 Data Valid
Digital Video Transport Stream2 Clock
Digital Video Transport Stream3 Data Bit 7
Digital Video Transport Stream3 Data Bit 6
Digital Video Transport Stream3 Data Bit 5
Digital Video Transport Stream3 Data Bit 4
Digital Video Transport Stream3 Data Bit 3
Digital Video Transport Stream3 Data Bit 2
Digital Video Transport Stream3 Data Bit 1
Digital Video Transport Stream3 Data Bit 0
Digital Video Transport Stream3 Start of Packet
Digital Video Transport Stream3 Error
Digital Video Transport Stream3 Data Valid
Digital Video Transport Stream3 Clock
Transport Stream Data Bit 7
I
I
I
I
I
I
I
I
DV2_ERR
I
DV2_VALID
DV2_CLK
I
I
DV3_DATA[7]
DV3_DATA[6]
DV3_DATA[5]
DV3_DATA[4]
DV3_DATA[3]
DV3_DATA[2]
DV3_DATA[1]
DV3_DATA[0]
DV3_SOP
I
Y24
I
Y25
I
Y26
I
W24
I
V23
I
W25
I
W26
I
V24
I
DV3_ERR
U23
I
DV3_VALID
DV3_CLK
V25
I
V26
I
TS_DATA[7]
TS_DATA[6]
TS_DATA[5]
AB23
AC25
AB24
I/O
I/O
I/O
Transport Stream Data Bit 6
Transport Stream Data Bit 5
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
13 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 12: Digital video bus…continued
# indicates multiplexed signal, see Section 6.2.1 for more details.
Symbol
Pin
Type
Description
Alternate
Function
TS_DATA[4]
TS_DATA[3]
TS_DATA[2]
TS_DATA[1]
TS_DATA[0]
TS_SOP
AA23
AC26
AB25
AB26
Y23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Transport Stream Data Bit 4
#
#
#
#
#
#
#
#
Transport Stream Data Bit 3
Transport Stream Data Bit 2
Transport Stream Data Bit 1
Transport Stream Data Bit 0
AA24
AA25
AA26
Transport Stream Start of Packet (Parallel/Serial)
Transport Stream Data Valid (Parallel/Serial)
Transport Stream Clock (Parallel/Serial)
TS_VALID
TS_CLK
Table 13: Phase Lock Loop (PLL)
Symbol
XTALI
Pin Type Description
C2
D3
W4
I
PLL Reference Crystal Input
XTALO
PLL_OUT
O
O
PLL Reference Crystal Feedback Driver
General Purpose PLL Clock Output
Table 14: Analog and digital power (PWR)
Symbol
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
Pin
Description
AB18
AB17
AB14
AB13
AB12
AB9
AB8
N5
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
P5
U5
V5
K5
J5
E14
E13
E10
E9
E15
E18
E19
U22
V22
P22
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
14 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 14: Analog and digital power (PWR)…continued
Symbol
Pin
N22
K22
J22
D1
Description
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC1
VDDC2
VDDC2
VSS
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
E2
System 1.26 Volts
E1
System 1.26 Volts
G4
System 1.26 Volts
F3
System 1.26 Volts
F2
System 1.26 Volts
F1
System 1.26 Volts
H4
System 1.26 Volts
G3
System 1.26 Volts
E4
System 1.26 Volts (Analog Power 1.728 GHz PLL)
System 1.26 Volts (Analog Power 1.728 GHz PLL)
System Ground (Analog Ground 1.728 GHz PLL)
System Ground (Analog Ground 1.728 GHz PLL)
System 3.3 Volts
E3
D2
VSS
F4
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
AB6
AB7
AB10
AB11
AB16
AB19
AB20
E12
E11
E8
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
E7
System 3.3 Volts
E16
E17
E20
E21
M22
L22
H22
G22
R22
T22
W22
Y22
T5
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
R5
System 3.3 Volts
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
15 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 14: Analog and digital power (PWR)…continued
Symbol
Pin
Description
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M5
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts
System 3.3 Volts (CAB)
System 3.3 Volts (CAB)
System 3.3 Volts (TM-PLL)
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
L5
W5
Y5
G5
H5
AB15
AF25
AF26
AE26
AE25
AC23
AB22
AB21
AA22
F22
E22
D23
C24
B25
A25
A26
B26
L15
L14
L13
L12
L11
M11
N11
P11
R11
T11
T12
T13
R13
R14
T14
T15
T16
R16
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
16 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 14: Analog and digital power (PWR)…continued
Symbol
Pin
AA5
AB5
AC4
AD3
AE2
AE1
AF1
AF2
F5
Description
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
System Ground
E5
E6
D4
B2
A2
A1
B1
R15
R12
P12
P13
N13
N14
P14
P15
P16
N16
N15
N12
M12
M13
M14
L16
M16
M15
Table 15: Test
Symbol
Pin Type Description
DBG_TDI
DBG_TDO
DBG_TCK
DBG_TMS
A3
B3
C3
C1
I
PR3940 Debug Port Data In
PR3940 Debug Port Data Out
PR3940 Debug Port Clock
O
I
I
PR3940 Debug Port Mode Select
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
17 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 15: Test…continued
Symbol Pin Type Description
JTAG_TRST G2
JTAG_TDI J4
I
JTAG Port Reset
JTAG Data IN
I
JTAG_TDO H2
JTAG_TCK G1
JTAG_TMS H3
O
I
JTAG Data OUT
JTAG Data Clock
JTAG Data Mode Select
I
Table 16: All pins
Symbol
Pin
A1
A2
A3
A4
A5
A6
Group Type
Description
VSS
PWR
PWR
TEST
-
-
I
System Ground
VSS
System Ground
DBG_TDI
I2C_SDA
USB_DP[1]
PHY_ISO_N
PR3940 Debug Port Data In
Serial Communications Port (I2C-bus) Data
I2C-bus I/O
USB
1394
I/O
I
Data Plus Bit 1
Signals type of isolation mode used at the PHY-Link interface.
0 = 1394-1995 Annex J type isolation. Enables differentiator circuitry.
1 = Direct connection or single capacitor isolation mode. This will
disable the differentiator circuitry.
PHY_D[0]
PHY_D[4]
MDQM[0]
MD[03]
MD[06]
MD[09]
MD[13]
MD[15]
MD[20]
MD[24]
MDQM[3]
MD[31]
MD[28]
MA[7]
A7
1394
1394
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
PWR
PWR
PWR
PWR
TEST
GPIO
I/O
I/O
O
PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets.
PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets.
SDRAM Control Bit 0
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Memory Data Bit 03
Memory Data Bit 06
Memory Data Bit 09
Memory Data Bit 13
Memory Data Bit 15
Memory Data Bit 20
Memory Data Bit 24
SDRAM Control Bit 3
I/O
I/O
O
Memory Data Bit 31
Memory Data Bit 28
Memory Address Bit 7
MA[9]
O
Memory Address Bit 9
MCS
O
Memory Chip Select
MCAS
MDQM[4]
VSS
O
Memory Column Address Select
SDRAM Control Bit 4
O
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
B2
-
System Ground
DBG_TDO
GPIO[2]
B3
O
PR3940 Debug Port Data Out
General Purpose Input/Output Bit 2
B4
I/O
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
18 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
Pin
Group Type
Description
PHY_LREQ
B5
1394
O
Used by the link to make bus requests and to access PHY registers.
This is a serial bus. A train of pulses is sent on this signal.
USB_DP[0]
PHY_CTL[1]
PHY_D[3]
PHY_D[7]
MD[01]
B6
USB
1394
1394
1394
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
PWR
PWR
TEST
PLL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Data Plus Bit 0
B7
PHY Control Bit 1. Indicates the mode for data on the Din port.
PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets.
Memory Data Bit 01
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
MD[05]
Memory Data Bit 05
MD[08]
Memory Data Bit 08
MD[12]
Memory Data Bit 12
MDQM[2]
MD[19]
SDRAM Control Bit 2
I/O
I/O
I/O
I/O
O
Memory Data Bit 19
MD[23]
Memory Data Bit 23
MD[27]
Memory Data Bit 27
MD[30]
Memory Data Bit 30
MCLK[0]
MA[1]
Memory Clock
O
Memory Address Bit 1
MA[10]
O
Memory Address Bit 10
MBA[0]
MRAS
O
SDRAM Bank Select
O
EDODRAM Row Address Strobe
Memory Write Enable
MWE
O
VSS
-
System Ground
VSS
-
System Ground
DBG_TMS
XTALI
I
PR3940 Debug Port Mode Select
PLL Reference Crystal Input
PR3940 Debug Port Clock
General Purpose Input/Output Bit 0
General Purpose Input/Output Bit 3
Data Minus Bit 0
C2
I
DBG_TCK
GPIO[0]
GPIO[3]
USB_DM[0]
PHY_CTL[0]
PHY_D[1]
PHY_D[5]
MD[00]
C3
TEST
GPIO
GPIO
USB
1394
1394
1394
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
I
C4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C5
C6
C7
PHY Control Bit 0. Indicates the mode for data on the Din port.
PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets.
PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets.
Memory Data Bit 00
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
MD[02]
Memory Data Bit 02
MD[07]
Memory Data Bit 07
MD[11]
Memory Data Bit 11
MD[16]
Memory Data Bit 16
MD[18]
Memory Data Bit 18
MD[22]
Memory Data Bit 22
MD[26]
Memory Data Bit 26
MD[29]
Memory Data Bit 29
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
19 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
MA[3]
Pin
C19
C20
C21
C22
C23
C24
C25
C26
D1
Group Type
Description
MMI
MMI
MMI
MMI
MMI
PWR
MMI
MMI
PWR
PWR
PLL
O
O
O
O
O
-
Memory Address Bit 3
MA[6]
Memory Address Bit 6
MA[8]
Memory Address Bit 8
MA[11]
MCKE
VSS
Memory Address Bit 11
Memory Clock Enable
System Ground
MD[32]
MCLK[1]
VDDC
I/O
O
-
Memory Data Bit 32
Memory Clock
System 1.26 Volts
VSS
D2
-
System Ground (Analog Ground 1.728 GHz PLL)
PLL Reference Crystal Feedback Driver
System Ground
XTALO
VSS
D3
O
-
D4
PWR
GPIO[1]
I2C_SCL
USB_DM[1]
CLK_L1394
PHY_D[2]
PHY_D[6]
MD[04]
MDQM[1]
MD[10]
MD[14]
MD[17]
MD[21]
MD[25]
MA[5]
D5
GPIO
I2C-bus I/O
I/O
General Purpose Input/Output Bit 1
Serial Communications Port (I2C-bus) Clock
Data Minus Bit 1
D6
D7
USB
1394
1394
1394
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
MMI
PWR
MMI
MMI
MMI
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I/O
I
D8
System clock. 49.152 MHz input
PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets.
Memory Data Bit 04
D9
I/O
I/O
I/O
O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
SDRAM Control Bit 1
I/O
I/O
I/O
I/O
I/O
O
Memory Data Bit 10
Memory Data Bit 14
Memory Data Bit 17
Memory Data Bit 21
Memory Data Bit 25
Memory Address Bit 5
MA[4]
O
Memory Address Bit 4
MA[2]
O
Memory Address Bit 2
MA[0]
O
Memory Address Bit 0
MBA[1]
VSS
O
SDRAM Bank Select
-
System Ground
MD[33]
MD[36]
MD[35]
VDDC1
I/O
I/O
I/O
-
Memory Data Bit 33
Memory Data Bit 36
Memory Data Bit 35
System 1.26 Volts
VDDC1
E2
-
System 1.26 Volts
VDDC2
E3
-
System 1.26 Volts (Analog Power 1.728 GHz PLL)
System 1.26 Volts (Analog Power 1.728 GHz PLL)
System Ground
VDDC2
E4
-
VSS
E5
-
VSS
E6
-
System Ground
VDD1
E7
-
System 3.3 Volts
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
20 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
VDD1
Pin
E8
Group Type
Description
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
MMI
-
System 3.3 Volts
VDDC1
VDDC1
VDD1
E9
-
System 1.26 Volts
System 1.26 Volts
System 3.3 Volts
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
-
-
VDD1
-
System 3.3 Volts
VDDC1
VDDC1
VDDC1
VDD1
-
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System 3.3 Volts
-
-
-
VDD1
-
System 3.3 Volts
VDDC1
VDDC1
VDD1
-
System 1.26 Volts
System 1.26 Volts
System 3.3 Volts
-
-
VDD1
-
System 3.3 Volts
VSS
-
System Ground
MD[34]
MD[37]
MD[38]
MDQM[5]
VDDC1
VDDC1
VDDC1
VSS
I/O
I/O
I/O
O
-
Memory Data Bit 34
Memory Data Bit 37
Memory Data Bit 38
SDRAM Control Bit 5
System 1.26 Volts
System 1.26 Volts
System 1.26 Volts
System Ground (Analog Ground 1.728 GHz PLL)
System Ground
MMI
MMI
MMI
PWR
PWR
PWR
PWR
PWR
PWR
MMI
F2
-
F3
-
F4
-
VSS
F5
-
VSS
F22
F23
F24
F25
F26
G1
-
System Ground
MD[39]
MD[40]
MD[41]
MD[42]
JTAG_TCK
JTAG_TRST
VDDC1
VDDC1
VDD2
I/O
I/O
I/O
I/O
I
Memory Data Bit 39
Memory Data Bit 40
Memory Data Bit 41
Memory Data Bit 42
JTAG Data Clock
MMI
MMI
MMI
TEST
TEST
PWR
PWR
PWR
PWR
MMI
G2
I
JTAG Port Reset
G3
-
System 1.26 Volts
System 1.26 Volts
System 3.3 Volts (CAB)
System 3.3 Volts
G4
-
G5
-
VDD1
G22
G23
G24
G25
G26
H1
-
MD[43]
MD[44]
MD[45]
MD[46]
I2C2_SCL
JTAG_TDO
I/O
I/O
I/O
I/O
Memory Data Bit 43
Memory Data Bit 44
Memory Data Bit 45
Memory Data Bit 46
Serial Communications Port (I2C-bus) Clock
JTAG Data OUT
MMI
MMI
MMI
I2C-bus I/O
H2
TEST
O
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
21 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
JTAG_TMS
VDDC1
Pin
H3
Group Type
Description
TEST
PWR
PWR
PWR
MMI
I
JTAG Data Mode Select
System 1.26 Volts
H4
-
VDD2
H5
-
System 3.3 Volts (CAB)
System 3.3 Volts
VDD1
H22
H23
H24
H25
H26
J1
-
MD[47]
I/O
O
Memory Data Bit 47
SDRAM Control Bit 6
Memory Data Bit 48
Memory Data Bit 49
Audio OUT1 Serial Clock
Audio OUT1 Data
MDQM[6]
MD[48]
MMI
MMI
I/O
I/O
I/O
O
MD[49]
MMI
I2S_OUT1_SCK
I2S_OUT1_SD
I2S_OUT1_WS
JTAG_TDI
VDDC1
AVIF
AVIF
AVIF
TEST
PWR
PWR
MMI
J2
J3
I/O
I
Audio OUT1 Word Select
JTAG Data IN
J4
J5
-
System 1.26 Volts
VDDC1
J22
J23
J24
J25
J26
K1
-
System 1.26 Volts
MD[50]
I/O
I/O
I/O
I/O
I/O
O
Memory Data Bit 50
Memory Data Bit 51
Memory Data Bit 52
Memory Data Bit 53
Audio OUT2 Word Select
Audio OUT2 OverSample Clock
Audio OUT1 OverSample Clock
Serial Communications Port (I2C-bus) Data
System 1.26 Volts
MD[51]
MMI
MD[52]
MMI
MD[53]
MMI
I2S_OUT2_WS
I2S_OUT2_OSCLK
I2S_OUT1_OSCLK
I2C2_SDA
VDDC1
AVIF
AVIF
AVIF
K2
K3
O
K4
I2C-bus I/O
K5
PWR
PWR
MMI
-
VDDC1
K22
K23
K24
K25
K26
L1
-
System 1.26 Volts
MD[54]
I/O
I/O
O
I/O
O
I/O
I/O
O
-
Memory Data Bit 54
Memory Data Bit 55
SDRAM Control Bit 7
Memory Data Bit 56
Horizontal Sync for primary display
Vertical Sync for primary display
Audio OUT2 Serial Clock
Audio OUT2 Data
MD[55]
MMI
MDQM[7]
MD[56]
MMI
MMI
HSYNC
VSYNC
AVIF
AVIF
AVIF
AVIF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
MMI
L2
I2S_OUT2_SCK
I2S_OUT2_SD
VDD1
L3
L4
L5
System 3.3 Volts
VSS
L11
L12
L13
L14
L15
L16
L22
L23
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDD1
-
System 3.3 Volts
MD[57]
I/O
Memory Data Bit 57
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
22 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
MD[58]
MD[59]
MD[60]
DV_OUT1[8]
DV_OUT1[9]
DV_CLK1
BLANK
VDD1
Pin
L24
L25
L26
M1
Group Type
Description
MMI
I/O
I/O
I/O
O
O
O
O
-
Memory Data Bit 58
MMI
Memory Data Bit 59
MMI
Memory Data Bit 60
AVIF
AVIF
AVIF
AVIF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
MMI
Digital Video Output1, Bit 8 for primary display channel from AICP
Digital Video Output1, Bit 9 for primary display channel from AICP
Digital Video Clock1 for primary display channel from AICP
Blanking for primary display
M2
M3
M4
M5
System 3.3 Volts
VSS
M11
M12
M13
M14
M15
M16
M22
M23
M24
M25
M26
N1
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDD1
-
System 3.3 Volts
MD[61]
MD[62]
MD[63]
GPIO[8]
DV_OUT1[5]
DV_OUT1[4]
DV_OUT1[6]
DV_OUT1[7]
VDDC1
I/O
I/O
I/O
I/O
O
O
O
O
-
Memory Data Bit 61
MMI
Memory Data Bit 62
MMI
Memory Data Bit 63
GPIO
AVIF
AVIF
AVIF
AVIF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GPIO
GPIO
COM
GPIO
AVIF
AVIF
AVIF
AVIF
PWR
PWR
General Purpose Input/Output Bit 8
Digital Video Output1, Bit 5 for primary display channel from AICP
Digital Video Output1, Bit 4 for primary display channel from AICP
Digital Video Output1, Bit 6 for primary display channel from AICP
Digital Video Output1, Bit 7 for primary display channel from AICP
System 1.26 Volts
N2
N3
N4
N5
VSS
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P1
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDDC1
-
System 1.26 Volts
GPIO[9]
GPIO[10]
SC2_SCCK
GPIO[11]
DV_OUT1[2]
DV_OUT1[3]
DV_OUT1[0]
DV_OUT1[1]
VDDC1
I/O
I/O
O
I/O
O
O
O
O
-
General Purpose Input/Output Bit 9
General Purpose Input/Output Bit 10
Smart Card2 Bit Clock
General Purpose Input/Output Bit 11
Digital Video Output1, Bit 2 for primary display channel from AICP
Digital Video Output1, Bit 3 for primary display channel from AICP
Digital Video Output1, Bit 0 for primary display channel from AICP
Digital Video Output1, Bit 1 for primary display channel from AICP
System 1.26 Volts
P2
P3
P4
P5
VSS
P11
-
System Ground
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
23 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
VSS
Pin
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
Group Type
Description
PWR
PWR
PWR
PWR
PWR
PWR
COM
COM
COM
COM
AVIF
AVIF
AVIF
AVIF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
COM
COM
COM
COM
AVIF
AVIF
AVIF
AVIF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
COM
COM
COM
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDDC1
-
System 1.26 Volts
SC2_DA
SC2_CMD
SC2_OFFN
SC2_RST
DV_CLK2
DV_OUT2[9]
DV_OUT2[7]
DV_OUT2[8]
VDD1
I/O
O
I
Smart Card2 Data
Smart Card2 Command
Smart Card2 Off
O
O
O
O
O
-
Smart Card2 Reset
Digital Video Clock2 for secondary display channel from AICP
R2
Digital Video Output2, Bit 9 for secondary display channel from AICP
R3
Digital Video Output2, Bit 7 for secondary display channel from AICP
R4
Digital Video Output2, Bit 8 for secondary display channel from AICP
R5
System 3.3 Volts
VSS
R11
R12
R13
R14
R15
R16
R22
R23
R24
R25
R26
T1
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDD1
-
System 3.3 Volts
SC1_CMD
SC1_RST
SC1_OFFN
SC1_SCCK
DV_OUT2[6]
DV_OUT2[5]
DV_OUT2[4]
DV_OUT2[2]
VDD1
O
O
I
Smart Card1 Command
Smart Card1 Reset
Smart Card1 Off
O
O
O
O
O
-
Smart Card1 Bit Clock
Digital Video Output2, Bit 6 for secondary display channel from AICP
T2
Digital Video Output2, Bit 5 for secondary display channel from AICP
T3
Digital Video Output2, Bit 4 for secondary display channel from AICP
T4
Digital Video Output2, Bit 2 for secondary display channel from AICP
T5
System 3.3 Volts
System Ground
VSS
T11
T12
T13
T14
T15
T16
T22
T23
T24
T25
-
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VSS
-
System Ground
VDD1
-
System 3.3 Volts
UART2 Transmit
UART2 Request To Send
UART2 Clear To Send
UA2_TX
UA2_RTSN
UA2_CTSN
I/O
I/O
I/O
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
24 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
Pin
T26
U1
Group Type
Description
SC1_DA
COM
AVIF
AVIF
AVIF
COM
PWR
PWR
DVB
I/O
O
O
O
I/O
-
Smart Card1 Data
DV_OUT2[3]
DV_OUT2[1]
DV_OUT2[0]
SSI_RXD
VDDC1
Digital Video Output2, Bit 3 for secondary display channel from AICP
Digital Video Output2, Bit 1 for secondary display channel from AICP
Digital Video Output2, Bit 0 for secondary display channel from AICP
Synchronous Serial Interface Receive
System 1.26 Volts
U2
U3
U4
U5
VDDC1
U22
U23
U24
U25
U26
V1
-
System 1.26 Volts
DV3_ERR
UA1_TX
I
Digital Video Transport Stream3 Error
UART1 Transmit
COM
COM
COM
COM
COM
COM
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
UA1_RX
UART1 Receive
UA2_RX
UART2 Receive
SSI_SCLK_CTSN
SSI_FS_RTSN
SSI_TXD
INTA
Synchronous Serial Interface CLock
Synchronous Serial Interface Frame Sync
Synchronous Serial Interface Transmit
Interrupt Acknowledge is asserted to request an interrupt.
System 1.26 Volts
V2
V3
V4
VDDC1
V5
PWR
PWR
DVB
VDDC1
V22
V23
V24
V25
V26
W1
-
System 1.26 Volts
DV3_DATA[2]
DV3_SOP
DV3_VALID
DV3_CLK
USB_PWR
I
Digital Video Transport Stream3 Data Bit 2
Digital Video Transport Stream3 Start of Packet
Digital Video Transport Stream3 Data Valid
Digital Video Transport Stream3 Clock
USB port power On/Off
DVB
I
DVB
I
DVB
I
USB
O
0 = Power on
1 = Power off
USB_OVRCUR
W2
USB
I
Indicates over current being drawn by a USB device:
0 = Over current detected
1 = No over current
RESET_IN
PLL_OUT
VDD1
W3
PCI
I
PCI Bus Global Reset
W4
PLL
O
General Purpose PLL Clock Output
System 3.3 Volts
W5
PWR
PWR
DVB
DVB
DVB
DVB
MISC
PCI
-
VDD1
W22
W23
W24
W25
W26
Y1
-
System 3.3 Volts
DV3_DATA[7]
DV3_DATA[3]
DV3_DATA[1]
DV3_DATA[0]
SYS_RSTN_OUT
REQ
I
Digital Video Transport Stream3 Data Bit 7
Digital Video Transport Stream3 Data Bit 3
Digital Video Transport Stream3 Data Bit 1
Digital Video Transport Stream3 Data Bit 0
System Reset Output
I
I
I
O
I/O
Y2
Arbitration Request on PCI Bus. Request is an output when using an
external arbiter and an input when using an internal arbiter.
GNT
Y3
PCI
I/O
Arbitration Grant is asserted to indicate access to the bus has been
granted. This pin is an input when an external arbiter is used and an
output when using the internal arbiter.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
25 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
Pin
Group Type
Description
GNT_A
Y4
PCI
I/O
Auxiliary Arbitration Grant_A is asserted to indicate bus access has
been granted to an external PCI master. Used where internal arbiter is
configured.
VDD1
Y5
PWR
PWR
DVB
DVB
DVB
DVB
PCI
-
System 3.3 Volts
VDD1
Y22
Y23
Y24
Y25
Y26
AA1
AA2
-
System 3.3 Volts
TS_DATA[0]
DV3_DATA[6]
DV3_DATA[5]
DV3_DATA[4]
CLK
I/O
Transport Stream Data Bit 0
Digital Video Transport Stream3 Data Bit 6
Digital Video Transport Stream3 Data Bit 5
Digital Video Transport Stream3 Data Bit 4
PCI Bus Clock
I
I
I
I
REQ_A
PCI
I/O
Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where
internal
arbiter is configured.
REQ_B
GNT_B
AA3
AA4
PCI
PCI
I/O
I/O
Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where
internal
arbiter is configured.
Auxiliary Arbitration Grant_B is asserted to indicate bus access has
been granted to an external PCI master. Used where internal arbiter is
configured.
VSS
AA5
PWR
PWR
DVB
DVB
DVB
DVB
PCI
-
System Ground
VSS
AA22
AA23
AA24
AA25
AA26
AB1
-
System Ground
TS_DATA[4]
TS_SOP
TS_VALID
TS_CLK
AD[31]
AD[30]
AD[29]
AD[28]
VSS
I/O
Transport Stream Data Bit 4
Transport Stream Start of Packet (Parallel/Serial)
Transport Stream Data Valid (Parallel/Serial)
Transport Stream Clock (Parallel/Serial)
Multiplexed Address or Data Bit 31
Multiplexed Address or Data Bit 30
Multiplexed Address or Data Bit 29
Multiplexed Address or Data Bit 28
System Ground
I/O
I/O
I/O
I/O
AB2
PCI
I/O
AB3
PCI
I/O
AB4
PCI
I/O
-
AB5
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDD1
AB6
-
System 3.3 Volts
VDD1
AB7
-
System 3.3 Volts
VDDC1
VDDC1
VDD1
AB8
-
System 1.26 Volts
AB9
-
System 1.26 Volts
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
-
System 3.3 Volts
VDD1
-
System 3.3 Volts
VDDC1
VDDC1
VDDC1
VDD1
-
System 1.26 Volts
-
System 1.26 Volts
-
System 1.26 Volts
-
System 3.3 Volts (TM-PLL)
System 3.3 Volts
VDD3
-
VDDC1
VDDC1
-
System 1.26 Volts
-
System 1.26 Volts
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
26 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
VDD1
Pin
Group Type
Description
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
PWR
PWR
PWR
PWR
DVB
DVB
DVB
DVB
PCI
-
System 3.3 Volts
VDD1
-
System 3.3 Volts
VSS
-
System Ground
VSS
-
System Ground
TS_DATA[7]
TS_DATA[5]
TS_DATA[2]
TS_DATA[1]
AD[27]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Transport Stream Data Bit 7
Transport Stream Data Bit 5
Transport Stream Data Bit 2
Transport Stream Data Bit 1
Multiplexed Address or Data Bit 27
Multiplexed Address or Data Bit 26
Multiplexed Address or Data Bit 25
System Ground
AD[26]
AC2
PCI
AD[25]
AC3
PCI
VSS
AC4
PWR
PCI
AD[17]
AC5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Multiplexed Address or Data Bit 17
Multiplexed Address or Data Bit 16
System Error
AD[16]
AC6
PCI
SERR
AC7
PCI
AD[14]
AC8
PCI
Multiplexed Address or Data Bit 14
Multiplexed Address or Data Bit 10
Multiplexed Address or Data Bit 7
Multiplexed Address or Data Bit 3
Multiplexed Address or Data Bit 0
External I/O Select1
AD[10]
AC9
PCI
AD[07]
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
PCI
AD[03]
PCI
AD[00]
PCI
XIO_SEL[1]
GPIO[4]
I2S_IO_WS
SPDIF_OUT
DV1_DATA[6]
DV1_DATA[1]
I2S_IN1_SCK
I2S_IN2_SCK
DV2_DATA[6]
DV2_DATA[3]
VSS
MISC
GPIO
AVIF
AVIF
DVB
DVB
AVIF
AVIF
DVB
DVB
PWR
DVB
DVB
DVB
PCI
General Purpose Input/Output Bit 4
Audio IN/OUT Word Select
Multi-channel/SPDIF Output
ITU-656 VIP Data Bit 6
I/O
I/O
I/O
I/O
I
ITU-656 VIP Data Bit 1
Audio IN1 Serial Clock
Audio IN2 Serial Clock
Digital Video Transport Stream2 Data Bit 6
Digital Video Transport Stream2 Data Bit 3
System Ground
I
-
DV2_CLK
TS_DATA[6]
TS_DATA[3]
C/BE[3]
I
Digital Video Transport Stream2 Clock
Transport Stream Data Bit 6
Transport Stream Data Bit 3
Multiplexed Command or Byte Enable 3
Multiplexed Address or Data Bit 24
System Ground
I/O
I/O
I/O
I/O
-
AD[24]
AD2
PCI
VSS
AD3
PWR
PCI
AD[20]
AD4
I/O
I/O
Multiplexed Address or Data Bit 20
Multiplexed Address or Data Bit 18
AD[18]
AD5
PCI
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
27 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
Pin
Group Type
Description
TRDY
AD6
PCI
I/O
Parity Error indicates data parity errors during all PCI transactions
except
Special Cycle.
PERR
AD7
PCI
I/O
Parity Error indicates data parity errors during all PCI transactions
except
Special Cycle.
AD[15]
AD8
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Multiplexed Address or Data Bit 15
Multiplexed Address or Data Bit 11
Multiplexed Command or Byte Enable 0
Multiplexed Address or Data Bit 4
Multiplexed Address or Data Bit 1
External I/O Select0
AD[11]
AD9
PCI
C/BE[0]
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
PCI
AD[04]
PCI
AD[01]
PCI
XIO_SEL[0]
GPIO[5]
MISC
GPIO
AVIF
AVIF
DVB
DVB
DVB
AVIF
AVIF
DVB
DVB
DVB
DVB
DVB
PWR
PWR
PCI
General Purpose Input/Output Bit 5
Audio IN/OUT Data Bit 3
I2S_IO_SD[3]
I2S_IO_SD[0]
DV1_DATA[8]
DV1_DATA[4]
DV1_DATA[0]
I2S_IN1_OSCLK
I2S_IN2_OSCLK
DV2_DATA[5]
DV2_DATA[2]
DV2_SOP
DV2_VALID
DV2_ERR
VSS
Audio IN/OUT Data Bit 0
ITU-656 VIP Data Bit 8
ITU-656 VIP Data Bit 4
ITU-656 VIP Data Bit 0 (Least Significant Bit)
Audio IN1 OverSample Clock
O
Audio IN2 OverSample Clock
I
Digital Video Transport Stream2 Data Bit 5
Digital Video Transport Stream2 Data Bit 2
Digital Video Transport Stream2 Start of Packet
Digital Video Transport Stream2 Data Valid
Digital Video Transport Stream2 Error
System Ground
I
I
I
I
-
VSS
AE2
-
System Ground
AD[23]
AE3
I/O
I/O
I/O
I/O
Multiplexed Address or Data Bit 23
Multiplexed Address or Data Bit 21
Multiplexed Address or Data Bit 19
AD[21]
AE4
PCI
AD[19]
AE5
PCI
IRDY
AE6
PCI
Initiator Ready is asserted during writes to indicate valid data on
AD[31:0]. Also asserted during reads to indicate the target is prepared
to accept data. Wait states are inserted until IRDY and TRDY are both
asserted.
STOP
AE7
PCI
I/O
Stop is asserted to indicate a request from the target for the master to
stop the current transmission.
C/BE[1]
AD[12]
AD[08]
AD[05]
AD[02]
XIO_A25
GPIO[7]
AE8
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Command or Byte Enable 1
Multiplexed Address or Data Bit 12
Multiplexed Address or Data Bit 8
Multiplexed Address or Data Bit 5
Multiplexed Address or Data Bit 2
XIO Address Bit 25
AE9
PCI
AE10
AE11
AE12
AE13
AE14
PCI
PCI
PCI
MISC
GPIO
General Purpose Input/Output Bit 7
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
28 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
Pin
Group Type
Description
I2S_IO_SCK
I2S_IO_SD[1]
DV1_DATA[9]
DV1_DATA[5]
DV1_DATA[2]
DV1_CLK
I2S_IN1_SD
I2S_IN2_SD
DV2_DATA[4]
DV2_DATA[1]
VSS
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AVIF
AVIF
DVB
DVB
DVB
DVB
AVIF
AVIF
DVB
DVB
PWR
PWR
PWR
PWR
PCI
I/O
Audio IN/OUT Serial Clock
Audio IN/OUT Data Bit 1
ITU-656 VIP Data Bit 9 (Most Significant Bit)
ITU-656 VIP Data Bit 5
ITU-656 VIP Data Bit 2
ITU-656 VIP Data Clock
Audio IN1 Data
I/O
I/O
I/O
I/O
I/O
I
I
Audio IN2 Data
I
Digital Video Transport Stream2 Data Bit 4
Digital Video Transport Stream2 Data Bit 1
System Ground
I
-
VSS
-
System Ground
VSS
-
System Ground
VSS
AF2
-
System Ground
IDSEL
AF3
I/O
Initialization Device Select provides chip select during configuration
read and write transactions.
AD[22]
C/BE[2]
FRAME
AF4
AF5
AF6
PCI
PCI
PCI
I/O
I/O
I/O
Multiplexed Address or Data Bit 22
Multiplexed Command or Byte Enable 2
Frame is asserted to indicate start of bus transaction and remains
asserted until final data phase begins.
DEVSEL
PAR
AF7
AF8
PCI
PCI
I/O
I/O
Device Select is asserted when a target address is decoded and
remains asserted to indicate that a target device is selected.
Parity supports even parity across the PCI Address/Data Bus
AD[31:0]) and Command/ Byte Enable Bus (C/BE[3:0]). Bus Master
drives PAR for address and write data phases. Target drives PAR for
the read data phases.
AD[13]
AF9
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Multiplexed Address or Data Bit 13
Multiplexed Address or Data Bit 9
Multiplexed Address or Data Bit 6
External I/O Select2
AD[09]
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
PCI
AD[06]
PCI
XIO_SEL[2]
XIO_ACK
MISC
MISC
GPIO
AVIF
AVIF
AVIF
DVB
DVB
DVB
AVIF
AVIF
DVB
XIO Acknowledge (EEPROM)
General Purpose Input/Output Bit 6
Audio IN/OUT OverSample Clock
Audio IN/OUT Data Bit 2
GPIO[6]
I2S_IO_OSCLK
I2S_IO_SD[2]
SPDIF_IN
Multi-ch/SPDIF Input
DV1_DATA[7]
DV1_DATA[3]
DV1_VALID
I2S_IN1_WS
I2S_IN2_WS
DV2_DATA[7]
I/O
I/O
I/O
I/O
I/O
I
ITU-656 VIP Data Bit 7
ITU-656 VIP Data Bit 3
ITU-656 VIP Data Valid
Audio IN1 Word Select
Audio IN2 Word Select
Digital Video Transport Stream2 Data Bit 7
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
29 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 16: All pins…continued
Symbol
DV2_DATA[0]
VSS
Pin
Group Type
Description
AF24
AF25
AF26
DVB
I
Digital Video Transport Stream2 Data Bit 0
System Ground
PWR
PWR
-
-
VSS
System Ground
6.2.1 Multi-function pins
Table 17 identifies and describes alternate signals that are available in the PNX8526.
In Section 6.2 alternate signals are also identified by a hash (#) within each functional
group of signals.
Remark: The PNX8526 has a number of General Purpose Input Output (GPIO) pins.
Some of these are dedicated pins, while others are configured as alternate signals on
multi function pins, as described below. The standard function of these pins may not
be required in some system configurations.
For more details on GPIO functionality, see PNX8526 User Manual, Chapter 10.
Table 17: Multiplexed (MUX) pins
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
AF15
AE15
AC15
AD15
AF16
AE16
AD16
I2S_IO_OSCLK
GPIO 45
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Audio IN/OUT Oversample Clock
General Purpose Input/Output 45
I2S_IO_SCK
GPIO 46
Audio IN/OUT Serial Clock
General Purpose Input/Output 46
I2S_IO_WS
GPIO 47
Audio IN/OUT Word Select
General Purpose Input/Output 47
I2S_IO_SD[3]
GPIO 51
Audio IN/OUT Data Bit 3
General Purpose Input/Output 51
I2S_IO_SD[2]
GPIO 50
Audio IN/OUT Data Bit 2
General Purpose Input/Output 50
I2S_IO_SD[1]
GPIO 49
Audio IN/OUT Data Bit 1
General Purpose Input/Output 49
I2S_IO_SD[0]
GPIO 48
Audio IN/OUT Data Bit 0
General Purpose Input/Output 48
R1
R2
DV_CLK2
Digital Video Clock2 for secondary display channel from AICP
Digital Video Output2, Bit 9 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 9
Digital Video Output2, Bit 8 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 8
Debug Support Unit1, TPC1
DV_OUT2[9]
SPY_OUT[9]
DV_OUT2[8]
SPY_OUT[8]
DSU_TPC1
DV_OUT2[7]
SPY_OUT[7]
DSU_TPC0
O
O
R4
R3
O
O
O
O
Digital Video Output2, Bit 7 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 7
Debug Support Unit0, TPC0
O
O
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
30 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
T1
DV_OUT2[6]
SPY_OUT[6]
DSU_PCST1[2]
DV_OUT2[5]
SPY_OUT[5]
DSU_PCST1[1]
DV_OUT2[4]
SPY_OUT[4]
DSU_PCST1[0]
DV_OUT2[3]
SPY_OUT[3]
DSU_PCST0[2]
DV_OUT2[2]
SPY_OUT[2]
DSU_PCST0[1]
DV_OUT2[1]
SPY_OUT[1]
DSU_PCST0[0]
DV_OUT2[0]
SPY_OUT[0]
DSU_CLK
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O
O
I/O
O
I
Digital Video Output2, Bit 6 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 6
Program Counter Status1, Bit 2
T2
T3
U1
T4
U2
U3
K2
L3
K1
L4
Digital Video Output2, Bit 5 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 5
Program Counter Status1, Bit 1
Digital Video Output2, Bit 4 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 4
Program Counter Status1, Bit 0
Digital Video Output2, Bit 3 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 3
Program Counter Status0, Bit 2
Digital Video Output2, Bit 2 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 2
Program Counter Status0, Bit 1
Digital Video Output2, Bit 1 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 1
Program Counter Status0, Bit 0
Digital Video Output2, Bit 0 for secondary display channel from AICP
SPY Micro-Architecture Output signal, Bit 0
Debug Support Unit Clock
I2S_OUT2_OSCLK
DV_OUT[20]
SPY_OUT[11]
I2S_OUT2_SCK
DV_OUT[21]
SPY_OUT[10]
I2S_OUT2_WS
DV_OUT[22]
DBG_EXT_STOP
I2S_OUT2_SD
DV_OUT[23]
CLK_SPY
Audio OUT2 Oversample Clock
AICP RGB Data Bit 20
SPY Micro-Architecture Output signal, Bit 11
Audio OUT2 Serial Clock
AICP RGB Data Bit 21
SPY Micro-Architecture Output signal, Bit 10
Audio OUT2 Word Select
AICP RGB Data Bit 22
External Stop Request signal
O
O
O
I
Audio OUT2 Data
AICP RGB Data Bit 23 (Most Significant Bit)
SPY Micro-Architecture Clock Output signal
ITU-656 VIP Data Bit 9 (Most Significant Bit)
General Purpose Input/Output 42
AE17
AD17
DV1_DATA[9]
GPIO 42
I/O
I
DV1_DATA[8]
GPIO 41
ITU-656 VIP Data Bit 8
I/O
General Purpose Input/Output 41
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
31 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
AF18
AC17
AE18
AD18
AF19
AE19
AC18
AD19
AF20
AE20
AF23
AC21
DV1_DATA[7]
GPIO 40
I
ITU-656 VIP Data Bit 7
I/O
General Purpose Input/Output 40
ITU-656 VIP Data Bit 6
DV1_DATA[6]
GPIO 39
I
I/O
General Purpose Input/Output 39
ITU-656 VIP Data Bit 5
DV1_DATA[5]
GPIO 38
I
I/O
General Purpose Input/Output 38
ITU-656 VIP Data Bit 4
DV1_DATA[4]
GPIO 37
I
I/O
General Purpose Input/Output 37
ITU-656 VIP Data Bit 3
DV1_DATA[3]
GPIO 36
I
I/O
General Purpose Input/Output 36
ITU-656 VIP Data Bit 2
DV1_DATA[2]
GPIO 35
I
I/O
General Purpose Input/Output 35
ITU-656 VIP Data Bit 1
DV1_DATA[1]
GPIO 34
I
I/O
General Purpose Input/Output 34
ITU-656 VIP Data Bit 0 (Least Significant Bit)
General Purpose Input/Output 33
ITU-656 VIP Data Valid
DV1_DATA[0]
GPIO 33
I
I/O
DV1_VALID
GPIO 44
I
I/O
General Purpose Input/Output 44
ITU-656 VIP Data Clock
DV1_CLK
GPIO 43
I
I/O
General Purpose Input/Output 43
Digital Video Transport Stream2 Data Bit 7
ITU-656 VIP Data Bit 9 (Most Significant Bit)
Digital Video Transport Stream2 Data Bit 6
ITU-656 VIP Data Bit 8
DV2_DATA[7]
VIP[9]
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DV2_DATA[6]
VIP[8]
TSS_DATA2
DV2_DATA[5]
VIP[7]
Digital Video Transport Stream2 Serial Data2
Digital Video Transport Stream2 Data Bit 5
ITU-656 VIP Data Bit 7
AD22
AE23
AC22
AD23
TSS_SOP2
DV2_DATA[4]
VIP[6]
Digital Video Transport Stream2 Serial Start of Packet2
Digital Video Transport Stream2 Data Bit 4
ITU-656 VIP Data Bit 6
TSS_ERR2
DV2_DATA[3]
VIP[5]
Digital Video Transport Stream2 Serial Error2
Digital Video Transport Stream2 Data Bit 3
ITU-656 VIP Data Bit 5
TSS_VALID2
DV2_DATA[2]
VIP[4]
Digital Video Transport Stream2 Serial Valid2
Digital Video Transport Stream2 Data Bit 2
ITU-656 VIP Data Bit 4
TSS_CLK2
Digital Video Transport Stream2 Serial Clock2
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
32 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
AE24
AF24
DV2_DATA[1]
VIP[3]
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Digital Video Transport Stream2 Data Bit 1
ITU-656 VIP Data Bit 3
DV2_DATA[0]
VIP[2]
Digital Video Transport Stream2 Data Bit 0
ITU-656 VIP Data Bit 2
TSS_DATA1
DV2_SOP
VIP[1]
Digital Video Transport Stream2 Serial Data1
Digital Video Transport Stream2 Start of Packet
ITU-656 VIP Data Bit 1
AD24
AD26
AD25
AC24
TSS_SOP1
DV2_ERR
VIP[0]
Digital Video Transport Stream2 Serial Start of Packet1
Digital Video Transport Stream2 Error
ITU-656 VIP Data Bit 0 (Least Significant Bit)
Digital Video Transport Stream2 Serial Error1
Digital Video Transport Stream2 Data Valid
ITU-656 VIP Data Valid
TSS_ERR1
DV2_VALID
VIP_VALID
TSS_VALID1
DV2_CLK
VIP_CLK
Digital Video Transport Stream2 Serial Valid1
Digital Video Transport Stream2 Clock
ITU-656 VIP Data Clock
TSS_CLK1
DV3_DATA[7]
VIP[9]
Digital Video Transport Stream2 Serial CLock1
Digital Video Transport Stream3 Data Bit 7
ITU-656 VIP Data Bit 9 (Most Significant Bit)
Digital Video Transport Stream3 Data Bit 6
ITU-656 VIP Data Bit 8
W23
Y24
DV3_DATA[6]
VIP[8]
TSS_DATA2
DV3_DATA[5]
VIP[7]
Digital Video Transport Stream3 Serial Data2
Digital Video Transport Stream3 Data Bit 5
ITU-656 VIP Data Bit 7
Y25
Y26
W24
V23
W25
TSS_SOP2
DV3_DATA[4]
VIP[6]
Digital Video Transport Stream3 Serial Start of Packet2
Digital Video Transport Stream3 Data Bit 4
ITU-656 VIP Data Bit 6
TSS_ERR2
DV3_DATA[3]
VIP[5]
Digital Video Transport Stream3 Serial Error2
Digital Video Transport Stream3 Data Bit 3
ITU-656 VIP Data Bit 5
TSS_VALID2
DV3_DATA[2]
VIP[4]
Digital Video Transport Stream3 Serial Valid2
Digital Video Transport Stream3 Data Bit 2
ITU-656 VIP Data Bit 4
TSS_CLK2
DV3_DATA[1]
VIP[3]
Digital Video Transport Stream3 Serial Clock2
Digital Video Transport Stream3 Data Bit 1
ITU-656 VIP Data Bit 3
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
33 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
W26
DV3_DATA[0]
VIP[2]
I
Digital Video Transport Stream3 Data Bit 0
ITU-656 VIP Data Bit 2
I
TSS_DATA1
DV3_SOP
VIP[1]
I
Digital Video Transport Stream3 Serial Data1
Digital Video Transport Stream3 Start of Packet
ITU-656 VIP Data Bit 1
V24
U23
V25
V26
I
I
TSS_SOP1
DV3_ERR
VIP[0]
I
Digital Video Transport Stream3 Serial Start of Packet1
Digital Video Transport Stream3 Error
ITU-656 VIP Data Bit 0 (Least Significant Bit)
Digital Video Transport Stream3 Serial Error1
Digital Video Transport Stream3 Data Valid
ITU-656 VIP Data Valid
I
I
TSS_ERR1
DV3_VALID
VIP_VALID
TSS_VALID1
DV3_CLK
VIP_CLK
TSS_CLK1
TS_DATA[7]
GPIO 29
I
I
I
I
Digital Video Transport Stream3 Serial Valid1
Digital Video Transport Stream3 Clock
ITU-656 VIP Data Clock
I
I
I
Digital Video Transport Stream3 Serial Clock1
Transport Stream Data Bit 7
AB23
AC25
AB24
AA23
AC26
AB25
AB26
Y23
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
I/O
O
I/O
O
I/O
General Purpose Input/Output 29
Transport Stream Data Bit 6
TS_DATA[6]
GPIO 28
General Purpose Input/Output 28
Transport Stream Data Bit 5
TS_DATA[5]
GPIO 27
General Purpose Input/Output 27
Transport Stream Data Bit 4
TS_DATA[4]
GPIO 26
General Purpose Input/Output 26
Transport Stream Data Bit 3
TS_DATA[3]
GPIO 25
General Purpose Input/Output 25
Transport Stream Data Bit 2
TS_DATA[2]
GPIO 24
General Purpose Input/Output 24
Transport Stream Data Bit 1
TS_DATA[1]
GPIO 23
General Purpose Input/Output 23
Transport Stream Data Bit 0
TS_DATA[0]
GPIO 22
General Purpose Input/Output 22
Transport Stream Serial Data Out
Transport Stream Start of Packet (Parallel/Serial)
General Purpose Input/Output 31
Transport Stream Data Valid (Parallel/Serial)
General Purpose Input/Output 32
Transport Stream Clock (Parallel/Serial)
General Purpose Input/Output 30
TS_SD
AA24
AA25
AA26
TS_SOP
GPIO 31
TS_VALID
GPIO 32
TS_CLK
GPIO 30
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
34 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
AA2
PCI_REQ_A*[1]
I/O
Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where
internal arbiter is configured.
GPIO 57
I/O
I/O
General Purpose Input/Output 57
AA3
Y4
PCI_REQ_B*
Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal arbiter
is configured.
GPIO 58
I/O
I/O
General Purpose Input/Output 58
PCI_GNT_A*
Auxiliary Arbitration Grant_A is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is configured.
GPIO 59
I/O
I/O
General Purpose Input/Output 59
AA4
PCI_GNT_B*
Auxiliary Arbitration Grant_B is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is configured.
GPIO 60
I/O
O
General Purpose Input/Output 60
External MMIO Select 2
General Purpose Input/Output 54
External MMIO Select 1
General Purpose Input/Output 53
External MMIO Select 0
General Purpose Input/Output 52
XIO Acknowledge (EEPROM)
General Purpose Input/Output 55
XIO Address bit 25
AF12
AC13
AD13
AF13
AE13
U24
XIO_SEL[2]*
GPIO 54
I/O
O
XIO_SEL[1]*
GPIO 53
I/O
O
XIO_SEL[0]*
GPIO 52
I/O
I
XIO_ACK*
GPIO 55
I/O
O
XIO_A25*
GPIO 56
I/O
O
General Purpose Input/Output 56
UART1 Transmit
UA1_TX
GPIO 12
I/O
I
General Purpose Input/Output 12
UART1 Receive
U25
UA1_RX
GPIO 13
I/O
O
General Purpose Input/Output 13
UART2 Transmit
T23
UA2_TX
GPIO 14
I/O
I
General Purpose Input/Output 14
U26
UA2_RX
UART2 Receive
ICAM1_SETVPP
GPIO 15
O
ICAM1 VPP**[2]
I/O
O
General Purpose Input/Output 15
UART2 Request To Send
ICAM1 C8**
T24
T25
UA2_RTSN
ICAM1_C8
GPIO 16
I
I/O
I
General Purpose Input/Output 16
UART2 Clear To Send
UA2_CTSN
ICAM1_C4
GPIO 17
I/O
I/O
ICAM1 C4
General Purpose Input/Output 17
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
35 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
V1
SSI_SCLK_CTSN
UART CTS
GPIO 21
I
Synchronous Serial Interface CLock Input
UART2 Clear To Send
I
I/O
I
General Purpose Input/Output 21
Synchronous Serial Interface Frame Sync
UART2 Request To Send
General Purpose Input/Output 20
Synchronous Serial Interface Receive
General Purpose Input/Output 19
Synchronous Serial Interface Transmit
General Purpose Input/Output 18
ICAM2 C4
V2
SSI_FS_RTSN
UART RTS
GPIO 20
O
I/O
I
U4
SSI_RXD
GPIO 19
I/O
O
V3
SSI_TXD
GPIO 18
I/O
I/O
I/O
I/O
I/O
O
N26
N24
N23
ICAM2_C4
GPIO 11
General Purpose Input/Output 11
ICAM2 C8
ICAM2_C8
GPIO 10
General Purpose Input/Output 10
ICAM2 VPP
ICAM2_SETVPP
GPIO 9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General Purpose Input/Output 9
General Purpose Input/Output 8
General Purpose Input/Output 7
General Purpose Input/Output 6
General Purpose Input/Output 5
General Purpose Input/Output 4
General Purpose Input/Output 3
Select Configuration Bit 2 during System Reset
General Purpose Input/Output 2
Select Configuration Bit 1 during System Reset
General Purpose Input/Output 1
Select Configuration Bit 0 during System Reset
General Purpose Input/Output 0
Smartcard Off
M26
AE14
AF14
AD14
AC14
C5
GPIO 8
GPIO 7
GPIO 6
GPIO 5
GPIO 4
GPIO 3
B4
Boot Mode [2]
GPIO 2
I/O
I
D5
Boot Mode [1]
GPIO 1
I/O
I
C4
Boot Mode [0]
GPIO 0
I/O
I
P25
P24
P26
N25
P23
SC2_OFFN
ICAM2_DETECT
SC2_CMD
ICAM2_SETVCC
SC2_RST
ICAM2_RESET
SC2_SCCK
ICAM2_CLK
SC2_DA
I
ICAM2 Detect
O
Smartcard Command
O
ICAM2 VCC
O
Smartcard Reset
O
ICAM2 Reset
O
Smartcard Clock
O
ICAM2 Clock
I/O
I/O
SmartCard2 Data
ICAM2_C7
ICAM2 C7
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
36 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 17: Multiplexed (MUX) pins…continued
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2 for more details.
Pin
MUX contacts Primary Type Description
signal and Alternate
Function
R25
R23
R24
R26
T26
SC1_OFFN
ICAM1_DETECT
SC1_CMD
I
Smartcard Off
ICAM1 Detect
Smartcard Command
ICAM1 VCC
I
O
O
O
O
O
O
I/O
I/O
ICAM1_SETVCC
SC1_RST
Smartcard Reset
ICAM1 Reset
ICAM1_RESET
SC1_SCCK
ICAM1_CLK
SC1_DA
Smartcard Clock
ICAM1 Clock
Smartcard1 Data
ICAM1 C7
ICAM1_C7
[1] *These pins are included in the XIO set. Refer to PNX8526 User Manual, Chapter 8 for additional functions.
[2] **The ICAM1_SETVPP and ICAM1_C8 signals are automatically selected when the ICAM function is selected. Refer to Table 18 (Offset
0x04 D600 IO_MUX_CTR). Selecting GPIO mode will disable this ICAM functionality.
7. Functional description
Figure 3 shows a block diagram of a typical PNX8526-based system. The system
shown is a “standalone system” which uses the internal MIPS host.
The PNX8526 runs on a single 27 MHz xtal from which all internal and external
clocks are derived by on-chip synthesizers. The PNX8526 boots directly from
attached Flash memory or ROM. If desired, custom boot methods can be
programmed using the optional I2C boot EEPROM.
The PNX8526 has three Digital Video inputs that accept digitized analog video
(ITU-656), although only two ITU-656 streams can be processed simultaneously. Two
of these inputs, DV2 and DV3, can also accept scrambled transport streams.
The DV inputs support parallel transport stream formats. In addition, a single
incoming 1394 transport stream is supported. Two selected transport streams can
undergo internal de-scrambling and decoding.
Based on the system implementation, one or both transport streams may pass
through Point of Deployment (POD) or Common Interface (CI) conditional access
modules before transfer into the PNX8526. Either a single companion IC, such as the
SCM Microsystems CIMaX™, or two CIMaX™ chips can be used. In the latter case, it
is possible to handle dual decoding no matter which conditional access system is
used.
The PNX8526 contains on-chip DVB, MULTI2 and DES hardware de-scramblers, as
well as an ICAM verifier. The entitlement system for these de-scramblers is provided
via two Smartcard interfaces.
The TM32 CPU does further processing on the result of the transport stream de-mux.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
37 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
For MPEG2 video, a slice level HL MPEG2 video decoder performs the majority of the
MPEG2 algorithm. This MPEG decoder is capable of full-resolution decoding. The
TM32 CPU does all MPEG2 processing above the slice level. Two simultaneous SD
streams or one HD stream may be processed.
All audio processing is done by the TM32 CPU. Compressed audio will be present in
memory from either the transport stream de-multiplex or from the SPDIF input port.
The SPDIF input port is intended primarily for DTV applications where a SPDIF
source is available from an external source device, such as a DVD player. PCM
(stereo sample) audio is present in memory from the I2S input ports or SPDIF input.
Two AC-3 (or equivalent) compressed audio streams may be decoded
simultaneously. The TM32 CPU may also process effects, enhancements and mix the
audio data. Multi-channel compressed audio or down-mixed stereo PCM audio is
transmitted over the SPDIF output interface. Multi-channel audio samples are Dolby
Pro Logic™ down-mixed into the two stereo I2S interfaces to the PNX8510
companion IC. In addition to the two I2S inputs and two I2S outputs, a bi-directional
I2S interface is provided. This allows connection of other audio inputs or
outputs– headphones, for example. Note that there is not enough compute power to
support encoding of multi-channel compressed audio simultaneous with video
processing. So the multi-channel compressed audio transmitted over SPDIF must be
from one of the original compressed sources.
Graphics rendering may be accomplished with the MIPS or the TM32 CPU by utilizing
the 2D Drawing and DMA engine. This engine can perform fast area fills, 3-operand
bitblt, monochrome data expansion, and lines. It can also be used as a generic DMA
engine to transfer data between memory locations on a byte-aligned basis. An alpha
bitblt capability is also provided to allow for anti-aliased text and lines as well as
source/destination blending operations.
Once all video and graphics data for specific fields or frames has been generated in
memory, the video display pipeline starts processing those images for display. The
video processing functions include 6-tap horizontal/vertical scaling, anti-flicker
filtering, and de-interlacing (when progressive output is required). The processed
images are then combined for each output. Up to four surfaces of any supported
format may be combined to produce the primary display output. Up to two surfaces
are combined to produce the secondary output. Compositing of more surfaces for
future video algorithms is possible by using the TM32 CPU and/or the memory based
scaler prior to invoking the compositing/display engine. This is subject to CPU and
memory bandwidth availability.
The PNX8526 contains a 1394 interface with 5C copy protection. The PNX8526 1394
can simultaneously transmit two transport streams while receiving one transport
stream. The transmitted streams can be partial transport streams (created by PID
filtering of an input) or one of the two streams can be software generated. In the case
of receiving a scrambled 1394 transport stream input, the stream can either use the
on-chip de-scramblers, or may be routed to the external companion CA IC for
de-scrambling by the POD/CI CA module(s).
The PNX8526 contains a variety of peripheral interfaces to support both ASTB and
DTV requirements. There are two Smartcard interfaces, two USB ports, two I2C
ports, one IrDA Data UART and two general purpose UARTs, one of which (UART3)
is multiplexed with an SSI interface for soft modem support. The PNX8526 also
contains an integrated IDE controller, which only requires an external isolation buffer
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
38 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
to implement a full disk interface with sustained speeds up to 10 MB/s. A third-party
PCI Super I/O chip may be utilized to provide peripheral functionality not contained on
the PNX8526. Functions such as IEEE-1284, 10/100 Ethernet, floppy drive support,
UDMA66 IDE controllers and others are currently available in low-cost, commercially
available parts.
to Dig VCR
16/32/64 MB
IEEE 1394
to HDTV set
from ext. tuner
SDRAM
PHY
64-bit
10
10
3
1
1394
TS (output)
transport stream
DV_OUT1
DV_OUT2
RGB or Y/C
CVBS
1
1
OOB in
Y
POD-1/
2
PNX8510
C (CVBS)
I S_OUT1
NRSS-B/CI
CA
INTERFACE
IC
2
2
OOB out
A1 R/L
A2 R/L
2
DV3 (656/TS in)
I S_OUT2
POD-2/
NRSS-B/CI
2
I C
2
5
I C-2
GPIO
PNX8526
27 MHz
transport stream
ANALOG
FRONT-END
OR MODEM
SSI/UART3
SPDIFOUT
PSTN
analog
video
711X
DV2 (656/TS in)
1
transport stream
SPDIF out
aux. audio
s/w I/O pins
2
I S
2
analog
video
I S I/O
711X
DV1 (656 in)
> = 12
GPIO
2
stereo audio (2×)
SPDIF in
I S_IN1/2
2
I C bus
2
SPDIFIN
GPIO
I C-1
IR remote
USB (2×)
UART2
IrDA data (UART1)
OPTIONAL
BOOT
EEPROM
SC1 & SC2
smartcard (2×)
TDA8004
XIO_SEL0
PCI-XIO8 expansion bus
DOCSIS
MODEM
PCI SUPER I/O
BUFFER
FLASH
MCE541
IDE
LAN
1284
IDE
UDMA66
10 MB/s
Fig 3. PNX8526-based system block diagram
8. I/O multiplexer control register
The I/O Multiplexer Control register is used to configure the multi function pins to
alternate functions as described in Table 17. Control is achieved via the Global 2
register IO_MUX_CTRL Table 18.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
39 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 18: Global 2 registers
Bit
Symbol
Access Value
Description
0x04 D600 IO_MUX_CTRL
31:15 Not used
Ignore during writes and read as zeroes.
I2S_IO Audio mode:
14
13
12
AIO_MUX_SEL
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0 = Select I2S_IO as Audio Out.
1 = Select I2S_IO as Audio In.
SSI_SEL
SSI or UART3 mode:
0 = Select UART3.
1 = Select SSI.
RGB24_SEL
Audio Out2 or RGB mode:
0 = Select Audio Out2.
1 = Select RGB (DV_OUT [23:20]).
11:10 SMCRD2_MUX_CTRL R/W
ICAM or SmartCard2 mode:
00 = SmartCard1 module ports go to SmartCard2 pins.
01 = SmartCard2 module ports go to SmartCard2 pins.
10 = ICAM1 module ports go to SmartCard2 pins.
11 = ICAM2 module ports go to SmartCard2 pins.
9:8
SMCRD1_MUX_CTRL R/W
0x0
ICAM or SmartCard2 mode:
00 = SmartCard1 module ports go to SmartCard1 pins.
01 = SmartCard2 module ports go to SmartCard1 pins.
10 = ICAM1 module ports go to SmartCard1 pins.
11 = ICAM2 module ports go to SmartCard1 pins.
7
Not used
-
Ignore during writes and read as zeroes.
VIP2 module selection:
6:4
VIP2_MUX_CTRL[2:0]
R/W
R/W
0x0
000 = VIP data from DV1 port
001 = VIP data from DV2 port
010 = VIP data from DV3 port
011 = VIP data from DV_OUT1(AICP1) port
100 = 1394 data from link core
3
Not used
-
Ignore during writes and read as zeroes.
VIP1 module selection:
2:0
VIP1_MUX_CTRL[2:0]
0x0
000 = VIP data from DV1 port
001 = VIP data from DV2 port
010 = VIP data from DV3 port
011 = VIP data from DV_OUT2 (AICP2) port
100 = 1394 data from link core
9. Power supply sequencing
Power application and power removal should obey the following rules:
9.1 Power on sequence
• Apply power to VDD 1.26 V
• Allow VDD 1.26 V to stabilize (approx.100 ms recommended)
• Apply power to VDD 3.3 V
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
40 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
9.2 Power off sequence
• Power may be removed from VDD 3.3 V and VDD 1.26 V at the same time
• Otherwise remove VDD 3.3 V followed by 1.26 V
10. Limiting values
Table 19: Maximum ratings
Symbol Parameter
Min
0
Max
70
Typical Unit
Tamb
Tstg
Tj
Ambient temperature
-
-
-
°C
°C
°C
V
Storage temperature
-40
-
+125
100
Junction temperature
3-volt I/O pin voltage with respect to VSS
-0.5
-0.5
VDD+0.5 -
5-volt tolerant I/O pin voltage with respect to
VSS
5.5
-
V
I/O with Non-Schmitt trigger input voltage
threshold
1.46 1.76
-
V
I/O with Schmitt trigger input threshold VILT
I/O with Schmitt trigger input threshold VIHT
I/O transient pin voltage
0.93 1.06
1.66 1.79
-
-
-
-
-
-
-
-
V
V
-
10
V
DC supply voltage (VDD I/O pad)
3.0
3.6
V
DC supply voltage (VDDC core logic)
Dynamic Power Dissipation
1.20 1.32
V
-
-
-
2
W
W
kV
Static Power Dissipation (AICP off)
Electrostatic Discharge (Human Body Model)
1
± 1.5
11. Thermal characteristics
PNX8526 can be used in different environments creating different junction
temperatures.
The thermal resistance from junction to ambient (i.e. θja) of the PNX8526 in its
HBGA456 package is around 11.7 C/W. This value is acheived using natural
convection, no external heatsink and using a JEDEC defined high-conductive board
(see JEDEC standards 51-2 and 51-7 for details).
Given the power dissipation of the PNX8526 and the ambient temperature inside the
enclosure, the expected junction temperature can be calculated using the following
equation:
Tj = Tamb + P x Rth(j-a)
In some applications the junction temperature may be judged too high, reducing the
acceptable lifetime (see Section 15). However cooling can be improved by fitting an
additional external heatsink, or increasing the airflow around the device. Table 20
shows the improvements that can be expected if these measures are taken.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
41 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 20: PNX8526 thermal data
Heatsink size = 37 x 37 x 10 mm
PNX8526
Thermal resistance Rth(j-a) (C/W)
Airflow
0 m/s
11.7
1 m/s
10.0
7.6
2 m/s
8.5
Standard
With external h’sink
9.5
6.3
12. Static characteristics
The characteristics listed in the following tables apply to standard operating
conditions, unless otherwise noted. All voltages are referenced to VSS (0V Ground).
Positive current flows into the referenced pin. The standard operating voltage range is
V
DD = 3.3 ± 0.3 VDC and VDDC = 1.26 ± 0.06 VDC. All digital I/O pins are 3.3 V tolerant.
In all cases described below, digital VDD = 3.3 V+ 5% and operating temperature is 0°
to 70° C.
All AC timings are based on a 30 pF test load and are measured at a 1.6 V threshold
(see Figure 4) Actual I/O voltage threshold is dependant on pad type e.g., Schmitt
trigger input (see Section 6.1).
handbook, 4 columns
2.4 V
1.6 V
0.8 V
MCE542
Fig 4. General AC characteristics
The AC voltage characteristics for active signal pins of the controller are listed in
Table 21. Signal names for the PCI bus configuration are listed, as well as the
minimum and maximum voltage, current, and capacitance for each pin.
Table 21: Digital AC/DC characteristics
Symbol
Parameter
Min
Max
Typical
Unit
V
V
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Current
Output High Current
-0.5
+0.8
-
-
-
-
-
-
-
-
-
-
-
-
VIH
2.4
Vdd + 0.5
V
VOL
VOH
Vss
Vss + 0.4
V
2.4
-
V
[1]
IOL1
-
-
-
-
-
-
-
-
5
mA
mA
mA
mA
mA
mA
mA
mA
IOH1
-5
8
[2]
IOL2
IOH2
-8
12
-12
14
-14
[3]
IOL3
IOH3
[4]
IOL4
IOH4
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
42 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 21: Digital AC/DC characteristics…continued
Symbol
Parameter
Min
Max
0.041
3.5
Typical
Unit
mA
pF
A
IOZ
Output Tri-state Current
Input Capacitance
Power Supply Current
Power Supply Current
-
-
-
-
-
CIN, COUT, CI/O
-
ICC
ICP
1.5
0.9
0.13
0.2
A
[1] lOL1 (4mA):
I2S_IN1_SCK, I2S_IN1_WS, I2S_IN2_SCK, I2S_IN2_WS, I2S_OUT1_SCK, I2S_OUT1_WS,
I2S_OUT1_SD, I2S_OUT2_SD, DV1_DATA[9:0], DV1_VALID, DV1_CLK, DBG_TDO, JTAG_TDO,
XTAL_OUT, UA1_TX, UA1_RX, UA2_TX, UA2_RX, UA2_RTS, UA2_CTS, SC1_DA, SC1_CMD,
SC1_RST, SC1_SCCK, SC2_DA, SC2_CMD, SC2_RST, SC2_SCCK, SSI_SCLK_CTSN,
SSI_FS_RTSN, SSI_RX, SSI_TX, USB_DM[1:0], USB_DP[1:0], USB_BUS_PWR
[2] IOL2 (8mA):
DV_OUT1[9:0], DV_OUT2[9:0], DV_CLK1, DV_CLK2, HSYNC, VSYNC, BLANK, I2S_IN1_OSCLK,
I2S_IN2_OSCLK, I2S_IO_OSCLK, I2S_IO_SCK, I2S_IO_WS, I2S_IO_SD[3:0], I2S_OUT1_OSCLK,
I2S_OUT2_OSCLK, I2S_OUT2_SCK, I2S_OUT2_WS, TS_DATA[7:0], TS_SOP, TS_VALID, TS_CLK,
PHY_DATA[7:0], PHY_CTL[1:0], PHY_LREQ, MM_DATA[63:0], MM_DQMM_[7:0], MM_CKE,
I2C1_SCL, I2C1_SDA, I2C2_SCL, I2C2_SDA, GPIO[11:0], SYS_RSTN_OUT, XIO_SEL[2:0],
XIO_ACK, XIO_AD25
[3] IOL3 (12mA):
PCI_AD[31:0], PCI_CBE[3:0], PCI_DEVSEL, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_STOP,
PCI_PERR, PCI_PAR, PCI_INTA, PCI_REQ, PCI_GNT, PCI_REQ_A, PCI_REQ_B, PCI_GNT_A,
PCI_GNT_B, PCI_SERR,MM_WE, PLL_OUT,
[4] IOL4 (14mA):
SPDIF_OUT, MM_CLK[1:0], MM_ADDR[11:0], MM_BA[1:0], MM_CS, MM_RAS, MM_CAS
The pin names used in the above notes are the primary names for PCI
configurations. Output signals multiplexed on some pins have the same drive level.
V
DD = 3.3 V +5%, Operating Temperature 0 °C to 70 °C
13. Dynamic characteristics
13.1 Reset timing
t
LOW
handbook, 4 columns
RESET_IN
MCE543
Fig 5. Reset timing
Table 22: Reset timing
Symbol
Parameter
RESET_IN active pulse width (after stable power)
Min Units
tLOW
400 µs
13.2 Peripheral Controller Interface (PCI) timing
For additional timing diagram information on XIO and IDE interfaces, see PNX8526
User Manual, Chapter 8.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
43 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
handbook, 4 columns
PCI CLOCK
t
t
su
h
PCI-XIO
INPUTS
t
OD(max)
t
OD(min)
PCI-XIO
OUTPUTS
MCE544
Fig 6. PCI timing
Table 23: PCI CLK-referenced input timing
Symbol
Parameter
Min Unit
tsu
th
PCI_AD[31:0], CBE[3:0], PCI_FRAME, PCI_IRDY
PCI_AD[31:0] hold
7
ns
ns
ns
ns
ns
0
th
PCI_C/BE[3:0], PCI_FRAME, PCI_IRDY, PCI_IDSEL hold
0
tsu
th
PCI_GNT setup
PCI_GNT hold
10
0
Table 24: PCI CLK-referenced output valid timing
Symbol
tOD
Parameter
Min
2
Max Unit
PCI_AD[31:0], PCI_CBE[3:0]
PCI_DEVSEL, PCI_PAR
PCI_STOP
11
11
11
11
12
ns
ns
ns
ns
ns
tOD
2
tOD
2
tOD
PCI_TRDY
2
tOD
PCI_REQ
2
[1] Minimum delay is the minimum time after the clock edge that a valid signal state from the previous
cycle will begin transition to the next state (become invalid). Maximum delay is the maximum time
after the clock edge that a signal state is valid for the next cycle.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
44 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
13.3 Main Memory Interface (MMI) timing
MCLK(f)
handbook, 4 columns
t
t
clk(H)
clk(L)
MMI CLK
t
ch
t
cs
MMI
CONTROL &
valid
t
MMI DATA
t
t
t
dsi, dso dhi, dho
MCE545
Fig 7. MMI Timing
Table 25: MMI timing (MCLK-referenced)
Symbol Parameter
Min Max Unit
tcs
Setup time with reference to clock
Hold time with reference to clock
1.5
0.8
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tch
tdso
tdho
tdsi
MMI data output setup time with reference to clock (write cycle) 1.5
MMI data output hold time with reference to clock (write cycle)
MMI data input setup with reference to clock (read cycle)
MMI data input hold with reference to clock (read cycle)
Clock low time
0.8
0
tdhi
2.0
2.9
2.9
-
tclk(L)
tclk(H)
Clock high time
MCLK(f) MMI_CLK[1:0]
166 MHz
13.4 General Purpose Input/Output (GPIO) timing
handbook, 4 columns
GPIO
1.5 V
MIN
MCE546
Fig 8. GPIO timing
Table 26: GPIO timing
Parameter
Min
10
Max
Unit
ns[1]
ns
GPIO as input
-
-
GPIO as output
75
[1] If GPIO is intended to be timestamped, the minimum pulse width is 75 ns
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
45 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
13.5 Universal Asynchronous Receiver/Transmitter (UART) timing
handbook, 4 columns
UART TX/RX
RTSN/CTSN
1.5 V
MIN
MCE547
Fig 9. UART timing
Table 27: UART CLK-referenced output timing
Parameter
UART TX
Min
4.3
4.3
4.3
4.3
Max
Unit
µs[1]
µs
-
-
-
-
UART RX
UART RTSN
UART CTSN
µs
µs
[1] Max baud rate: 230 kBs
13.6 Synchronous Serial Interface (SSI) timing
t
t
clk(H)
clk(L)
handbook, 4 columns
SSI_SCLK
t
cs
t
ch
CONTROL
DATA
valid
t
t
t
t
dsi, dso dhi, dho
MCE548
Fig 10. SSI timing
Table 28: SSI interface timing (MCLK-referenced)
Symbol
tcs
Parameter
Min Max Unit
Setup time with reference to clock
Hold time with reference to clock
Data output setup time with reference to clock
Data output hold time with reference to clock
Data input setup with reference to clock
Data input hold with reference to clock
Clock low time
3
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tch
2
tdso
3
tdho
2
tdsi
1.0
1.0
25
25
tdhi
tclk(L)
tclk(H)
Clock high time
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
46 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
13.7 I2C-bus timing
t
t
LOW
HIGH
handbook, 4 columns
SCL
t
t
su(STA) h(STA)
SDA
SCL
t
t
h(SDA) dv(STO)
t
t
su(SDA)
dv(SDA)
SDA
valid
MCE549
Fig 11. I2C-bus timing
Table 29: I2C-bus timing
Symbol
SCL
Parameter
Min
Max
Unit
kHz
µs
SCL clock frequency
-
400
tsu(STA)
th(STA)
tLOW
Start condition setup time
Start condition hold time
SCL LOW time
1
-
1
-
µs
1
-
µs
tHIGH
SCL HIGH time
1
-
µs
tsu(SDA)
th(SDA)
tdv(SDA)
tdv(SDO)
Data setup time
100
0
-
ns
Data hold time
-
ns
SCL LOW to data out valid
SCL HIGH to data out
-
0.5
-
µs
1
µs
13.8 IEEE 1394 Phy-Link interface
f
1394
h
CLK_1394
t
t
h
su
1394 Link
Input Port
t
p
1394 Link
Output Port
MCE550
Fig 12. IEEE 1394 Phy-Link interface timing
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
47 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 30: IEEE 1394 Phy-Link interface signals
Symbol
Parameter
Min
Max
Unit
f1394
tsu
th
CLK_1394 frequency
49.147 49.157 MHz
Input setup time for PHY_DATA[7:0], PHY_CTL[1:0]
Input hold time
6
0
-
-
ns
ns
ns
-
tp
Output propagation delay for PHY_DATA[9:0],
PHY_LREQ, PHY_CTL[1:0]
9
13.9 I2S audio input & output timing
f
Al_SCK
handbook, 4 columns
Al_SCK
t
t
su(CLK)
h(CLK)
Al_SD
Al_WS
valid
t
ws(SCK)
valid
Al_WS
MCE551
Fig 13. I2S audio input timing
Table 31: I2S audio input
Symbol
fAI_SCK
tsu(CLK)
th(CLK)
Parameter
Min Max Unit
Audio In AI_SCK clock frequency
-
20
-
MHz
ns
Input Setup Time to AI_SCK (Audio interface as slave)
Input Hold Time from AI_SCK (Audio interface as slave)
AI_SCK to AI_WS
3
2
2
-
ns
tws(SCK)
10
ns
[1] Timing measurements are done with respect to the SCK clock edge. The PNX8526 is the source of
AI_WS.
handbook, 4 columns
AO_SCK
t
SCK(DV)
AO_SD
valid
valid
t
ws(SCK)
AO_WS
MCE552
Fig 14. I2S audio output timing
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
48 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 32: I2S audio output
Symbol
Parameter
Min Max Unit
AO_SCK
tSCK(DV)
tsu(SCK)
th_SCK
Audio Out to AO_SCK clock frequency
AO_SCK to AO_SC valid
-
20
-
MHz
ns
2
2
2
-
Input Setup Time to AO_SCK (Audio interface as slave)
Input Hold Time from AO_SCK (Audio interface as slave)
AO_SCK to AO_WS
-
ns
-
ns
tws(SCK)
10
ns
13.10 Sony Philips Digital Interface (SPDIF) timing
handbook, 4 columns
t
t
HIGH
LOW
MCE553
Fig 15. SPDIF timing
Table 33: SPDIF timing
Symbol Parameter
Min
Typical Max
Unit
tHIGH
tLOW
CLK High Time (PCI)
CLK Low Time (PCI)
-
-
5.2
5.2
-
-
µs
µs
13.11 Digital Video Output (DV Out) timing
handbook, 4 columns
DV_CLK
t
t
su(CLK) h(CLK)
HSYNC
VSYNC
BLANK
valid
t
CLK(DV)
DV_OUT
(Data)
valid
MCE554
Fig 16. DV Out timing
Table 34: DV Out timing
Symbol
DV_CLK
tCLK(DV)
tsu(CLK)
th(CLK)
Parameter
Min
27
-3.7
3
Max
Unit
MHz[1]
ns
Video out clock frequency
DV_CLK to DV_OUT
-
0
-
VSYNC Setup Time to DV_CLK (as input)
ns
CRT Control Hold Time from DV_CLK
HSYNC, VSYNC, BLANK
0
-
ns
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
49 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
[1] DV_CLK period is programmable via the internal PLL
13.12 Digital Video Input (DV Input) timing
f
DVB
handbook, 4 columns
CLOCK
1.5 V
t
t
su
h
INPUTS
(DATA, SOP,
1.5 V
1.5 V
ERROR, VALID)
MCE555
Fig 17. DV Input timing
Table 35: DV Input timing (VDICLK-referenced)
Symbol Parameter
Min
Typical Max
Unit
ns
tsu
[7:0] setup
[7:0] hold
Clock
3
3
-
-
-
-
-
th
-
ns
fDVB
27
MHz
13.13 Transport Stream Output (TSO) timing
handbook, 4 columns
CLOCK
t
t
h
su
OUTPUT
(DATA, SOP,
VALID)
MCE556
Fig 18. TSO timing
Table 36: TSO timing
Symbol Parameter
Min
3
Typical Max
Unit
ns
tsu
th
Data setup
Data hold
-
-
-
-
0
ns
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
50 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
13.14 JTAG test contacts
t
t
h(TCK)
su(TCK)
handbook, 4 columns
TDI
TMS
valid
TCK
TDO
t
clk(TDO)
valid
MCE557
Fig 19. JTAG timing
Table 37: JTAG timing
Symbol
tclk(TDO)
tsu(TCK)
th(TCK)
Parameter
Min
Max
Unit
JTAG_TCK to JTAG_TDO Valid delay
Input Setup Time JTAG_TCK
Input Setup Time JTAG_TCK
TBD
TBD
TBD
14. Delta compared to PNX8525
There are a number of differences between the PNX8526 and the PNX8525 with
respect to the physical interfacing of the device. These differences are described in
Table 38.
Table 38: Differences - 8525 / 8526
Characteristic
PNX8525
PNX8526
Core supply voltage
1.8 V ± 5%
1.26 V ± 0.06 V
I2C-bus pads
IEEE-1394 pads
PCI Interface
GPIO pads with schmitt trigger and pull-ups
Special I2C pads designed to meet the I2C
specification
GPIO pads with schmitt trigger and pull-ups
Special IEEE-1394 pads designed to meet the
IEEE-1394 Link to Phy specification
Supports 5 V tolerant interface with 3.3 V
signalling
No 5 V tolerant interface, all signals limited to 3.3 V
System reset output (SYS_RSTN_OUT)
Drive capability 12 mA
Drive capability 8 mA
Drive capability 8 mA
Clock output (PLL_OUT)
Drive capability 12 mA
SPDIF output
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
51 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Table 38: Differences - 8525 / 8526…continued
Characteristic
PNX8525
PNX8526
Drive capability 16 mA
Drive capability 14 mA
DV1 port, SSI, Uart2, Smart Card1, Smart Card2
Drive capability 4 mA
Drive capability 5 mA, INputs support Hysteresis
Drive capability 5 mA
I2S CLK and WS
Drive capability 4 mA
TS interface and I2S data lines
Hysteresis on inputs not supported
Hysteresis on inputs supported
SDRAM interface
Supports 5 V tolerant signalling, with 3.3 V
drive. (AD[11:0],CLK[1:0], RAS,CAS, CS,
BA[1:0] have drive capability 16 mA)
No 5 V tolerant signalling. Drive capability 14 mA
XIO SEL[2:0], ACK, A25
Drive capability 12 mA
Peripheral power supply
Drive capability 8 mA
Single connection on PCB for all VDD bondpads Requires separation of VDDC into 3 segments,
each segment filtered and star connected back to
source.[1]
Core power supply
Single connection on PCB for all VDDC
bondpads
Requires separation of VDDC into 2 segments,
each segment filtered and star connected back to
source.[2]
[1] The new connections are
VDD1 - The I/O supply connection
VDD2 - Analogue clock generation unit (CAB-Custom Analogue Block)
VDD3 - Trimedia™ clock generation PLL
[2] The new connections are
VDDC1 - Main core supply connection
VDDC2 - 1.728GHz PLL supply connection
15. Lifetime versus temperature
The relationship between operating (junction) temperature and the expected lifetime
of a device is shown in Figure 20.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
52 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
MGX461
25
handbook, halfpage
useful
life
(years)
20
15
10
5
0
100
105
110
115
120
125
T (°C)
j
Useful life (yrs) vs junction temperature (C). 1% cumm. fails, 8 hrs/day.
Fig 20. Lifetime dependency to temperature
Referring to Figure 20, at a junction temperature of 110 °C a 10 year lifetime can be
expected (8 hours/day). If increased to 125 °C, lifetime can be reduced to 4 years.
Junction temperature can be influenced by following the guidelines in Section 11.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
53 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
16. Package outline
HBGA456: plastic thermal enhanced ball grid array package; 456 balls;
body 35 x 35 x 1.8 mm; heatsink
SOT610-1
B
D
A
D
1
ball A1
index area
A
2
A
j
E
E
1
A
1
detail X
C
e
1
y
y
e
1/2 e
v
w
M
M
C
1
b
C
A
B
C
AF
AE
AD
AC
AB
AA
Y
e
W
V
U
T
R
P
e
2
N
M
L
1/2 e
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
shape
2
4
6
8
X
optional (4x)
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
E
e
e
e
2
j
y
y
D
D
E
v
w
1
1
1
2
1
1
max.
0.7
0.5
1.90
1.65
0.9
0.6
35.2 30.75 35.2 30.75
34.8 29.75 34.8 29.75
26
22
mm
2.6
0.2
0.35
1.27 31.75 31.75
0.3
0.15
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
00-12-13
02-01-30
SOT610-1
144E
MS-034
- - -
Fig 21. HBGA package outline
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
54 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
17. Soldering
17.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering can still
be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In
these situations reflow soldering is recommended. In these situations reflow soldering
is recommended.
17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
— for all BGA and SSOP-T packages
— for packages with a thickness ≥Š 2.5 mm
— for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11715
Preliminary data
Rev. 01 – 6 October 2003
55 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
• For packages with leads on two sides and a pitch (e):
— larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
— smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
17.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
17.5 Package related soldering information
Table 39: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, LBGA, LFBGA, SQFP, SSOP-T[3],
TFBGA, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP,
HSOP, HTQFP, HTSSOP, HVQFN, HVSON,
SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
PMFP[8]
suitable
suitable
not recommended[5][6]
not recommended[7]
not suitable
suitable
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
56 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side,
the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the
heatsink on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Hot bar or manual soldering is suitable for PMFP packages.
18. Revision history
Table 40: Revision history
Rev Date
CPCN
-
Description
01 20031006
Preliminary data (9397 750 11715)
9397 750 11715
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
57 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
19. Data sheet status
Level
Data sheet
status[1]
Product
status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published at a later
date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the
design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make
changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be
communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a
design.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
The product status of the device(s) described in this data sheet may have changed
since this data sheet was published. The latest information is available on the
Internet at URL http://www.semiconductors.philips.com.
Right to make changes – Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
[3]
For data sheets describing multiple type numbers, the highest-level product status
determines the data sheet status
20. Definitions
Short-form specification – The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition – Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
22. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
Application information – Applications that are described herein for any of
these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
21. Disclaimers
23. Trademarks
Life support – These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Nexperia – is a trademark of Koninklijke Philips Electronics N.V.
TriMedia – is a trademark of TriMedia Technologies Inc.
OpenCable – is a trademark of Cable Television Laboratories Inc.
Dolby ProLogic – is a registered trademark of Dolby Laboratories
CIMaX – is a registered trademark of SCM Microsystems Inc.
24. Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com.
9397 750 11715
© Philips Electronics N.V. 2003 All rights reserved.
Preliminary data
Rev. 01 – 6 October 2003
58 of 59
PNX8526
Programmable Source Decoder with Integrated Peripherals
Philips Semiconductors
Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
21
22
23
24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Contact information . . . . . . . . . . . . . . . . . . . . 58
6
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Multi-function pins. . . . . . . . . . . . . . . . . . . . . . 30
6.1
6.2
6.2.1
7
8
Functional description . . . . . . . . . . . . . . . . . . 37
I/O multiplexer control register. . . . . . . . . . . . 39
9
9.1
9.2
Power supply sequencing. . . . . . . . . . . . . . . . 40
Power on sequence . . . . . . . . . . . . . . . . . . . . 40
Power off sequence . . . . . . . . . . . . . . . . . . . . 41
10
11
12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal characteristics. . . . . . . . . . . . . . . . . . 41
Static characteristics. . . . . . . . . . . . . . . . . . . . 42
13
Dynamic characteristics . . . . . . . . . . . . . . . . . 43
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Peripheral Controller Interface (PCI) timing . . 43
Main Memory Interface (MMI) timing . . . . . . . 45
General Purpose Input/Output (GPIO) timing. 45
Universal Asynchronous Receiver/Transmitter
(UART) timing . . . . . . . . . . . . . . . . . . . . . . . . . 46
Synchronous Serial Interface (SSI) timing . . . 46
I2C-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . 47
IEEE 1394 Phy-Link interface. . . . . . . . . . . . . 47
I2S audio input & output timing. . . . . . . . . . . . 48
Sony Philips Digital Interface (SPDIF) timing . 49
Digital Video Output (DV Out) timing . . . . . . . 49
Digital Video Input (DV Input) timing. . . . . . . . 50
Transport Stream Output (TSO) timing. . . . . . 50
JTAG test contacts . . . . . . . . . . . . . . . . . . . . . 51
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12
13.13
13.14
14
Delta compared to PNX8525 . . . . . . . . . . . . . . 51
Lifetime versus temperature. . . . . . . . . . . . . . 52
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54
15
16
17
17.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Introduction to soldering surface mount packages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 55
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 55
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 56
Package related soldering information . . . . . . 56
17.2
17.3
17.4
17.5
18
19
20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 57
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 58
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
© Koninklijke Philips Electronics N.V. 2003.
Printed in Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 6 October 2003
Document order number: 9397 750 11715
相关型号:
PNX8526EH/M0
IC SPECIALTY CONSUMER CIRCUIT, PBGA456, 35 X 35 MM, 1.8 MM HEIGHT, PLASTIC, MS-034, SOT610-1, HBGA-456, Consumer IC:Other
NXP
PNX8526EH/M0/G
IC SPECIALTY CONSUMER CIRCUIT, PBGA456, 35 X 35 MM, 1.8 MM HEIGHT, LEAD FREE, PLASTIC, MS-034, SOT610-1, HBGA-456, Consumer IC:Other
NXP
©2020 ICPDF网 联系我们和版权申明