PPC5561MVZ80R_技术文档

Document Number: MPC5561

Rev. 3, June 2012

Freescale

Data Sheet: Technical Data

MPC5561

Microcontroller Data Sheet

Contents

This document provides electrical specifications, pin

assignments, and package diagrams for the MPC5561

microcontroller device. For functional characteristics,

refer to the MPC5561 Microcontroller Reference

Manual.

1

2

3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5

3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 EMI (Electromagnetic Interference) Characteristics 8

3.5 ESD (Electromagnetic Static Discharge) Characteris-

tics9

1

Overview

3.6 Voltage Regulator Controller (VRC) and

The MPC5561 microcontroller (MCU) is a member of

the MPC5500 family of microcontrollers built on the

Power-On Reset (POR) Electrical Specifications9

3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10

3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 14

3.9 Oscillator and FMPLL Electrical Characteristics . . 20

3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22

3.11 H7Fa Flash Memory Electrical Characteristics . . . 23

3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26



Power Architecture embedded technology. This family

of parts has many new features coupled with high

performance CMOS technology to provide substantial

reduction of cost per feature and significant performance

improvement over the MPC500 family.

4

5

Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.1 MPC5561 324 PBGA Pinouts . . . . . . . . . . . . . . . . 44

4.2 MPC5561 324-Pin Package Dimensions . . . . . . . 45

The host processor core of this device complies with the

Power Architecture embedded category that is 100%

user-mode compatible (including floating point library)

with the original PowerPC instruction set.The embedded

architecture enhancements improve the performance in

embedded applications. The core also has additional

instructions, including digital signal processing (DSP)

instructions, beyond the original PowerPC instruction

set.

Revision History for the MPC5561 Data Sheet . . . . . . 47

5.1 Information Changed Between Revisions 2.0 and 3.0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.2 Information Changed Between Revisions 1.0 and 2.0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3 Information Changed Between Revisions 0.0 and 1.0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Overview

The MPC5500 family of parts contains many new features coupled with high performance CMOS

technology to provide significant performance improvement over the MPC565.

The host processor core of the MPC5561 also includes an instruction set enhancement allowing variable

length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this

enhancement, it is possible to significantly reduce the code size footprint.

The MPC5561 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)

unified cache. The next level in the hierarchy contains the 192-KB on-chip internal SRAM and one

megabyte (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data.

The external bus interface is designed to support most of the standard memories used with the MPC5xx

family.

The less complex timer functions of the MPC5561 are performed by the enhanced modular input/output

system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,

pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include

edge-aligned and center-aligned PWM.

Off-chip communication is performed by a suite of serial protocols including controller area networks

(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications

interfaces (eSCIs).

The Parallel Digital Interface (PDI) block provides a glueless interface from the MPC5500 family of

devices to high speed external parallel devices such as Analog to Digital Convertors (ADCs) and image

sensors. The PDI module, with its internal Direct Memory Access (DMA) engine, moves external parallel

data into system memory with minimum intervention from the host processor. The host processor can also

read data from the PDI via an interrupt directly.

The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC).324 s 40-channels.

The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration

and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset

control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of

eQADC trigger sources and external interrupt signal multiplexing.

The FlexRay controller provides functional node networking, with static and dynamic host access, to

develop highly dependable automotive control systems that require the full implementation of the FlexRay

protocol, as published in FlexRay Protocol Specification 2.0. The FlexRay module uses fault-tolerant,

time-triggered events and clock synchronization mechanisms to maintain the global time of the functional

nodes. Bus guardian operations are available for each channel in a multi- or redundant-channel

configuration.

MPC5561 Microcontroller Data Sheet, Rev. 3

2

Freescale Semiconductor

Ordering Information

2

Ordering Information

5561

R

ZQ

80

M PC

M

Qualification status

Core code

Device number

Temperature range

Package identifier

Operating frequency (MHz)

Tape and reel status

Tape and Reel Status

R = Tape and reel

(blank) = Trays

Operating Frequency

80 = 80 MHz

112 = 112 MHz

132 = 132 MHz

Package Identifier

ZQ = 324PBGA SnPb

VZ = 324PBGA Pb-free

Temperature Range

M = –40° C to 125° C

Qualification Status

P = Pre qualification

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

Note: Not all options are available on all devices. Refer to Table 1.

Figure 1. MPC5500 Family Part Number Example

Unless noted in this data sheet, all specifications apply from T to T .

L

H

Table 1. Orderable Part Numbers

Operating Temperature ²

Speed (MHz)

Freescale Part Number¹

Package Description

Nominal

Max. ³(f_MAX

)

Min. (T_L)

Max. (T_H)

MPC5561MVZ132

MPC5561MVZ112

MPC5561MVZ80

MPC5561MZQ132

MPC5561MZQ112

MPC5561MZQ80

132

112

80

135

114

82

MPC5561 324 package

Lead-free (PbFree)

–40° C

125° C

132

112

80

135

114

82

MPC5561 324 package

Leaded (SnPb)

–40° C

125° C

1

All devices are PPC5561, rather than MPC5561 or SPC5561, until product qualifications are complete. Not all configurations are

available in the PPC parts.

2

3

The lowest ambient operating temperature is referenced by T_L; the highest ambient operating temperature is referenced by T_H.

Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).

82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and

135 MHz parts allow for 132 MHz system clock + 2% FM.

MPC5561 Microcontroller Data Sheet, Rev. 3

3

Freescale

Electrical Characteristics

3

Electrical Characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and

AC timing specifications for the MCU.

3.1

Maximum Ratings

1

Table 2. Absolute Maximum Ratings

Spec

Characteristic

1.5 V core supply voltage ²

Symbol

Min.

Max.

Unit

1

2

4

5

6

7

8

9

V_DD

V_PP

–0.3

1.7

6.5

4.6

1.7

4.6

5.5

4.6

6.5

V

Flash program/erase voltage

Flash read voltage

V_FLASH

V_STBY

V_DDSYN

V_DD33

V_RC33

V_DDA

SRAM standby voltage

Clock synthesizer voltage

3.3 V I/O buffer voltage

Voltage regulator control input voltage

Analog supply voltage (reference to V_SSA

)

10 I/O supply voltage (fast I/O pads) ³

11 I/O supply voltage (slow and medium I/O pads) ³

12 DC input voltage ⁴

V_DDEHpowered I/O pads

V_DDEpowered I/O pads

V_DDE

V_DDEH

V_IN

–1.0 ⁵

6.5 ⁶

4.6 ⁷

V

13 Analog reference high voltage (reference to V_RL

)

V_RH

–0.3

–0.1

5.5

0.1

V

14

15

V

_SSto V_SSAdifferential voltage

_DDto V_DDAdifferential voltage

V_SS– V_SSA

V_DD– V_DDA

V_RH– V_RL

V

–V_DDA

–0.3

V_DD

5.5

16 V_REFdifferential voltage

17

18

V

_RHto V_DDAdifferential voltage

_RLto V_SSAdifferential voltage

V_RH– V_DDA

V_RL– V_SSA

V_DDEH– V_DDA

V_DDF– V_DD

–5.5

5.5

V

–0.3

0.3

19 V_DDEHto V_DDAdifferential voltage

–V_DDA

–0.3

V_DDEH

0.3

20

21

V_DDFto V_DDdifferential voltage

V_RC33to V_DDSYNdifferential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a.

22 V_SSSYNto V_SSdifferential voltage

23 _RCVSSto V_SSdifferential voltage

24 Maximum DC digital input current ⁸

V_SSSYN– V_SS

V_RCVSS– V_SS

I_MAXD

–0.1

–2

0.1

2

V

mA

4

(per pin, applies to all digital pins)

25 Maximum DC analog input current ⁹

(per pin, applies to all analog pins)

26 Maximum operating temperature range ¹⁰

Die junction temperature

I_MAXA

T_J

–3

T_L

3

mA

^oC

150.0

27 Storage temperature range

T_STG

–55.0

MPC5561 Microcontroller Data Sheet, Rev. 3

4

Freescale Semiconductor

Electrical Characteristics

1

Table 2. Absolute Maximum Ratings (continued)

Spec

Characteristic

Symbol

Min.

Max.

Unit

28 Maximum solder temperature ¹¹

Lead free (Pb-free)

Leaded (SnPb)

29 Moisture sensitivity level ¹²

T_SDR

MSL

—

260.0

245.0

^oC

—

3

1

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,

and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability

or cause permanent damage to the device.

2

3

4

1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 ^oC.

All functional non-supply I/O pins are clamped to V_SSand V_DDE, or V_DDEH

.

AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of

60 hours over the complete lifetime of the device (injection current not limited for this duration).

5

6

7

Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC

voltage greater than –0.6 V on SINB during the internal power-on reset (POR) state.

Internal structures hold the input voltage less than the maximum voltage on all pads powered by V_DDEHsupplies, if the

maximum injection current specification is met (2 mA for all pins) and V_DDEHis within the operating voltage specifications.

Internal structures hold the input voltage less than the maximum voltage on all pads powered by V_DDEsupplies, if the maximum

injection current specification is met (2 mA for all pins) and V_DDEis within the operating voltage specifications.

Total injection current for all pins (including both digital and analog) must not exceed 25 mA.

Total injection current for all analog input pins must not exceed 15 mA.

8

9

¹⁰Lifetime operation at these specification limits is not guaranteed.

¹¹Moisture sensitivity profile per IPC/JEDEC J-STD-020D.

¹²Moisture sensitivity per JEDEC test method A112.

3.2

Thermal Characteristics

The shaded rows in the following table indicate information specific to a four-layer board.

Table 3. MPC5561 Thermal Characteristics (Preliminary Values)

Spec

MPC5561 Thermal Characteristic

Symbol

324 PBGA

Unit

1

2

3

4

5

6

7

Junction to ambient ^{1, 2}, natural convection (one-layer board)

Junction to ambient ^{1, 3}, natural convection (four-layer board 2s2p)

Junction to ambient (@200 ft./min., one-layer board)

Junction to ambient (@200 ft./min., four-layer board 2s2p)

Junction to board (four-layer board 2s2p) ⁴

R_JA

R_JMA

R_JB

R_JC

_JT

29

19

22

16

10

7

°C/W

Junction to case ⁵

Junction to package top, natural convection ⁶

2

1

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2

3

4

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

5

6

MPC5561 Microcontroller Data Sheet, Rev. 3

5

Freescale

Electrical Characteristics

3.2.1

General Notes for Specifications at Maximum Junction Temperature

An estimation of the device junction temperature, T , can be obtained from the equation:

J

T = T + (R

 P )

D

J

A

JA

where:

o

T = ambient temperature for the package ( C)

A

o

R

= junction to ambient thermal resistance ( C/W)

JA

P = power dissipation in the package (W)

D

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide

consistent values for estimations and comparisons. The difference between the values determined for the

single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground

plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance

depends on the:

•

Construction of the application board (number of planes)

Effective size of the board which cools the component

Quality of the thermal and electrical connections to the planes

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to

connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal

performance. When the clearance between the vias leave the planes virtually disconnected, the thermal

performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly

packed printed circuit board. The value obtained on a board with the internal planes is usually within the

normal range if the application board has:

•

One oz. (35 micron nominal thickness) internal planes

Components are well separated

2

Overall power dissipation on the board is less than 0.02 W/cm

The thermal performance of any component depends on the power dissipation of the surrounding

components. In addition, the ambient temperature varies widely within the application. For many natural

convection and especially closed box applications, the board temperature at the perimeter (edge) of the

package is approximately the same as the local air temperature near the device. Specifying the local

ambient conditions explicitly as the board temperature provides a more precise description of the local

ambient conditions that determine the temperature of the device.

MPC5561 Microcontroller Data Sheet, Rev. 3

6

Freescale Semiconductor

Electrical Characteristics

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

 P )

D

J

B

JB

where:

o

T = junction temperature ( C)

J

o

T = board temperature at the package perimeter ( C/W)

B

o

R

= junction-to-board thermal resistance ( C/W) per JESD51-8

JB

P = power dissipation in the package (W)

D

When the heat loss from the package case to the air does not factor into the calculation, an acceptable value

for the junction temperature is predictable. Ensure the application board is similar to the thermal test

condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a

case-to-ambient thermal resistance:

R

= R

+ R

JA

JC CA

where:

o

R

= junction-to-ambient thermal resistance ( C/W)

JA

JC

CA

o

= junction-to-case thermal resistance ( C/W)

o

= case-to-ambient thermal resistance ( C/W)

R

is device related and is not affected by other factors. The thermal environment can be controlled to

JC

change the case-to-ambient thermal resistance, R

. For example, change the air flow around the device,

CA

add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal

dissipation on the printed circuit board surrounding the device. This description is most useful for

packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.

For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal

resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes

when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The

junction-to-board thermal resistance describes the thermal performance when most of the heat is

conducted to the printed circuit board. This model can be used to generate simple estimations and for

computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the

thermal characterization parameter ( ) to determine the junction temperature by measuring the

JT

temperature at the top center of the package case using the following equation:

T = T + (  P )

J

T

JT

D

where:

o

T = thermocouple temperature on top of the package ( C)

T

o



= thermal characterization parameter ( C/W)

JT

P = power dissipation in the package (W)

D

MPC5561 Microcontroller Data Sheet, Rev. 3

7

Freescale

Electrical Characteristics

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using

a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple

so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple

junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat

against the package case to avoid measurement errors caused by the cooling effects of the thermocouple

wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Rd.

San Jose, CA., 95134

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at

800-854-7179 or 303-397-7956.

JEDEC specifications are available on the web at http://www.jedec.org.

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive

Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applica-

tions,” Electronic Packaging and Production, pp. 53–58, March 1998.

3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and

Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

3.3

Package

The MPC5561 is available in packaged form. Read the package options in Section 2, “Ordering

Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.

3.4

EMI (Electromagnetic Interference) Characteristics

1

Table 4. EMI Testing Specifications

Spec

Characteristic

Minimum

Typical

Maximum

Unit

1

2

3

4

5

6

Scan range

0.15

—

1000

f_MAX

—

MHz

V

Operating frequency

V_DDoperating voltages

_DDSYN, V_RC33, V_DD33, V_FLASH, V_DDEoperating voltages

—

1.5

3.3

5.0

—

V

—

V

V_PP, V_DDEH, V_DDAoperating voltages

Maximum amplitude

—

14 ²

32 ³

V

—

dBuV

7

Operating temperature

—

25

^oC

1

EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554

and applied to the MPC5500 family as generic EMI performance data.

2

3

Measured with the single-chip EMI program.

Measured with the expanded EMI program.

MPC5561 Microcontroller Data Sheet, Rev. 3

8

Freescale Semiconductor

Electrical Characteristics

3.5

ESD (Electromagnetic Static Discharge) Characteristics

1, 2

Table 5. ESD Ratings

Characteristic

Symbol

Value

Unit

ESD for human body model (HBM)

HBM circuit description

2000

1500

V



R1

C

100

pF

500 (all pins)

750 (corner pins)

ESD for field induced charge model (FDCM)

V

Number of pulses per pin:

Positive pulses (HBM)

Negative pulses (HBM)

—

1

—

Interval of pulses

—

1

second

1

All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2

Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements,

which includes the complete DC parametric and functional testing at room temperature and hot temperature.

3.6

Voltage Regulator Controller (V ) and

Power-On Reset (POR) Electrical Specifications

RC

The following table lists the V and POR electrical specifications:

RC

Table 6. V and POR Electrical Specifications

RC

Spec

Characteristic

Negated (ramp up)

Symbol

V_POR15

Min.

Max. Units

1.1

1.35

V

1

1.5 V (V_DD) POR ¹

Asserted (ramp down)

1.35

Asserted (ramp up)

Negated (ramp up)

Asserted (ramp down)

Negated (ramp down)

0.0

2.0

0.0

0.30

2.85

0.30

2

3.3 V (V_DDSYN) POR ¹

V_POR33

V

Negated (ramp up)

2.0

2.85

RESET pin supply

(V_DDEH6) POR ^{1, 2}

3

4

5

V_POR5

V

Asserted (ramp down)

Before V_RCallows the pass

transistor to start turning on

V_{TRANS_START}

V_{TRANS_ON}

1.0

2.0

V

When V_RCallows the pass

2.85

V_RC33voltage

transistor to completely turn on ^{3, 4}

When the voltage is greater than

the voltage at which the V_RCkeeps

the 1.5 V supply in regulation ^{5, 6}

–40^oC

25^oC

6

7

8

V_VRC33REG

3.0

—

V

Current can be sourced

by V_RCCTLat Tj:

11.0

9.0

—

mA

7

I_VRCCTL

150^oC

7.5

Voltage differential during power up such that:

V_DD33can lag V_DDSYNor V_DDEH6before V_DDSYNand V_DDEH6reach the

V_POR33and V_POR5minimums respectively.

V_{DD33_LAG}

—

1.0

V

MPC5561 Microcontroller Data Sheet, Rev. 3

9

Freescale

Electrical Characteristics

Spec

Table 6. V and POR Electrical Specifications (continued)

RC

Characteristic

Symbol

Min.

Max. Units

9

Absolute value of slew rate on power supply pins

—

50

—

V/ms

—

Required gain at Tj:

I_DD I_VRCCTL(@ f_sys= f_MAX

– 40^oC

25^oC

60

)

BETA¹⁰

65

85

—

10

6, 7, 8, 9

150^oC

500

—

1

The internal POR signals are V_POR15, V_POR33, and V_POR5. On power up, assert RESET before the internal POR negates.

RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical

Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the

internal POR asserts.

2

3

4

5

6

V_{IL_S}(Table 9, Spec15) is guaranteed to scale with V_DDEH6down to V_POR5

.

Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.

It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.

At peak current for device.

Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal

traces/routing from the V_RCCTLpackage signal to the base of the external pass transistor and between the emitter of the pass

transistor to the V_DDpackage signals must have a maximum of 100 nH inductance and minimal resistance

(less than 1 ). V_RCCTLmust have a nominal 1 F phase compensation capacitor to ground. V_DDmust have a 20 F (nominal)

bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of

eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the V_DDsupply signals.

7

8

9

I_VRCCTLis measured at the following conditions: V_DD= 1.35 V, V_RC33= 3.1 V, V_VRCCTL= 2.2 V.

Refer to Table 1 for the maximum operating frequency.

Values are based on I_DDfrom high-use applications as explained in the I_DDElectrical Specification.

¹⁰Represents the worst-case external transistor BETA. It is measured on a per-part basis and calculated as (I_DD I_VRCCTL).

3.7

Power-Up/Down Sequencing

Power sequencing between the 1.5 V power supply and V

or the RESET power supplies is required

DDSYN

if using an external 1.5 V power supply with V

tied to ground (GND). To avoid power-sequencing,

RC33

V

must be powered up within the specified operating range, even if the on-chip voltage regulator

RC33

controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and

Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”

Power sequencing requires that V

must reach a certain voltage where the values are read as ones

DD33

before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on

VDD33.”

Although power sequencing is not required between V

and V

during power up, V

must

RC33

DDSYN

not lead V

by more than 600 mV or lag by more than 100 mV for the V stage turn-on to operate

DDSYN

RC

within specification. Higher spikes in the emitter current of the pass transistor occur if V

leads or lags

RC33

V

by more than these amounts. The value of that higher spike in current depends on the board power

DDSYN

supply circuitry and the amount of board level capacitance.

Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase

of the current consumed by V . If V lags V by more than 100 mV, the increase in current

RC33

DDSYN

consumed can drop V low enough to assert the 1.5 V POR again. Oscillations are possible when the

DD

MPC5561 Microcontroller Data Sheet, Rev. 3

10

Freescale Semiconductor

Electrical Characteristics

1.5 V POR asserts and stops the system clock, causing the voltage on V to rise until the 1.5 V POR

DD

negates again. All oscillations stop when V

is powered sufficiently.

RC33

When powering down, V

and V

have no delta requirement to each other, because the bypass

RC33

DDSYN

capacitors internal and external to the device are already charged. When not powering up or down, no delta

between V and V is required for the V to operate within specification.

RC33

DDSYN

RC

There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current

spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending

on which supplies are powered.

Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).

Table 7. Pin Status for Fast Pads During the Power Sequence

Pin Status for Fast Pad Output Driver

V_DDE

V_DD33

V_DD

POR

pad_fc (fast)

Low

—

Asserted

Negated

Low

V_DDE

Low

V_DD

Low

V_DD

High

Low

V_DD33

High impedance (Hi-Z)

Hi-Z

Functional

Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and

pad_sh (slow type).

Table 8. Pin Status for Medium and Slow Pads During the Power Sequence

Pin Status for Medium and Slow Pad Output Driver

V_DDEH

V_DD

POR

pad_mh (medium) pad_sh (slow)

Low

—

Asserted

Negated

Low

High impedance (Hi-Z)

Hi-Z

V_DDEH

Low

V_DD

Functional

The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins

during power up.

Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR

negates. When the internal POR negates, the functional state of the signal during reset applies and the

weak-pull devices

(up or down) are enabled as defined in the device reference manual. If V is too low to correctly

DD

propagate the logic signals, the weak-pull devices can pull the signals to V

and V

.

DDE

DDEH

To avoid this condition, minimize the ramp time of the V supply to a time period less than the time

DD

required to enable the external circuitry connected to the device outputs.

MPC5561 Microcontroller Data Sheet, Rev. 3

11

Freescale

Electrical Characteristics

During initial power ramp-up, when V

is 0.6v or above. a typical current of 1-3mA and maximum of

stby

4mA may be seen until V is applied. This current will not reoccur until V

is lowered below V

DD

stby

min. specification.

Figure 2 shows an approximate interpolation of the I

worst-case specification to estimate values at

STBY

different voltages and temperatures. The vertical lines shown at 25 ^C, 60 ^C, and 150 ^C in Figure 2 are

the actual I

specifications (27d) listed in Table 9.

DD_STBY

Figure 2. fI

Worst-case Specifications

STBY

MPC5561 Microcontroller Data Sheet, Rev. 3

12

Freescale Semiconductor

Electrical Characteristics

3.7.1

Input Value of Pins During POR Dependent on V_DD33

When powering up the device, V

must not lag the latest V

or RESET power pin (V

) by

DD33

DDSYN

DDEH6

more than the V

lag specification listed in Table 6, spec 8. This avoids accidentally selecting the

DD33

bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and

therefore cannot read the default state when POR negates. V can lag V or the RESET power

DD33

DDSYN

pin (V

), but cannot lag both by more than the V

lag specification. This V

lag specification

DDEH6

DD33

applies during power up only. V

has no lead or lag requirements when powering down.

DD33

3.7.2

Power-Up Sequence (V_RC33Grounded)

The 1.5 V V power supply must rise to 1.35 V before the 3.3 V V

power supply and the RESET

DDSYN

DD

power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does

not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V

POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since

they can negate as low as 2.0 V, V must be within specification before the 3.3 V POR and the RESET

DD

POR negate.

V_DDSYNand RESET Power

V_DD

2.0 V

1.35 V

V_DDmust reach 1.35 V before V_DDSYNand the RESET power reach 2.0 V

Figure 3. Power-Up Sequence (V

Grounded)

RC33

3.7.3

Power-Down Sequence (V_RC33Grounded)

The only requirement for the power-down sequence with V

grounded is if V decreases to less than

DD

RC33

its operating range, V

or the RESET power must decrease to less than 2.0 V before the V power

DDSYN

DD

increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed

POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See

Table 6, footnote 1.

MPC5561 Microcontroller Data Sheet, Rev. 3

13

Freescale

Electrical Characteristics

3.8

DC Electrical Specifications

Table 9. DC Electrical Specifications (T = T to T )

A

L

H

Spec

Characteristic

Symbol

Min

Max.

Unit

1

2

3

4

5

6

8

9

Core supply voltage (average DC RMS voltage)

Input/output supply voltage (fast input/output) ¹

Input/output supply voltage (slow and medium input/output)

3.3 V input/output buffer voltage

V_DD

V_DDE

1.35

1.62

3.0

4.5

3.0

0.8

3.0

1.65

3.6

V

V_DDEH

V_DD33

V_RC33

V_DDA

5.25

3.6

Voltage regulator control input voltage

Analog supply voltage ²

3.6

5.25

Flash programming voltage ³

V_PP

5.25

Flash read voltage

V_FLASH

V_STBY

V_DDSYN

V_{IH_F}

3.6

10 SRAM standby voltage ⁴

1.2

11 Clock synthesizer operating voltage

12 Fast I/O input high voltage

3.6

0.65  V_DDE

V_SS– 0.3

V_DDE+ 0.3

0.35  V_DDE

V_DDEH+ 0.3

0.35  V_DDEH

13 Fast I/O input low voltage

V_{IL_F}

14 Medium and slow I/O input high voltage

15 Medium and slow I/O input low voltage

16 Fast input hysteresis

V_{IH_S}

V_{IL_S}

0.65  V_DDEH

V_SS– 0.3

V_{HYS_F}

V_{HYS_S}

V_INDC

V_{OH_F}

0.1  V_DDE

0.1  V_DDEH

17 Medium and slow I/O input hysteresis

18 Analog input voltage

V_SSA– 0.3

V_DDA+ 0.3

—

19 Fast output high voltage (I_{OH_F}= –2.0 mA)

0.8  V_DDE

20 Slow and medium output high voltage

I_{OH_S}= –2.0 mA

V_{OH_S}

V_{OL_F}

V_{OL_S}

0.80  V_DDEH

0.85  V_DDEH

—

V

I_{OH_S}= –1.0 mA

21 Fast output low voltage (I_{OL_F}= 2.0 mA)

—

0.2  V_DDE

V

22 Slow and medium output low voltage

I_{OL_S}= 2.0 mA

0.20  V_DDEH

0.15  V_DDEH

I_{OL_S}= 1.0 mA

23 Load capacitance (fast I/O) ⁵

DSC (SIU_PCR[8:9]) = 0b00

—

10

20

30

50

pF

= 0b01

= 0b10

= 0b11

C_L

24 Input capacitance (digital pins)

25 Input capacitance (analog pins)

C_IN

—

7

pF

C_{IN_A}

10

26 Input capacitance:

(Shared digital and analog pins AN[12]_MA[0]_SDS,

AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)

C_{IN_M}

—

12

pF

MPC5561 Microcontroller Data Sheet, Rev. 3

14

Freescale Semiconductor

Electrical Characteristics

Table 9. DC Electrical Specifications (T = T to T ) (continued)

A

L

H

Spec

Characteristic

Symbol

Min

Max.

Unit

27a Operating current 1.5 V supplies @ 135 MHz: ⁶

8-way cache ⁷

V_DD(including V_DDFmax current) @1.65 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.35 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

4-way cache ¹¹

I_DD

—

620

440

670

490

mA

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

I_DD

—

610

430

mA

27b Operating current 1.5 V supplies @ 114 MHz: ⁶

8-way cache ⁷

V_DD(including V_DDFmax current) @1.65 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.35 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

4-way cache ¹¹

I_DD

—

590

395

580

390

mA

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

I_DD

—

550

385

mA

27c Operating current 1.5 V supplies @ 82 MHz: ⁶

8-way cache ⁷

V_DD(including V_DDFmax current) @1.65 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.35 V typical use ^{8, 9}

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

4-way cache ¹¹

I_DD

—

485

320

470

315

mA

V_DD(including V_DDFmax current) @1.65 V high use ^{9, 10}

V_DD(including V_DDFmax current) @1.35 V high use ^{9, 10}

I_DD

—

400

310

mA

27d RAM standby current.¹²

I_{DD_STBY}@ 25^oC

V_STBY@ 0.8 V

I_{DD_STBY}

—

20

30

50

A

V_STBY@ 1.0 V

V_STBY@ 1.2 V

I_{DD_STBY}@ 60^oC

V_STBY@ 0.8 V

V_STBY@ 1.0 V

V_STBY@ 1.2 V

I_{DD_STBY}

—

70

100

200

A

I_{DD_STBY}@ 150^oC (Tj)

V_STBY@ 0.8 V

I_{DD_STBY}

—

1200

1500

2000

A

V_STBY@ 1.0 V

V_STBY@ 1.2 V

28 Operating current 3.3 V supplies @ f_MAXMHz

13

V_DD33

I_{DD_33}

—

2 + (values

derived from

procedure of

mA

footnote ¹³

)

V_FLASH

V_DDSYN

I_VFLASH

I_DDSYN

—

10

15

mA

MPC5561 Microcontroller Data Sheet, Rev. 3

15

Freescale

Electrical Characteristics

Table 9. DC Electrical Specifications (T = T to T ) (continued)

A

L

H

Spec

Characteristic

Symbol

Min

Max.

Unit

29 Operating current 5.0 V supplies (12 MHz ADCLK):

V_DDA(V_DDA0+ V_DDA1

)

I_{DD_A}

I_REF

I_PP

—

20.0

1.0

25.0

mA

Analog reference supply current (V_RH, V_RL

)

V_PP

30 Operating current V_DDEsupplies: ¹⁴

V_DDEH1

V_DDE2

V_DDE3

V_DDEH4

V_DDE5

V_DDEH6

V_DDE7

V_DDEH8

V_DDEH9

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

I_DD8

I_DD9

—

Refer to

mA

footnote ¹⁴

31 Fast I/O weak pullup current ¹⁵

1.62–1.98 V

10

20

110

130

170

A

2.25–2.75 V

3.00–3.60 V

I_{ACT_F}

Fast I/O weak pulldown current ¹⁵

1.62–1.98 V

10

20

100

130

170

A

2.25–2.75 V

3.00–3.60 V

32 Slow and medium I/O weak pullup/down current ¹⁵

3.0–3.6 V

4.5–5.5 V

I_{ACT_S}

10

20

150

170

A

33 I/O input leakage current ¹⁶

34 DC injection current (per pin)

35 Analog input current, channel off ¹⁷

I_{INACT_D}

I_IC

–2.5

–2.0

–150

2.5

2.0

A

mA

nA

I_{INACT_A}

150

35a Analog input current, shared analog / digital pins

(AN[12], AN[13], AN[14], AN[15])

I_{INACT_AD}

–2.5

2.5

A

36

V

_SSto V_SSAdifferential voltage ¹⁸

V_SS– V_SSA

V_RL

V_RL– V_SSA

V_RH

–100

V_SSA– 0.1

–100

100

V_SSA+ 0.1

100

mV

V

37 Analog reference low voltage

38 V_RLdifferential voltage

mV

V

39 Analog reference high voltage

V_DDA– 0.1

4.5

V_DDA+ 0.1

5.25

40 V_REFdifferential voltage

V_RH– V_RL

V

41 V_SSSYNto V_SSdifferential voltage

42 V_RCVSSto V_SSdifferential voltage

43 V_DDFto V_DDdifferential voltage

43a V_RC33to V_DDSYNdifferential voltage

44 Analog input differential signal range (with common mode 2.5 V)

V_SSSYN– V_SS

V_RCVSS– V_SS

V_DDF– V_DD

V_RC33– V_DDSYN

V_IDIFF

–50

50

mV

V

–50

50

–100

100

–0.1

0.1 ¹⁹

2.5

–2.5

V

MPC5561 Microcontroller Data Sheet, Rev. 3

16

Freescale Semiconductor

Electrical Characteristics

Table 9. DC Electrical Specifications (T = T to T ) (continued)

A

L

H

Spec

Characteristic

Symbol

Min

Max.

Unit

45 Operating temperature range, ambient (packaged)

46 Slew rate on power-supply pins

T_A= (T_Lto T_H)

—

T_L

—

T_H

50

^C

V/ms

1

V_DDE2and V_DDE3are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; V_DDE2and V_DDE3have a range of 1.6–3.6 V if

SIU_ECCR[EBTS] = 1.

2

3

4

5

6

7

8

9

| V_DDA0– V_DDA1| must be < 0.1 V.

V_PPcan drop to 3.0 V during read operations.

If standby operation is not required, connect V_STBYto ground.

Applies to CLKOUT, external bus pins, and Nexus pins.

Maximum average RMS DC current.

Eight-way cache enabled (L1CSR0[CORG] = 0b0).

Average current measured on automotive benchmark.

Peak currents can be higher on specialized code.

¹⁰High-use current measured while running optimized SPE assembly code with all code and data 100% locked in cache

(0% miss rate) with all channels of the eMIOS running autonomously, plus the eDMA transferring data continuously from SRAM to

SRAM. Higher currents are possible if an ‘idle’ loop that crosses cache lines is run from cache. Write code to avoid this condition.

¹¹Four-way cache enabled (L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,

L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).

¹²The current specification relates to average standby operation after SRAM has been loaded with data. For power up current see

Section 3.7, “Power-Up/Down Sequencing”, Figure 2.

¹³Power requirements for the V_DD33supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O

segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.

¹⁴Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O

segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The

total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.

¹⁵Absolute value of current, measured at V_ILand V_IH.

¹⁶Weak pullup/down inactive. Measured at V_DDE= 3.6 V and V_DDEH= 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.

¹⁷Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 ^oC

to 12 ^oC, in the ambient temperature range of 50 ^oC to 125 ^oC. Applies to pad types: pad_a and pad_ae.

18

V

refers to both V_SSA0and V_SSA1. | V_SSA0– V_SSA1| must be < 0.1 V.

SSA

¹⁹Up to 0.6 V during power up and power down.

MPC5561 Microcontroller Data Sheet, Rev. 3

17

Freescale

Electrical Characteristics

3.8.1

I/O Pad Current Specifications

The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The

power consumption is the sum of all output pin currents for a segment. The output pin current can be

calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to

calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 10.

1

Table 10. I/O Pad Average DC Current (T = T to T )

A

L

H

Drive Select /

Slew Rate

Control Setting

Frequency

(MHz)

Spec

Pad Type

Symbol

Load²(pF)

Voltage (V)

Current (mA)

1

25

10

2

50

200

50

200

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

5.25

3.6

11

01

00

11

01

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

8.0

3.2

0.7

2.4

17.3

6.5

1.1

3.9

2.8

5.2

8.5

11.0

1.6

2.9

4.2

6.7

2.4

4.4

7.2

9.3

1.3

2.5

3.5

5.7

1.7

3.1

5.1

6.6

1.0

1.8

2.5

4.0

2

Slow

I_{DRV_SH}

3

4

2

5

50

20

3.33

66

56

40

6

Medium

I_{DRV_MH}

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

3.6

1.98

3.6

Fast

I_{DRV_FC}

1.98

3.6

1.98

1

2

These values are estimates from simulation and are not tested. Currents apply to output pins only.

All loads are lumped.

MPC5561 Microcontroller Data Sheet, Rev. 3

18

Freescale Semiconductor

Electrical Characteristics

3.8.2

I/O Pad V_DD33Current Specifications

The power consumption of the V

supply dependents on the usage of the pins on all I/O segments. The

DD33

power consumption is the sum of all input and output pin V

currents for all I/O segments. The output

DD33

pin V

current can be calculated from Table 11 based on the voltage, frequency, and load on all fast

DD33

(pad_fc) pins. The input pin V

current can be calculated from Table 11 based on the voltage,

DD33

frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,

frequency, and load parameters that fall outside the values given in Table 11.

1

Table 11. V

Pad Average DC Current (T = T to T )

DD33

A

L

H

Frequency

(MHz)

Load ²

(pF)

V_DD33

(V)

V_DDE

(V)

Drive

Select

Current

(mA)

Spec

Pad Type

Symbol

Inputs

1

2

Slow

I_{33_SH}

I_{33_MH}

66

0.5

3.6

5.5

NA

0.003

Medium

Outputs

3

66

56

40

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

10

20

30

50

3.6

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0.35

0.53

0.62

0.79

0.35

0.44

0.53

0.70

0.30

0.45

0.52

0.67

0.30

0.37

0.45

0.60

0.21

0.31

0.37

0.48

0.21

0.27

0.32

0.42

4

5

3.6

6

3.6

7

1.98

3.6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

3.6

Fast

I_{33_FC}

1.98

3.6

1.98

1

2

These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input

pins for the slow and medium pads only.

All loads are lumped.

MPC5561 Microcontroller Data Sheet, Rev. 3

19

Freescale

Electrical Characteristics

3.9

Oscillator and FMPLL Electrical Characteristics

Table 12. FMPLL Electrical Specifications

(V_DDSYN= 3.0–3.6 V; V_SS= V_SSSYN= 0.0 V; T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Minimum

Maximum

Unit

PLL reference frequency range: ¹

Crystal reference (20)²

f_{ref_crystal}

f_{ref_ext}

f_{ref_1:1}

8

> 20

8

> 20

24

20

40

20

40

Crystal reference (40)³

1

MHz

External reference (20)²

External reference (40)³

Dual controller (1:1 mode)

f_sys 2

5

2

3

4

5

System frequency ⁴

f_sys

t_CYC

f

_ICO(MIN) 2^RFD

f_MAX

MHz

ns

System clock period

—

100

7.4

1  f_sys

1000

17.5

—

Loss of reference frequency ⁶

Self-clocked mode (SCM) frequency ⁷

EXTAL input high voltage crystal mode ⁸

f_LOR

kHz

MHz

V

f_SCM

V_IHEXT

V_XTAL+ 0.4 V

6

7

All other modes

[dual controller (1:1), bypass, external reference]

V_IHEXT

V_ILEXT

(V_DDE5 2) + 0.4 V

—

V

EXTAL input low voltage crystal mode ⁹

—

V

_XTAL– 0.4 V

All other modes

[dual controller (1:1), bypass, external reference]

V_ILEXT

I_XTAL

—

2

(V_DDE52) – 0.4 V

V

8

9

XTAL current ¹⁰

6

mA

pF

Total on-chip stray capacitance on XTAL

Total on-chip stray capacitance on EXTAL

C_{S_XTAL}

C_{S_EXTAL}

C_L

—

1.5

10

Crystal manufacturer’s recommended capacitive

load

Refer to crystal

specification

Refer to crystal

specification

11

12

Discrete load capacitance to connect to EXTAL

Discrete load capacitance to connect to XTAL

PLL lock time ¹²

C_{L_EXTAL}

(2  C_L)– C_{S_EXTAL}

– C_{PCB_EXTAL}

pF

—

11

C_{L_XTAL}

(2  C_L) – C_{S_XTAL}

13

14

15

11

– C_{PCB_XTAL}

t_lpll

—

750

2

s

Dual controller (1:1) clock skew

t_skew

–2

ns

(between CLKOUT and EXTAL) ^{13, 14}

16

17

18

Duty cycle of reference

Frequency unLOCK range

Frequency LOCK range

t_DC

f_UL

40

60

4.0

2.0

%

–4.0

–2.0

% f_SYS

f_LCK

MPC5561 Microcontroller Data Sheet, Rev. 3

20

Freescale Semiconductor

Electrical Characteristics

Table 12. FMPLL Electrical Specifications (continued)

(V_DDSYN= 3.0–3.6 V; V_SS= V_SSSYN= 0.0 V; T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Minimum

Maximum

Unit

CLKOUT period jitter, measured at f_SYSmax: ^{15, 16}

Peak-to-peak jitter (clock edge to clock edge)

Long term jitter (averaged over a 2 ms interval)

C_JITTER

%

f_CLKOUT

19

—

5.0

0.01

Frequency modulation range limit ¹⁷

(do not exceed f_sysmaximum)

%f_SYS

20

C_MOD

0.8

2.4

ICO frequency

21

22

f_ico= [f_{ref_crystal} (MFD + 4)] (PREDIV + 1) ¹⁸

f_ico= [f_{ref_ext} (MFD + 4)] (PREDIV + 1)

f_ico

48

4

f_MAX

MHz

Predivider output frequency (to PLL)

f_PREDIV

20 ¹⁹

1

Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency

remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.

The designer must thoroughly understand the drift margin of the source clock.

2

3

The 8–20 MHz crystal or external reference values have PLLCFG[2] pulled low.

The 20–40 MHz crystal and external reference values have PLLCFG[2] pulled high, and the minimum frequency must be greater

than 20 MHz. Use the 8–20 MHz setting (PLLCFG[2] pulled low) if a 20 MHz crystal or external reference is required.

To exit RESET when using 40 MHz, set PLLCFG[2] to 1.

4

5

6

All internal registers retain data at 0 Hz.

Up to the maximum frequency rating of the device (refer to Table 1).

Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked

mode.

7

The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f_LOR. SCM frequency is

measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.

NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.

8

9

Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or

resonators). (V_extal– V_xtal) must be  400 mV for the oscillator’s comparator to produce the output clock.

Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or

resonators). (V_xtal– V_extal) must be  400 mV for the oscillator’s comparator to produce the output clock.

10

11

I

is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

xtal

C

and C_{PCB_XTAL}are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

PCB_EXTAL

¹²This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal

startup time.

¹³PLL is operating in 1:1 PLL mode.

14

V

= 3.0–3.6 V.

DDE

¹⁵Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDSYNand V_SSSYNand variation in crystal oscillator frequency increase the jitter percentage

for a given interval. CLKOUT divider is set to divide-by-two.

¹⁶Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).

¹⁷Modulation depth selected must not result in f_sysvalue greater than the f_sysmaximum specified value.

¹⁸f = f  (2^RFD).

sys

ico

¹⁹Maximum value for dual controller (1:1) mode is (f_MAX2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).

MPC5561 Microcontroller Data Sheet, Rev. 3

21

Freescale

Electrical Characteristics

3.10 eQADC Electrical Characteristics

Table 13. eQADC Conversion Specifications (T_A= T_Lto T_H)

Spec

Characteristic

ADC clock (ADCLK) frequency ¹

Symbol

Minimum

Maximum

Unit

1

F_ADCLK

CC

1

12

MHz

Conversion cycles

Differential

ADCLK

cycles

2

13 + 2 (15)

14 + 2 (16)

13 + 128 (141)

14 + 128 (142)

Single ended

3

4

5

6

7

8

9

Stop mode recovery time ²

Resolution ³

T_SR

—

10

1.25

–4

—

4

s

mV

INL: 6 MHz ADC clock

INL: 12 MHz ADC clock

DNL: 6 MHz ADC clock

DNL: 12 MHz ADC clock

Offset error with calibration

INL6

Counts ³

Counts

mA

INL12

DNL6

DNL12

OFFWC

GAINWC

I_INJ

–8

8

–3 ⁴

–6 ⁴

–4 ⁵

–8 ⁶

–1

3 ⁴

6 ⁴

4 ⁵

8 ⁶

1

10 Full-scale gain error with calibration

11 Disruptive input injection current ^{7, 8, 9, 10}

Incremental error due to injection current. All channels are

10 k < Rs <100 k

12

E_INJ

–4

4

Counts

Channel under test has Rs = 10 k,

I_INJ= I_INJMAX, I_INJMIN

Total unadjusted error (TUE) for single ended conversions

13

TUE

–4

4

Counts

with calibration ^{11, 12, 13, 14, 15}

1

2

Conversion characteristics vary with F_ADCLKrate. Reduced conversion accuracy occurs at maximum F_ADCLKrate. The

maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a

maximum 16 factor.

Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform

conversions.

3

4

5

6

7

At V_RH– V_RL= 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.

Guaranteed 10-bit mono tonicity.

The absolute value of the offset error without calibration  100 counts.

The absolute value of the full scale gain error without calibration  120 counts.

Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than

V_RH, and 0x000 for values less than V_RL. This assumes that V_RH V_DDAand V_RL V_SSAdue to the presence of the sample

amplifier. Other channels are not affected by non-disruptive conditions.

8

9

Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not

affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= – 0.3 V, then use the larger of the calculated values.

¹⁰This condition applies to two adjacent pads on the internal pad.

¹¹The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.

¹²TUE does not apply to differential conversions.

¹³Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.

¹⁴TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).

¹⁵Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can

affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].

MPC5561 Microcontroller Data Sheet, Rev. 3

22

Freescale Semiconductor

Electrical Characteristics

3.11 H7Fa Flash Memory Electrical Characteristics

Table 14. Flash Program and Erase Specifications (T = T to T )

A

L

H

Initial

Spec

Flash Program Characteristic

Symbol

Min.

Typical ¹

Max. ³Unit

Max. ²

3

4

Doubleword (64 bits) program time ⁴

Page program time ⁴

T_dwprogram

T_pprogram

—

10

—

500

s

22

44 ⁵

400

500

1250

7

16 KB block pre-program and erase time

48 KB block pre-program and erase time

64 KB block pre-program and erase time

128 KB block pre-program and erase time

T_16kpperase

T_48kpperase

T_64kpperase

T_128kpperase

265

345

415

500

5000

7500

ms

9

10

8

Minimum operating frequency for program and erase

operations ⁶

11

—

25

—

MHz

Typical program and erase times are calculated at 25 ^oC operating temperature using nominal supply values.

Initial factory condition: 100program/erase cycles, 25 ^oC, using a typical supply voltage measured at a minimum system

1

2

frequency of 80 MHz.

3

The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized

but not guaranteed.

4

5

6

Actual hardware programming times. This does not include software overhead.

Page size is 256 bits (8 words).

The read frequency of the flash can range up to the maximum operating frequency. There is no minimum read frequency

condition.

Table 15. Flash EEPROM Module Life (T = T to T )

A

L

H

Spec

Characteristic

Symbol

Min.

Typical ¹Unit

cycles

100,000 cycles

Number of program/erase cycles per block for 16 KB, 48 KB, and

64 KB blocks over the operating temperature range (T_J)

1a

P/E

100,000

—

Number of program/erase cycles per block for 128 KB blocks over the

operating temperature range (T_J)

1b

2

P/E

1000

Data retention

Retention

Blocks with 0–1,000 P/E cycles

Blocks with 1,001–100,000 P/E cycles

20

5

—

years

Typical endurance is evaluated at 25^oC. Product qualification is performed to the minimum specification. For additional

information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for

Nonvolatile Memory.

1

MPC5561 Microcontroller Data Sheet, Rev. 3

23

Freescale

Electrical Characteristics

Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference

manual for definitions of these bit fields.

1

Table 16. FLASH_BIU Settings vs. Frequency of Operation

Maximum Frequency (MHz)

APC

RWSC

WWSC DPFEN ²IPFEN ²

PFLIM ³

BFEN ⁴

Up to and including 82 MHz ⁵

0b001

0b01

0b11

0b00

0b01

0b11

0b00

0b01

0b11

0b000

to

0b110

0b0

0b1

Up to and including 102 MHz ⁶

Up to and including 135 MHz ⁷

Default setting after reset

0b001

0b010

0b111

0b010

0b011

0b111

0b00

0b01

0b11

0b00

0b01

0b11

0b000

to

0b110

0b0

0b1

0b00

0b01

0b11

0b00

0b01

0b11

0b000

to

0b110

0b0

0b1

0b00

0b000

0b0

1

Illegal combinations exist. Use entries from the same row in this table.

For maximum flash performance, set to 0b11.

2

3

4

5

6

7

For maximum flash performance, set to 0b110.

For maximum flash performance, set to 0b1.

82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).

102 MHz parts allow for 100 MHz system clock + 2% FM.

135 MHz parts allow for 132 MHz system clock + 2% FM.

3.12 AC Specifications

3.12.1 Pad AC Specifications

1

Table 17. Pad AC Specifications (V_DDEH= 5.0 V, V_DDE= 1.8 V)

2, 3, 4

SRC / DSC

(binary)

Out Delay

(ns)

Rise / Fall ^{4, 5}

(ns)

Load Drive

(pF)

Spec

Pad

26

82

15

60

50

200

50

11

01

00

11

01

00

75

40

1

Slow high voltage (SH)

137

377

476

16

80

200

50

200

260

8

200

50

43

30

200

50

34

15

2

Medium high voltage (MH)

61

35

200

50

192

239

100

125

200

MPC5561 Microcontroller Data Sheet, Rev. 3

24

Freescale Semiconductor

Electrical Characteristics

1

Table 17. Pad AC Specifications (V_DDEH= 5.0 V, V_DDE= 1.8 V) (continued)

2, 3, 4

SRC / DSC

(binary)

Out Delay

(ns)

Rise / Fall ^{4, 5}

(ns)

Load Drive

(pF)

Spec

Pad

00

01

10

11

—

2.7

2.5

10

20

30

50

3

Fast

3.1

2.4

2.3

4

5

Pullup/down (3.6 V max)

Pullup/down (5.5 V max)

—

7500

9000

1

These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:

_DD= 1.35–1.65 V; V_DDE= 1.62–1.98 V; V_DDEH= 4.5–5.25 V; V_DD33and V_DDSYN= 3.0–3.6 V; and T_A= T_Lto T_H.

V

2

3

This parameter is supplied for reference and is guaranteed by design (not tested).

The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock,

add a maximum of one system clock to the output delay.

4

5

The output delay and rise and fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization rather than 100% tested.

1

Table 18. Derated Pad AC Specifications (V_DDEH= 3.3 V, V_DDE= 3.3 V)

2, 3, 4

SRC/DSC

(binary)

Out Delay

(ns)

Rise / Fall ^{3, 5}

(ns)

Load Drive

(pF)

Spec

Pad

39

120

101

188

507

597

23

87

50

200

50

11

01

00

11

01

00

52

1

Slow high voltage (SH)

111

248

312

12

200

50

200

50

64

44

200

50

22

2

3

Medium high voltage (MH)

90

50

200

50

261

305

123

156

2.4

2.2

2.1

7500

9500

200

10

00

01

10

11

—

20

Fast

3.2

30

50

4

5

Pullup/down (3.6 V max)

Pullup/down (5.5 V max)

—

50

1

2

These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:

V_DD= 1.35–1.65 V; V_DDE= 3.0–3.6 V; V_DDEH= 3.0–3.6 V; V_DD33and V_DDSYN= 3.0–3.6 V; and T_A= T_Lto T_H.

This parameter is supplied for reference and guaranteed by design (not tested).

MPC5561 Microcontroller Data Sheet, Rev. 3

25

Freescale

Electrical Characteristics

3

The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal.

4

The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one

system clock to the output delay.

5

This parameter is guaranteed by characterization rather than 100% tested.

V_DD2

Pad

internal data

input signal

Rising-edge

out

Falling-edge

out

delay

V_OH

Pad

output

V_OL

Figure 4. Pad Output Delay

3.13 AC Timing

3.13.1 Reset and Configuration Pin Timing

1

Table 19. Reset and Configuration Pin Timing

Spec

Characteristic

Symbol

Min.

Max.

Unit

1

2

3

4

RESET pulse width

t_RPW

t_GPW

t_RCSU

t_RCH

10

2

—

t_CYC

RESET glitch detect pulse width

PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid

PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid

10

0

1

Reset timing specified at: V_DDEH= 3.0–5.25 V and T_A= T_Lto T_H.

MPC5561 Microcontroller Data Sheet, Rev. 3

26

Freescale Semiconductor

Electrical Characteristics

2

RESET

1

RSTOUT

3

PLLCFG

BOOTCFG

RSTCFG

WKPCFG

4

Figure 5. Reset and Configuration Pin Timing

3.13.2 IEEE 1149.1 Interface Timing

1

Table 20. JTAG Pin AC Electrical Characteristics

Spec

Characteristic

Symbol

Min.

Max.

Unit

1

2

3

4

5

6

7

8

9

TCK cycle time

t_JCYC

t_JDC

100

40

—

5

—

60

3

ns

TCK clock pulse width (measured at V_DDE 2)

TCK rise and fall times (40% to 70%)

TMS, TDI data setup time

t_TCKRISE

t_{TMSS, TDIS}

t_{TMSH, TDIH}

t_TDOV

t_TDOI

t

—

20

—

20

—

50

—

TMS, TDI data hold time

t

25

—

0

TCK low to TDO data valid

TCK low to TDO data invalid

TCK low to TDO high impedance

JCOMP assertion time

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

—

100

40

—

50

10 JCOMP setup time to TCK low

11 TCK falling-edge to output valid

12 TCK falling-edge to output valid out of high impedance

13 TCK falling-edge to output high impedance (Hi-Z)

14 Boundary scan input valid to TCK rising-edge

15 TCK rising-edge to boundary scan input invalid

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

1

These specifications apply to JTAG boundary scan only. JTAG timing specified at: V_DDE= 3.0–3.6 V and T_A= T_Lto T_H.

Refer to Table 21 for Nexus specifications.

MPC5561 Microcontroller Data Sheet, Rev. 3

27

Freescale

Electrical Characteristics

TCK

2

3

2

1

Figure 6. JTAG Test Clock Input Timing

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 7. JTAG Test Access Port Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

28

Freescale Semiconductor

Electrical Characteristics

TCK

10

JCOMP

9

Figure 8. JTAG JCOMP Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

29

Freescale

Electrical Characteristics

TCK

11

13

Output

signals

12

Output

signals

14

15

Input

signals

Figure 9. JTAG Boundary Scan Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

30

Freescale Semiconductor

Electrical Characteristics

3.13.3 Nexus Timing

1

Table 21. Nexus Debug Port Timing

Spec

Characteristic

Symbol

Min.

Max.

Unit

1

2

3

4

5

6

7

8

9

MCKO cycle time

t_MCYC

t_MDC

1 ²

40

8

t_CYC

%

MCKO duty cycle

60

3.0

—

MCKO low to MDO data valid ³

MCKO low to MSEO data valid ³

MCKO low to EVTO data valid ³

EVTI pulse width

t_MDOV

–1.5

4.0

1

ns

t_MSEOV

t_EVTOV

ns

t_EVTIPW

t_EVTOPW

t_TCYC

t_MCYC

t_CYC

%

EVTO pulse width

—

TCK cycle time

4 ⁴

—

TCK duty cycle

t_TDC

40

60

—

10 TDI, TMS data setup time

11 TDI, TMS data hold time

TCK low to TDO data valid

t

_NTDIS,t_NTMSS

8

ns

t

_NTDIH,t_NTMSH

t_JOV

5

—

ns

12

V_DDE= 2.25–3.0 V

_DDE= 3.0–3.6 V

13 RDY valid to MCKO ⁵

0

12

10

—

ns

—

V

—

1

2

JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of

MCKO and 50% of the respective signal. Nexus timing specified at V_DD= 1.35–1.65 V, V_DDE= 2.25–3.6 V,

V_DD33and V_DDSYN= 3.0–3.6 V, T_A= T_Lto T_H, and CL = 30 pF with DSC = 0b10.

The Nexus AUX port runs up to 82 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency

is greater than 82 MHz.

3

4

MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.

Limit the maximum frequency to approximately 16 MHz (V_DDE= 2.25–3.0 V) or 20 MHz (V_DDE= 3.0–3.6 V) to meet the timing

specification for t_JOVof [0.2 x t_JCYC] as outlined in the IEEE-ISTO 5001-2003 specification.

5

The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly.

1

2

MCKO

4

5

3

MDO

MSEO

EVTO

Output Data Valid

Figure 10. Nexus Output Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

31

Freescale

Electrical Characteristics

TCK

10

11

TMS, TDI

12

TDO

Figure 11. Nexus TDI, TMS, TDO Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

32

Freescale Semiconductor

Electrical Characteristics

3.13.4 External Bus Interface (EBI) Timing

lists the timing information for the external bus interface (EBI).

1

Table 22. Bus Operation Timing

External Bus Frequency ^{2, 3}

40 MHz 56 MHz 66 MHz

Characteristic

and

Description

Spec

Symbol

Unit

Notes

Min.

Max.

—

Min.

Max.

—

Min.

Max.

Signals are measured

1

CLKOUT period

T_C

24.4

17.5

14.9

—

ns

at 50% V_DDE

.

2

3

4

CLKOUT duty cycle

CLKOUT rise time

CLKOUT fall time

t_CDC

t_CRT

t_CFT

t_COH

45%

—

55%

45%

—

55%

45% 55% T_C

4

—

ns

4

—

1.0⁸

—

1.0⁸

—

CLKOUT positive edge to output

1.0⁸

EBTS = 0

EBTS = 1

signal invalid or Hi-Z (hold time)

—

ns

1.5

External bus interface

CS[0:3]

ADDR[8:31]

DATA[0:31] ⁵

BDIP

Hold time selectable

via SIU_ECCR

[EBTS] bit.

5

OE

RD_WR

TA

TEA ⁶

TS

WE/BE[0:3] ⁷

CLKOUT positive edge to output

signal valid (output delay)

t_COV

10.0⁸

7.5⁸

8.5

6.0⁸

7.0

EBTS = 0

EBTS = 1

—

ns

11.0

External bus interface

CS[0:3]

ADDR[8:31]

DATA[0:31] ⁵

BDIP

Output valid time

selectable via

SIU_ECCR

6

[EBTS] bit.

OE

RD_WR

TA

TEA ⁶

TS

WE/BE[0:3] ⁷

MPC5561 Microcontroller Data Sheet, Rev. 3

33

Freescale

Electrical Characteristics

Characteristic

1

Table 22. Bus Operation Timing (continued)

External Bus Frequency ^{2, 3}

Spec

and

Description

Symbol

Unit

Notes

40 MHz

56 MHz

66 MHz

Min.

Max.

Min.

Max.

Min.

Max.

Input signal valid to CLKOUT

positive edge (setup time)

External bus interface

ADDR[8:31]

DATA[0:31] ⁵

RD_WR

TA

7

t_CIS

10.0

—

7.0

—

5.0

—

ns

TEA ⁶

TS

CLKOUT positive edge to input

signal invalid (hold time)

External bus interface

ADDR[8:31]

DATA[0:31] ⁵

RD_WR

TA

8

t_CIH

1.0

—

1.0

—

1.0

—

ns

TEA ⁶

TS

1

2

EBI timing specified at: V_DDE= 1.6–3.6 V (unless stated otherwise); T_A= T_Lto T_H; and CL = 30 pF with DSC = 0b10.

Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).

82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and

135 MHz parts allow for 132 MHz system clock + 2% FM.

3

4

5

6

7

8

The external bus is limited to half the speed of the internal bus.

Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).

Due to pin limitations, the DATA[16:31] signals are not available on the 324 package.

Due to pin limitations, the TEA signal is not available on the 324 package.

Due to pin limitations, the WE/BE[2:3] signals are not available on the 324 package.

SIU_ECCR[EBTS] = 0 timings are tested and valid at V_DDE= 2.25–3.6 V only; SIU_ECCR[EBTS] = 1 timings are tested and

valid at V_DDE= 1.6–3.6 V.

Voh_f

V_DDE2

Vol_f

CLKOUT

2

3

2

4

1

Figure 12. CLKOUT Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

34

Freescale Semiconductor

Electrical Characteristics

V_DDE2

CLKOUT

6

5

V_DDE2

5

Output

bus

V_DDE2

6

5

Output

signal

V_DDE2

6

Output

signal

V_DDE2

Figure 13. Synchronous Output Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

35

Freescale

Electrical Characteristics

CLKOUT

V_DDE2

7

8

Input

bus

V_DDE2

7

8

Input

signal

V_DDE2

Figure 14. Synchronous Input Timing

3.13.5 External Interrupt Timing (IRQ Signals)

1

Table 23. External Interrupt Timing

Spec

Characteristic

Symbol

Min.

Max.

Unit

1

2

3

IRQ pulse-width low

IRQ pulse-width high

IRQ edge-to-edge time ²

t_IPWL

T_IPWH

t_ICYC

3

6

—

t_CYC

1

2

IRQ timing specified at: V_DDEH= 3.0–5.25 V and T_A= T_Lto T_H.

Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.

MPC5561 Microcontroller Data Sheet, Rev. 3

36

Freescale Semiconductor

Electrical Characteristics

IRQ

2

1

3

Figure 15. External Interrupt Timing

3.13.6 eMIOS Timing

1

Table 24. eMIOS Timing

Spec

Characteristic

Symbol

Min.

Max.

Unit

1

2

eMIOS input pulse width

eMIOS output pulse width

t_MIPW

4

1 ²

—

t_CYC

t_MOPW

1

2

eMIOS timing specified at: V_DDEH= 3.0–5.25 V and T_A= T_Lto T_H.

This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).

2

eMIOS

output

eMIOS input

1

Figure 16. eMIOS Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

37

Freescale

Electrical Characteristics

3.13.7 DSPI Timing

1

2

Table 25. DSPI Timing ’

80 MHz

Symbol

112 MHz

132 MHz

Spec

Characteristic

SCK cycle time^{3, 4}

PCS to SCK delay⁵

After SCK delay⁶

SCK duty cycle

Unit

Min.

Max.

Min.

Max.

Min.

Max.

1

2

3

t_SCK

t_CSC

t_ASC

24.4 ns

23

2.9 ms

—

17.5 ns

15

2.1 ms 14.8 ns 1.8 ms

—

ns

—

13

12

—

22

—

14

(t_SCK 2) (t_SCK 2) (t_SCK 2) (t_SCK 2) (t_SCK 2) (t_SCK 2)

4

5

6

t_SDC

t_A

ns

– 2 ns

+ 2 ns

– 2 ns

+ 2 ns

– 2 ns

+ 2 ns

Slave access time

(SS active to SOUT driven)

—

25

—

25

—

25

Slave SOUT disable time

(SS inactive to SOUT Hi-Z, or invalid)

t_DIS

—

25

—

25

—

25

7

8

PCSx to PCSS time

PCSS to PCSx time

t_PCSC

t_PASC

t_SUI

4

5

—

4

5

—

4

5

—

ns

Data setup time for inputs

Master (MTFE = 0)

20

2

–4

20

—

20

2

3

—

20

2

6

—

ns

9

Slave

Master (MTFE = 1, CPHA = 0)⁷

Master (MTFE = 1, CPHA = 1)

20

Data hold time for inputs

Master (MTFE = 0)

t_HI

t_SUO

t_HO

–4

7

21

–4

—

–4

7

14

–4

—

–4

7

12

–4

—

ns

10

11

12

Slave

Master (MTFE = 1, CPHA = 0)⁷

Master (MTFE = 1, CPHA = 1)

Data valid (after SCK edge)

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

—

5

25

18

5

—

5

25

14

5

—

5

25

13

5

ns

Data hold time for outputs

Master (MTFE = 0)

–5

5.5

8

—

–5

5.5

4

—

–5

5.5

3

—

ns

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

–5

1

2

3

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types

of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: V_DDEH= 3.0–5.25 V;T_A= T_Lto T_H;

and CL = 50 pF with SRC = 0b11.

Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).

82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and

135 MHz parts allow for 132 MHz system clock + 2% FM.

The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.

These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.

4

5

6

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

MPC5561 Microcontroller Data Sheet, Rev. 3

38

Freescale Semiconductor

Electrical Characteristics

7

This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.

2

3

PCSx

1

4

SCK output

(CPOL=0)

4

SCK output

(CPOL=1)

10

9

Last data

SIN

First data

Data

12

11

First data

Last data

SOUT

Figure 17. DSPI Classic SPI Timing—Master, CPHA = 0

PCSx

SCK output

(CPOL=0)

10

SCK output

(CPOL=1)

9

Data

First data

Last data

SIN

12

11

SOUT

Last data

First data

Figure 18. DSPI Classic SPI Timing—Master, CPHA = 1

MPC5561 Microcontroller Data Sheet, Rev. 3

39

Freescale

Electrical Characteristics

3

2

SS

1

4

SCK input

(CPOL=0)

4

SCK input

(CPOL=1)

5

11

12

Data

6

First data

Last data

SOUT

9

10

First data

Data

Last data

SIN

Figure 19. DSPI Classic SPI Timing—Slave, CPHA = 0

SS

SCK input

(CPOL=0)

SCK input

(CPOL=1)

11

5

6

12

Last data

Data

SOUT

SIN

First data

10

9

Last data

First data

Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 1

MPC5561 Microcontroller Data Sheet, Rev. 3

40

Freescale Semiconductor

Electrical Characteristics

3

PCSx

4

1

2

SCK output

(CPOL=0)

4

SCK output

(CPOL=1)

9

10

SIN

First data

Last data

Data

12

11

SOUT

First data

Data

Figure 21. DSPI Modified Transfer Format Timing—Master, CPHA = 0

PCSx

SCK output

(CPOL=0)

SCK output

(CPOL=1)

10

9

SIN

Last data

First data

Data

12

Data

11

First data

Last data

SOUT

Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 1

MPC5561 Microcontroller Data Sheet, Rev. 3

41

Freescale

Electrical Characteristics

3

2

SS

1

SCK input

(CPOL=0)

4

SCK input

(CPOL=1)

12

11

6

5

First data

9

Data

Last data

10

SOUT

Last data

First data

SIN

Figure 23. DSPI Modified Transfer Format Timing—Slave, CPHA = 0

SS

SCK input

(CPOL=0)

SCK input

(CPOL=1)

11

5

6

12

Last data

First data

10

Data

SOUT

SIN

9

First data

Last data

Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 1

8

7

PCSS

PCSx

Figure 25. DSPI PCS Strobe (PCSS) Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

42

Freescale Semiconductor

Electrical Characteristics

3.13.8 eQADC SSI Timing

Table 26. EQADC SSI Timing Characteristics

Spec

Rating

Symbol

Minimum

Typical

Maximum

Unit

1, 2

2

3

4

5

6

7

8

FCK period (t_FCK= 1  f_FCK

Clock (FCK) high time

Clock (FCK) low time

SDS lead / lag time

)

t_FCK

2

—

17

t_{SYS_CLK}

ns

t_FCKHT

t_FCKLT

t_{SDS_LL}

t_{SDO_LL}

t_{EQ_SU}

t_{EQ_HO}

t_{SYS_CLK} 6.5

9  (t_{SYS_CLK} 6.5)

t_{SYS_CLK} 6.5

8  (t_{SYS_CLK} 6.5)

ns

–7.5

22

+7.5

—

ns

SDO lead / lag time

ns

EQADC data setup time (inputs)

EQADC data hold time (inputs)

ns

1

—

ns

1

2

SS timing specified at V_DDEH= 3.0–5.25 V, T_A= T_Lto T_H, and CL = 25 pF with SRC = 0b11. Maximum operating frequency

varies depending on track delays, master pad delays, and slave pad delays.

FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.

2

3

4

FCK

SDS

5

6

4

5

25th

1st (MSB)

2nd

26th

SDO

External device data sample at

FCK falling-edge

8

7

1st (MSB) 2nd

25th

26th

SDI

EQADC data sample at

FCK rising-edge

Figure 26. EQADC SSI Timing

MPC5561 Microcontroller Data Sheet, Rev. 3

43

Freescale

Mechanicals

4

Mechanicals

4.1

MPC5561 324 PBGA Pinouts

Figure 27 is a pinout for the MPC5561 324 PBGA package.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

VSSA1 AN1

AN5

VRH

VRL

AN27 AN28 AN35 VSSA0 AN12 MDO11 MDO10 MDO8 VDD VDD33 VSS

A

B

VSS

VDD VSTBY AN37

AN11 VDDA1

A

B

C

D

E

F

REF

BYPC

AN16

AN0

AN4

AN3

AN23

AN26 AN31 AN32 VSSA0 AN13 MDO9 MDO7 MDO4 MDO0

VSS VDDE7

VDD33 VSS

VDD

VSS

AN36

VDD

VSS

AN39

AN8

AN19

AN17

AN38

ETPUA ETPUA

30

AN20 AN21

AN7

AN2

AN22 AN25 AN30 AN33 VDDA0 AN14 MDO5 MDO2 MDO1

VDDEH

VSS VDDE7 VDD

C

D

E

31

ETPUA ETPUA ETPUA

28 29 26

AN9

AN10 AN18

AN6

AN24 AN29

AN34

AN15 MDO6 MDO3

VSS VDDE7 TCK

VDDE7 TMS TDO

VDDE7 JCOMP EVTI

TDI

VDD

9

ETPUA ETPUA ETPUA ETPUA

24 27 25 21

TEST

EVTO

ETPUA ETPUA ETPUA ETPUA

23

F

22

17

18

ETPUA ETPUA ETPUA ETPUA

RDY MCKO MSEO0 MSEO1

G

H

J

G

H

J

20

19

14

13

ETPUA ETPUA ETPUA VDDEH

VDDEH GPIO GPIO

SINB

16 15 10

1

10

203

204

ETPUA ETPUA ETPUA ETPUA

12 11

VSS

VSS VDDE7

SOUTB PCSB3 PCSB0 PCSB1

PCSA3 PCSB4 SCKB PCSB2

PCSB5 SOUTA SINA SCKA

PCSA1 PCSA0 PCSA2 VPP

PCSA4 TXDA PCSA5 VFLASH

6

9

ETPUA ETPUA ETPUA ETPUA

VSS

K

L

8

7

2

5

ETPUA ETPUA ETPUA ETPUA

L

4

3

0

1

TCRCLK

A

VDDE2 VDDE2 VSS

M

N

P

BDIP

CS1

CS0

M

N

P

R

T

VSS

VSS VDDE2 VSS

CS3

CS2

WE1

WE0

ADDR ADDR

RST

CNTXC RXDA RSTOUT

CFG

RD_WR

VDDE2

VDD33

TA

16

17

ADDR ADDR

WKP

CNRXC TXDB RESET

CFG

R

T

18

19

PLL

CFG2

ADDR ADDR ADDR

20 21 12

BOOT

CFG1

VSS

SYN

RXDB

TS

NC

Note:

No connect. Reserved (W18 & Y19 are shorted to each other)

ADDR ADDR ADDR ADDR

VDDEH PLL

BOOT

EXTAL

XTAL

U

V

U

22

23

13

14

6

CFG1 CFG0

ADDR ADDR ADDR ADDR

VRC

CTL

PLL

CFG0

VDD

V

24

25

15

31

ADDR

26

ADDR

30

DATA DATA DATA EMIOS EMIOS VDDEH EMIOS EMIOS

VDD

SYN

W

VDDE2 VDD33 VDDE2

VDDE5

NC

VSS

NC

VDD VRC33

VSS

W

Y

VDDE2

VSS

VDD

11

12

14

2

8

4

12

21

ADDR ADDR

28

DATA DATA DATA GPIO DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS

VDDE2

CNTXA VDDE5

VDD VDD33

VSS

VDD

Y

27

8

9

10

207

13

15

6

10

15

17

22

ADDR

29

DATA

1

GPIO DATA DATA

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS

VDDE2

CNRXA VDDE5 CLKOUT VSS

VDD

AA

VSS

AA

AB

206

5

7

OE

9

3

5

9

13

16

19

23

DATA DATA DATA DATA DATA

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS

ENG

CNTXB CNRXB VDDE5

CLK

VSS

22

AB VSS

1

VDD VDDE2

0

2

3

4

6

0

1

4

7

11

14

18

20

2

3

4

5

6

7

8

10

11

12

13

14

15

16

17

18

19

20

21

Figure 27. MPC5561 324 Package

MPC5561 Microcontroller Data Sheet, Rev. 3

44

Freescale Semiconductor

Mechanicals

4.2

MPC5561 324-Pin Package Dimensions

The package drawings of the MPC5561 324-pin TEPBGA package are shown in Figure 28.

Figure 28. MPC5561 324 TEPBGA Package

MPC5561 Microcontroller Data Sheet, Rev. 3

45

Freescale

Mechanicals

Figure 28. MPC5561 324 TEPBGA Package (continued)

MPC5561 Microcontroller Data Sheet, Rev. 3

46

Freescale Semiconductor

Revision History for the MPC5561 Data Sheet

5

Revision History for the MPC5561 Data Sheet

The history of revisions made to this data sheet are shown in this section. The changes are divided into

each revision of this document. The substantive changes incorporated in MPC5561 Data Sheet Rev. 0.0 to

produce Rev. 1.0 of this document are grouped as follows:

•

Global and text changes

Table and figure changes

Within each group, the changes are listed in sequential order.

5.1

Information Changed Between Revisions 2.0 and 3.0

The following table lists the changes made throughout the document.

Table 27. Information Changed Between Rev. 2.0 and Rev. 3.0

Added the following paragraph in Section 3.7, “Power-Up/Down Sequencing”:

“During initial power ramp-up, when V_stbyis 0.6v or above. a typical current of 1-3mA and maximum

of 4mA may be seen until VDD is applied. This current will not reoccur until V_stbyis lowered below

Vstby min. specification”.

Section 3.7,

“Power-Up/Down

Sequencing”

Moved Figure 2 (fISTBY Worst-case Specifications) “ISTBY Worst-case Specifications” to

Section 3.7, “Power-Up/Down Sequencing”.

Removed the footnote “Figure 3 shows an illustration of the IDD_STBY values interpolated for these

temperature values”.

Section 3.8, “DC

Electrical

Specifications”

Changed the footnote attached to IDD_STBY to “The current specification relates to average standby

operation after SRAM has been loaded with data. For power up current see Section 3.7,

“Power-Up/Down Sequencing”,Figure 2 (fISTBY Worst-case Specifications).”

In Table 9 (DC Electrical Specifications (T_A= T_{L to}T_H)) the Characteristic “Refer to Figure 3 for an

interpolation of this data” changed to “RAM standby current”.

5.2

Information Changed Between Revisions 1.0 and 2.0

The following table lists the changes made throughout the document.

Table 28. Information Changed Between Rev. 1.0 and Rev. 2.0

Location

Description of Changes

Section 1, “Overview”

Added new 11th paragraph about FlexRay. Removed discussion in the SIU and DSPI paragraphs about

deserialization and serialization, and chaining. Removed reference to SIU_DISR register.

Table 6 (V_RCand POR Electrical Specifications) VCR/POR Electrical Specifications:

Added to Specs 1, 2 and 3 that reads: On power up, assert RESET before V_POR15, V_POR33, and V_POR5negate

(internal POR). RESET must remain asserted until the power supplies are within the operating conditions as

specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall

outside the operating conditions and until the internal POR asserts.

MPC5561 Microcontroller Data Sheet, Rev. 3

47

Freescale

Revision History for the MPC5561 Data Sheet

Table 28. Information Changed Between Rev. 1.0 and Rev. 2.0 (continued)

Description of Changes

Location

Table 9 (DC Electrical Specifications (T_A= T_{L to}T_H)) DC Electrical Specifications

• Added footnote that reads: V_DDE2and V_DDE3are limited to 2.25–3.6 V only if EBTS = 0; V_DDE2and V_DDE3have

a range of 1.6–3.6 V if EBTS =1.

• Spec 27a, Operating current 1.5 V supplies @ 135 MHz:

-- 8-way 1.65 V typical use: from 630 to 620

-- 8-way 1.35 V typical use: from 500 to 440

-- 8-way 1.65 V high use: from 785 to 670

-- 8-way 1.35 V high use: from 630 to 490

-- 4-way 1.65 V high use: from 710 to 620

-- 4-way 1.35 V high use: from 550 to 430

• Spec 27b, Operating current 1.5 V supplies @ 114 MHz:

-- 8-way 1.65 V typical use: from 600 to 590

-- 8-way 1.35 V typical use: from 450 to 395

-- 8-way 1.65 V high use: from 680 to 580

-- 8-way 1.35 V high use: from 500 to 390

-- 4-way 1.65 V high use: from 650 to 550

-- 4-way 1.35 V high use: from 490 to 385

• Spec 27c, Operating current 1.5 V supplies @ 82 MHz:

-- 8-way 1.65 V typical use: from 490 to 485

-- 8-way 1.35 V typical use: from 360 to 320

-- 8-way 1.65 V high use: from 545 to 470

-- 8-way 1.35 V high use: from 400 to 315

-- 4-way 1.65 V high use: from 530 to 460

-- 4-way 1.35 V high use: from 395 to 310

• Removed footnote 12 on all these changed values: Preliminary. Specification pending final characterization.

Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications

• Footnote 1, changed ‘V_DDEH= 4.5–5.5;’ to ‘V_DDEH= 4.5–5.25;’

• Footnote 1, deleted ‘f_SYS= 132 MHz.’

• Footnote 2, changed from ‘tested’ to ‘(not tested).’

• Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,

• Changed from ‘Add a maximum of one system clock to the output delay to get the output delay with respect to

the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system

clock to the output delay.’

• Footnote 4: changed ‘Delay’ to ‘The output delay.’

• Footnote 5: deleted ‘before qualification.’

• Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This

parameter is supplied for reference and is guaranteed by design and tested.’

Table 22 (Bus Operation Timing) Bus Operation Timing:

• External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum

frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow

for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts

allow for 132 MHz system clock + 2% FM.

• Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5

• Specs 7 and 8: Removed from external bus interface: BDIP, OE, TSIZ[0:1], and WE/BE[0:3].

• Added a footnote each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin limitations, the

DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.

MPC5561 Microcontroller Data Sheet, Rev. 3

48

Freescale Semiconductor

Revision History for the MPC5561 Data Sheet

Table 28. Information Changed Between Rev. 1.0 and Rev. 2.0 (continued)

Description of Changes

Location

Table 24 (eMIOS Timing) eMIOS Timing:

• Footnote 1, changed ‘V_DDEH= 4.5–5.5;’ to ‘V_DDEH= 4.5–5.25;’

• Deleted (MTS) from the heading, table, and footnotes.

• Footnote 1: Deleted ‘. . .f_SYS= 132 MHz. . .’, ‘. . .V_DD33and V_DDSYN= 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF

with SRC = 0b11.’

• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum

eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad

configuration registers (PCR).’

Table 25 (DSPI Timing’) DSPI Timing:

• Footnote 1, changed ‘V_DDEH= 4.5–5.5;’ to ‘V_DDEH= 4.5–5.25;’

• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max. speed is the maximum

speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;

114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts allow for 132 MHz system clock +

2% FM.

Table 26 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics:

• Footnote 1, changed ‘V_DDEH= 4.5–5.5;’ to ‘V_DDEH= 4.5–5.25;’

• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’

• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’

• Spec 1: FCK frequency -- removed.

• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 to Spec 2.

• Footnote 1, deleted ‘V_DD= 1.35–1.65 V’ and ‘V_DD33and V_DDSYN= 3.0–3.6V.’

Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’

• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .

Figure 27 (MPC5561 324 Package) MPC5561 324 PBGA Pinouts:

• Changed ball labels on the 324 PBGA to show only signals available on the device:

• C1 -> PSCS3, C2 -> PCSC4,

• D1 -> PCSC1, D2 -> PCSC2, D3 -> IRQ14

• E1 -> IRQ12, E2 -> IRQ15, E3 -> IRQ13, E4 -> IRQ9

• F1 -> IRQ11, F2 -> IRQ10, F3 -> PDI_DATA6, F4 -> PDI_DATA7

• G1 -> IRQ8, G2 -> PDI_DATA8, G3 -> PCSB4, G4 -> PCSB3

• H1 -> PDI_DATA5, H2 -> PCSB5, H3 -> PDICHSEL2

• J1 -> PCSB1, J2 -> PDI_DATA0, J3 -> FRN_RX, J4 -> PDICHSEL1

• K1 -> PDICHSEL0, K2 -> GPIO121, K3 -> PDI_FRAME_VALID, K4 -> FRBTXEN, K19 -> RXDD

• L1 -> FRBTX, L2 -> PDISNCLK, L3 -> GPIO114, L4 -> PDILINEVALID, L20 -> PCSC5, L21 -> PCSC2,

L22 -> PCSC1

• M2 -> IRQ7, M19 -> PCSB2, M20 -> TXDC, M21 -> TXDD

• N19 -> RXDC, N21 -> PCSB3

• AB18 -> PCSC3, AB19 -> PCSC4

5.3

Information Changed Between Revisions 0.0 and 1.0

The following table lists the global changes made throughout the document, as well as substantive changes

to text that is not in a table of figure.

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Revision History for the MPC5561 Data Sheet

Table 29. Global and Text Changes Between Rev. 0.0 and Rev. 1.0

Description of Changes

Location

Global Changes throughout the document

• Replaced kilobytes with KB.

• Replaced megabytes with MB.

Section 1, “Overview”:

• First paragraph: text changed from “. . . based on the PowerPC Book E architecture” to “. . . built on the Power

Architecture embedded technology.”

• Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.

• Added new third paragraph about VLE feature.

• Added new eighth paragraph about the parallel digital interface (PDI).

• Paragraph nine: changed “the MPC5561 has an on-chip 20-channel enhanced queued analog-to-digital

converter (eQADC)” to “. . . has an on-chip 40-channel dual enhanced queued . . .”

• Added the sentence preceding Table 1: ‘Unless noted in this data sheet, all specifications apply from T_Lto T_H.’

Sections 3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:

• Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33,” then

• Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” then

• Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).

Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33,” changed:

From: ‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones

(1s) when POR negates, V_DD33must not lag V_DDSYNand the RESET pin power (V_DDEH6) when powering the device

by more than the V_DD33lag specification in Table 6. V_DD33individually can lag either V_DDSYNor the RESET power

pin (V_DDEH6) by more than the V_DD33lag specification. V_DD33can lag one of the V_DDSYNor V_DDEH6supplies, but

cannot lag both by more than the V_DD33lag specification. This V_DD33lag specification only applies during power up.

V_DD33has no lead or lag requirements when powering down.’

To:

‘When powering the device, V_DD33must not lag V_DDSYNand the RESET power pin (V_DDEH6) by more than the

V_DD33lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the

internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when

POR negates. V_DD33can lag V_DDSYNor the RESET power pin (V_DDEH6), but cannot lag both by more than the

V_DD33lag specification. This V_DD33lag specification only applies during power up. V_DD33has no lead or lag

requirements when powering down.’

Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33:”

Added the following text directly before this section and after Table 8 Pin Status for Medium / Slow Pads During the

Power-on Sequence:

‘The values in Table 7 and Table 8 do not include the effect of the weak pull devices on the output pins during power

up.

Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When the

internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or down)

are enabled as defined in the device Reference Manual. If V_DDis too low to correctly propagate the logic signals,

the weak-pull devices can pull the signals to V_DDEand V_DDEH

.

To avoid this condition, minimize the ramp time of the V_DDsupply to a time period less than the time required to

enable the external circuitry connected to the device outputs.’

Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)” Deleted the underscore in ORed_POR to become ORed POR.

Section 3.13.6, “eTPU Timing”

Deleted entire section, including table and figure, because the MPC5561 does not have the eTPU module.

The following table describes the changes made to information in tables and figures:

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0

Description of Changes

Location

Figure 1 (MPC5500 Family Part Number Example) MPC5500 Family Part Numbers:

• Removed the 2 in the tape and reel designator in both the graphic and in the Tape and Reel Status text.

• Changed Qualification Status by adding ‘, general market flow’ to the M designator, and added an ‘S’ designator

with the description of ‘Fully spec. qualified, automotive flow.

• Changed footnote 1 to read: All devices are PPC5561, rather than MPC5561 or SPC5561, until product

qualifications are complete. Not all configurations are available in the PPC parts.

Table 1 (Orderable Part Numbers) Orderable Part Numbers:

• Increased the frequency values in the Maximum column by 2 ns.

• Changed the maximum operating frequency from 132 MHz to 135 MHz.

• Reordered rows to group devices by lead-free package types in descending frequency order, and leaded

package types.

• Footnote 2: added ‘ambient’ between ‘lowest’ and ‘operating’ and ‘highest’ and ‘operating.’

• Changed footnote 3 from ‘132 MHz allows only 128 MHz + 2% FM’ to ‘135 MHz allows for 132 MHz + 2% FM’.

Table 2 (Absolute Maximum Ratings) Absolute Maximum Ratings:

• Deleted Spec 3, “Flash core voltage.”

• Spec 12 “DC Input Voltage”: Deleted from second line‘. . .except for eTPUB15 and SINB (DSPI_B_SIN)’ leaving

V_DDEHpowered I/O pads. Deleted third line ‘V_DDEHpowered by I/O pads (eTPUB15 and SINB), including the

min. and max values of -0.3 and 6.5 respectively, and deleted old footnote 7.

• Spec 12 “DC Input Voltage”: Added footnote 8 to second line “V_DDEpowered I/O pads” that reads: ‘Internal

structures hold the input voltage less than the maximum voltage on all pads powered by the V_DDEsupplies, if the

maximum injection current specification is met (s mA for all pins) and V_DDEis within the operating voltage

specifications.

• Spec 14, column 2, changed: ‘V_SSdifferential voltage’ to ‘V_SSto V_SSAdifferential voltage.’

• Spec 15, column 2, changed: ‘V_DDdifferential voltage’ to ‘V_DDto V_DDAdifferential voltage.’

• Spec 21, Added the name of the spec, ‘V_RC33to V_DDSYNdifferential voltage,’ as well as the name and cross

reference to Table 9, DC Electrical Specifications, to which the Spec was moved.

• Spec 28 “Maximum Solder Temperature”: Added two sublines:

Lead free (PbFree) and Leaded (SnPb) with maximum values of 260 C and 245 C respectively.

• Footnote 1, added: ‘any of’ between ‘beyond’ and ‘the listed maxima.’

• Deleted footnote 2: ‘Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum

specifications for device stress have not yet been determined.’Spec 26 “Maximum Operating Temperature

Range”: replaced -40 C with T_L.

• Footnote 6 (now footnote 5): Added the following sentence to the end, “Keep the negative DC voltage greater

than -0.6 V on SINB during the internal power-on reset (POR) state.”

Table 4 (EMI Testing Specifications) EMI Testing Specifications:

• Changed the maximum operating frequency to from 132 to f_MAX

.

• Footnote 2: Deleted ‘Refer to Table 1 for the maximum operating frequency.’

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)

Description of Changes

Location

Table 5 (ESD Ratings ,) ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title.

Table 6 (V_RCand POR Electrical Specifications) VCR/POR Electrical Specifications:

• Subscript all symbol names that appear after the first underscore character.

• Specs 7 and 10: added ‘at Tj ‘at the end of the first line in the second column: Characteristic.

• Footnote 10: Deleted ‘Preliminary value. Final specification pending characterization.”

• Added to Spec 2:

3.3 V (V_DDSYN) POR negated (ramp down) Min. 0.0

3.3 V (V_DDSYN) POR asserted (ramp up) Min. 0.0

Max. 0.30

V

• Spec 3: Added new footnote 3 for both lines: ‘It is possible to reach the current limit during ramp up--do not treat

this event as a short circuit current.’

• Spec 5: Changed old Footnote 1 (now footnote 2): ‘User must be able to supply full operating current for the 1.5V

supply when the 3.3V supply reaches this range.” to ‘Supply full operating current for the 1.5 V supply when the

3.3 V supply reaches this range.”

• Spec 10:

• Changed the minimum values of: -40 C = 60; 25 C = 65; 150 C = 85.

• Added old footnote 5 as new footnote 6.

• Removed ‘Tj ‘after ‘150 C’ in the last line, second column: Characteristic.

• Added a new footnote 7, ‘Refer to Table 1 for the maximum operating frequency.’

• Rewrote old footnote 7(new footnote 9) to: Represents the worst-case external transistor BETA. It is measured

on a per part basis and calculated as (I_DD I_VRCCTL).

• Added cross-reference to footnote 6: ‘I_VRCCTLis measured at the following conditions: V_DD= 1.35 V,

V_RC33= 3.1 V, V_VRCCTL= 2.2 V.’ Changed ‘(@ V_DD= 1.35 V, f_sys= f_MAX)‘ to ‘(@ f_sys= f_MAX).’

• Added new footnote 1 to Spec 3: “ V_{IL_S}(Table 9, Spec 15) is guaranteed to scale with V_DDEH6down to V_POR5

• Rewrote old footnote 7(new footnote 9) to: Represents the worst-case external transistor BETA. It is measured

on a per part basis and calculated as (I_DD I_VRCCTL).

.

• Deleted old footnote 8: ‘Preliminary value. Final specification pending characterization.’

Table 7 (Pin Status for Fast Pads During the Power Sequence) Power Sequence Pin Status for Fast Pads

• Changed title to Pin Status for Fast Pads During the Power Sequence

• Changed preceding paragraph

From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive

current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting

POR, the pads are in a high impedance state (Hi-Z).

To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current

spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies

are powered.

• Deleted the ‘Comment’ column.

• Added a POR column after the V_DDcolumn.

• Added row 2:’ V_DDE, Low, Low, Asserted, High’ and row 5: V_DDE, V_DD33, V_DD, Asserted, Hi-Z.

Table 8 (Pin Status for Medium and Slow Pads During the Power Sequence) Power Sequence Pin Status for Medium/Slow Pads:

• Changed title to Pin Status for Medium and Slow Pads During the Power Sequence

• Updated preceding paragraph.

• Deleted the ‘Comment’ column.

• Added a POR column after the V_DDcolumn.

• Added row 3:’ V_DDEH, V_DD, Asserted, Hi-Z.’

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)

Description of Changes

Location

Table 9 (DC Electrical Specifications (T_A= T_{L to}T_H)) DC Electrical Specifications:

• Spelled out meaning of the slash ‘/’ as ‘and’ as well as ‘I/O’ as ‘input/output.’ Sentence still very confusing.

Deleted ‘input/output’ from the specs to improve clarity.

• Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (I_{OH_S}= –2.0 mA):’

Created a left-justified second line and moved ‘I_{OH_S}= –2.0 mA’ from the 1st line to the second line and deleted

the parentheses. Created a left-justified third line that reads ‘I_{OH_S}= –1.0 mA.’

• Spec 20, column 4, Min.: Added a blank line before and after ‘0.80  V_DDEH’ and put ‘0.85  V_DDEH’ on the last

line.

• Spec 22, column 2,’Slow and medium output low voltage (I_{OL_S}= 2.0 mA):’ Created a left-justified second line

and moved ‘I_{OL_S}= 2.0 mA.’ from the 1st line to the second line and deleted the parentheses. Created a

left-justified third line that reads ‘I_{OL_S}= 1.0 mA.’

• Spec 22, column 5, Max.: Added a blank line before and after ‘0.20  V_DDEH’ and put ‘0.15  V_DDEH’ on the last

line.

• Spec 26: Changed ‘AN[12]_MA[1]_SDO’ to ‘AN[13]_MA[1]_SDO’.

• Spec 27a: Changed 132 MHz to 135 MHz. Added maximum values for 8-way cache:

1.65 typical = 630

1.35 typical = 500

1.65 high = 785

1.35 high = 630

All 8-way cache max values have footnote 11.

Added 4-way cache with footnote 10:

1.65 high = 685 with footnote 11

1.35 high = TBD with footnote 12

• Spec 27b, Operating current 1.5 V supplies @ 114 MHz: Added maximum values for 8-way cache:

1.65 typical = 600,

1.35 typical = 450,

1.65 high = 680,

1.35 high = 500.

All 8-way cache max values have footnote 11.

Added 4-way cache with footnote 10:

1.65 and 1.35 high = TBD with footnote 12

Table 9 (DC Electrical Specifications (T_A= T_{L to}T_H)) DC Electrical Specifications: (continued)

• Spec 27c, Operating current 1.5 V supplies @ 82 MHz: Added maximum values for 8-way cache:

1.65 typical = 490,

1.35 typical = 360,

1.65 high = 520,

1.35 high = 390.

All 8-way cache max values have footnote 11.

Added 4-way cache values

1.65 high = TBD and 1.35 high = TBD, both with footnote 12.

• Spec 28: Changed 132 MHz to 135 MHz.

• Spec 29: Deleted frequency information.

• Corrected footnote 3 to read: If standby operation is not required, connect the V_STBYto ground.

• Combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line

that reads: Eight-way cache enabled (L1CSR0[CORG] = 0b0).

• Added footnote 10 to specs 27a, b, and c on the 4-way cache line that reads: Four-way cache enabled

(L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,

L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).

• Added footnote 11 to specs 27a, b, and c on the max numeric values: “Preliminary. Specification pending final

characterization.”

• Added footnote 12 to specs 27a, b, and c on the max TBD values: “Specification pending final characterization.”

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)

Description of Changes

Location

Figure 2 (fISTBY Worst-case Specifications) Added figure to show interpolated IDD_STBYvalues listed in Table 9 (DC Electrical

Specifications (T_A= T_{L to}T_H)).

Table 12 (FMPLL Electrical Specifications) FMPLL Electrical Characteristics:

• Added (T_A= T_L– T_H) to the second line of the table title.

• Spec 1, footnote 1 in column 2: ‘PLL reference frequency range.’: Changed to read ‘Nominal crystal and external

reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within

5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.

The designer must thoroughly understand the drift margin of the source clock.‘

• Spec 1, added two more lines to the PLL reference frequency range’ to read as follows

crystal reference (20)

crystal reference (40)

external reference (20)

external reference (40)

fref_crystal

fref_ext

8

> 20

8

 20

40

 20

40

fref_ext

> 20

• Spec 1, footnote 2 in column 2: ‘PLL reference frequency range.’: Changed to: ‘The 8–20 MHz crystal or external

reference values have PLLCFG[2] pulled low’ and applies to spec 1, column 2, crystal reference and external

reference.

• Spec 1, footnote 2 in column 2: ‘PLL reference frequency range,’ Changed to: The 20–40 MHz crystal and

external reference values have PLLCFG[2] pulled high, and the minimum frequency must be greater than 20

MHz. Use the 8–20 MHz setting (PLLCFG[2] pulled low) if a 20 MHz crystal or external reference is required. To

exit RESET when using 40 MHz, set PLLCFG[2] to 1.

• Specs 12 and 13: Grouped (2 x Cl).

• Spec 21, column 2: Changed f_{ref_crystal}to f_refin ICO frequency equation, and

added the same equation but substituted f_{ref_ext}for f_reffor the external reference clock, giving:

f_ico= [ f_{ref_crystal} (MFD + 4) ] (PREDIV + 1)

f_ico= [ f_{ref_ext} (MFD + 4) ] (PREDIV + 1)

• Spec 21, column 4, Max.: Deleted old footnote 18 that reads:

The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL

synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).

Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the

ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’

• Spec 21: Changed column 5 from ‘82 or 66 MHz’ to: ‘150’.

• Spec 22: Changed column 4, Max. Value from f_MAXto 20, and added footnote 20 to read, ‘Maximum value for

dual controller (1:1) mode is (f_MAX2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’

Table 13 (eQADC Conversion Specifications (TA = TL to TH)) eQADC Conversion Specifications: Added (T_A= T_L– T_H) to the

table title.

Table 14 (Flash Program and Erase Specifications (T_A= T_Lto T_H)) Flash Program and Erase Specifications:

• Added (T_A= T_L– T_H) to the table title.

• Specs 7, 8, 9, and 10:

Changed typical values — 48 KB: from 340 to 345; 64 KB: from 400 to 415

Spec 8, 128KB block pre-program and erase time, Max. column value from 15,000 to 7,500.

• Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.

• Footnote 2: Changed from: ‘Initial factory condition: 100program/erase cycles, 25 ^oC, typical supply voltage,

80 MHz minimum system frequency.‘ to: ‘Initial factory condition: 100program/erase cycles, 25 ^oC, using a

typical supply voltage measured at a minimum system frequency of 80 MHz.’

Table 15 (Flash EEPROM Module Life (T_A= T_Lto T_H)) Flash EEPROM Module Life:

• Replaced (Full Temperature Range) with (T_A= T_L– T_H) in the table title.

• Spec 1b, Min. column value changed from 10,000 to 1,000.

MPC5561 Microcontroller Data Sheet, Rev. 3

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)

Description of Changes

Location

Table 16 (FLASH_BIU Settings vs. Frequency of Operation) FLASH BIU Settings vs. Frequency of Operations:

• Changed the Maximum Operating Frequency column entry from: Up to and including132 MHz to: Up to and

including134 MHz.

• Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from the

same row in this table.’

• Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.

• Deleted the x-refs in the ‘DPFEN’ column for the rows.

• Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.

• Deleted the x-refs in the ‘IPFEN’ column for the rows.

• Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.

• Deleted the x-refs in the ‘PFLIM’ column for the rows.

• Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.

• Deleted the x-refs in the ‘BFEN’ column for the rows.

• Changed footnote 6 from: ‘Allows for 128 MHz system clock with 2% frequency modulation’ to: ‘Allows for 132

MHz system clock with 2% frequency modulation.’

Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications and Table 18 (Derated Pad AC

Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)) Derated Pad AC Specifications:

• Footnote 1, deleted ‘f_SYS= 132 MHz.’

• Footnote 2, changed from ‘tested’ to ‘(not tested).’

• Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,

• Changed from ‘Add a maximum of one system clock to the output delay to get the output delay with respect to

the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system

clock to the output delay.’

• Footnote 4: changed ‘Delay’ to ‘The output delay.’

• Footnote 5: deleted ‘before qualification.’

• Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This

parameter is supplied for reference and is guaranteed by design and tested.’

Table 19 (Reset and Configuration Pin Timing) Reset and Configuration Pin Timing: Footnote 1, deleted ‘f_SYS= 132 MHz.’

Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics:

• Footnote 1, deleted: ‘f_SYS= 132 MHz.’ and ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’

• Footnote 1, changed ‘functional’ to ‘Nexus.’

Table 21 (Nexus Debug Port Timing) Nexus Debug Port Timing.

• Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4

from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.

• Footnote 5, changed from ‘to MCKO. The timing is. . .’ to: ‘to ‘MCKO and is . . .’

Table 22 (Bus Operation Timing) Bus Operation Timing:

• Changed Spec 1 for the minimum 67 MHz column from: 15.2 to 14.9.

• Specs 5 and 6: corrected format to show the bus timing values for various frequencies with EBTS bit = 0 and

EBTS bit = 1.

Table 23 (External Interrupt Timing) External Interrupt Timing:

• Footnote 1: Deleted ‘f_SYS= 132 MHz’, ‘.V_DD33and V_DDSYN= 3.0–3.6 V’ and ‘and CL = 200 pF with SRC = 0b11.’

• Deleted second figure after table ‘External Interrupt Setup Timing.’

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Revision History for the MPC5561 Data Sheet

Table 30. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)

Description of Changes

Location

Table 24 eTPU Timing, Figure 16 eTPU Timing and Figure 17 eTPU Input/Output Timing: Deleted – No eTPU in MPC5561.

Table 24 (eMIOS Timing) eMIOS Timing:

• Deleted (MTS) from the heading, table, and footnotes.

• Footnote 1: Deleted ‘. . .f_SYS= 132 MHz. . .’, ‘. . .V_DD33and V_DDSYN= 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF

with SRC = 0b11.’

• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum

eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad

configuration registers (PCR).’

Figure 16 (eMIOS Timing) eMIOS Timing Added figure.

Table 25 (DSPI Timing’) DSPI Timing:

• Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad

type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’

• Footnote 1: Deleted ‘V_DD= 1.35–1.65 V’ and ‘V_DD33and V_DDSYN= 3.0–3.6 V.

Table 26 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics:

• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’

• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’

• Spec 1: FCK frequency -- removed.

• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 to Spec 2.

• Footnote 1, deleted ‘V_DD= 1.35–1.65 V’ and ‘V_DD33and V_DDSYN= 3.0–3.6V.’

Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’

• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .

Figure 27 (MPC5561 324 Package) MPC5561 324 Package:

• Changed ball label T21 from VRCVSS to PLLCFG2.

• Deleted the version number and date.

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Document Number: MPC5561

Rev. 3

6/2012


型号：	PPC5561MVZ80R
厂家：	NXP
描述：	Microcontroller Data Sheet 微控制器
文件：	总58页 (文件大小：1736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PPC5561MVZ80R [NXP]

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