PPC5777CCK3MME3R_技术文档

Document Number: MPC5777C

Rev. 14, 01/2020

NXP Semiconductors

Data Sheet: Technical Data

MPC5777C

MPC5777C Microcontroller

Data Sheet

Features

For functional characteristics and the programming

model, see the MPC5777C Reference Manual.

•

This document provides electrical specifications, pin

assignments, and package diagram information for the

MPC5777C series of microcontroller units (MCUs).

•

NXP reserves the right to change the proudction detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1 Introduction...............................................................................3

3.11.1

3.11.2

3.11.3

3.11.4

Power management electrical characteristics40

Power management integration.....................43

Device voltage monitoring..............................44

Power sequencing requirements....................46

1.1 Features summary..........................................................3

1.2 Block diagram..................................................................4

2 Pinouts......................................................................................5

2.1 416-ball MAPBGA pin assignments................................5

2.2 516-ball MAPBGA pin assignments................................6

3 Electrical characteristics............................................................7

3.1 Absolute maximum ratings..............................................7

3.2 Electromagnetic interference (EMI) characteristics.........9

3.3 Electrostatic discharge (ESD) characteristics.................9

3.4 Operating conditions.......................................................9

3.5 DC electrical specifications.............................................12

3.6 I/O pad specifications......................................................13

3.12 Flash memory specifications...........................................47

3.12.1

Flash memory program and erase

specifications..................................................48

Flash memory Array Integrity and Margin

Read specifications........................................48

Flash memory module life specifications.......49

Data retention vs program/erase cycles.........50

Flash memory AC timing specifications.........50

Flash memory read wait-state and address-

pipeline control settings..................................51

3.12.2

3.12.3

3.12.4

3.12.5

3.12.6

3.6.1

3.6.2

3.6.3

Input pad specifications..................................13

Output pad specifications...............................15

I/O pad current specifications.........................19

3.13 AC timing.........................................................................52

3.13.1

3.13.2

3.13.3

3.13.4

3.13.5

3.13.6

3.13.7

3.13.8

3.13.9

Generic timing diagrams................................52

Reset and configuration pin timing.................53

IEEE 1149.1 interface timing..........................54

Nexus timing..................................................57

External Bus Interface (EBI) timing................59

External interrupt timing (IRQ/NMI pin)..........63

eTPU timing...................................................64

eMIOS timing.................................................65

DSPI timing with CMOS and LVDS pads.......66

3.7 Oscillator and PLL electrical specifications.....................19

3.7.1

3.7.2

PLL electrical specifications...........................20

Oscillator electrical specifications..................21

3.8 Analog-to-Digital Converter (ADC) electrical

specifications...................................................................23

3.8.1

Enhanced Queued Analog-to-Digital

Converter (eQADC)........................................23

Sigma-Delta ADC (SDADC)...........................25

3.8.2

3.9 Temperature Sensor.......................................................34

3.10 LVDS Fast Asynchronous Serial Transmission (LFAST)

pad electrical characteristics...........................................34

3.13.10 FEC timing.....................................................78

4 Package information.................................................................83

4.1 Thermal characteristics...................................................83

3.10.1

3.10.2

LFAST interface timing diagrams...................34

LFAST and MSC/DSPI LVDS interface

4.1.1

General notes for thermal characteristics......84

5 Ordering information.................................................................87

6 Document revision history.........................................................88

electrical characteristics.................................36

LFAST PLL electrical characteristics.............39

3.10.3

3.11 Power management: PMC, POR/LVD, power

sequencing......................................................................40

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Introduction

1 Introduction

1.1 Features summary

On-chip modules available within the family include the following features:

• Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep

• Power Architecture embedded specification compliance

• Instruction set enhancement allowing variable length encoding (VLE), optional

encoding of mixed 16-bit and 32-bit instructions, for code size footprint

reduction

• On the two computational cores: Signal processing extension (SPE1.1)

instruction support for digital signal processing (DSP)

• Single-precision floating point operations

• On the two computational cores: 16 KB I-Cache and 16 KB D-Cache

• Hardware cache coherency between cores

• 16 hardware semaphores

• 3-channel CRC module

• 8 MB on-chip flash memory

• Supports read during program and erase operations, and multiple blocks

allowing EEPROM emulation

• 512 KB on-chip general-purpose SRAM including 64 KB standby RAM

• Two multichannel direct memory access controllers (eDMA)

• 64 channels per eDMA

• Dual core Interrupt Controller (INTC)

• Dual phase-locked loops (PLLs) with stable clock domain for peripherals and

frequency modulation (FM) domain for computational shell

• Crossbar Switch architecture for concurrent access to peripherals, flash memory, or

RAM from multiple bus masters with End-To-End ECC

• External Bus Interface (EBI) for calibration and application use

• System Integration Unit (SIU)

• Error Injection Module (EIM) and Error Reporting Module (ERM)

• Four protected port output (PPO) pins

• Boot Assist Module (BAM) supports serial bootload via CAN or SCI

• Three second-generation Enhanced Time Processor Units (eTPUs)

• 32 channels per eTPU

• Total of 36 KB code RAM

• Total of 9 KB parameter RAM

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

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Introduction

• Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channels

with each channel capable of single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with:

• Two separate analog converters per eQADC module

• Support for a total of 70 analog input pins, expandable to 182 inputs with off-

chip multiplexers

• Interface to twelve hardware Decimation Filters

• Enhanced "Tap" command to route any conversion to two separate Decimation

Filters

• Four independent 16-bit Sigma-Delta ADCs (SDADCs)

• 10-channel Reaction Module

• Ethernet (FEC)

• Two PSI5 modules

• Two SENT Receiver (SRX) modules supporting 12 channels

• Zipwire: SIPI and LFAST modules

• Five Deserial Serial Peripheral Interface (DSPI) modules

• Five Enhanced Serial Communication Interface (eSCI) modules

• Four Controller Area Network (FlexCAN) modules

• Two M_CAN modules that support FD

• Fault Collection and Control Unit (FCCU)

• Clock Monitor Units (CMUs)

• Tamper Detection Module (TDM)

• Cryptographic Services Engine (CSE)

• Complies with Secure Hardware Extension (SHE) Functional Specification

Version 1.1 security functions

• Includes software selectable enhancement to key usage flag for MAC

verification and increase in number of memory slots for security keys

• PASS module to support security features

• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some

support for 2010 standard

• Device and board test support per Joint Test Action Group (JTAG) IEEE 1149.1 and

1149.7

• On-chip voltage regulator controller (VRC) that derives the core logic supply voltage

from the high-voltage supply

• On-chip voltage regulator for flash memory

• Self Test capability

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Pinouts

1.2 Block diagram

The following figure shows a top-level block diagram of the MPC5777C. The purpose of

the block diagram is to show the general interconnection of functional modules through

the crossbar switch.

FLEXCAN_A-B

COMPUTATIONAL SHELL

MCAN_0-1

e200z7 checker

core complex

DEBUG

DSPI_A-C

eSCI_A-C

JTAG

MMU

SWT

STM

INTC

SWT

STM

INTC

e200z7

(dual issue)

Nexus 3+ DTS

FPU

ETPU_C

w/RAM

VLE

eMIOS_0

64ch eDMA

Ethernet

16K I-Cache

16K D-Cache

16K I-Cache

16K D-Cache

eQADC_A

& Temp Sensors

DECFILTER_A-L

SDADC_1/3

SRX_0

MMU

Crossbar Switch with ECC

MPU

Safety

Monitor

PSI5_0

REACM2

Zipwire/

SIPI/LFAST

Bridge B

Bridge A

SRAM

Flash Control

EBI

Control

Security

Dual PLL/

OSC/IRC

Tamper

Detection

CRC

CSE

Flash w/ EEPROM

SRAM

PCM/ERM

Figure 1. MPC5777C block diagram

2 Pinouts

2.1 416-ball MAPBGA pin assignments

Figure 2 shows the 416-ball MAPBGA pin assignments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Pinouts

Figure 2. MPC5777C 416-ball MAPBGA (full diagram)

2.2 516-ball MAPBGA pin assignments

Figure 3 shows the 516-ball MAPBGA pin assignments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Figure 3. MPC5777C 516-ball MAPBGA (full diagram)

3 Electrical characteristics

The following information includes details about power considerations, DC/AC electrical

characteristics, and AC timing specifications.

3.1 Absolute maximum ratings

Absolute maximum specifications are stress ratings only. Functional operation at these

maxima is not guaranteed.

CAUTION

Stress beyond listed maxima may affect device reliability or

cause permanent damage to the device.

See Operating conditions for functional operation specifications.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Symbol

Table 1. Absolute maximum ratings

Value

Parameter

Conditions¹

Unit

Min

Max

1000k

1.5

Cycle

V_DD

Lifetime power cycles

1.2 V core supply voltage^{2, 3, 4}

—

V

–0.3

V_DDEHx

V_DDEx

V_DDPMC

I/O supply voltage (medium I/O pads)⁵

I/O supply voltage (fast I/O pads)⁵

6.0

Power Management Controller supply

voltage⁵

6.0

V_DDFLA

V_STBY

Decoupling pin for flash regulator⁶

RAM standby supply voltage⁵

SDADC ground voltage

—

–0.3

4.5

6.0

0.3

6.0

0.3

6.0

V

V_{SSA_SD}

V_{SSA_EQ}

V_{DDA_EQA/B}

V_{DDA_SD}

V_{RL_SD}

Reference to V_SS

eQADC ground voltage

Reference to V_SS

eQADC supply voltage

Reference to V_{SSA_EQ}

Reference to V_{SSA_SD}

Reference to V_SS

SDADC supply voltage

SDADC ground reference

eQADC ground reference

eQADC alternate reference

SDADC alternate reference

V_{RL_EQ}

Reference to V_SS

V_{RH_EQ}

Reference to V_{RL_EQ}

Reference to V_{RL_SD}

V_{RH_SD}

V_REFBYPC

eQADC reference decoupling capacitor REFBYPCA25, REFBYPCA75,

pins

REFBYPCB25, REFBYPC75

V_{DDA_MISC}

V_DDPWR

TRNG and IRC supply voltage

SMPS driver supply pin

V_{SSA_EQ}differential voltage

V_{SSA_SD}differential voltage

V_{RL_EQ}differential voltage

V_{RL_SD}differential voltage

I/O input voltage range⁷

—

–0.3

—

6.0

0.3

6.0

0.3

—

V

—

V_SSPWR

Reference to V_SS

V

V_SS– V_{SSA_EQ}

V_SS– V_{SSA_SD}

V_SS– V_{RL_EQ}

V_SS– V_{RL_SD}

V_IN

—

V

—

V

—

V

—

V

—

V

Relative to V_DDEx/V_DDEHx

Relative to V_SS

V

–0.3

–5

V

I_INJD

I_INJA

Maximum DC injection current for digital Per pin, applies to all digital pins

pad

5

mA

Maximum DC injection current for

analog pad

Per pin, applies to all analog pins

–5

5

mA

°C

8, 9

I_MAXSEG

Maximum current per I/O power

segment

—

–120 120

T_STG

STORAGE

T_SDR

Storage temperature range and non-

operating times

–55

—

175

20

Maximum storage time, assembled part No supply; storage temperature in

programmed in ECU

Maximum solder temperature¹⁰

years

°C

range –40 °C to 60 °C

—

260

Pb-free package

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Table 1. Absolute maximum ratings (continued)

Value

Unit

Symbol

Parameter

Conditions¹

Min

Max

MSL

Moisture sensitivity level¹¹

—

3

—

1. Voltages are referred to V_SSif not specified otherwise

2. Allowed 1.45 V – 1.5 V for 60 seconds cumulative time at maximum T_J= 150 °C; remaining time as defined in note 3 and

note 4

3. Allowed 1.375 V – 1.45 V for 10 hours cumulative time at maximum T_J= 150 °C; remaining time as defined in note 4

4. 1.32 V – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at

maximum T_J= 150 °C

5. Allowed 5.5 V – 6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, T_J

= 150 °C; remaining time at or below 5.5 V

6. Allowed 3.6 V – 4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, T_J

= 150 °C; remaining time at or below 3.6 V

7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current

condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin

to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal

calculations.

8. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_DDEx/V_DDEHxpower segment

is defined as one or more GPIO pins located between two V_DDEx/V_DDEHxsupply pins.

9. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current.

10. Solder profile per IPC/JEDEC J-STD-020D

11. Moisture sensitivity per JEDEC test method A112

3.2 Electromagnetic interference (EMI) characteristics

Test reports with EMC measurements to IC-level IEC standards are available on request.

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions, go to nxp.com and perform a keyword search for

"radiated emissions."

3.3 Electrostatic discharge (ESD) characteristics

Table 2. ESD Ratings^{1, 2}

Symbol

V_HBM

Parameter

Conditions

All pins

Value

2000

750

Unit

V

ESD for Human Body Model (HBM)

ESD for Charged Device Model (CDM)

V_CDM

Corner pins

Non-corner pins

V

500

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

requirements.

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Electrical characteristics

3.4 Operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the data sheet are valid, except where explicitly noted.

If the device operating conditions are exceeded, the functionality of the device is not

guaranteed.

Table 3. Device operating conditions

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Frequency

f_SYS

f_PLATF

f_ETPU

f_EBI

Device operating frequency¹

Platform operating frequency

eTPU operating frequency

EBI operating frequency

—

264/300²MHz

132/150³MHz

200/240⁴MHz

—

66

MHz

f_PER

Peripheral block operating

frequency

132/150³MHz

f_{FM_PER}

Frequency-modulated peripheral —

block operating frequency

—

132/150³MHz

t_CYC

Platform clock period

eTPU clock period

—

1/f_PLATF

1/f_ETPU

1/f_PER

ns

t_{CYC_ETPU}

t_{CYC_PER}

Peripheral clock period

Temperature

T_J

Junction operating temperature Packaged devices

range

–40.0

—

150.0

°C

T_A(T_Lto T_H)

Ambient operating temperature Packaged devices

range

125.0⁵

Voltage

V_DD

External core supply voltage^{6, 7}LVD/HVD enabled

1.2

3.5

4.5

3.0

4.5

3.0

4.5

—

1.32

1.38

5.5

V

LVD/HVD disabled^{8, 9, 10, 11}

V_{DDA_MISC}

V_DDEx

TRNG and IRC supply voltage

—

V

I/O supply voltage (fast I/O pads) 5 V range

3.3 V range

5.5

3.6

5.5

11

V_DDEHx

I/O supply voltage (medium I/O 5 V range

V

pads)

3.3 V range

3.6

5.5

V_DDEH1

eTPU_A, eSCI_A, eSCI_B, and 5 V range

configuration I/O supply voltage

(medium I/O pads)

12

V_DDPMC

Power Management Controller

(PMC) supply voltage

Full functionality

3.15

—

5.5

V

V_DDPWR

V_DDFLA

V_STBY

SMPS driver supply voltage

Flash core voltage

Reference to V_SSPWR

3.0

3.15

0.95¹³

—

5.5

3.6

5.5

V

—

RAM standby supply voltage

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Table 3. Device operating conditions (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

V_{STBY_BO}

Standby RAM brownout flag trip

point voltage

—

0.9¹⁴

V

V_{RL_SD}

SDADC ground reference

voltage

V_{SSA_SD}

V_{DDA_SD}

V_{DDA_EQA/B}

V_{RH_SD}

SDADC supply voltage¹⁵

eQADC supply voltage

SDADC reference

—

4.5

4.75

4.5

—

5.5

5.25

5.5

V

V_{DDA_SD}

—

V

V_{DDA_SD}– V_{RH_SD}SDADC reference differential

voltage

25

mV

V_{SSA_SD}– V_{RL_SD}V_{RL_SD}differential voltage

—

–25

4.75

—

25

5.25

25

mV

V

V_{RH_EQ}

eQADC reference

V_{DDA_EQA/B}

V_{RH_EQ}

–

eQADC reference differential

voltage

mV

V_{SSA_EQ}– V_{RL_EQ}V_{RL_EQ}differential voltage

—

–25

—

25

mV

V_{SSA_EQ}– V_SS

V_{SSA_SD}– V_SS

V_RAMP

V_{SSA_EQ}differential voltage

V_{SSA_SD}differential voltage

Slew rate on power supply pins

25

mV

100

V/ms

Current

I_IC

DC injection current (per pin)^16,Digital pins and analog pins

–3.0

–80

—

3.0

80

mA

17, 18

I_MAXSEG

Maximum current per power

segment^{19, 20}

—

1. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking

chapter in the MPC5777C Microcontroller Reference Manual for more information on the clock limitations for the various IP

blocks on the device.

2. If frequency modulation (FM) is enabled for the operating frequency of 264MHz, the maximum frequency still cannot

exceed this value (frequency modulation must spread below nominal frequency). If frequency modulation is enabled for the

operating frequency of 300MHz, this maximum frequency can be exceeded (frequency modulation can be center spread

from 300MHz).

3. 132 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 150 MHz applies to the version with

300 MHz operating frequency.

4. 200 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 240 MHz applies to the version

with 300 MHz operating frequency.

5. The maximum specification for operating junction temperature T_Jmust be respected. Thermal characteristics provides

details.

6. Core voltage as measured on device pin to guarantee published silicon performance

7. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct

silicon operation is guaranteed. See power management and reset management for description.

8. Maximum core voltage is not permitted for entire product life. See absolute maximum rating.

9. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor

externally supply voltage may result in erroneous operation of the device.

10. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the

reset sequence, and the LVD/HVD are active until that point.

11. This spec does not apply to V_DDEH1

.

12. When internal flash memory regulator is used:

• Flash memory read operation is supported for a minimum V_DDPMCvalue of 3.15 V.

• Flash memory read, program, and erase operations are supported for a minimum V_DDPMCvalue of 3.5 V.

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Electrical characteristics

When flash memory power is supplied externally (V_DDPMCshorted to V_DDFLA): The V_DDPMCrange must be within the limits

specified for LVD_FLASH and HVD_FLASH monitoring. Table 29 provides the monitored LVD_FLASH and HVD_FLASH

limits.

13. If the standby RAM regulator is not used, the V_STBYsupply input pin must be tied to ground.

14. V_{STBY_BO}is the maximum voltage that sets the standby RAM brownout flag in the device logic. The minimum voltage for

RAM data retention is guaranteed always to be less than the V_{STBY_BO}maximum value.

15. For supply voltages between 3.0 V and 4.0 V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will

recover to a fully functional state when the voltage rises above 4.0 V.

16. Full device lifetime without performance degradation

17. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

absolute maximum ratings table for maximum input current for reliability requirements.

18. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network

calculation, assume a typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

19. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_DDEx/V_DDEHxpower segment

is defined as one or more GPIO pins located between two V_DDEx/V_DDEHxsupply pins.

20. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current.

3.5 DC electrical specifications

NOTE

I_{DDA_MISC}is the sum of current consumption of IRC, I_TRNG

and I_STBYin the 5 V domain. IRC current is provided in the

IRC specifications.

,

NOTE

I/O, XOSC, EQADC, SDADC, and Temperature Sensor current

specifications are in those components' dedicated sections.

Table 4. DC electrical specifications

Value

Symbol

Parameter

Conditions

Unit

Min

Typ Max

0.65 1.35

I_DD

Operating current on the V_DDcore logic

supply¹

LVD/HVD enabled, V_DD= 1.2 V

to 1.32 V

—

A

LVD/HVD disabled, V_DD= 1.2 V

to 1.38 V

—

0.65

—

1.4

85

I_{DD_PE}

I_DDPMC

Operating current on the V_DDsupply for flash

memory program/erase

Operating current on the V_DDPMCsupply²

—

mA

Flash memory read

Flash memory program/erase

PMC only

—

40

70

35

10

40

5

Operating current on the V_DDPMCsupply

(internal core regulator bypassed)

Flash memory read

Flash memory program/erase

PMC only

mA

I_REGCTL

Core regulator DC current output on V_REGCTL

—

25

Table continues on the next page...

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Electrical characteristics

Table 4. DC electrical specifications (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

Typ Max

I_STBY

Standby RAM supply current

1.08 V, T_J= 150°C

—

1140 μA

1.25 V to 5.5 V, T_J= 150°C

1.25 V to 5.5 V, T_J= 85°C

1.25 V to 5.5 V, T_J= 40°C

—

1170

360

120

50

—

I_{DD_PWR}

I_{BG_REF}

I_TRNG

Operating current on the V_DDPWRsupply

Bandgap reference current consumption³

True Random Number Generator current

mA

μA

600

2.1

—

mA

1. I_DDmeasured on an application-specific pattern with all cores enabled at full frequency, T_J= 40°C to 150°C. Flash memory

program/erase current on the V_DDsupply not included.

2. This value is considering the use of the internal core regulator with the simulation of an external transistor with the

minimum value of h_FEof 60.

3. This bandgap reference is for EQADC calibration and Temperature Sensors.

3.6 I/O pad specifications

The following table describes the different pad types on the chip.

Table 5. I/O pad specification descriptions

Pad type

Description

General-purpose I/O

pads

General-purpose I/O and EBI data bus pads with four selectable output slew rate settings; also

called SR pads

EBI pads

Provide necessary speed for fast external memory interfaces on the EBI CLKOUT, address, and

control signals; also called FC pads

LVDS pads

Low Voltage Differential Signal interface pads

Input-only pads

Low-input-leakage pads that are associated with the ADC channels

NOTE

Each I/O pin on the device supports specific drive

configurations. See the signal description table in the device

reference manual for the available drive configurations for each

I/O pin.

NOTE

Throughout the I/O pad specifications, the symbol V_DDEx

represents all V_DDExand V_DDEHxsegments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

3.6.1 Input pad specifications

Table 6 provides input DC electrical characteristics as described in Figure 4.

V IN

V DD

V IH

V HYS

V IL

V INTERNAL

(SIU register)

Figure 4. I/O input DC electrical characteristics definition

Table 6. I/O input DC electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

V_{IHCMOS_H}Input high level CMOS (with

hysteresis)

3.0 V < V_DDEx< 3.6 V and

4.5 V < V_DDEx< 5.5 V

0.65 * V_DDEx

—

V_DDEx+ 0.3

V

V_IHCMOSInput high level CMOS (without 3.0 V < V_DDEx< 3.6 V and

0.55 * V_DDEx

–0.3

—

V_DDEx+ 0.3

0.35 * V_DDEx

0.4 * V_DDEx

—

V

hysteresis)

4.5 V < V_DDEx< 5.5 V

V_{ILCMOS_H}Input low level CMOS (with

hysteresis)

3.0 V < V_DDEx< 3.6 V and

4.5 V < V_DDEx< 5.5 V

V_ILCMOS

Input low level CMOS (without

hysteresis)

3.0 V < V_DDEx< 3.6 V and

4.5 V < V_DDEx< 5.5 V

–0.3

V_HYSCMOSInput hysteresis CMOS

3.0 V < V_DDEx< 3.6 V and

0.1 * V_DDEx

4.5 V < V_DDEx< 5.5 V

Input Characteristics¹

V_SS< V_IN< V_DDEx/V_DDEHx

I_LKG

Digital input leakage

—

2.5

μA

I_{LKG_FAST}Digital input leakage for EBI

address/control signal pads

I_LKGA

Analog pin input leakage (5 V

range)

V_{SSA_SD}< V_IN< V_{DDA_SD}

V_{SSA_EQ}< V_IN< V_{DDA_EQA/B}

,

—

220

7

nA

pF

C_IN

Digital input capacitance

GPIO and EBI input pins

1. For LFAST, microsecond bus, and LVDS input characteristics, see dedicated communication module sections.

Table 7 provides current specifications for weak pullup and pulldown.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Table 7. I/O pullup/pulldown DC electrical characteristics

Value

Typ

—

Symbol

Parameter

Conditions

Unit

Min

Max

I_WPU

Weak pullup current

V_IN= 0.35 * V_DDEx

4.5 V < V_DDEx< 5.5 V

V_IN= 0.35 * V_DDEx

3.0 V < V_DDEx< 3.6 V

V_IN= 0.65 * V_DDEx

4.5 V < V_DDEx< 5.5 V

V_IN= 0.65 * V_DDEx

3.0 V < V_DDEx< 3.6 V

40

120

μA

25

40

25

—

80

120

80

I_WPD

Weak pulldown current

μA

The specifications in Table 8 apply to the pins ANA0_SDA0 to ANA7, ANA16_SDB0 to

ANA23_SDC3, and ANB0_SDD0 to ANB7_SDD7.

Table 8. I/O pullup/pulldown resistance electrical characteristics

Value

Symbol Parameter

Conditions

Unit

Min

130

65

Typ

200

100

5

Max

280

140

7.5

5

R_PUPDAnalog input bias / diagnostic pullup/

pulldown resistance

200 kΩ

100 kΩ

5 kΩ

kΩ

1.4

—

Δ_PUPDR_PUPDpullup/pulldown resistance mismatch —

—

%

3.6.2 Output pad specifications

Figure 5 shows output DC electrical characteristics.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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15

Electrical characteristics

core side input

VDD/2

tPD

(low to high)

tPD

(high to low)

VDDEx

VSSEx

Voh

Vol

PAD

Rise

Time

Fall

Time

Figure 5. I/O output DC electrical characteristics definition

The following tables specify output DC electrical characteristics.

Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR

pads)¹

Value³

Symbol Parameter

Conditions²

Unit

Min

25

Typ

—

Max

—

I_OH

GPIO pad output high

current

V_OH= 0.8 * V_DDEx

PCR[SRC] = 11b or 01b

PCR[SRC] = 10b or 00b

PCR[SRC] = 11b or 01b

PCR[SRC] = 10b or 00b

PCR[SRC] = 11b or 01b

PCR[SRC] = 10b or 00b

PCR[SRC] = 11b or 01b

PCR[SRC] = 10b or 00b

mA

15

—

4.5 V < V_DDEx< 5.5 V

V_OH= 0.8 * V_DDEx

13

—

8

—

3.0 V < V_DDEx< 3.6 V

V_OL= 0.2 * V_DDEx

I_OL

GPIO pad output low

current

48

—

mA

22

—

4.5 V < V_DDEx< 5.5 V

V_OL= 0.2 * V_DDEx

17

—

10.5

—

3.0 V < V_DDEx< 3.6 V

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)¹

(continued)

Value³

Typ

—

Symbol Parameter

Conditions²

Unit

Min

—

Max

1.2

2.5

8

t_{R_F}

GPIO pad output

PCR[SRC] = 11b

C_L= 25 pF

C_L= 50 pF

C_L= 200 pF

C_L= 25 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

C_L= 50 pF

C_L= 200 pF

ns

transition time (rise/fall)

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 11b

1.7

3.25

12

5

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 10b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 10b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 01b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 01b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 00b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 00b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 11b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 11b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 10b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 10b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 01b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 01b

3.0 V < V_DDEx< 3.6 V

PCR[SRC] = 00b

4.5 V < V_DDEx< 5.5 V

PCR[SRC] = 00b

3.0 V < V_DDEx< 3.6 V

—

18

7

25

13

24

25

30

24

50

40

51

6

t_PD

GPIO pad output

ns

propagation delay time

13

8.25

19.5

9

22

12.5

35

27

40

45

65

40

65

75

100

25

|t_{SKEW_W}| Difference between rise

and fall time

%

1. All GPIO pad output specifications are valid for 3.0 V < V_DDEx< 5.5 V, except where explicitly stated.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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17

Electrical characteristics

2. PCR[SRC] values refer to the setting of that register field in the SIU.

3. All values to be confirmed during device validation.

The following table shows the EBI CLKOUT, address, and control signal pad electrical

characteristics. These pads can also be used for GPIO.

Table 10. GPIO and EBI CLKOUT, address, and control signal pad output

buffer electrical characteristics (FC pads)

Value

Symbol

Parameter

Conditions¹

Unit

Min

EBI Mode Output Specifications: valid for 3.0 V < V_DDEx< 3.6 V

Typ

Max

C_DRV

External bus load

capacitance

PCR[DSC] = 01b

PCR[DSC] = 10b

PCR[DSC] = 11b

—

10

20

30

66

pF

f_{MAX_EBI}

External bus maximum C_DRV= 10/20/30 pF

operating frequency

MHz

mA

GPIO and EBI Mode Output Specifications

I_{OH_EBI}

GPIO and external bus V_OH= 0.8 * V_DDEx

pad output high current

PCR[DSC] = 11b

PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

PCR[DSC] = 11b

PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

PCR[DSC] = 11b

PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

PCR[DSC] = 11b

PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

C_L= 30 pF

30

22

13

2

—

4.5 V < V_DDEx< 5.5 V

—

V_OH= 0.8 * V_DDEx

16

12

7

—

3.0 V < V_DDEx< 3.6 V

—

1

—

I_{OL_EBI}

GPIO and external bus V_OL= 0.2 * V_DDEx

pad output low current

54

25

16

2

—

mA

—

4.5 V < V_DDEx< 5.5 V

—

V_OL= 0.2 * V_DDEx

17

14

8

—

3.0 V < V_DDEx< 3.6 V

—

1

—

t_{R_F_EBI}

GPIO and external bus PCR[DSC] = 11b

pad output transition

time (rise/fall)

—

1.5

2.4

1.5

1.85

45

4.2

5.5

4.2

4.4

59

ns

C_L= 50 pF

PCR[DSC] = 10b

C_L= 20 pF

PCR[DSC] = 01b

PCR[DSC] = 00b

C_L= 10 pF

C_L= 50 pF

t_{PD_EBI}

GPIO and external bus PCR[DSC] = 11b

pad output propagation

delay time

C_L= 30 pF

C_L= 50 pF

PCR[DSC] = 10b

C_L= 20 pF

PCR[DSC] = 01b

PCR[DSC] = 00b

C_L= 10 pF

C_L= 50 pF

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

1. PCR[DSC] values refer to the setting of that register field in the SIU.

3.6.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segments. Each I/O supply segment is

associated with a V_DDExsupply segment.

Table 11 provides I/O consumption figures.

To ensure device reliability, the average current of the I/O on a single segment should

remain below the I_MAXSEGvalue given in Table 1.

To ensure device functionality, the average current of the I/O on a single segment should

remain below the I_MAXSEGvalue given in Table 3.

NOTE

The MPC5777C I/O Signal Description and Input Multiplexing

Tables are contained in a Microsoft Excel® file attached to the

Reference Manual. In the spreadsheet, select the I/O Signal

Table tab.

The EBI power segments have been designed to operate within the maximum per-

segment current specification when the pins on the segment are used for EBI function. If

the pins are used instead for GPIO function, the user must ensure the sum of the current

used on each pin in the segment does not exceed the spec.

Table 11. I/O consumption

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

I_{AVG_GPIO}

Average I/O current for GPIO pads C_L= 25 pF, 2 MHz

—

0.42

mA

(per pad)

V_DDEx= 5.0 V 10%

C_L= 50 pF, 1 MHz

—

0.35

9

V_DDEx= 5.0 V 10%

I_{AVG_EBI}

Average I/O current for external

bus output pins (per pad)

C_DRV= 10 pF, f_EBI= 66 MHz

mA

V_DDEx= 3.3 V 10%

C_DRV= 20 pF, f_EBI= 66 MHz

V_DDEx= 3.3 V 10%

18

30

C_DRV= 30 pF, f_EBI= 66 MHz

V_DDEx= 3.3 V 10%

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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19

Electrical characteristics

3.7 Oscillator and PLL electrical specifications

The on-chip dual PLL—consisting of the peripheral clock and reference PLL (PLL0) and

the frequency-modulated system PLL (PLL1)—generates the system and auxiliary clocks

from the main oscillator driver.

PLL0_PHI

IRC

PLL0_PHI1

PLL0

XOSC

PLL1_PHI

PLL1

Figure 6. PLL integration

3.7.1 PLL electrical specifications

Table 12. PLL0 electrical characteristics

Value

Typ

—

Symbol

Parameter

Conditions

Unit

Min

8

Max

44

f_PLL0IN

Δ_PLL0IN

f_PLL0VCO

f_PLL0PHI

PLL0 input clock^{1, 2}

—

MHz

%

PLL0 input clock duty cycle²

PLL0 VCO frequency

PLL0 output frequency

40

—

60

600

4.762

—

1250

MHz

—

200/24 MHz

0³

t_PLL0LOCK

PLL0 lock time

—

110

200

μs

ps

|Δ_PLL0PHISPJ

|

PLL0_PHI single period jitter

f_PLL0IN= 20 MHz (resonator)

f_PLL0PHI= 200 MHz, 6-sigma

|Δ_PLL0PHI1SPJ

|

PLL0_PHI1 single period jitter f_PLL0PHI1= 40 MHz, 6-sigma

f_PLL0IN= 20 MHz (resonator)

—

300⁴

ps

Δ_PLL0LTJ

PLL0 output long term jitter⁴

10 periods accumulated jitter (80 MHz

equivalent frequency), 6-sigma pk-pk

—

250

300

500

7.5

ps

f_PLL0IN= 20 MHz (resonator),

VCO frequency = 800 MHz

16 periods accumulated jitter (50 MHz

equivalent frequency), 6-sigma pk-pk

long term jitter (< 1 MHz equivalent

frequency), 6-sigma pk-pk)

ps

I_PLL0

PLL0 consumption

FINE LOCK state

mA

1. Ensure that the f_PLL0INfrequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8 MHz to 20 MHz.

2. PLL0IN clock retrieved directly from either internal IRC or external XOSC clock. Input characteristics are granted when

using internal IRC or external oscillator is used in functional mode.

3. 200 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 240 MHz applies to the version with

300 MHz operating frequency

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Electrical characteristics

4. Noise on the V_DDsupply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the V_DD

supply with frequency content in the range of 40 kHz – 50 MHz must be filtered externally to the device.

Table 13. PLL1 electrical characteristics

Value

Symbol

Parameter

PLL1 input clock¹

PLL1 input clock duty cycle¹

PLL1 VCO frequency

PLL1 output clock PHI

PLL1 lock time

Conditions

Unit

Min

38

Typ

—

Max

78

f_PLL1IN

Δ_PLL1IN

f_PLL1VCO

f_PLL1PHI

t_PLL1LOCK

|Δ_PLL1PHISPJ

—

MHz

%

35

—

65

600

4.762

—

1250

264/300²

100

MHz

μs

—

|

PLL1_PHI single period peak-to- f_PLL1PHI= 200 MHz, 6-

peak jitter

—

500³

ps

sigma

f_PLL1MOD

PLL1 modulation frequency

—

0.25

0.5

—

250

2

kHz

%

|δ_PLL1MOD

|

PLL1 modulation depth (when

enabled)

Center spread

Down spread

FINE LOCK state

4

%

I_PLL1

PLL1 consumption

6

mA

1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when

using internal PLL0 or external oscillator in functional mode.

2. 264 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 300 MHz applies to the version

with 300 MHz operating frequency

3. Noise on the V_DDsupply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the V_DD

supply with frequency content in the range of 40 kHz – 50 MHz must be filtered externally to the device.

3.7.2 Oscillator electrical specifications

NOTE

All oscillator specifications in Table 14 are valid for V_DDEH6

3.0 V to 5.5 V.

=

Table 14. External oscillator (XOSC) electrical specifications

Value

Symbol

Parameter

Conditions

Unit

Min

Max

f_XTAL

t_cst

Crystal frequency range

—

8

—

40

MHz

ms

V

Crystal start-up time^{1, 2}

Crystal recovery time³

T_J= 150 °C

—

5

0.5

t_rec

—

V_IHEXT

V_ILEXT

EXTAL input high voltage (external reference) V_REF= 0.28 * V_DDEH6

EXTAL input low voltage (external reference) V_REF= 0.28 * V_DDEH6

V_REF+ 0.6

—

V_REF– 0.6

3.0

V

C_{S_EXTAL}Total on-chip stray capacitance on EXTAL pin⁴416-ball MAPBGA

2.3

pF

516-ball MAPBGA

2.1

2.8

C_{S_XTAL}

Total on-chip stray capacitance on XTAL pin⁴416-ball MAPBGA

516-ball MAPBGA

2.3

3.0

pF

2.2

2.9

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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21

Electrical characteristics

Table 14. External oscillator (XOSC) electrical specifications

(continued)

Value

Symbol

Parameter

Conditions

Unit

Min

3

Max

10

g_m

Oscillator transconductance⁵

Low

mA/V

Medium

High

—

10

12

0.5

27

35

V_EXTAL

Oscillation amplitude on the EXTAL pin after

startup⁶

1.6

V

V_HYS

I_XTAL

Comparator hysteresis

XTAL current^{6, 7}

—

0.1

—

1.0

14

V

mA

1. This value is determined by the crystal manufacturer and board design.

2. Proper PC board layout procedures must be followed to achieve specifications.

3. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load

capacitor value.

4. See crystal manufacturer's specification for recommended load capacitor (C_L) values.The external oscillator requires

external load capacitors when operating in a "low" transconductance range. Account for on-chip stray capacitance

(C_{S_EXTAL}/C_{S_XTAL}) and PCB capacitance when selecting a load capacitor value. When operating in a "medium" or "high"

transconductance range, the integrated load capacitor value is selected via software to match the crystal manufacturer's

specification, while accounting for on-chip and PCB capacitance.

5. Select a "low," "medium," or "high" setting using the UTEST Miscellaneous DCF client's XOSC_LF_EN and

XOSC_EN_HIGH fields. "Low" is the setting commonly used for crystals at 8 MHz, "medium" is commonly used for

crystals greater than 8 MHz to 20 MHz, and "high" is commonly used for crystals greater than 20 MHz to 40 MHz.

However, the user must characterize carefully to determine the best g_msetting for the intended application because crystal

load capacitance, board layout, and other factors affect the g_mvalue that is needed. The user may need an additional

Rshunt to optimize g_mdepending on the system environment. Use of overtone crystals is not recommended.

6. Amplitude on the EXTAL pin after startup is determined by the ALC block (that is, the Automatic Level Control Circuit). The

function of the ALC is to provide high drive current during oscillator startup, while reducing current after oscillation to

reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on

the crystal value and loading conditions.

7. I_XTALis the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum

current during startup of the oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent on the

load and series resistance of the crystal. Test circuit is shown in Figure 7.

Table 15. Selectable load capacitance

load_cap_sel[4:0] from DCF record

Load capacitance^{1, 2}(pF)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

1.8

2.8

3.7

4.6

5.6

6.5

7.4

8.4

9.3

10.2

11.2

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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Electrical characteristics

Table 15. Selectable load capacitance (continued)

load_cap_sel[4:0] from DCF record

01011

Load capacitance^{1, 2}(pF)

12.1

01100

01101

01110

01111

13.0

13.9

14.9

15.8

1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values

vary 12% across process, 0.25% across voltage, and no variation across temperature.

2. Values in this table do not include the die and package capacitances given by C_{S_XTAL}/C_{S_EXTAL}in Table 14.

VDDEH6

Bias

Current

ALC

I

XTAL

-

EXTAL

VSSOSC

Comparator

+

A

OFF

V

VSS

Conditions

Z = R + jωL

VEXTAL = 0 V

VXTAL = 0 V

ALC INACTIVE

Tester

PCB

GND

Figure 7. Test circuit

Table 16. Internal RC (IRC) oscillator electrical specifications

Value

Symbol

Parameter

Conditions

Unit

Min

—

Typ Max

f_Target

IRC target frequency

IRC frequency variation

—

16

—

8

MHz

%

δf_{var_T}

T < 150 °C

–8

3.8 Analog-to-Digital Converter (ADC) electrical specifications

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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23

Electrical characteristics

3.8.1 Enhanced Queued Analog-to-Digital Converter (eQADC)

Table 17. eQADC conversion specifications (operating)

Value

Symbol

Parameter

Unit

Min

2

Max

f_ADCLK

CC

ADC Clock (ADCLK) Frequency

Conversion Cycles

Stop Mode Recovery Time²

Resolution³

33

MHz

ADCLK cycles

μs

2 + 13

10

1.25

–4

–6

–3

0

128 + 15¹

T_SR

—

4

mV

LSB⁵

INL

INL: 16.5 MHz eQADC clock⁴

INL: 33 MHz eQADC clock⁴

DNL: 16.5 MHz eQADC clock⁴

DNL: 33 MHz eQADC clock⁴

Offset Error without Calibration

Offset Error with Calibration

Full Scale Gain Error without Calibration

Full Scale Gain Error with Calibration

Disruptive Input Injection Current^{6, 7, 8, 9}

Incremental Error due to injection current^{10, 11}

TUE value^{12, 13}(with calibration)

Variable gain amplifier accuracy (gain = 1)¹⁴

INL, 16.5 MHz ADC

6

LSB

DNL

3

LSB

3

LSB

OFFNC

OFFWC

GAINNC

GAINWC

I_INJ

140

8

LSB

–8

–150

–8

–3

—

LSB

0

LSB

8

LSB

3

mA

E_INJ

+4

8

Counts

Counts¹⁶

TUE

—

GAINVGA1

-

–4

–8

–3¹⁵

-

4

INL, 33 MHz ADC

8

DNL, 16.5 MHz ADC

3¹⁵

-

DNL, 33 MHz ADC

Variable gain amplifier accuracy (gain = 2)¹⁴

GAINVGA2

GAINVGA4

Counts

INL, 16.5 MHz ADC

–5

–8

–3

-

5

INL, 33 MHz ADC

8

DNL, 16.5 MHz ADC

3

DNL, 33 MHz ADC

Variable gain amplifier accuracy (gain = 4)¹⁴

3

-

INL, 16.5 MHz ADC

–7

–8

–4

—

7

INL, 33 MHz ADC

8

DNL, 16.5 MHz ADC

4

DNL, 33 MHz ADC

4

I_ADC

I_ADR

Current consumption per ADC (two ADCs per EQADC)

Reference voltage current consumption per EQADC

10

200

mA

μA

—

1. 128 sampling cycles (LST=128), differential conversion, pregain of x4

2. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time

that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.

3. At V_{RH_EQ}– V_{RL_EQ}= 5.12 V, one count = 1.25 mV without using pregain. Based on 12-bit conversion result; does not

account for AC and DC errors

4. INL and DNL are tested from V_RL+ 50 LSB to V_RH– 50 LSB.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Electrical characteristics

5. At V_{RH_EQ}– V_{RL_EQ}= 5.12 V, one LSB = 1.25 mV.

6. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater

than V_RHand $000 for values less than V_RL. Other channels are not affected by non-disruptive conditions.

7. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit

do not affect device reliability or cause permanent damage.

8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= –0.3 V, then use the larger of the calculated

values.

9. Condition applies to two adjacent pins at injection limits.

10. Performance expected with production silicon.

11. All channels have same 10 kΩ < Rs < 100 kΩ Channel under test has Rs = 10 kΩ, I_INJ=I_INJMAX,I_INJMIN

.

12. The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.

13. TUE, Gain, and Offset specifications do not apply to differential conversions.

14. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of ×1, ×2, or

×4. Settings are for differential input only. Tested at ×1 gain. Values for other settings are guaranteed as indicated.

15. Guaranteed 10-bit monotonicity.

16. At V_{RH_EQ}– V_{RL_EQ}= 5.12 V, one LSB = 1.25 mV.

3.8.2 Sigma-Delta ADC (SDADC)

The SDADC is a 16-bit Sigma-Delta analog-to-digital converter with a 333 Ksps

maximum output conversion rate.

NOTE

The voltage range is 4.5 V to 5.5 V for SDADC specifications,

except where noted otherwise.

Table 18. SDADC electrical specifications

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

V_IN

ADC input signal

—

0

—

V_{DDA_SD}

V

1

V_{IN_PK2PK}

Input range peak to

peak

Single ended

V_INM= V_{RL_SD}

Single ended

V_INM= 0.5*V_{RH_SD}

GAIN = 1

V_{RH_SD}/GAIN

2

V_{IN_PK2PK}= V_INP

V_INM

–

0.5*V_{RH_SD}

V_{RH_SD}/GAIN

, 3

Single ended

V_INM= 0.5*V_{RH_SD}

GAIN = 2,4,8,16

Differential

0 < V_IN< V_DDEx

—

f_{ADCD_M}

f_{ADCD_S}

—

SD clock frequency⁴

Conversion rate

4

14.4

—

16

MHz

Ksps

—

24

333

256

Oversampling ratio

Internal modulator

—

RESOLUTION SD register resolution⁵2's complement notation

16

bit

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Electrical characteristics

Table 18. SDADC electrical specifications (continued)

Value

Symbol

Parameter

ADC gain

Conditions

Unit

Min

Typ

Max

GAIN

Defined through

1

—

16

—

SDADC_MCR[PGAN]. Only integer

powers of 2 are valid gain values.

|δ_GAIN

|

Absolute value of the Before calibration (applies to gain

—

1.5

5

%

ADC gain error^{6, 7}

setting = 1)

After calibration

mV

ΔV_{RH_SD}< 5%, ΔV_{DDA_SD}< 10%

ΔT_J< 50 °C

After calibration

—

7.5

10

ΔV_{RH_SD}< 5%, ΔV_{DDA_SD}< 10%

ΔT_J< 100 °C

After calibration

ΔV_{RH_SD}< 5%, ΔV_{DDA_SD}< 10%

ΔT_J< 150 °C

V_OFFSET

Conversion offset^{6, 7}

Before calibration (applies to all gain

settings: 1, 2, 4, 8, 16)

—

10*(1+1/

gain)

20

5

mV

After calibration

ΔV_{DDA_SD}< 10%

ΔT_J< 50 °C

—

After calibration

ΔV_{DDA_SD}< 10%

ΔT_J< 100 °C

—

7.5

10

After calibration

ΔV_{DDA_SD}< 10%

ΔT_J< 150 °C

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Table 18. SDADC electrical specifications (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

SNR_DIFF150Signal to noise ratio in 4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

80

—

dB

differential mode, 150

V_{RH_SD}= V_{DDA_SD}

Ksps output rate

GAIN = 1

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

77

74

71

68

71

70

68

65

62

—

GAIN = 2

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 4

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 8

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 16

SNR_DIFF333Signal to noise ratio in 4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

dB

differential mode, 333

V_{RH_SD}= V_{DDA_SD}

Ksps output rate

GAIN = 1

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 2

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 4

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 8

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 16

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Electrical characteristics

Table 18. SDADC electrical specifications (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

SNR_SE150

Signal to noise ratio in 4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

72

—

dB

single ended mode,

V_{RH_SD}= V_{DDA_SD}

150 Ksps output rate

GAIN = 1

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 2

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 4

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 8

4.5 V < V_{DDA_SD}< 5.5 V^{8, 9}

V_{RH_SD}= V_{DDA_SD}

GAIN = 16

69

66

—

62

54

SINAD_DIFF150Signal to noise and

distortion ratio in

Gain = 1

72

dBFS

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

differential mode, 150

Ksps output rate

72

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

69

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

68.8

64.8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

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Table 18. SDADC electrical specifications (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

SINAD_DIFF333Signal to noise and

distortion ratio in

Gain = 1

66

—

dBFS

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

differential mode, 333

Ksps output rate

66

63

62

59

66

63

62

54

—

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 1

SINAD_SE150Signal to noise and

distortion ratio in

dBFS

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

single-ended mode,

150 Ksps output rate

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

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Electrical characteristics

Table 18. SDADC electrical specifications (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

THD_DIFF150Total harmonic

Gain = 1

65

—

dBFS

distortion in differential

mode, 150 Ksps

output rate

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

68

74

80

65

68

74

80

—

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 1

THD_DIFF333Total harmonic

dBFS

distortion in differential

mode, 333 Ksps

output rate

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

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Table 18. SDADC electrical specifications (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

THD_SE150

Total harmonic

Gain = 1

68

—

dBFS

distortion in single-

ended mode, 150

Ksps output rate

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 2

68

66

68

60

—

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 4

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 8

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

Gain = 16

4.5 V < V_{DDA_SD}< 5.5 V

V_{RH_SD}= V_{DDA_SD}

SFDR

Z_DIFF

Spurious free dynamic Any GAIN

range

dB

kΩ

Differential input

impedance^{10, 11}

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

1000

600

300

200

1400

1000

700

500

110

–12

1250

800

400

250

1800

1300

950

650

144

—

1500

1000

500

300

Z_CM

Common Mode input GAIN = 1

2200

1600

1150

800

kΩ

impedance^{11, 12}

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

800

R_BIAS

Bare bias resistance

—

180

kΩ

%

ΔV_INTCM

Common Mode input

reference voltage¹³

+12

V_BIAS

δV_BIAS

CMRR

Bias voltage

—

–2.5

20

V_{RH_SD}/2

—

+2.5

—

V

%

Bias voltage accuracy

—

Common mode

rejection ratio

dB

R_Caaf

Anti-aliasing filter

External series resistance

Filter capacitances

—

220

0.01

–1

—

20

—

kΩ

pF

f_PASSBAND

Pass band⁹

Pass band ripple¹⁴

0.333 * f_{ADCD_S}kHz

δ_RIPPLE

0.333 * f_{ADCD_S}

1

%

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Table 18. SDADC electrical specifications (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

40

45

50

55

60

—

Typ

—

Max

—

F_rolloff

Stop band attenuation [0.5 * f_{ADCD_S}, 1.0 * f_{ADCD_S}

]

dB

[1.0 * f_{ADCD_S}, 1.5 * f_{ADCD_S}

—

[1.5 * f_{ADCD_S}, 2.0 * f_{ADCD_S}

—

[2.0 * f_{ADCD_S}, 2.5 * f_{ADCD_S}

—

[2.5 * f_{ADCD_S}, f_{ADCD_M}/2]

—

δ_GROUP

Group delay

Within pass band: Tclk is f_{ADCD_M}/ 2

—

OSR = 24

235.5

275

Tclk

OSR = 28

OSR = 32

314.5

354

OSR = 36

OSR = 40

393.5

433

OSR = 44

OSR = 48

472.5

551.5

630.5

709.5

696

OSR = 56

OSR = 64

OSR = 72

OSR = 75

OSR = 80

788.5

867.5

946.5

1104.5

1262.5

1420.5

1578.5

1736.5

1894.5

2210.5

2526.5

+0.5/ f_{ADCD_S}

OSR = 88

OSR = 96

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

OSR = 256

Distortion within pass band

–0.5/

f_{ADCD_S}

—

μs

—

f_HIGH

High pass filter 3 dB

frequency

Enabled

—

10e–5*

fADCD_S

—

t_STARTUP

t_LATENCY

Startup time from

power down state

—

100

Latency between input HPF = ON

data and converted

δ_GROUP+

f_{ADCD_S}

data when input mux

HPF = OFF

δ_GROUP

does not change¹⁵

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Table 18. SDADC electrical specifications (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

t_SETTLING

Settling time after mux Analog inputs are muxed

—

2*δ_GROUP

+

—

change

3*f_{ADCD_S}

HPF = ON

HPF = OFF

—

2*δ_GROUP+

2*f_{ADCD_S}

t_ODRECOVERYOverdrive recovery

time

After input comes within range from

saturation

2*δ_GROUP

+

—

f_{ADCD_S}

HPF = ON

HPF = OFF

GAIN = 1, 2, 4, 8

GAIN = 16

—

2*δ_GROUP

75*GAIN

600

C_{S_D}

SDADC sampling

capacitance after

sampling switch¹⁶

fF

I_BIAS

Bias consumption

At least one SDADC enabled

Per SDADC enabled

—

3.5

mA

I_{ADV_D}

SDADC supply

consumption

4.325

I_{ADR_D}

SDADC reference

Per SDADC enabled

—

20

μA

current consumption

1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the

signal will only be “clipped.”

2. VINP is the input voltage applied to the positive terminal of the SDADC

3. VINM is the input voltage applied to the negative terminal of the SDADC

4. Sampling is generated internally f_SAMPLING= f_{ADCD_M}/2

5. For Gain = 16, SDADC resolution is 15 bit.

6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*V_{RH_SD}for differential

mode and single ended mode with negative input = 0.5*V_{RH_SD}. Offset Calibration should be done with respect to 0 for

single ended mode with negative input = 0. Both Offset and Gain Calibration is guaranteed for +/–5% variation of V_{RH_SD}

+/–10% variation of V_{DDA_SD}, +/–50 C temperature variation.

,

7. Offset and gain error due to temperature drift can occur in either direction (+/–) for each of the SDADCs on the device.

8. SDADC is functional in the range 3.6 V < V_{DDA_SD}< 4.0 V: SNR parameter degrades by 3 dB. SDADC is functional in the

range 3.0 V < V_{RH_SD}< 4.0 V: SNR parameter degrades by 9 dB.

9. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the

frequency range of f_{ADCD_M}– f_{ADCD_S}to f_{ADCD_M}+ f_{ADCD_S}, where f_{ADCD_M}is the input sampling frequency and f_{ADCD_S}is

the output sample frequency. A proper external input filter should be used to remove any interfering signals in this

frequency range.

10. Input impedance in differential mode Z_IN= Z_DIFF

11. Input impedance given at f_{ADCD_M}= 16 MHz. Impedance is inversely proportional to SDADC clock frequency. Z_DIFF

(f_{ADCD_M}) = (16 MHz / f_{ADCD_M}) * Z_DIFF, Z_CM(f_{ADCD_M}) = (16 MHz / f_{ADCD_M}) * Z_CM

12. Input impedance in single-ended mode Z_IN= (2 * Z_DIFF* Z_CM) / (Z_DIFF+ Z_CM

.

)

13. V_INTCMis the Common Mode input reference voltage for the SDADC. It has a nominal value of (V_{RH_SD}- V_{RL_SD}) / 2.

14. The 1% passband ripple specification is equivalent to 20 * log₁₀(0.99) = 0.087 dB.

15. Propagation of the information from the pin to the register CDR[CDATA] and the flags SFR[DFEF] and SFR[DFFF] is

given by the different modules that must be crossed: delta/sigma filters, high pass filter, FIFO module, and clock domain

synchronizers. The time elapsed between data availability at the pin and internal SDADC module registers is given by the

following formula, where f_{ADCD_S}is the frequency of the sampling clock, f_{ADCD_M}is the frequency of the modulator, and

f_{FM_PER_CLK}is the frequency of the peripheral bridge clock feeds to the SDADC module:

REGISTER LATENCY = t_LATENCY+ 0.5/f_{ADCD_S}+ 2 (~+1)/f_{ADCD_M}+ 2(~+1)f_{FM_PER_CLK}

The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to

resynchronization of the signal during clock domain crossing.

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Electrical characteristics

Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received

from the SDADC module.

16. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

3.9 Temperature Sensor

The following table describes the Temperature Sensor electrical characteristics.

Table 19. Temperature Sensor electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

–40

—

Typ

—

Max

150

—

Temperature monitoring range

Sensitivity

—

°C

mV/°C

°C

T_SENS

T_ACC

5.18

—

Accuracy

–40°C < T_J< 150°C

—

–5

5

I_{TEMP_SENS}V_{DDA_EQA}power supply current, per Temp

Sensor

—

700

μA

3.10 LVDS Fast Asynchronous Serial Transmission (LFAST) pad

electrical characteristics

The LFAST pad electrical characteristics apply to the SIPI interface on the chip. The

same LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces,

with different characteristics given in the following tables.

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3.10.1 LFAST interface timing diagrams

Signal excursions above this level NOT allowed

Max. common mode input at RX

1743 mV

1600 mV

|Vo D|

Max Differential Voltage =

285 mV p-p (LFAST)

400 mV p-p (MSC/DSPI)

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)

0.50 * T (MSC/DSPI)

V_{OS =}1.2 V +/- 10%

TX common mode

“No-Go” Area

|Vo D|

Min Differential Voltage =

100 mV p-p (LFAST)

150 mV p-p (MSC/DSPI)

V_ICOM

|PER

EYE

|PER

EYE

Data Bit Period

T = 1 /F_DATA

Min. common mode input at RX

150 mV

0 V

Signal excursions below this level NOT allowed

Figure 8. LFAST and MSC/DSPI LVDS timing definition

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Electrical characteristics

H

L

lfast_pwr_down

t_{PD2NM_TX}

Differential

Data Lines

TX

pad_p/pad_n

Data Valid

Figure 9. Power-down exit time

VIH

VIL

Differential

Data Lines

TX

90%

10%

pad_p/pad_n

tTR

Figure 10. Rise/fall time

3.10.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Table 20. LVDS pad startup and receiver electrical characteristics¹

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

STARTUP²,³

t_{STRT_BIAS}

Bias current reference startup time⁴

—

0.5

4

μs

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Electrical characteristics

Table 20. LVDS pad startup and receiver electrical characteristics¹(continued)

Value

Typ

0.4

Symbol

Parameter

Conditions

Unit

Min

Max

t_{PD2NM_TX}

Transmitter startup time (power down to —

Normal mode)⁵

—

2.75

μs

t_{SM2NM_TX}

t_{PD2NM_RX}

t_{PD2SM_RX}

I_{LVDS_BIAS}

Transmitter startup time (Sleep mode to Not applicable to the MSC/DSPI

—

0.2

20

—

0.5

40

μs

ns

Normal mode)⁶

LVDS pad

Receiver startup time (power down to

Normal mode)⁷

—

Receiver startup time (power down to

Sleep mode)⁸

Not applicable to the MSC/DSPI

LVDS pad

50

ns

LVDS bias current consumption

Tx or Rx enabled

0.95

mA

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic

impedance

Transmission line differential impedance —

RECEIVER

Z₀

—

47.5

95

50

52.5

105

Ω

Z_DIFF

100

V_ICOM

|ΔVI|

V_HYS

R_IN

Common mode voltage

Differential input voltage

Input hysteresis

—

0.15⁹

100

25

—

1.6¹⁰

—

V

—

mV

Ω

—

Terminating resistance

Differential input capacitance¹¹

V_DDEH= 3.0 V to 5.5 V

80

125

3.5

—

150

6.0

0.5

C_IN

—

pF

mA

I_{LVDS_RX}

Receiver DC current consumption

Enabled

—

1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST and the MSC/DSPI

LVDS pad except where noted in the conditions.

2. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the

LVDS control registers (LCR) of the LFAST and High-Speed Debug modules.

3. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter

electrical characteristic tables.

4. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being

enabled.

5. Total transmitter startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_TX}+ 2 peripheral bridge clock

periods.

6. Total transmitter startup time from sleep mode to normal mode is t_{SM2NM_TX}+ 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

7. Total receiver startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_RX}+ 2 peripheral bridge clock periods.

8. Total receiver startup time from power down to sleep mode is t_{PD2SM_RX}+ 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

9. Absolute min = 0.15 V – (285 mV/2) = 0 V

10. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

11. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare

die devices, subtract the package value given in Figure 11.

Table 21. LFAST transmitter electrical characteristics¹

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

f_DATA

Data rate

—

240

Mbps

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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37

Electrical characteristics

Table 21. LFAST transmitter electrical characteristics¹(continued)

Value

Typ

—

Symbol

Parameter

Conditions

Unit

Min

1.08

110

0.26

—

Max

1.32

285

1.5

V_OS

Common mode voltage

—

V

|V_OD

t_TR

|

Differential output voltage swing (terminated)²,³

Rise/fall time (10% – 90% of swing)²,³

External lumped differential load capacitance²

200

—

mV

ns

C_L

V_DDE= 4.5 V

V_DDE= 3.0 V

Enabled

—

12.0

8.5

pF

—

I_{LVDS_TX}Transmitter DC current consumption

—

3.2

mA

1. The LFAST pad electrical characteristics are based on worst-case internal capacitance values shown in Figure 11.

2. Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown in

Figure 11.

3. Valid for maximum external load CL.

Table 22. MSC/DSPI LVDS transmitter electrical characteristics¹

Value

Symbol

Parameter

Conditions

Unit

Min

—

Typ

—

Max

80

f_DATA

V_OS

Data rate

—

Mbps

V

Common mode voltage

1.08

150

0.8

—

1.32

400

4.0

50

|V_OD

t_TR

|

Differential output voltage swing (terminated)²,³

Rise/Fall time (10%–90% of swing)²,³

External lumped differential load capacitance²

200

—

mV

ns

C_L

V_DDE= 4.5 V

V_DDE= 3.0 V

Enabled

—

pF

—

39

I_{LVDS_TX}Transmitter DC current consumption

—

4.0

mA

1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst-case internal

capacitance values given in Figure 11.

2. Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown in

Figure 11.

3. Valid for maximum external load C_L.

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Electrical characteristics

bond pad

GPIO Driver

CL

1pF

2.5pF

100Ω

terminator

LVDS Driver

bond pad

GPIO Driver

CL

1pF

2.5pF

Die

Package

PCB

Figure 11. LVDS pad external load diagram

3.10.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

Table 23. LFAST PLL electrical characteristics¹

Value

Symbol

Parameter

Conditions

Unit

Min

10

–1

45

—

Nominal

Max

26

f_{RF_REF}PLL reference clock frequency

ERR_REFPLL reference clock frequency error

DC_REFPLL reference clock duty cycle

—

MHz

%

1

—

55

%

PN

Integrated phase noise (single side band) f_{RF_REF}= 20 MHz

—

–58

–64

—

dBc

f_{RF_REF}= 10 MHz

—

480²

f_VCO

PLL VCO frequency

PLL phase lock³

—

MHz

μs

t_LOCK

—

40

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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39

Electrical characteristics

Table 23. LFAST PLL electrical characteristics¹(continued)

Value

Nominal

—

Symbol

Parameter

Conditions

Unit

Min

—

Max

300

500

400

ΔPER_REFInput reference clock jitter (peak to peak) Single period, f_{RF_REF}= 10 MHz

ps

Long term, f_{RF_REF}= 10 MHz

–500

—

ΔPER_EYEOutput Eye Jitter (peak to peak)⁴

—

ps

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. The 480 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 13 MHz or 26 MHz reference, the

VCO frequency is 468 MHz.

3. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device.

4. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See Figure 11.

3.11 Power management: PMC, POR/LVD, power sequencing

3.11.1 Power management electrical characteristics

The power management module monitors the different power supplies. It also generates

the internal supplies that are required for correct device functionality. The power

management is supplied by the V_DDPMCsupply.

3.11.1.1 LDO mode recommended power transistors

Only specific orderable part numbers of MPC5777C support LDO regulation mode. See

Ordering information for MPC5777C parts that support this regulation mode.

The following NPN transistors are recommended for use with the on-chip LDO voltage

regulator controller: ON Semiconductor™ NJD2873. The collector of the external

transistor is preferably connected to the same voltage supply source as the output stage of

the regulator.

The following table describes the characteristics of the power transistors.

Table 24. Recommended operating characteristics

Symbol

h_FE

Parameter

Value

60-550

1.60

2.0

Unit

—

W

DC current gain (Beta)

P_D

Absolute minimum power dissipation

Maximum DC collector current

Collector to emitter saturation voltage

Base to emitter voltage

I_CMaxDC

VCE_SAT

V_BE

A

300

mV

V

0.95

2.5

V_c

Minimum voltage at transistor collector

V

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Electrical characteristics

The following table shows the recommended components to be used in LDO regulation

mode.

Table 25. Recommended operating characteristics

Part name Part type

Q1 NPN BJT h_FE= 400

Capacitor 4.7 µF - 20 V

Nominal

Description

NJD2873: ON Semiconductor LDO voltage regulator controller (VRC)

Ceramic capacitor, total ESR < 70 mΩ

CI

CE

CV

CD

Capacitor 0.047–0.049 µF - 7 V Ceramic—one capacitor for each V_DDpin

Capacitor 22 µF - 20 V

Ceramic V_DDPMC(optional 0.1 µF)

Ceramic supply decoupling capacitor, ESR < 50 mΩ (as close as possible

to NPN collector)

CB

R

Capacitor 0.1 µF - 7 V

Ceramic V_DDPWR

Resistor

Application specific

Optional; reduces thermal loading on the NPN with high V_DDPMClevels

The following diagram shows the LDO configuration connection.

VDDPMC

REGSEL

CD

R

CV

VSSPMC (clean ground)

VDDPWR

Q1

REGCTL

VSSPWR

CB

VDD

VSS

CI

CE

Figure 12. VRC 1.2 V LDO configuration

3.11.1.2 SMPS mode recommended external components and

characteristics

The following table shows the recommended components to be used in SMPS regulation

mode.

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41

Electrical characteristics

Part name Part type

Table 26. Recommended operating characteristics

Nominal

3 A - 20 V

Description

Q1

p-MOS

SQ2301ES / FDC642P or equivalent: low threshold p-MOS, Vth < 2.0 V, Rdson

@ 4.5 V < 100 mΩ, Cg < 5 nF

D1

L

Schottky

Inductor

2 A - 20 V

SS8P3L or equivalent: Vishay™ low Vf Schottky diode

Buck shielded coil low ESR

3-4 μH - 1.5 A

CI

Capacitor 22 μF - 20 V

Capacitor 0.1 μF - 7 V

Capacitor 22 μF - 20 V

Ceramic capacitor, total ESR < 70 mΩ

CE

CV

CD

Ceramic—one capacitor for each V_DDpin

Ceramic V_DDPMC(optional 0.1 μF capacitor in parallel)

Ceramic supply decoupling capacitor, ESR < 50 mΩ (as close as possible to

the p-MOS source)

R

Resistor

2.0-4.7 kΩ

Pullup for power p-MOS gate

CB

Capacitor 22 μF - 20 V

Ceramic, connect 100 nF capacitor in parallel (as close as possible to package

to reduce current loop from V_DDPWRto V_SSPWR

)

The following diagram shows the SMPS configuration connection.

VDDPMC

REGSEL

CD

CV

VSSPMC (clean ground)

VDDPWR

R

REGCTL

VSSPWR

Q1

CE

CB

D1

L

VDD

VSS

CI

Figure 13. SMPS configuration

NOTE

The REGSEL pin is tied to V_DDPMCto select SMPS. If

REGSEL is 0, the chip boots with the linear regulator.

See Power sequencing requirements for details about V_DDPMC

and V_DDPWR

.

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Electrical characteristics

The SMPS regulator characteristics appear in the following table.

Table 27. SMPS electrical characteristics

Value

Unit

Symbol

Parameter

Conditions

Min

825

0.01

—

Typ

1000

0.025

70

Max

1220

0.05

—

SMPS_CLOCK

SMPS_SLOPE

SMPS_EFF

SMPS oscillator frequency

SMPS soft-start ramp slope

SMPS typical efficiency

Trimmed

kHz

V/μs

%

—

3.11.2 Power management integration

To ensure correct functionality of the device, use the following recommended integration

scheme for LDO mode.

C _{HV_PMC}

C _{HV_FLA}

VDDPWR

VDD

1

C _SMPSPWR

n x C _LV

VSSPWR

VSS

MPC5777C

REF BY

VDDE(H)x

VSS

PC

C _REFEQ

2

n x C _{HV_IO}

VSS

1

2

One capacitance near each VDD pin

One capacitance near each VDDE(H)x pin

Figure 14. Recommended supply pin circuits

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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43

Electrical characteristics

The following table describes the supply stability capacitances required on the device for

proper operation.

Table 28. Device power supply integration

Value¹

Symbol

Parameter

Conditions

Unit

Min Typ Max

C_LV

Minimum V_DDexternal bulk capacitance^{2, 3}

LDO mode

4.7

22

—

μF

SMPS mode

—

C_SMPSPWR

C_{HV_PMC}

Minimum SMPS driver supply capacitance

Minimum V_DDPMCexternal bulk capacitance^{4, 5}

—

LDO mode

SMPS mode

—

4.7⁶

C_{HV_IO}

Minimum V_DDEx/V_DDEHxexternal capacitance²

Minimum V_{DD_FLA}external capacitance⁷

—

C_{HV_FLA}

1.0 2.0

C_{HV_ADC_EQA/B}Minimum V_{DDA_EQA/B}external capacitance⁸

C_REFEQ

Minimum REF_BYPCA/Bexternal capacitance⁹

C_{HV_ADC_SD}Minimum V_{DDA_SD}external capacitance¹⁰

0.01

—

1.0 2.2

1. See Figure 14 for capacitor integration.

2. Recommended X7R or X5R ceramic low ESR capacitors, 15% variation over process, voltage, temperature, and aging.

3. Each V_DDpin requires both a 47 nF and a 0.01 μF capacitor for high-frequency bypass and EMC requirements.

4. Recommended X7R or X5R ceramic low ESR capacitors, 15% variation over process, voltage, temperature, and aging.

5. Each V_DDPMCpin requires both a 47 nF and a 0.01 μF capacitor for high-frequency bypass and EMC requirements.

6. The actual capacitance should be selected based on the I/O usage in order to keep the supply voltage within its operating

range.

7. The recommended flash regulator composition capacitor is 2.0 μF typical X7R or X5R, with -50% and +35% as min and

max. This puts the min cap at 0.75 μF.

8. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between V_{DDA_EQA/B}and

V_{SSA_EQ}

.

9. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between REF_BYPCA/Band V_SS

10. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 μF between V_{DDA_SD}and

.

V_{SSA_SD}

.

3.11.3 Device voltage monitoring

The LVD/HVDs for the device and their levels are given in the following table. Voltage

monitoring threshold definition is provided in the following figure.

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Electrical characteristics

V DD_xxx

V HVD(rise)

V HVD(fall)

V LVD(rise)

V LVD(fall)

t VDASSERT

t VDRELEASE

HVD TRIGGER

(INTERNAL)

t VDRELEASE

t VDASSERT

LVD TRIGGER

(INTERNAL)

Figure 15. Voltage monitor threshold definition

Table 29. Voltage monitor electrical characteristics^{1, 2}

Configuration

Value

Unit

Symbol

Parameter

Conditions

Trim Mask Pow.

Min

Typ Max

bits Opt.

Up

No Enab. 960 1010 1060 mV

940 990 1040

POR098_c³

LV internal supply power Rising voltage (powerup)

N/A

on reset

Falling voltage (power

down)

LVD_core_hot LV internal⁴supply low

voltage monitoring

Rising voltage (untrimmed)

Falling voltage (untrimmed)

Rising voltage (trimmed)

Falling voltage (trimmed)

Rising voltage

4bit

No Enab. 1100 1140 1183 mV

1080 1120 1163

1142 1165 1183

1122 1145 1163

LVD_core_cold LV external⁵supply low

voltage monitoring

4bit

Yes Disab. 1165 1180 1198 mV

1136 1160 1178

Falling voltage

HVD_core

LV internal cold supply

high voltage monitoring

Rising voltage

Yes Disab. 1338 1365 1385 mV

1318 1345 1365

Falling voltage

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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45

Electrical characteristics

Table 29. Voltage monitor electrical characteristics^{1, 2}(continued)

Configuration

Value

Symbol

Parameter

Conditions

Unit

Trim Mask Pow.

bits Opt. Up

Min

Typ Max

POR_HV

HV V_DDPMCsupply power Rising voltage (powerup)

N/A

No Enab. 2444 2600 2756 mV

2424 2580 2736

on reset threshold

Falling voltage (power

down)

LVD_HV

HV internal V_DDPMCsupply Rising voltage (untrimmed)

4bit

No Enab. 2935 3023 3112 mV

2922 3010 3099

low voltage monitoring

Falling voltage (untrimmed)

Rising voltage (trimmed)

Falling voltage (trimmed)

2946 3010 3066

2934 2998 3044

HVD_HV

HV internal V_DDPMCsupply Rising voltage

4bit

Yes Disab. 5696 5860 5968 mV

5666 5830 5938

high voltage monitoring

Falling voltage

LVD_FLASH FLASH supply low voltage Rising voltage (untrimmed)

No Enab. 2935 3023 3112 mV

2922 3010 3099

monitoring⁶

Falling voltage (untrimmed)

Rising voltage (trimmed)

Falling voltage (trimmed)

2956 3010 3053

2944 2998 3041

HVD_FLASH FLASH supply high

voltage monitoring⁶

Rising voltage

4bit

Yes Disab. 3456 3530 3584 mV

3426 3500 3554

Falling voltage

LVD_IO

Main I/O V_DDEH1supply

low voltage monitoring

Rising voltage (untrimmed)

Falling voltage (untrimmed)

Rising voltage (trimmed)

Falling voltage (trimmed)

No Enab. 3250 3350 3488 mV

3220 3320 3458

3347 3420 3468

3317 3390 3438

t_VDASSERT

Voltage detector threshold —

crossing assertion

—

0.1

—

2.0

μs

t_VDRELEASE

Voltage detector threshold —

crossing de-assertion

5

—

20

1. LVD is released after t_VDRELEASEtemporization when upper threshold is crossed; LVD is asserted t_VDASSERTafter detection

when lower threshold is crossed.

2. HVD is released after t_VDRELEASEtemporization when lower threshold is crossed; HVD is asserted t_VDASSERTafter

detection when upper threshold is crossed.

3. POR098_c threshold is an untrimmed value, before the completion of the power-up sequence. All other LVD/HVD

thresholds are provided after trimming.

4. LV internal supply levels are measured on device internal supply grid after internal voltage drop.

5. LV external supply levels are measured on the die side of the package bond wire after package voltage drop.

6. V_DDFLArange is guaranteed when internal flash memory regulator is used.

3.11.4 Power sequencing requirements

Requirements for power sequencing include the following.

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Electrical characteristics

NOTE

In these descriptions, star route layout means a track split as

close as possible to the power supply source. Each of the split

tracks is routed individually to the intended end connection.

1. For both LDO mode and SMPS mode, V_DDPMCand V_DDPWRmust be connected

together (shorted) to ensure aligned voltage ramping up/down. In addition:

• For SMPS mode, a star route layout of the power track is required to minimize

mutual noise. If SMPS mode is not used, the star route layout is not required.

V_DDPWRis the supply pin for the SMPS circuitry.

• For 3.3 V operation, V_DDFLAmust also be star routed and shorted to V_DDPWR

and V_DDPMC. This triple connection is required because 3.3 V does not guarantee

correct functionality of the internal V_DDFLAregulator. Consequently, V_DDFLAis

supplied externally.

2. V_{DDA_MISC}: IRC operation is required to provide the clock for chip startup.

• The V_DDPMC, V_DD, and V_DDEH1(reset pin pad segment) supplies are monitored.

They hold IRC until all of them reach operational voltage. In other words,

V_{DDA_MISC}must reach its specified minimum operating voltage before or at the

same time that all of these monitored voltages reach their respective specified

minimum voltages.

• An alternative is to connect the same supply voltage to both V_DDEH1and

V_{DDA_MISC}. This alternative approach requires a star route layout to minimize

mutual noise.

3. Multiple V_DDExsupplies can be powered up in any order.

During any time when V_DDis powered up but V_DDExis not yet powered up: pad

outputs are unpowered.

During any time when V_DDExis powered up before all other supplies: all pad output

buffers are tristated.

4. Ramp up V_{DDA_EQ}before V_DD. Otherwise, a reset might occur.

5. When the device is powering down while using the internal SMPS regulator,

V_DDPMCand V_DDPWRsupplies must ramp down through the voltage range from 2.5

V to 1.5 V in less than 1 second. Slower ramp-down times might result in reduced

lifetime reliability of the device.

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47

Electrical characteristics

3.12 Flash memory specifications

3.12.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this

section are defined for a single embedded flash memory within

an SoC, and represent average currents for given supplies and

operations.

Table 30 shows the estimated Program/Erase times.

Table 30. Flash memory program and erase specifications

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C ≤150°C ≤150°C cycles cycles

t_dwpgm

Doubleword (64 bits) program time 43

100 150 55 500

μs

t_ppgm

Page (256 bits) program time

73

200

800

300

108

396

500

μs

t_qppgm

Quad-page (1024 bits) program

time

268

1,200

2,000

t_16kers

16 KB Block erase time

16 KB Block program time

32 KB Block erase time

32 KB Block program time

64 KB Block erase time

64 KB Block program time

256 KB Block erase time

256 KB Block program time

168

34

290

45

320

50

250

40

1,000

1,200

1,600

4,000

ms

t_16kpgm

t_32kers

t_32kpgm

t_64kers

217

69

360

100

490

180

1,520

720

390

110

590

210

2,030

880

310

90

315

138

884

552

420

170

1,080

650

t_64kpgm

t_256kers

t_256kpgm

—

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ T_J≤ 150°C, full spec voltage.

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Electrical characteristics

3.12.2 Flash memory Array Integrity and Margin Read specifications

Table 31. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max¹

Units

2

t_ai16kseq

Array Integrity time for sequential sequence on 16 KB block.

—

512 x

Tperiod x

Nread

—

t_ai32kseq

Array Integrity time for sequential sequence on 32 KB block.

Array Integrity time for sequential sequence on 64 KB block.

Array Integrity time for sequential sequence on 256 KB block.

—

1024 x

Tperiod x

Nread

t_ai64kseq

2048 x

Tperiod x

Nread

8192 x

Tperiod x

Nread

tai256kseq

t_mr16kseq

t_mr32kseq

t_mr64kseq

t_mr256kseq

Margin Read time for sequential sequence on 16 KB block.

Margin Read time for sequential sequence on 32 KB block.

Margin Read time for sequential sequence on 64 KB block.

Margin Read time for sequential sequence on 256 KB block.

73.81

128.43

237.65

893.01

—

110.7

192.6

μs

356.5

1,339.5

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and

Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires

6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the

address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

3.12.3 Flash memory module life specifications

Table 32. Flash memory module life specifications

Symbol

Characteristic

Conditions

Min

Typical

Units

P/E

Array P/E

cycles

Number of program/erase cycles per block

for 16 KB, 32 KB and 64 KB blocks.¹

—

250,000

—

cycles

Number of program/erase cycles per block

for 256 KB blocks.²

1,000

250,000

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 - 1,000 P/E 50

cycles.

—

Years

Blocks with 100,000 P/E

cycles.

20

Blocks with 250,000 P/E

cycles.

10

1. Program and erase supported across standard temperature specs.

2. Program and erase supported across standard temperature specs.

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Electrical characteristics

3.12.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the

following figure. The spec window represents qualified limits. The extrapolated dotted

line demonstrates technology capability, however is beyond the qualification limits.

3.12.5 Flash memory AC timing specifications

Table 33. Flash memory AC timing specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

to a 1.

—

9.4

11.5

μs

plus four

system

clock

plus four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

—

16

20.8

μs

ns

plus four

system

clock

plus four

system

clock

periods

t_res

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

100

Table continues on the next page...

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Electrical characteristics

Table 33. Flash memory AC timing specifications (continued)

Symbol

Characteristic

Min

Typical

Max

Units

t_done

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

—

5

ns

t_dones

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

—

16

20.8

μs

plus four

system

clock

plus four

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16

—

45

μs

plus seven

system

clock

plus seven

system

clock

periods.

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

—

20.42

μs

plus four

system

clock

plus four

system

clock

periods

3.12.6 Flash memory read wait-state and address-pipeline control

settings

The following table describes the recommended settings of the Flash Memory

Controller's PFCR1[RWSC] and PFCR1[APC] fields at various flash memory operating

frequencies, based on specified intrinsic flash memory access times of the C55FMC array

at 150°C.

Table 34. Flash memory read wait-state and address-pipeline control

combinations

Flash memory read latency on

mini-cache miss (# of f_PLATF

clock periods)

Flash memory read latency on

mini-cache hit (# of f_PLATFclock

periods)

Flash memory frequency

RWSC

APC

0 MHz < f_PLATF≤ 33 MHz

33 MHz < f_PLATF≤ 100 MHz

0

2

0

1

3

5

1

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Table 34. Flash memory read wait-state and address-pipeline control combinations

(continued)

Flash memory read latency on

mini-cache miss (# of f_PLATF

clock periods)

Flash memory read latency on

mini-cache hit (# of f_PLATFclock

periods)

Flash memory frequency

RWSC

APC

100 MHz < f_PLATF≤ 150 MHz

3

1

6

1

3.13 AC timing

3.13.1 Generic timing diagrams

The generic timing diagrams in Figure 16 and Figure 17 apply to all I/O pins with pad

types SR and FC. See the associated MPC5777C Microsoft Excel® file in the Reference

Manual for the pad type for each pin.

D_CLKOUT

V_{DDE /}

2

A

B

I/O Outputs

V_{DDEn / 2}

V_{DDEHn / 2}

B – Minimum Output Hold Time

A – Maximum Output Delay Time

Figure 16. Generic output delay/hold timing

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D_CLKOUT

V_{DDE /}

2

B

A

I/O Inputs

V_{DDEn / 2}

V_{DDEHn / 2}

B – Minimum Input Hold Time

A – Maximum Input Delay Time

Figure 17. Generic input setup/hold timing

3.13.2 Reset and configuration pin timing

Table 35. Reset and configuration pin timing¹

Spec Characteristic

Symbol

t_RPW

Min

10

2

Max

—

Unit

2

1

2

3

4

RESET Pulse Width

t_cyc

2

RESET Glitch Detect Pulse Width

t_GPW

—

t_cyc

2

PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid

PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid

t_RCSU

t_RCH

10

0

—

t_cyc

2

—

t_cyc

1. Reset timing specified at: V_DDEH= 3.0 V to 5.25 V, V_DD= 1.08 V to 1.32 V, TA = TL to TH.

2. For further information on t_cyc, see Table 3.

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2

RESET

1

RSTOUT

3

PLLCFG

BOOTCFG

WKPCFG

4

Figure 18. Reset and configuration pin timing

3.13.3 IEEE 1149.1 interface timing

Table 36. JTAG pin AC electrical characteristics¹

Value

#

Symbol

Characteristic

Unit

Min

100

40

—

5

Max

—

1

2

t_JCYC

t_JDC

TCK cycle time

ns

%

TCK clock pulse width

60

3

t_TCKRISE

t_TMSS, t_TDIS

t_TMSH, t_TDIH

t_TDOV

TCK rise and fall times (40%–70%)

TMS, TDI data setup time

3

ns

4

—

5

TMS, TDI data hold time

5

—

16²

6

TCK low to TDO data valid

—

0

7

t_TDOI

TCK low to TDO data invalid

—

8

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

TCK low to TDO high impedance

JCOMP assertion time

—

100

40

—

15

9

—

10

11

12

13

14

15

JCOMP setup time to TCK low

—

TCK falling edge to output valid

TCK falling edge to output valid out of high impedance

TCK falling edge to output high impedance

Boundary scan input valid to TCK rising edge

TCK rising edge to boundary scan input invalid

600³

600

—

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

—

1. These specifications apply to JTAG boundary scan only. See Table 37 for functional specifications.

2. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

3. Applies to all pins, limited by pad slew rate. Refer to I/O delay and transition specification and add 20 ns for JTAG delay.

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TCK

2

3

2

1

Figure 19. JTAG test clock input timing

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 20. JTAG test access port timing

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TCK

10

JCOMP

9

Figure 21. JTAG JCOMP timing

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TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 22. JTAG boundary scan timing

3.13.4 Nexus timing

Table 37. Nexus debug port timing¹

Spec Characteristic

Symbol

t_MCYC

Min

2

Max

8

Unit

t_CYC

1

2

3

4

5

6

7

8

MCKO Cycle Time

MCKO Duty Cycle

t_MDC

40

60

0.2

—

%

MCKO Low to MDO Data Valid²

MCKO Low to MSEO Data Valid²

MCKO Low to EVTO Data Valid²

EVTI Pulse Width

t_MDOV

–0.1

4.0

1

t_MCYC

t_TCYC

t_MCYC

t_CYC

t_MSEOV

t_EVTOV

t_EVTIPW

t_EVTOPW

t_TCYC

EVTO Pulse Width

—

TCK Cycle Time

2³

—

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Table 37. Nexus debug port timing¹(continued)

Spec Characteristic

Symbol

Min

Max

Unit

8

Absolute minimum TCK cycle time⁴(TDO sampled on

posedge of TCK)

t_TCYC

40⁵

—

ns

Absolute minimum TCK cycle time⁴(TDO sampled on

negedge of TCK)

20⁵

—

9

TCK Duty Cycle

t_TDC

t_NTDIS, t_NTMSS

T_NTDIH, t_NTMSH

t_NTDOV

40

8

60

—

18

—

%

ns

—

ns

10

11

12

13

14

TDI, TMS Data Setup Time⁶

TDI, TMS Data Hold Time⁶

TCK Low to TDO Data Valid⁶

RDY Valid to MCKO⁷

5

0

—

1

TDO hold time after TCLK low⁶

t_NTDOH

1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing

specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30

pF with DSC = 0b10.

2. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the absolute

minimum TCK period specification.

4. This value is TDO propagation time plus 2 ns setup time to sampling edge.

5. This may require a maximum clock speed that is less than the maximum functional capability of the design depending on

the actual system frequency being used.

6. Applies to TMS pin timing for the bit frame when using the 1149.7 advanced protocol.

7. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

1

2

MCKO

3

4

5

MDO

Output Data Valid

7

MSEO

EVTO

6

EVTI

Figure 23. Nexus timings

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8

9

TCK

10

11

TMS, TDI

14

12

TDO

Figure 24. Nexus TCK, TDI, TMS, TDO Timing

3.13.5 External Bus Interface (EBI) timing

Table 38. Bus operation timing¹

66 MHz (Ext. bus freq.)^{2, 3}

Spec

Characteristic

D_CLKOUT Period

Symbol

Unit Notes

ns Signals are measured at 50%

Min

Max

1

t_C

15.2

—

V_DDE

.

2

3

4

D_CLKOUT Duty Cycle

D_CLKOUT Rise Time

D_CLKOUT Fall Time

t_CDC

t_CRT

t_CFT

45%

—

55%

t_C

ns

—

4

—

4

—

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Table 38. Bus operation timing¹(continued)

66 MHz (Ext. bus freq.)^{2, 3}

Spec

Characteristic

Symbol

Unit Notes

Min

Max

5

D_CLKOUT Posedge to Output

Signal Invalid or High Z (Hold

Time)

t_COH

1.0/1.5

—

ns Hold time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 1.0 ns

EBTS = 1: 1.5 ns

D_ADD[9:30]

D_BDIP

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

6

D_CLKOUT Posedge to Output

Signal Valid (Output Delay)

t_COV

—

8.5/9.0

ns Output valid time selectable via

SIU_ECCR[EBTS] bit:

D_ADD[9:30]

D_BDIP

EBTS = 0: 8.5 ns

EBTS = 1: 9.0 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

11.5

—

8.5/9.0

Output valid time selectable via

SIU_ECCR[EBTS] bit:

D_RD_WR

D_TA

EBTS = 0: 8.5 ns

EBTS = 1: 9.0 ns

D_TS

D_WE[0:3]/D_BE[0:3]

7

8

9

Input Signal Valid to D_CLKOUT

Posedge (Setup Time)

t_CIS

7.5

1.0

6.5

—

ns

—

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

D_CLKOUT Posedge to Input

Signal Invalid (Hold Time)

t_CIH

ns

—

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

D_ALE Pulse Width

t_APW

ns The timing is for Asynchronous

external memory system.

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Table 38. Bus operation timing¹(continued)

66 MHz (Ext. bus freq.)^{2, 3}

Spec

Characteristic

Symbol

Unit Notes

Min

Max

10

D_ALE Negated to Address

Invalid

t_AAI

2.0/1.0 ⁵

—

ns The timing is for Asynchronous

external memory system.

ALE is measured at 50% of VDDE.

1. EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30 pF with SIU_PCR[DSC] =

11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/ALE.

2. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation

(FM).

3. Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus

frequency. The maximum external bus frequency is 66 MHz.

4. Refer to D_CLKOUT pad timing in Table 10.

5. ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0°C. 2.0ns spec applies to

temperatures > 0°C. This spec has no dependency on the SIU_ECCR[EBTS] bit.

V_{OH_F}

VDDE / 2

V_{OL_F}

D_CLKOUT

2

3

2

4

1

Figure 25. D_CLKOUT timing

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V_{DDE /}

2

D_CLKOUT

6

5

Output

Bus

V_{DDE /}

2

6

5

Output

Signal

V_{DDE /}

2

6

Output

Signal

V_{DDE /}

2

Figure 26. Synchronous output timing

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D_CLKOUT

V_{DDE /}

2

7

8

Input

Bus

V_{DDE /}

2

7

8

Input

Signal

V_{DDE /}

2

Figure 27. Synchronous input timing

ipg_clk

D_CLKOUT

D_ALE

D_TS

D_ADD/D_DAT

DATA

ADDR

9

10

Figure 28. ALE signal timing

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3.13.6 External interrupt timing (IRQ/NMI pin)

Table 39. External Interrupt timing¹

Spec Characteristic

Symbol

t_IPWL

Min

3

Max

—

Unit

2

1

2

3

IRQ/NMI Pulse Width Low

t_cyc

2

IRQ/NMI Pulse Width High

IRQ/NMI Edge to Edge Time³

t_IPWH

3

—

t_cyc

2

t_ICYC

6

—

t_cyc

1. IRQ/NMI timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, T_A= T_Lto T_H.

2. For further information on t_cyc, see Table 3.

3. Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.

IRQ

1

2

3

Figure 29. External interrupt timing

3.13.7 eTPU timing

Table 40. eTPU timing¹

Spec Characteristic

Symbol

t_ICPW

Min

4

1³

Max

Unit

2

1

2

eTPU Input Channel Pulse Width

eTPU Output Channel Pulse Width

—

t_{CYC_ETPU}

t_OCPW

1. eTPU timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, T_A= T_Lto T_H, and C_L= 200 pF with SRC = 0b00.

2. For further information on _{tCYC_ETPU}, see Table 3.

3. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the

rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

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eTPU Input

and TCRCLK

1

2

eTPU

Output

Figure 30. eTPU timing

3.13.8 eMIOS timing

Table 41. eMIOS timing¹

Spec

Characteristic

Symbol

Min

4

1³

Max

—

Unit

2

1

2

eMIOS Input Pulse Width

eMIOS Output Pulse Width

t_MIPW

t_{CYC_PER}

t_MOPW

—

1. eMIOS timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, T_A= T_Lto T_H, and C_L= 50 pF with SRC = 0b00.

2. For further information on t_{CYC_PER}, see Table 3.

3. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the

rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

eMIOS Input

1

2

eMIOS

Output

Figure 31. eMIOS timing

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3.13.9 DSPI timing with CMOS and LVDS pads

NOTE

The DSPI in TSB mode with LVDS pads can be used to

implement the Micro Second Channel (MSC) bus protocol.

DSPI channel frequency support is shown in Table 42. Timing specifications are shown

in Table 43, Table 44, Table 45, Table 46, and Table 47.

Table 42. DSPI channel frequency support

DSPI use mode

CMOS (Master mode) Full duplex – Classic timing (Table 43)

Full duplex – Modified timing (Table 44)

Max usable frequency (MHz)^{1, 2}

17

30

40

Output only mode (SCK/SOUT/PCS) (Table 43 and Table 44)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 47)

Full duplex – Modified timing (Table 45)

LVDS (Master mode)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 46)

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

2. Maximum usable frequency does not take into account external device propagation delay.

3.13.9.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.13.9.1.1 DSPI CMOS Master Mode — Classic Timing

Table 43. DSPI CMOS master classic timing (full duplex and output only) –

MTFE = 0, CPHA = 0 or 1¹

Condition²

Pad drive⁴

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

25 pF

50 pF

25 pF

50 pF

Min

33.0

Max

—

1

t_SCK

SCK cycle time

PCR[SRC]=11b

PCR[SRC]=10b

ns

80.0

—

PCR[SRC]=01b

200.0

—

2

t_CSC

PCS to SCK delay

PCR[SRC]=11b

(N⁵× t_SYS^{, 6}) – 16

(N⁵× t_SYS^{, 6}) – 18

(N⁵× t_SYS^{, 6}) – 45

—

ns

PCR[SRC]=10b

—

PCR[SRC]=01b

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

—

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Table 43. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA

= 0 or 1¹(continued)

Condition²

Pad drive⁴

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

0 pF

Min

Max

3

t_ASC

After SCK delay

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

(M⁷× t_SYS^{, 6}) – 35

—

ns

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

PCR[SRC]=11b

4

t_SDC

SCK duty cycle⁸

1/2t_SCK– 2

1/2t_SCK– 5

1/2t_SCK+ 2

1/2t_SCK+ 5

ns

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

PCS strobe timing

5

6

t_PCSC

t_PASC

PCSx to PCSS

time⁹

PCR[SRC]=10b

25 pF

13.0

—

ns

PCSS to PCSx

time⁹

PCR[SRC]=10b

25 pF

SIN setup time

7

8

t_SUI

SIN setup time to

SCK¹⁰

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

29.0

31.0

62.0

—

ns

SIN hold time

t_HI

SIN hold time from

SCK¹⁰

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

0 pF

–1.0

—

SOUT data valid time (after SCK edge)

9

t_SUO

SOUT data valid

time from SCK¹¹

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

—

7.0

8.0

18.0

SOUT data hold time (after SCK edge)

10

t_HO

SOUT data hold

time after SCK¹¹

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

–9.0

–10.0

–21.0

—

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified

otherwise.

3. All timing values for output signals in this table are measured to 50% of the output voltage.

4. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all

signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.

5. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

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SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

6. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t_SYS= 10

ns).

7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

8. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

9. PCSx and PCSS using same pad configuration.

10. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

t _CSC

t _ASC

PCSx

t _SCK

t _SDC

SCK Output

(CPOL = 0)

t _SDC

SCK Output

(CPOL = 1)

t _SUI

t _HI

Last Data

SIN

First Data

Data

t _SUO

t _HO

Data

Last Data

SOUT

Figure 32. DSPI CMOS master mode – classic timing, CPHA = 0

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PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t _SUI

t _HI

Data

Last Data

First Data

SIN

t _SUO

t _HO

Data

SOUT

First Data

Last Data

Figure 33. DSPI CMOS master mode – classic timing, CPHA = 1

tPCSC

tPASC

PCSS

PCSx

Figure 34. DSPI PCS strobe (PCSS) timing (master mode)

3.13.9.1.2 DSPI CMOS Master Mode – Modified Timing

Table 44. DSPI CMOS master modified timing (full duplex and output only) –

MTFE = 1, CPHA = 0 or 1¹

Condition²

Pad drive⁴

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

25 pF

50 pF

25 pF

50 pF

Min

33.0

Max

—

1

t_SCK

SCK cycle time

PCR[SRC]=11b

PCR[SRC]=10b

ns

80.0

—

PCR[SRC]=01b

200.0

—

2

t_CSC

PCS to SCK delay

PCR[SRC]=11b

(N⁵× t_SYS^{, 6}) – 16

(N⁵× t_SYS^{, 6}) – 18

(N⁵× t_SYS^{, 6}) – 45

—

ns

PCR[SRC]=10b

—

PCR[SRC]=01b

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

—

Table continues on the next page...

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Electrical characteristics

Table 44. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,

CPHA = 0 or 1¹(continued)

Condition²

Pad drive⁴

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

0 pF

Min

Max

3

t_ASC

After SCK delay

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

(M⁷× t_SYS^{, 6}) – 35

—

ns

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

PCR[SRC]=11b

4

t_SDC

SCK duty cycle⁸

1/2t_SCK– 2

1/2t_SCK– 5

1/2t_SCK+ 2

1/2t_SCK+ 5

ns

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

PCS strobe timing

5

6

t_PCSC

t_PASC

PCSx to PCSS

time⁹

PCR[SRC]=10b

25 pF

13.0

—

ns

PCSS to PCSx

time⁹

PCR[SRC]=10b

25 pF

SIN setup time

, 6

7

8

9

t_SUI

SIN setup time to

SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

25 pF

50 pF

29 – (P¹¹× t_SYS

31 – (P¹¹× t_SYS

62 – (P¹¹× t_SYS

29.0

)

—

ns

, 6

)

CPHA = 0¹⁰

SIN setup time to

SCK

31.0

CPHA = 1¹⁰

62.0

SIN hold time

12

, 6

t_HI

SIN hold time from

SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

0 pF

–1 + (P¹¹× t_SYS

–1.0

)

—

ns

CPHA = 0¹⁰

SIN hold time from

SCK

–1.0

CPHA = 1¹⁰

–1.0

SOUT data valid time (after SCK edge)

6

t_SUO

SOUT data valid

time from SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

25 pF

50 pF

—

7.0 + t_SYS

ns

6

8.0 + t_SYS

CPHA = 0¹³

6

18.0 + t_SYS

7.0

SOUT data valid

time from SCK

8.0

CPHA = 1¹³

18.0

SOUT data hold time (after SCK edge)

Table continues on the next page...

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Table 44. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,

CPHA = 0 or 1¹(continued)

Condition²

Pad drive⁴

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

25 pF

Min

–9.0 + t_SYS

–10.0 + t_SYS

–21.0 + t_SYS

–9.0

Max

—

6

10

t_HO

SOUT data hold

time after SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

ns

6

50 pF

—

CPHA = 0¹³

50 pF

—

SOUT data hold

time after SCK

25 pF

—

ns

50 pF

–10.0

—

CPHA = 1¹³

50 pF

–21.0

—

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified

otherwise.

3. All timing values for output signals in this table are measured to 50% of the output voltage.

4. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all

signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.

5. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

6. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t_SYS= 10

ns).

7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

8. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

9. PCSx and PCSS using same pad configuration.

10. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

11. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set

to 1.

12. The 0 pF load condition given in the DSPI AC timing applies to theoretical worst-case hold timing. This guarantees worst-

case operation, and additional margin can be achieved in the applications by applying a realistic load.

13. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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Electrical characteristics

t _CSC

t _ASC

PCSx

t _SCK

t _SDC

SCK Output

(CPOL = 0)

t _SDC

SCK Output

(CPOL = 1)

t _SUI

t _HI

Last Data

SIN

First Data

Data

t _SUO

t _HO

Data

Last Data

SOUT

Figure 35. DSPI CMOS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t _HI

t _SUI

t _HI

Data

Last Data

First Data

SIN

t _SUO

t _HO

Data

SOUT

First Data

Last Data

Figure 36. DSPI CMOS master mode – modified timing, CPHA = 1

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Electrical characteristics

tPCSC

tPASC

PCSS

PCSx

Figure 37. DSPI PCS strobe (PCSS) timing (master mode)

3.13.9.1.3 DSPI LVDS Master Mode – Modified Timing

Table 45. DSPI LVDS master timing – full duplex – modified transfer format

(MTFE = 1), CPHA = 0 or 1

Condition¹

Pad drive³

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

1

t_SCK

SCK cycle time

LVDS

15 pF to 25 pF

differential

33.3

—

ns

2

t_CSC

PCS to SCK delay

(LVDS SCK)

PCS: PCR[SRC]=11b

PCS: PCR[SRC]=10b

PCS: PCR[SRC]=01b

PCS: PCR[SRC]=11b

25 pF

(N⁴× t_SYS^{, 5}) – 10

(N⁴× t_SYS^{, 5}) – 32

(M⁶× t_SYS^{, 5}) – 8

—

ns

50 pF

3

t_ASC

After SCK delay

(LVDS SCK)

PCS: 0 pF

SCK: 25 pF

PCS: 0 pF

SCK: 25 pF

PCS: 0 pF

SCK: 25 pF

PCS: PCR[SRC]=10b

PCS: PCR[SRC]=01b

LVDS

(M⁶× t_SYS^{, 5}) – 8

1/2t_SCK– 2

—

ns

4

7

t_SDC

t_SUI

SCK duty cycle⁷

15 pF to 25 pF

differential

1/2t_SCK+2

SIN setup time

, 5

SIN setup time to

SCK

LVDS

15 pF to 25 pF

differential

23 – (P⁹× t_SYS

)

—

ns

CPHA = 0⁸

SIN setup time to

SCK

15 pF to 25 pF

differential

23

CPHA = 1⁸

8

t_HI

SIN hold time

, 5

SIN hold time from

SCK

LVDS

0 pF differential

–1 + (P⁹× t_SYS

)

—

ns

CPHA = 0⁸

SIN hold time from

SCK

0 pF differential

–1

CPHA = 1⁸

Table continues on the next page...

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Electrical characteristics

Table 45. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1),

CPHA = 0 or 1 (continued)

Condition¹

Pad drive³

SOUT data valid time (after SCK edge)

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

9

t_SUO

5

SOUT data valid

time from SCK

LVDS

15 pF to 25 pF

differential

—

7.0 + t_SYS

ns

CPHA = 0¹⁰

SOUT data valid

time from SCK

LVDS

15 pF to 25 pF

differential

—

7.0

ns

CPHA = 1¹⁰

10

t_HO

SOUT data hold time (after SCK edge)

5

SOUT data hold

time after SCK

LVDS

15 pF to 25 pF

differential

–7.5 + t_SYS

—

ns

CPHA = 0¹⁰

SOUT data hold

time after SCK

LVDS

15 pF to 25 pF

differential

–7.5

CPHA = 1¹⁰

1. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified

otherwise.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all

signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.

4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

5. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS =

10 ns).

6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

7. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = 100 mV.

9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set

to 1.

10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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Electrical characteristics

t _CSC

t _ASC

PCSx

t _SCK

t _SDC

SCK Output

(CPOL = 0)

t _SDC

SCK Output

(CPOL = 1)

t _SUI

t _HI

Last Data

SIN

First Data

Data

t _SUO

t _HO

Data

Last Data

SOUT

Figure 38. DSPI LVDS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t _HI

t _SUI

t _HI

Data

Last Data

First Data

SIN

t _SUO

t _HO

Data

SOUT

First Data

Last Data

Figure 39. DSPI LVDS master mode – modified timing, CPHA = 1

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Electrical characteristics

3.13.9.1.4 DSPI Master Mode – Output Only

Table 46. DSPI LVDS master timing — output only — timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock^{1, 2}

Condition³

Pad drive⁵

Value⁴

#

Symbol

Characteristic

SCK cycle time

Unit

Load (C_L)

Min

Max

1

t_SCK

LVDS

15 pF to 50 pF

differential

25

—

ns

2

3

4

t_CSV

t_CSH

t_SDC

PCS valid after SCK⁶

(SCK with 50 pF

differential load cap.)

PCS hold after SCK⁶

(SCK with 50 pF

differential load cap.)

PCR[SRC]=11b

PCR[SRC]=10b

25 pF

50 pF

—

8

ns

12

PCR[SRC]=11b

PCR[SRC]=10b

0 pF

–4.0

—

ns

SCK duty cycle (SCK

with 50 pF differential

load cap.)

LVDS

15 pF to 50 pF

differential

1/2t_SCK– 2

1/2t_SCK+ 2

ns

SOUT data valid time (after SCK edge)

5

6

t_SUO

SOUT data valid time

from SCK⁷

LVDS

15 pF to 50 pF

differential

—

6

ns

SOUT data hold time (after SCK edge)

t_HO

SOUT data hold time

after SCK⁷

LVDS

15 pF to 50 pF

differential

–7.0

—

1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad

driver strength as defined. Timing may degrade for weaker output drivers.

2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified

otherwise.

4. All timing values for output signals in this table are measured to 50% of the output voltage.

5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all

signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.

6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

Table 47. DSPI CMOS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock ^{1, 2}

Condition³

Pad drive⁵

Value⁴

#

Symbol

Characteristic

SCK cycle time

Unit

Load (C_L)

25 pF

50 pF

25 pF

50 pF

Min

33.0

80.0

200.0

7

Max

—

1

t_SCK

PCR[SRC]=11b

PCR[SRC]=10b

ns

—

PCR[SRC]=01b

—

2

t_CSV

PCS valid after SCK⁶

PCR[SRC]=11b

—

PCR[SRC]=10b

8

—

PCR[SRC]=01b

18

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

45

—

Table continues on the next page...

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Electrical characteristics

Table 47. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB

= 1, CPOL = 0 or 1, continuous SCK clock ^{1, 2}(continued)

Condition³

Pad drive⁵

Value⁴

#

Symbol

Characteristic

Unit

Load (C_L)

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

PCS: 0 pF

SCK: 50 pF

0 pF

Min

Max

3

t_CSH

PCS hold after SCK⁶

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

–14

—

ns

–14

–33

–35

—

ns

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

PCR[SRC]=11b

4

9

t_SDC

t_SUO

t_HO

SCK duty cycle⁷

1/2t_SCK– 2

1/2t_SCK– 5

1/2t_SCK+ 2

1/2t_SCK+ 5

ns

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

SOUT data valid time (after SCK edge)

SOUT data valid time

from SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

—

7.0

8.0

ns

CPHA = 1⁸

18.0

SOUT data hold time (after SCK edge)

10

SOUT data hold time

after SCK

PCR[SRC]=11b

PCR[SRC]=10b

PCR[SRC]=01b

25 pF

50 pF

–9.0

–10.0

–21.0

—

ns

CPHA = 1⁸

1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified

otherwise.

4. All timing values for output signals in this table are measured to 50% of the output voltage.

5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all

signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.

6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

7. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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Electrical characteristics

PCSx

t

CSV

t

SCK

SDC

CSH

SCK Output

(CPOL = 0)

t

SUO

t

HO

First Data

Last Data

SOUT

Data

Figure 40. DSPI LVDS and CMOS master timing – output only – modified transfer format

MTFE = 1, CHPA = 1

3.13.10 FEC timing

3.13.10.1 MII receive signal timing (RXD[3:0], RX_DV, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the RX_CLK frequency.

Table 48. MII receive signal timing¹

Value

Symbol

Characteristic

Unit

Min

5

Max

—

M1

M2

M3

M4

RXD[3:0], RX_DV to RX_CLK setup

RX_CLK to RXD[3:0], RX_DV hold

RX_CLK pulse width high

ns

5

—

ns

35%

65%

RX_CLK period

RX_CLK pulse width low

1. All timing specifications valid to the pad input levels defined in I/O pad current specifications.

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Electrical characteristics

M3

RX_CLK (input)

M4

RXD[3:0] (inputs)

RX_DV

M1

M2

Figure 41. MII receive signal timing diagram

3.13.10.2 MII transmit signal timing (TXD[3:0], TX_EN, and TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz

+1%. There is no minimum frequency requirement. The system clock frequency must be

at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN) can be programmed to transition from either

the rising or falling edge of TX_CLK, and the timing is the same in either case. This

options allows the use of noncompliant MII PHYs.

Refer to the MPC5777C Microcontroller Reference Manual's Fast Ethernet Controller

(FEC) chapter for details of this option and how to enable it.

Table 49. MII transmit signal timing¹

Value²

Symbol

Characteristic

Unit

Min

4.5

Max

—

M5

M6

M7

M8

TX_CLK to TXD[3:0], TX_EN invalid

TX_CLK to TXD[3:0], TX_EN valid

TX_CLK pulse width high

ns

—

25

ns

35%

65%

TX_CLK period

TX_CLK pulse width low

1. All timing specifications valid to the pad input levels defined in I/O pad specifications.

2. Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package capacitance

is accounted for, and does not need to be subtracted from the 25 pF value.

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Electrical characteristics

M7

TX_CLK (input)

M5

M8

TXD[3:0] (outputs)

TX_EN

M6

Figure 42. MII transmit signal timing diagram

3.13.10.3 MII async inputs signal timing (CRS)

Table 50. MII async inputs signal timing

Value

Symbol

Characteristic

Unit

Min

Max

M9

CRS minimum pulse width

1.5

—

TX_CLK period

CRS

M9

Figure 43. MII async inputs timing diagram

3.13.10.4 MII and RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 51. MII serial management channel timing¹

Value²

Symbol

Characteristic

Unit

Min

Max

M10

MDC falling edge to MDIO output invalid (minimum

propagation delay)

0

—

ns

M11

M12

M13

M14

M15

MDC falling edge to MDIO output valid (max prop delay)

MDIO (input) to MDC rising edge setup

MDIO (input) to MDC rising edge hold

MDC pulse width high

—

10

25

—

ns

0

—

ns

40%

60%

MDC period

MDC pulse width low

1. All timing specifications valid to the pad input levels defined in I/O pad specifications.

2. Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package capacitance

is accounted for, and does not need to be subtracted from the 25 pF value

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Electrical characteristics

M14

M15

MDC (output)

MDIO (output)

M10

M11

MDIO (input)

M12

M13

Figure 44. MII serial management channel timing diagram

3.13.10.5 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK

frequency.

Table 52. RMII receive signal timing¹

Value

Symbol

Characteristic

Unit

Min

4

Max

—

R1

R2

R3

R4

RXD[1:0], CRS_DV to REF_CLK setup

REF_CLK to RXD[1:0], CRS_DV hold

REF_CLK pulse width high

ns

2

—

ns

35%

65%

REF_CLK period

REF_CLK pulse width low

1. All timing specifications valid to the pad input levels defined in I/O pad specifications.

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Electrical characteristics

R3

REF_CLK (input)

R4

RXD[1:0] (inputs)

CRS_DV

R1

R2

Figure 45. RMII receive signal timing diagram

3.13.10.6 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz +

1%. There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK

frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either

the rising or falling edge of REF_CLK, and the timing is the same in either case. This

options allows the use of non-compliant RMII PHYs.

Table 53. RMII transmit signal timing¹

Value²

Symbol

Characteristic

Unit

Min

2

Max

—

R5

R6

R7

R8

REF_CLK to TXD[1:0], TX_EN invalid

REF_CLK to TXD[1:0], TX_EN valid

REF_CLK pulse width high

ns

—

16

ns

35%

65%

REF_CLK period

REF_CLK pulse width low

1. All timing specifications valid to the pad input levels defined in I/O pad specifications.

2. Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package capacitance

is accounted for, and does not need to be subtracted from the 25 pF value.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Package information

R7

REF_CLK (input)

R5

R8

TXD[1:0] (outputs)

TX_EN

R6

Figure 46. RMII transmit signal timing diagram

4 Package information

To find the package drawing for each package, go to http://www.nxp.com and perform a

keyword search for the drawing’s document number:

If you want the drawing for this package

416-ball MAPBGA

Then use this document number

98ASA00562D

98ASA00623D

516-ball MAPBGA

4.1 Thermal characteristics

Table 54. Thermal characteristics, 416-ball MAPBGA package

Characteristic

Symbol

R_ΘJA

Value

Unit

°C/W

Junction to Ambient ^{1, 2}Natural Convection (Single layer board)

Junction to Ambient ^{1, 3}Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁴

28.8

19.6

21.3

15.1

9.5

R_ΘJA

R_ΘJMA

R_ΘJB

Junction to Case ⁵

Junction to Package Top ⁶Natural Convection

R_ΘJC

4.8

Ψ_JT

0.2

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

83

Package information

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

Table 55. Thermal characteristics, 516-ball MAPBGA package

Characteristic

Symbol

R_ΘJA

Value

28.5

20.0

21.3

15.5

8.8

Unit

°C/W

Junction to Ambient ^{1, 2}Natural Convection (Single layer board)

Junction to Ambient ^{1, 3}Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁴

R_ΘJA

R_ΘJMA

R_ΘJB

Junction to Case ⁵

Junction to Package Top ⁶Natural Convection

R_ΘJC

4.8

Ψ_JT

0.2

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

4.1.1 General notes for thermal characteristics

An estimation of the chip junction temperature, T_J, can be obtained from the equation:

where:

T_A= ambient temperature for the package (°C)

R_ΘJA= junction-to-ambient thermal resistance (°C/W)

P_D= power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards

to provide consistent values for estimations and comparisons. The difference between the

values determined for the single-layer (1s) board compared to a four-layer board that has

two signal layers, a power and a ground plane (2s2p), demonstrate that the effective

thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the application board (number of planes)

• Effective size of the board which cools the component

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Package information

• Quality of the thermal and electrical connections to the planes

• Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball.

Using fewer vias to connect the package to the planes reduces the thermal performance.

Thinner planes also reduce the thermal performance. When the clearance between the

vias leave the planes virtually disconnected, the thermal performance is also greatly

reduced.

As a general rule, the value obtained on a single-layer board is within the normal range

for the tightly packed printed circuit board. The value obtained on a board with the

internal planes is usually within the normal range if the application board has:

• One oz. (35 micron nominal thickness) internal planes

• Components are well separated

• Overall power dissipation on the board is less than 0.02 W/cm²

The thermal performance of any component depends on the power dissipation of the

surrounding components. In addition, the ambient temperature varies widely within the

application. For many natural convection and especially closed box applications, the

board temperature at the perimeter (edge) of the package is approximately the same as the

local air temperature near the device. Specifying the local ambient conditions explicitly

as the board temperature provides a more precise description of the local ambient

conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following

equation:

where:

T_B= board temperature for the package perimeter (°C)

R_ΘJB= junction-to-board thermal resistance (°C/W) per JESD51-8

P_D= power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation,

the junction temperature is predictable if the application board is similar to the thermal

test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance

plus a case-to-ambient thermal resistance:

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

85

Package information

where:

R_ΘJA= junction-to-ambient thermal resistance (°C/W)

R_ΘJC= junction-to-case thermal resistance (°C/W)

R_ΘCA= case to ambient thermal resistance (°C/W)

R_ΘJCis device related and is not affected by other factors. The thermal environment can

be controlled to change the case-to-ambient thermal resistance, R_ΘCA. For example,

change the air flow around the device, add a heat sink, change the mounting arrangement

on the printed circuit board, or change the thermal dissipation on the printed circuit board

surrounding the device. This description is most useful for packages with heat sinks

where 90% of the heat flow is through the case to heat sink to ambient. For most

packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-

board thermal resistance and the junction-to-case thermal resistance. The junction-to-case

thermal resistance describes when using a heat sink or where a substantial amount of heat

is dissipated from the top of the package. The junction-to-board thermal resistance

describes the thermal performance when most of the heat is conducted to the printed

circuit board. This model can be used to generate simple estimations and for

computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm

models can be generated upon request.

To determine the junction temperature of the device in the application on a prototype

board, use the thermal characterization parameter (Ψ_JT) to determine the junction

temperature by measuring the temperature at the top center of the package case using the

following equation:

where:

T_T= thermocouple temperature on top of the package (°C)

Ψ_JT= thermal characterization parameter (°C/W)

P_D= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2

specification using a 40-gauge type T thermocouple epoxied to the top center of the

package case. Position the thermocouple so that the thermocouple junction rests on the

package. Place a small amount of epoxy on the thermocouple junction and approximately

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Ordering information

1 mm of wire extending from the junction. Place the thermocouple wire flat against the

package case to avoid measurement errors caused by the cooling effects of the

thermocouple wire.

When board temperature is perfectly defined below the device, it is possible to use the

thermal characterization parameter (Ψ_JPB) to determine the junction temperature by

measuring the temperature at the bottom center of the package case (exposed pad) using

the following equation:

where:

T_T= thermocouple temperature on bottom of the package (°C)

Ψ_JT= thermal characterization parameter (°C/W)

P_D= power dissipation in the package (W)

5 Ordering information

Figure 47 and Table 56 describe orderable part numbers for the MPC5777C.

M PC 5777C

X

K3 M ME 3/4 R

Qualification status

Core code

Device number

Optional features field

Fab/Revision

Temperature range

Package identifier

Operating frequency

Tape and reel status

R = Tape and reel

(blank) = Trays

Package identifier

ME = 416 MAPBGA Pb-Free

MO = 516 MAPBGA Pb-Free

Qualification status

P = Pre-qualification

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

Temperature range

M = –40 °C to 125 °C

Operating frequency

3 = 2 x 264 MHz

4 = 2 x 300 MHz

Optional features field

(blank) = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07

A = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08

R = ISO-compliant CAN FD not available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08

C = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07

D = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08

L = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08

S = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes RSA-enhanced security firmware

T = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes RSA-enhanced security firmware

Note: Not all options are available on all devices.

Figure 47. MPC5777C Orderable part number description

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

87

Document revision history

Table 56. Example orderable part numbers

Operating temperature³

Part number¹

Package description

Speed (MHz)²

Min (T_L)

Max (T_H)

SPC5777CCK3MME3

MPC5777C 416 package

Lead-free (Pb-free)

264

–40 °C

125 °C

SPC5777CK3MME3

SPC5777CCK3MMO3

SPC5777CK3MMO3

MPC5777C 416 package

Lead-free (Pb-free)

264

–40 °C

125 °C

MPC5777C 516 package

Lead-free (Pb-free)

MPC5777C 516 package

Lead-free (Pb-free)

1. All packaged devices are PPC5777C, rather than MPC5777C or SPC5777C, until product qualifications are complete. The

unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.

Not all configurations are available in the PPC parts.

2. For the operating mode frequency of various blocks on the device, see Table 3.

3. The lowest ambient operating temperature is referenced by T_L; the highest ambient operating temperature is referenced by

T_H.

6 Document revision history

The following table summarizes revisions to this document since the previous release.

Table 57. Revision history

Revision

Date

Description of changes

14

01/2020 In Table 17, updated the footnote from "TUE does not apply to differential conversions" to "TUE,

Gain, and Offset specifications do not apply to differential conversions".

In Table 4 added Max value 120 μA for 40°C and 360 μA for 85°C for I_STBY

.

13

08/2018 In Table 3, added information for 300 MHZ frequency:

• f_SYS

• f_PLATF

• f_ETPU

• f_PER

• f_{fFM_PER}

In Table 12 added Max value 240 MHz for f_PLL0PHIand Table 13 added Max value 300 MHz for

f_PLL1PHI

.

In Table 34 updated the row from "100 MHz > fPLATF ≤ 133 MHz" to "100 MHz > fPLATF ≤ 150

MHz" under "Flash memory frequency" column.

In Figure 47 added 300 MHz frequency orderable part number.

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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NXP Semiconductors

Document revision history

Table 57. Revision history (continued)

Revision

Date

Description of changes

12

08/2018 In Table 12 of PLL electrical specifications, changed text of footnote 1:

• from: "f_PLL0INfrequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure

PFD input signal is in the range 8 MHz to 20 MHz."

• to: "Ensure that the f_PLL0INfrequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8

MHz to 20 MHz."

In Table 17 of Enhanced Queued Analog-to-Digital Converter (eQADC), added footnote about Max

value of Conversion Cycles (CC): "128 sampling cycles (LST=128), differential conversion, pregain

of x4"

In Table 38 of External Bus Interface (EBI) timing, changed text of footnote 1:

• from: "EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 30 pF with SIU_PCR[DSC] = 10b for ADDR/CTRL and SIU_PCR[DSC] = 11b for

CLKOUT/DATA."

• to: "EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/

ALE."

In I/O pad current specifications added the text "The EBI power segments have..........segment does

not exceed the spec".

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

89

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Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any

particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including “typicals,” must be validated for each customer application

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found at the following address: nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to unidentified

vulnerabilities. Customers are responsible for the design and operation of their applications and

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NXP accepts no liability for any vulnerability that is discovered. Customers should implement

appropriate design and operating safeguards to minimize the risks associated with their applications

and products.

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Document Number MPC5777C

Revision 14, 01/2020


型号：	PPC5777CCK3MME3R
厂家：	NXP
描述：	MPC5777C Microcontroller PC 微控制器
文件：	总90页 (文件大小：1087K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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