PSMN004-25P [NXP]

N-channel logic level TrenchMOS transistor; N沟道逻辑电平的TrenchMOS晶体管


型号：	PSMN004-25P
厂家：	NXP
描述：	N-channel logic level TrenchMOS transistor N沟道逻辑电平的TrenchMOS晶体管晶体晶体管
文件：	总9页 (文件大小：104K)
中文：	中文翻译
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Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

V_DSS= 25 V

I_D= 75 A

• Low thermal resistance

R_DS(ON)≤ 4.3 mΩ (V_GS= 10 V)

R_DS(ON)≤ 5 mΩ (V_GS= 5 V)

GENERAL DESCRIPTION

SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in

each package at each voltage rating.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

The PSMN004-25P is supplied in the SOT78 (TO220AB) conventional leaded package.

The PSMN004-25B is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404 (D²PAK)

DESCRIPTION

tab

gate

drain¹

source

drain

tab

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

Drain-source voltage

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 15

Drain-gate voltage

Continuous gate-source

voltage

V_GSM

I_D

Peak pulsed gate-source

voltage

Continuous drain current

T_j≤ 150 ˚C

± 20

T_mb= 25 ˚C; V_GS= 5 V

T_mb= 100 ˚C; V_GS= 5 V

T_mb= 25 ˚C

75²

240

230

175

˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

- 55

1 It is not possible to make connection to pin:2 of the SOT404 package

2 maximum continuous current limited by package

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

THERMAL RESISTANCES

SYMBOL PARAMETER

R_{th j-mb}Thermal resistance junction

to mounting base

Thermal resistance junction SOT78 package, vertical in still air

CONDITIONS

MIN. TYP. MAX. UNIT

0.65 K/W

R_{th j-a}

K/W

to ambient

SOT404 package, pcb mounted, minimum

footprint

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

E_ASNon-repetitive avalanche

CONDITIONS

MIN.

MAX.

UNIT

Unclamped inductive load, I_AS= 75 A;

t_p= 100 µs; T_jprior to avalanche = 25˚C;

120

energy

V_DD≤ 15 V; R_GS= 50 Ω; V_GS= 5 V

I_AS

Non-repetitive avalanche

current

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

Drain-source breakdown

voltage

Gate threshold voltage

V_GS= 0 V; I_D= 0.25 mA;

0.5

mΩ

T_j= -55˚C

1.5

V_GS(TO)

V_DS= V_GS; I_D= 1 mA

T_j= 175˚C

T_j= -55˚C

2.3

4.3

5.4

9.25 mΩ

R_DS(ON)

Drain-source on-state

resistance

V_GS= 10 V; I_D= 25 A

V_GS= 5 V; I_D= 25 A

V_GS= 4.5 V; I_D= 25 A

V_GS= 5 V; I_D= 25 A; T_j= 175˚C

3.5

I_GSS

I_DSS

Gate-source leakage current V_GS= ± 10 V; V_DS= 0 V;

Zero gate voltage drain

current

0.02 100

0.05

µA

V_DS= 25 V; V_GS= 0 V;

500

T_j= 175˚C

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 75 A; V_DD= 15 V; V_GS= 5 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 15 V; R_D= 1.2 Ω

V_GS= 5 V; R_G= 5.6 Ω

Resistive load

220

435

320

L_d

Internal drain inductance

Measured tab to centre of die

Measured from drain lead to centre of die

(SOT78 package only)

3.5

4.5

L_s

Internal source inductance

Measured from source lead to source

bond pad

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 20 V; f = 1 MHz

6000

1700

1400

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

I_SM

V_SD

240

I_F= 25 A; V_GS= 0 V

I_F= 75 A; V_GS= 0 V

0.85

1.1

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 20 A; -dI_F/dt = 100 A/µs;

V_GS= 0 V; V_R= 25 V

400

µC

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

Transient thermal impedance, Zth j-mb (K/W)

Normalised Power Derating, PD (%)

100

0.1

D = 0.5

0.2

0.1

0.05

0.02

D = tp/T

0.01

single pulse

1E-05

0.001

1E-06

1E-04

1E-03

1E-02

1E-01

1E+00

100

125

150

175

Pulse width, tp (s)

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Drain Current, ID (A)

100

Normalised Current Derating, ID (%)

10 V

Tj = 25 C

2.8 V

100

4.5 V

5 V

VGS = 2.6 V

2.4 V

2.2 V

2 V

1.8 V

100

125

150

175

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Mounting Base temperature, Tmb (C)

Drain-Source Voltage, VDS (V)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb)

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS)

Peak Pulsed Drain Current, IDM (A)

1000

Drain-Source On Resistance, RDS(on) (Ohms)

0.02

RDS(on) = VDS/ ID

2.4 V

2 V

2.2 V

2.6 V

0.018

0.016

0.014

0.012

0.01

tp = 10 us

100 us

100

1 ms

2.8 V

4.5 V

D.C.

10 ms

0.008

0.006

0.004

0.002

100 ms

5 V

VGS = 10V

Tj = 25 C

Drain-Source Voltage, VDS (V)

100

90 100

Drain Current, ID (A)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D)

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

Threshold Voltage, VGS(TO) (V)

Drain current, ID (A)

VDS > ID X RDS(ON)

2.25

100

maximum

typical

1.75

1.5

1.25

minimum

175 C

0.75

0.5

0.25

Tj = 25 C

0.2 0.4 0.6 0.8

1.2 1.4 1.6 1.8

2.2 2.4 2.6 2.8

-60

-40

-20

100 120 140 160 180

Gate-source voltage, VGS (V)

Junction Temperature, Tj (C)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS)

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Drain current, ID (A)

Transconductance, gfs (S)

1.0E-01

140

120

100

Tj = 25 C

VDS = 5 V

VDS > ID X RDS(ON)

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06

175 C

minimum

typical

maximum

0.5

1.5

2.5

100

Drain current, ID (A)

Gate-source voltage, VGS (V)

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D)

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised On-state Resistance

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

Capacitances, Ciss, Coss, Crss (pF)

100000

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

10000

1000

Ciss

Coss

Crss

-60

-40

-20

100 120 140 160 180

0.1

100

Junction temperature, Tj (C)

Drain-Source Voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j)

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

Gate-source voltage, VGS (V)

Maximum Avalanche Current, I_AS(A)

100

ID = 75 A

VDD = 15 V

Tj = 25 C

25 C

Tj prior to avalanche = 150 C

0.001

100 125 150 175 200 225 250

Gate charge, QG (nC)

0.01

0.1

Avalanche time, t_AV(ms)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

Fig.15. Maximum permissible non-repetitive

avalanche current (I_AS) versus avalanche time (t_AV);

unclamped inductive load

Source-Drain Diode Current, IF (A)

100

VGS = 0 V

175 C

Tj = 25 C

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Source-Drain Voltage, VSDS (V)

1.1 1.2

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220

SOT78

(1)

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

4.5

4.1

1.39

1.27

0.9

0.7

1.3

1.0

0.7

0.4

15.8

15.2

6.4

5.9

10.3

9.7

15.0

13.5

3.30

2.79

3.8

3.6

3.0

2.7

2.6

2.2

3.0

2.54

Note

1. Terminals in this zone are not tinned.

REFERENCES

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

JEDEC

EIAJ

97-06-11

SOT78

TO-220

Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads

(one lead cropped)

SOT404

mounting

base

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.40 2.60

2.10 14.80 2.20

2.54

REFERENCES

JEDEC

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

EIAJ

98-12-14

99-06-25

SOT404

Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

October 1999

Rev 1.100

Philips Semiconductors

Product specification

N-channel logic level TrenchMOS transistor

PSMN004-25B, PSMN004-25P

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.18. SOT404 : soldering pattern for surface mounting.

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

October 1999

Rev 1.100

PSMN004-25P [NXP]

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