PSMN059-150Y [NXP]
N-channel TrenchMOS standard level FET; N沟道的TrenchMOS标准水平FET
| 型号： | PSMN059-150Y |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS standard level FET |
| 文件： | 总12页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSMN059-150Y
N-channel TrenchMOS standard level FET
Rev. 01 — 5 May 2008
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using
TrenchMOS technology.
1.2 Features
I Low body Qr
I Fast switching
1.3 Applications
I Industrial DC motor control
I Class D audio
I DC-to-DC converters
I Switched-mode power supplies
1.4 Quick reference data
I VDS ≤ 150 V
I ID ≤ 43 A
I RDSon ≤ 59 mΩ
I QGD = 9.1 nC (typ)
2. Pinning information
Table 1.
Pin
Pinning
Description
source (S)
gate (G)
Simplified outline
Symbol
1, 2, 3
4
mb
D
S
mb
mounting base; connected to drain
(D)
G
mbb076
1
2 3 4
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package; 4 leads
Version
PSMN059-150Y
LFPAK
SOT669
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VDGR
VGS
ID
drain-source voltage
25 °C ≤ Tj ≤ 150 °C
-
150
150
±20
43
V
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
V
-
V
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3
Tmb = 100 °C; VGS = 10 V; see Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tmb = 25 °C; see Figure 1
-
A
-
27.7
129
113
+150
+150
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
52
A
A
ISM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
208
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 12.1 A;
tp = 0.21 ms; VDS ≤ 150 V; RGS = 50 Ω;
-
255
mJ
VGS = 10 V; starting at Tj = 25 °C
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
2 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab937
003aac023
120
120
P
I
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
T
(°C)
T
(°C)
mb
mb
Ptot
ID
Pder
=
× 100 %
Ider
=
× 100 %
-----------------------
-------------------
Ptot(25°C)
ID(25°C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab749
3
10
I
D
Limit R
= V / I
DS D
DSon
(A)
2
10
t
= 10 µs
p
10
100 µs
1 ms
DC
10 ms
1
100 ms
−1
10
2
3
1
10
10
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
3 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 4.
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
1.1 K/W
[1]
Rth(j-mb) thermal resistance from junction to mounting base see Figure 4
-
-
[1] Mounted on a printed-circuit board; vertical in still air.
003aac268
10
Z
th(j-mb)
(K/W)
1
d = 0.5
0.2
−1 0.1
10
10
10
0.05
t
p
0.02
P
δ =
T
−2
single shot
t
t
p
T
−3
−6
−5
−4
−3
−2
−1
10
10
10
10
10
10
1
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
4 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
150
133
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain leakage current
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
2
1
-
3
-
4
V
V
V
Tj = 150 °C
-
Tj = −55 °C
-
4.4
IDSS
VDS = 120 V; VGS = 0 V
Tj = 25 °C
-
-
-
-
-
1
µA
µA
nA
Ω
Tj = 150 °C
-
100
100
-
IGSS
RG
gate leakage current
gate resistance
VGS = ±20 V; VDS = 0 V
f = 1 MHz
-
1.1
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 12 A; see Figure 6 and 8
Tj = 25 °C
-
-
46
59
mΩ
mΩ
Tj = 150 °C
101
135
Dynamic characteristics
QG(tot)
QGS
QGD
VGS(pl)
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain charge
gate-source plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 12 A; VDS = 75 V; VGS = 10 V;
see Figure 11 and 12
-
-
-
-
-
-
-
-
-
-
-
27.9
6.3
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
V
9.1
4.8
VGS = 0 V; VDS = 30 V; f = 1 MHz;
see Figure 14
1529
208
66
pF
pF
pF
ns
ns
ns
ns
VDS = 75 V; RL = 3 Ω; VGS = 10 V; RG = 5.6 Ω
14.2
42
td(off)
tf
turn-off delay time
fall time
54.2
11.1
Source-drain diode
VSD
trr
source-drain voltage
IS = 12 A; VGS = 0 V; see Figure 13
-
-
-
0.9
1.2
V
reverse recovery time
recovered charge
IS = 12 A; dIS/dt = −100 A/µs; VGS = 0 V
114
175
-
-
ns
nC
Qr
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
5 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab751
7 6
003aab752
50
150
4.5
5
5.5
10
I
R
DSon
D
(A)
(mΩ)
40
120
V
(V) = 6
GS
V
(V) = 5.5
30
20
10
0
90
60
30
0
GS
7
10
5
4.5
0
1
2
3
4
5
0
10
20
30
40
50
V
(V)
I (A)
D
DS
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
03al51
003aab753
3
60
V
> I × R
DS
D
DSon
I
D
a
(A)
45
2
30
15
0
T = 150 °C
1
25 °C
j
0
−75
−25
25
75
125
175
0
2
4
6
8
T (°C)
j
V
(V)
GS
Tj = 25 °C and 150 °C; VDS > ID × RDSon
RDSon
a =
-----------------------------
RDSon(25°C)
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
6 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab852
003aab853
−1
−2
−3
−4
−5
−6
5
10
I
V
D
GS(th)
(A)
(V)
min
typ
max
4
10
10
10
10
10
max
typ
3
2
1
0
min
−60
0
60
120
160
0
2
4
6
T (°C)
V
(V)
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab754
10
I
= 12 A
V
(V)
D
GS
T = 25 °C
j
8
6
4
2
0
30
V
DS
75
I
D
V
= 120 V
V
DS
GS(pl)
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
0
7.5
15
22.5
30
Q
(nC)
G
003aaa508
ID = 12 A; VDS = 30, 75 and 120 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
7 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aab756
003aab755
4
3
2
80
10
I
S
C
(pF)
(X)
60
C
iss
10
40
20
0
T = 25 °C
j
150 °C
C
C
oss
10
rss
10
10
−1
2
0
0.3
0.6
0.9
1.2
1
10
10
V
(V)
V
(V)
DS
SD
Tj = 25 °C and 150 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
8 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 15. Package outline SOT669 (LFPAK)
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
9 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN059-150Y_1
20080505
Product data sheet
-
-
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
10 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
11 of 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS standard level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 May 2008
Document identifier: PSMN059_150Y_1
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